DDR Memory Frequency Adjustment Method, Computer Device, and Computer Readable Storage Medium

Abstract

The present invention provides a method for adjusting the frequency of a DDR memory, a computer device, and a computer-readable storage medium. The method includes obtaining the bandwidth increment value required for the current transmission transaction, obtaining the current real-time bandwidth value, and determining whether the ratio between the sum of the bandwidth increment value and the real-time bandwidth value and the theoretical total bandwidth of the current frequency of the DDR memory exceeds a preset upper threshold of the bandwidth occupancy ratio. If so, calculate the frequency value that needs to be upshifted according to the sum of the bandwidth increment value and the real-time bandwidth value, and increase the operating frequency of the DDR memory. The present invention also provides a computer device and a computer-readable storage medium for implementing the above method. The present invention can increase the bandwidth of the DDR memory in advance to avoid the problem of system operation jamming, and can timely adjust the operating frequency of the DDR memory to avoid the problem of excessive power.

Description

Technical Field

[0001] The present invention relates to the technical field of DDR memory frequency management of electronic devices. Specifically, it is a method for adjusting the frequency of a DDR memory, as well as a computer device and a computer-readable storage medium for implementing this method. Background Art

[0002] Double Data Rate Synchronous Dynamic Random Access Memory, also known as DDR memory, is a memory widely used in electronic devices. Due to the relatively large power consumption during the operation of DDR memory, for a small on-chip system, the power consumption occupied by the operation of DDR memory accounts for a relatively large proportion in the total power consumption of the system. Therefore, reducing the power consumption of DDR memory has become an important way to reduce the total power consumption of the on-chip system.

[0003] Generally, the power consumption of DDR memory is related to the operating frequency of the DDR memory, that is, when the operating frequency of the DDR memory is relatively high, its power consumption is relatively large. Therefore, an important means to reduce the power consumption of DDR memory is to reduce the operating frequency of the DDR memory. For example, in some application scenarios, if the bandwidth requirement for the DDR memory is not high, the operating frequency of the DDR memory can be reasonably adjusted to achieve the purpose of reducing the power consumption of the DDR memory.

[0004] During the operation of the on-chip system, the operating states of various hardware devices are dynamic. Therefore, it is necessary to dynamically adjust the operating frequency of the DDR memory to meet the operating requirements of the hardware devices and, as much as possible, reduce the operating frequency of the DDR memory. The traditional frequency modulation strategy of the Linux kernel DDR memory adopts a method of sampling the bandwidth of the DDR memory at the time that has occurred and estimating the bandwidth requirement of the system DDR memory at a future time based on this. This method has the following defects: First, this method is a lagging strategy in principle. It must sense the high bandwidth requirement of the system after a high bandwidth scenario has occurred, and then initiate the frequency increase action. Therefore, system lag phenomena are inevitable. Second, using the past bandwidth performance to estimate the future and predicting new problems with old experience has the defect of poor accuracy. The performance requirements and bandwidth supply do not match, and system lag and power consumption waste phenomena cannot be avoided. Summary of the Invention

[0005] The first object of the present invention is to provide a method for adjusting the frequency of a DDR memory that can effectively adjust the operating frequency of the DDR memory and can effectively avoid system lag.

[0006] The second object of the present invention is to provide a computer device for implementing the above method for adjusting the frequency of a DDR memory.

[0007] The third object of the present invention is to provide a computer-readable storage medium for implementing the above DDR memory frequency adjustment method.

[0008] To achieve the first object of the present invention, the DDR memory frequency adjustment method provided by the present invention includes obtaining the bandwidth increment value required for the current transmission transaction, obtaining the current real-time bandwidth value, and determining whether the ratio between the sum of the bandwidth increment value and the real-time bandwidth value and the theoretical total bandwidth of the current frequency of the DDR memory exceeds a preset upper threshold of the bandwidth occupancy ratio. If so, calculate the frequency value to be upshifted according to the sum of the bandwidth increment value and the real-time bandwidth value, and increase the operating frequency of the DDR memory.

[0009] As can be seen from the above solution, the present invention calculates in advance the bandwidth increment value required for the current transmission transaction, that is, predicts in advance the additional bandwidth amount required for the current transmission transaction, and dynamically adjusts the frequency of the DDR memory according to the additional evidence bandwidth amount, so that the frequency of the DDR memory meets the requirements of the transmission transaction. Since the additional bandwidth amount required for the current transmission transaction is calculated in advance, it can effectively avoid the stuttering phenomenon caused by insufficient DDR memory bandwidth during system operation.

[0010] A preferred solution is that calculating the frequency value to be upshifted according to the sum of the bandwidth increment value and the real-time bandwidth value includes: calculating the first target frequency point corresponding to the frequency value to be upshifted according to the sum of the bandwidth increment value and the real-time bandwidth value, and increasing the operating frequency of the DDR memory to the first target frequency point.

[0011] Thus, it can be seen that the frequency value corresponding to the first target frequency point can meet the bandwidth requirements of the current transmission transaction, can effectively improve the data transmission speed of the DDR memory, and avoid the occurrence of system stuttering.

[0012] A further solution is that increasing the operating frequency of the DDR memory includes: obtaining a frequency modulation lock, and releasing the frequency modulation lock after increasing the operating frequency of the DDR memory to the first target frequency point.

[0013] It can be seen that by obtaining the frequency modulation lock to adjust the frequency and immediately releasing the frequency modulation lock after the frequency adjustment, it can ensure that the operating frequency of the DDR memory remains stable when the frequency does not need to be adjusted.

[0014] A further preferred solution is that after increasing the operating frequency of the DDR memory, determine whether the current transmission transaction is completed. If so, enable the downshift process. Preferably, after obtaining the bandwidth increment value required for the current transmission transaction, close the downshift process.

[0015] It can be seen that by turning off the down - frequency process before up - frequency and enabling the down - frequency process immediately after the current transmission transaction ends, unnecessary up - frequency of the DDR memory can be avoided to save the power consumed by the DDR memory.

[0016] A preferred solution is that in the down - frequency process, it is judged whether the calculated current real - time bandwidth ratio is lower than a preset lower - limit threshold of the bandwidth ratio. If so, the second target frequency point after down - frequency is calculated according to the current real - time bandwidth ratio, and the operating frequency of the DDR memory is adjusted down to the second target frequency point.

[0017] It can be seen that when the real - time bandwidth ratio is relatively low, reducing the operating frequency of the DDR memory in a timely manner can reduce the power consumed by the DDR memory.

[0018] A further solution is that the method further includes: judging whether the calculated current real - time bandwidth ratio is higher than a preset upper - limit threshold of the bandwidth ratio. If so, the third target frequency point for up - frequency is calculated according to the current real - time bandwidth ratio, and the operating frequency of the DDR memory is adjusted up to the third target frequency point.

[0019] It can be seen that if the real - time bandwidth ratio is relatively high, the system automatically adjusts up the operating frequency of the DDR memory, which can avoid the system from getting stuck.

[0020] To achieve the above - mentioned second object, the computer device provided by the present invention includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, each step of the above - mentioned DDR memory frequency adjustment method is implemented.

[0021] To achieve the above - mentioned third object, a computer program is stored on a computer - readable storage medium, and when the computer program is executed by the processor, each step of the above - mentioned DDR memory frequency adjustment method is implemented. Description of the Drawings

[0022] Figure 1 is a system block diagram of an embodiment of the DDR memory frequency adjustment method of the present invention.

[0023] Figure 2 is a schematic diagram of calculating the real - time bandwidth in an embodiment of the DDR memory frequency adjustment method of the present invention.

[0024] Figure 3 is a flowchart of initialization when adjusting the frequency of the DDR memory in an embodiment of the DDR memory frequency adjustment method of the present invention.

[0025] Figure 4 is a background down - frequency flowchart in an embodiment of the DDR memory frequency adjustment method of the present invention.

[0026] Figure 5It is the up - frequency diagram of the embodiment of the DDR memory frequency adjustment method of the present invention.

[0027] Figure 6 It is the flowchart of the DDR host management up - frequency in the embodiment of the DDR memory frequency adjustment method of the present invention.

[0028] The present invention will be further described below in conjunction with the accompanying drawings and embodiments. Specific embodiments

[0029] The DDR memory frequency adjustment method of the present invention is applied to electronic devices, such as dash cams, set - top boxes and other electronic devices, to dynamically adjust the operating frequency of the DDR memory, avoid system operation jams, and at the same time minimize the power consumption of the DDR memory. Preferably, the electronic device is provided with a processor and a memory, and a computer program is stored on the memory. The processor implements the DDR memory frequency adjustment method by executing the computer program.

[0030] Embodiment of the DDR memory frequency adjustment method:

[0031] This embodiment is applied to an electronic device which has a DDR memory. This embodiment is mainly used to adjust the operating frequency of the DDR memory. By estimating the future DDR memory bandwidth demand increment before initiating a transmission transaction, and accurately calculating the required DDR bandwidth in combination with the real - time bandwidth of the DDR memory at the current moment, it can avoid system operation jams and also avoid the problem of excessive power consumption caused by too high an operating frequency of the DDR memory.

[0032] See Figure 1 The DDR memory frequency adjustment method of this embodiment is implemented by a frequency modulation device. The frequency modulation device has a background frequency management module 11, a down - frequency lock management module 12, a real - time bandwidth acquisition module 13, a bandwidth increment calculation module 14, a DDR host (DDR Master) bandwidth management module 15, a bandwidth upper and lower limit threshold management module 16, a frequency modulation lock management module 17, a frequency modulation execution module 18, and an interrupt management module 19.

[0033] The background frequency management module 11 is used to manage the operating frequency of the DDR memory. For example, it dynamically adjusts the operating frequency of the DDR memory according to the usage of the real-time bandwidth. When the real-time bandwidth occupancy ratio of the DDR memory is relatively low, the operating frequency of the DDR memory is reduced. For example, a down-frequency lock is obtained through the down-frequency lock management module 12, and the down-frequency operation is executed by the frequency modulation execution module 18. If the real-time bandwidth occupancy ratio of the DDR memory is relatively high, the operating frequency of the DDR memory needs to be increased. For example, an interrupt up-frequency request is sent through the interrupt management module 19, a frequency modulation lock is obtained by the frequency modulation lock management module 17, and the up-frequency operation is executed by the frequency modulation execution module 18.

[0034] The DDR host bandwidth management module 15 calculates the bandwidth increase required for the current transmission transaction through the bandwidth increment calculation module 14 according to the current transmission transaction. At the same time, the real-time bandwidth acquisition module 13 is used to collect the bandwidth of the current DDR memory in real time, compare it with the theoretical upper limit threshold and lower limit threshold of the operating frequency of the DDR memory recorded by the bandwidth upper and lower limit threshold management module 16 at the current frequency point, and calculate the bandwidth required for the current transmission transaction, that is, the minimum operating frequency, and determine the corresponding frequency point. If frequency modulation is required, a frequency modulation lock is obtained through the frequency modulation lock management module 17, and the frequency modulation operation is performed by the frequency modulation execution module 18.

[0035] In this embodiment, the operating frequency of the DDR memory is mainly adjusted in three ways. Specifically, it is managed through three operating paths. The first way is to implement frequency management through the background frequency management process. Specifically, when the system bandwidth is relatively idle, that is, when the down-frequency enabling condition is met, the background frequency management module 11 reduces the operating frequency of the DDR memory, so as to achieve the purpose of reducing the system power consumption. The operating path of the first way is as Figure 1 shown in process A in the figure. After the background frequency management module 11 obtains a down-frequency lock through the down-frequency lock management module 12, it obtains a frequency modulation lock through the frequency modulation lock management module 17, and then performs a frequency modulation operation through the frequency modulation execution module 18.

[0036] The second way is the interrupt up-frequency process. For example, when the operating frequency of the DDR memory is too low, for example, when the bandwidth requirement of the current transmission transaction is high, but the operating frequency of the current DDR memory is low, the interrupt management module 19 sends an interrupt up-frequency request, and a frequency modulation lock is obtained through the frequency modulation lock management module 17, and then the fast up-frequency operation is realized through the frequency modulation execution module 18. The operating path of the second way is as Figure 1 shown in process B in the figure.

[0037] The third method is the DDR host bandwidth management process. The DDR host bandwidth management module 15 requests the bandwidth increment calculation module 14 to calculate the upcoming bandwidth increment. If the current bandwidth of the system cannot meet the demand for the bandwidth increment, the operating frequency of the DDR memory is adjusted in a timely manner to meet the bandwidth budget for future scenarios in advance and avoid system lag. The operating path of the second method is as shown in Figure 1 Process C in. Once the bandwidth increment calculation module 14 calculates and confirms that the current bandwidth is insufficient to meet the requirements of future scenarios, the frequency modulation lock management module 17 acquires the frequency modulation lock, and then the frequency modulation execution module 18 realizes the operation of rapid frequency increase. Preferably, the background frequency reduction process is turned off during the frequency increase process to avoid interference with the operation of the ongoing high-bandwidth scenario.

[0038] The following combines Figure 2 to illustrate the real-time bandwidth calculation process of this embodiment. This embodiment presets an observation window time period length T. For each observation window time period, the data transmission duration t of the DDR memory within the observation window is calculated respectively. For example, for the observation window time period T1, there are 2 data transmissions. The actual transmission time of the first data 21 is t11, and the actual transmission time of the second data 22 is t12. Then the data transmission duration t1 of the DDR memory within the observation window time period length T1 is the sum of the time t11 and the time t12. By analogy, the data transmission durations t2, t3, etc. of the DDR memory for other observation window time periods T2, T3 can be calculated.

[0039] When the DDR memory operates, its operating frequency will be set at a certain fixed frequency point, such as F n (n = 1, 2, 3, 4, 5...) represents the frequency modulation points of the DDR memory, and each frequency point increases gradually with the increase of the value of n. Correspondingly, at each frequency point, there is a corresponding total DDR bandwidth, such as B n (n = 1, 2, 3, 4, 5...) represents the total bandwidth corresponding to each frequency point F n (n = 1, 2, 3, 4, 5...), and the total bandwidth increases gradually with the increase of the value of n.

[0040] In addition, assume that the current operating frequency of the DDR memory is F cur , the theoretical total DDR bandwidth at the current frequency point is B cur , W is the bit width of the DDR memory, P up and P down respectively represent the upper threshold value and the lower threshold value of the preset bandwidth occupancy ratio, and B delta represents the bandwidth increment required for the current scenario. Then, according to the DDR bandwidth principle, the following formula holds:

[0041] Bn = (F n × W × 2) / 8 (Equation 1)

[0042] According to Equation 1, the theoretical total bandwidths B1 / B2 / B3 / B4 / B5 corresponding to each frequency point F1 / F2 / F3 / F4 / F5 of the DDR memory can be calculated.

[0043] Assume that the length T of the real-time bandwidth observation window is set during the system initialization phase, and the duration t of the actual data transmission within each observation window needs to be updated at the end of each observation window. Therefore, the following formula can be obtained:

[0044] t / T = B rel / B cur (Equation 2)

[0045] Therefore, the following formula can be derived:

[0046] B rel = B cur × (t / T) (Equation 3)

[0047] It can be seen that according to Equation 3, based on the theoretical total bandwidth B cur at the current frequency point, the duration t of data transmission within the observation window, and the time period length T of the observation window, the real-time bandwidth B of the current measurement window can be calculated rel .

[0048] Refer to Figure 3 , when initializing the operating frequency of the DDR memory, first perform step S1 to set the upper limit threshold P up and the lower limit threshold P down of the bandwidth ratio of the DDR memory. Then, perform step S2 to set the time period length T of the DDR memory bandwidth observation window. Next, perform step S3 to initialize the down-frequency lock to the state allowing down-frequency, and perform step S4 to enable the DDR memory bandwidth upper limit threshold interrupt. Finally, perform step S5 to initialize the frequency modulation lock. It can be seen that after initialization, the operating frequency of the DDR memory can be down-frequencyed, and an up-frequency interrupt request can be received, and an up-frequency operation can be performed after receiving the up-frequency interrupt request signal.

[0049] The following introduces the background down-frequency process in combination with Figure 4 . First, perform step S11 to determine whether the current state is the state of running down-frequency, for example, whether the current system setting is the state allowing down-frequency. If so, perform step S12, otherwise, continue to judge. In step S12, judge whether the current real-time bandwidth ratio of the DDR memory is lower than the lower limit threshold of the bandwidth ratio, where the current real-time bandwidth ratio is the real-time bandwidth B relCompared with the theoretical total bandwidth B of DDR at the current frequency point cur Therefore, step S12 is to determine whether B rel / B cur <P down Is it true, that is, to judge whether t / T <P down If the result of the judgment is yes, it means that the total bandwidth at the current frequency point is sufficient, and the operating frequency of the DDR memory can be lowered to save system power consumption. At this time, step S13 is executed, and the theoretical total bandwidth B of the DDR at the current frequency point is cur Start searching downwards one by one and find the first one that satisfies B rel / B n >P down The third target bandwidth B n , the third target bandwidth B n The corresponding frequency F n That is the third target frequency that needs to be reduced.

[0050] Then, step S14 is executed to apply for the frequency modulation lock through the frequency modulation lock association module 17, and step S15 is executed to perform the frequency reduction operation through the frequency modulation execution module 18, and finally step S16 is executed to release the frequency modulation lock.

[0051] See also Figure 5 When the DDR memory is running, it is necessary to obtain the current real-time bandwidth value, that is, to execute step S21, and to execute step S22 to determine whether the frequency needs to be increased according to the current real-time bandwidth value, for example, to determine whether the current real-time bandwidth ratio of the DDR memory is higher than the bandwidth ratio upper limit threshold, that is, to determine whether B is satisfied. rel / B cur >P up The condition is to determine whether t / T>P up If the result of step S22 is yes, it means that the bandwidth of the DDR memory is tight at the current frequency, and the operating frequency of the DDR memory needs to be increased to increase the total bandwidth supply. At this time, step S23 is executed to calculate the total theoretical bandwidth B of the DDR memory at the current frequency. cur Start searching upwards one by one and find the first one that satisfies B n / B cur <P up The second target bandwidth B n , at this time, with the second target bandwidth B n The corresponding frequency F n It is the second target frequency that needs to be up-converted.

[0052] Then, step S24 is executed to apply for the frequency modulation lock through the frequency modulation lock association module 17, and step S25 is executed to perform the frequency increase operation through the frequency modulation execution module 18, and finally step S26 is executed to release the frequency modulation lock.

[0053] Combine the following Figure 6 The proactive early frequency increase process initiated by the DDR host bandwidth management module 15 is introduced. First, step S31 is executed, and the bandwidth increment calculation module 14 calculates the bandwidth increment required for the current transmission transaction, for example, according to the amount of data required to be transmitted for the current transmission transaction and the current real-time bandwidth value, the bandwidth increment required for the current transmission transaction is calculated. Specifically, according to the amount of data required to be transmitted for the current transmission transaction and the required transmission time, the theoretically required bandwidth value can be calculated, and the difference between the theoretically required bandwidth value and the current real-time bandwidth value is used as the bandwidth increment value B required for the current transmission transaction. delta .

[0054] Then, step S32 is executed to close the background frequency reduction process. At this time, step S11 determines whether frequency reduction is currently allowed, and the result is no. Then, step S33 is executed to obtain the current real-time bandwidth value B rel And the theoretical total bandwidth B of DDR at the current frequency point cur Then, step S34 is executed to determine whether the frequency needs to be upgraded. Specifically, the bandwidth increment value B is determined. delta And the real-time bandwidth value B rel The sum of the theoretical total bandwidth B of the current frequency of the DDR memory cur Whether the ratio between them exceeds the preset bandwidth ratio upper limit threshold P up , that is, to judge (B rel +B delta ) / B cur >P up Is it true? If so, it means that the future bandwidth supply will be tight at the current frequency, and the operating frequency of the DDR memory needs to be increased to increase the total bandwidth supply.

[0055] At this time, step S35 is executed to obtain the theoretical total bandwidth B of DDR at the current frequency point. cur Start searching upwards one by one and find the first one that satisfies (B rel +B delta ) / B cur <P up The first target bandwidth B n , then with the first target bandwidth B n The corresponding frequency F n It is the first target frequency that needs to be up-converted.

[0056] Then, step S36 is executed to apply for a frequency modulation lock through the frequency modulation lock association module 17, step S37 is executed to perform a frequency increase operation through the frequency modulation execution module 18, and step S38 is executed to release the frequency modulation lock. Then, step S39 is executed to determine whether the current transmission transaction has been completed. If so, step S40 is executed to enable the background frequency reduction program. At this time, the system operates the DDR memory to reduce the frequency.

[0057] During the process of the proactive early frequency increase executed by the DDR host bandwidth management module 15, by closing the background frequency reduction process, it is possible to avoid the problem of operation chaos caused by triggering the frequency reduction process during the proactive frequency increase process. And after the current transmission transaction ends, enabling the frequency reduction process can restore the frequency reduction operation of the DDR memory to ensure that the DDR memory can flexibly adjust the frequency according to the actual operation needs to reduce the system power consumption.

[0058] It can be seen that this embodiment can estimate the bandwidth demand increment of this transaction in advance before initiating the transmission transaction. The system provides the corresponding bandwidth supply in advance according to this demand increment, avoiding the situation of system jamming. At the same time, it can accurately meet the system bandwidth demand on the premise of the minimum power consumption cost, ensuring that the system is not jammed, and meeting the requirements of reducing power consumption and improving performance in both aspects.

[0059] Embodiment of the computer device:

[0060] The computer device of this embodiment can be an electronic device such as a driving recorder or a set-top box. The computer device includes a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements each step of the above DDR memory frequency adjustment method.

[0061] For example, the computer program can be divided into one or more modules. One or more modules are stored in the memory and executed by the processor to complete each module of the present invention. One or more modules can be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device.

[0062] The processor referred to in the present invention may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, connecting various parts of the entire terminal device through various interfaces and circuits.

[0063] The memory can be used to store computer programs and / or modules. By running or executing the computer programs and / or modules stored in the memory, and by calling the data stored in the memory, the processor realizes various functions of the terminal device. The memory mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system, application programs required for at least one function (such as a sound playback function, an image playback function, etc.); the data storage area can store data created according to the use of the mobile phone (such as audio data, phone book, etc.). In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, Flash Card, at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage devices.

[0064] Computer-readable storage medium:

[0065] If the computer program stored in the above computer device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-mentioned embodiment methods of the present invention, it can also be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, it can implement each step of the above DDR memory frequency adjustment method.

[0066] Among them, the computer program includes computer program code, which can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice within the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0067] Finally, it should be emphasized that the present invention is not limited to the above embodiments. For example, the number of multiple frequency points of the preset DDR memory, the change of the corresponding frequency, or the change of the upper limit threshold and lower limit threshold of the set bandwidth ratio, etc. These changes should also be included in the protection scope of the claims of the present invention.

Claims

1. A method for adjusting the frequency of a DDR memory, characterized in that, Including: Obtain the bandwidth increment value required for the current transmission transaction, and obtain the current real-time bandwidth value. Determine whether the ratio between the sum of the bandwidth increment value and the real-time bandwidth value and the theoretical total bandwidth of the current frequency of the DDR memory exceeds a preset bandwidth ratio upper limit threshold. If so, calculate the frequency value that needs to be upshifted according to the sum of the bandwidth increment value and the real-time bandwidth value, and upshift the operating frequency of the DDR memory; Among them, obtaining the bandwidth increment value required for the current transmission transaction includes: calculating the theoretically required bandwidth value according to the data volume to be transmitted and the transmission time required for the current transmission transaction, and using the difference between the theoretically required bandwidth value and the current real-time bandwidth value as the bandwidth increment value required for the current transmission transaction; Calculating the frequency value that needs to be upshifted according to the sum of the bandwidth increment value and the real-time bandwidth value includes: calculating the first target frequency point corresponding to the frequency value that needs to be upshifted according to the sum of the bandwidth increment value and the real-time bandwidth value, and upshifting the operating frequency of the DDR memory to the first target frequency point; Among them, starting from the total theoretical DDR bandwidth at the current frequency point and searching upward successively, the first target bandwidth B rel +B delta ) / B cur <P up is found. The first target bandwidth B n , then the frequency point F n corresponding to the first target bandwidth B n is the first target frequency point that needs to be up-converted. Among them, B rel is the current real-time bandwidth value, B delta is the bandwidth increment value, B cur is the total theoretical DDR bandwidth at the current frequency point, and P up is the preset upper threshold of the bandwidth ratio.

2. The DDR memory frequency adjustment method according to claim 1, wherein: Upshifting the operating frequency of the DDR memory includes: obtaining a frequency modulation lock, and releasing the frequency modulation lock after upshifting the operating frequency of the DDR memory to the first target frequency point.

3. The DDR memory frequency adjustment method according to claim 1 or 2, wherein: After upshifting the operating frequency of the DDR memory, determine whether the current transmission transaction has been completed. If so, enable the downshifting process.

4. The DDR memory frequency adjustment method according to claim 3, wherein: After obtaining the bandwidth increment value required for the current transmission transaction, close the downshifting process.

5. The DDR memory frequency adjustment method according to claim 3, wherein: Under the downshifting process, determine whether the calculated current real-time bandwidth ratio is lower than a preset bandwidth ratio lower limit threshold. If so, calculate the second target frequency point after downshifting according to the current real-time bandwidth ratio, and downshift the operating frequency of the DDR memory to the second target frequency point.

6. The DDR memory frequency adjustment method according to claim 1 or 2, wherein: The method further includes: determining whether the calculated current real-time bandwidth ratio is higher than a preset bandwidth ratio upper limit threshold. If so, calculate the third target frequency point that needs to be upshifted according to the current real-time bandwidth ratio, and upshift the operating frequency of the DDR memory to the third target frequency point.

7. Computer device, characterized in that, Including a processor and a memory, the memory stores a computer program, and when the computer program is executed by the processor, each step of the DDR memory frequency adjustment method described in any one of claims 1 to 6 is implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, each step of the DDR memory frequency adjustment method described in any one of claims 1 to 6 is implemented.

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