Chip verification method, device, equipment and medium

Abstract

The present disclosure provides a chip verification method, device, equipment and medium, which relates to the field of computer technology, and in particular to the field of chips. The implementation scheme is: determine a first number of instruction streams; for any instruction stream, perform a verification operation, the verification operation at least includes: for each operation descriptor, enable at least one operation module among multiple operation modules to perform data processing for the operation descriptor to obtain the processing result corresponding to the operation descriptor; in response to executing to the abort descriptor, determine the feedback result corresponding to at least one operation descriptor located before the abort descriptor, wherein the feedback result is obtained according to the processing result corresponding to each operation descriptor in at least one operation descriptor; and compare the feedback result corresponding to at least one operation descriptor with the simulation result corresponding to at least one operation descriptor to determine the verification result of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the field of chips, and specifically to a chip verification method, device, electronic device, computer-readable storage medium, and computer program product. Background Art

[0002] In the process of chip development and use, chip verification is a very important link and a necessary method to ensure the correctness of chip functions. At present, the mainstream framework for chip verification is Universal Verification Methodology (UVM), which is a universal verification methodology that provides a standardization of design patterns and provides a basic library for building platforms.

[0003] The methods described in this section are not necessarily methods that have been previously conceived or employed. Unless otherwise indicated, it should not be assumed that any method described in this section is considered to be prior art simply because it is included in this section. Similarly, unless otherwise indicated, the issues mentioned in this section should not be considered to have been recognized in any prior art. Summary of the invention

[0004] The present disclosure provides a chip verification method, device, electronic device, computer-readable storage medium and computer program product.

[0005] According to one aspect of the present disclosure, a chip verification method is provided, wherein the chip includes multiple operation modules, and the method includes: determining a first number of instruction streams, wherein each instruction stream in the first number of instruction streams includes multiple operation descriptors and at least one abort descriptor; and performing a verification operation for any instruction stream in the first number of instruction streams, the verification operation at least including: for each operation descriptor in the multiple operation descriptors included in the instruction stream, causing at least one operation module in the multiple operation modules to perform data processing for the operation descriptor to obtain a processing result corresponding to the operation descriptor; in response to the instruction stream executing to the abort descriptor, determining a feedback result corresponding to at least one operation descriptor in the instruction stream that is located before the abort descriptor, wherein the feedback result is obtained based on the processing result corresponding to each operation descriptor in the at least one operation descriptor; and comparing the feedback result corresponding to the at least one operation descriptor with the simulation result corresponding to the at least one operation descriptor to determine the verification result of the chip.

[0006] According to another aspect of the present disclosure, a chip verification device is provided, wherein the chip includes a plurality of operation modules, and the device includes: a determination unit configured to determine a first number of instruction streams, wherein each instruction stream in the first number of instruction streams includes a plurality of operation descriptors and at least one abort descriptor; and an execution unit configured to perform a verification operation on any instruction stream in the first number of instruction streams, the execution unit at least including: an enabling subunit configured to enable at least one operation module in the plurality of operation modules to perform data processing on each operation descriptor in the plurality of operation descriptors included in the instruction stream to obtain a processing result corresponding to the operation descriptor; a determining subunit configured to determine, in response to the instruction stream executing to the abort descriptor, a feedback result corresponding to at least one operation descriptor in the instruction stream that is located before the abort descriptor, wherein the feedback result is obtained according to the processing result corresponding to each operation descriptor in the at least one operation descriptor; and a comparing subunit configured to compare the feedback result corresponding to the at least one operation descriptor with the simulation result corresponding to the at least one operation descriptor to determine a verification result of the chip.

[0007] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform a chip verification method.

[0008] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute a chip verification method.

[0009] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, wherein the computer program implements a chip verification method when executed by a processor.

[0010] According to one or more embodiments of the present disclosure, chip verification can be performed by determining a first number of instruction streams. By enabling the computing units in the chip to execute each computing descriptor in the instruction stream in sequence, the collaborative operation mode between the various computing modules of the chip in the real scenario can be restored, thereby effectively improving the accuracy of chip verification.

[0011] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings exemplarily illustrate the embodiments and constitute a part of the specification, and together with the text description of the specification, are used to explain the exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0013] Figure 1 A flow chart of a chip verification method according to an embodiment of the present disclosure is shown;

[0014] Figure 2 A schematic diagram showing the overall process of chip verification according to an embodiment of the present disclosure is shown;

[0015] Figure 3 A schematic diagram showing an instruction flow according to an embodiment of the present disclosure;

[0016] Figure 4 A flowchart of chip system-level verification according to an embodiment of the present disclosure is shown;

[0017] Figure 5 A structural block diagram of a chip verification device according to an embodiment of the present disclosure is shown; and

[0018] Figure 6 A structural block diagram of an exemplary electronic device that can be used to implement the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0019] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0020] In the present disclosure, unless otherwise specified, the use of the terms "first", "second", etc. to describe various elements is not intended to limit the positional relationship, timing relationship, or importance relationship of these elements, and such terms are only used to distinguish one element from another element. In some examples, the first element and the second element may refer to the same instance of the element, and in some cases, based on the description of the context, they may also refer to different instances.

[0021] The terms used in the description of various examples in this disclosure are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. In addition, the term "and / or" used in this disclosure covers any one of the listed items and all possible combinations.

[0022] In the prior art, the verification of chips based on custom instruction sets cannot use software programs written in high-level languages ​​as verification incentives. During the chip development stage, the various computing modules in the chip cannot execute the programs written in the software. The verification personnel can only understand the instruction functions by themselves and construct directional or random instruction verification in the verification platform to verify the correctness of the calculation function. These directional or random instructions are very short or lack connection between instructions, which makes the verification out of the real scene and the verification effect is poor.

[0023] In order to solve the above problems, the present invention performs chip verification by determining a first number of instruction streams, and by enabling the computing units in the chip to execute each computing descriptor in the instruction stream in sequence, it can restore the collaborative operation mode between various computing modules of the chip in the real scenario, and effectively improve the accuracy of chip verification.

[0024] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 FIG. 1 is a flow chart of a chip verification method according to an embodiment of the present disclosure. Figure 1 As shown, the chip verification method 100 includes: step S101, determining a first number of instruction streams, wherein each instruction stream in the first number of instruction streams includes multiple operation descriptors and at least one abort descriptor; and step S102, performing a verification operation on any instruction stream in the first number of instruction streams, the verification operation at least including: step S102-1, for each operation descriptor in the multiple operation descriptors included in the instruction stream, enabling at least one operation module in the multiple operation modules to perform data processing on the operation descriptor to obtain a processing result corresponding to the operation descriptor; step S102-2, in response to the instruction stream executing to the abort descriptor, determining a feedback result corresponding to at least one operation descriptor in the instruction stream that is located before the abort descriptor, wherein the feedback result is obtained according to the processing result corresponding to each operation descriptor in the at least one operation descriptor; and step S102-3, comparing the feedback result corresponding to the at least one operation descriptor with the simulation result corresponding to the at least one operation descriptor to determine the verification result of the chip.

[0026] Therefore, by performing chip verification through a determined first number of instruction streams and enabling the computing units in the chip to execute each computing descriptor in the instruction stream in sequence, the collaborative operation mode between the various computing modules of the chip in the real scene can be restored, so that the chip can complete the real computing function and effectively improve the accuracy of chip verification.

[0027] According to some embodiments, the above verification method may be implemented by a verification component capable of performing data communication with a verification chip.

[0028] Among them, the operation descriptor can be regarded as a sub-instruction stream composed of multiple instructions, which performs calculations in a computing unit of a specified type.

[0029] In step S101, according to some embodiments, determining the first number of instruction streams may include: obtaining a verification stimulus corresponding to the task to be verified, wherein the verification stimulus is compiled using a compiler corresponding to the chip; and determining the first number of instruction streams based on the verification stimulus.

[0030] In one example, a corresponding verification program can be written for the task to be verified in a high-level programming language, such as C++, where the task to be verified can be, for example, a computing function that the chip can complete, and accordingly, the verification program can also implement this computing function. Therefore, by writing the verification program, the real computing function that the chip is to perform in the real scene is restored, which can effectively improve the accuracy of chip verification.

[0031] According to some embodiments, the verification program written in the high-level programming language is compiled by a compiler, and a data file in a specified format, i.e., a verification stimulus, is obtained for chip verification. The verification stimulus may include: an original data file in a specified format, which is used to initialize the memory when performing system-level verification on the chip system, and to initialize the chip memory simulated by the chip verification platform when verifying the subsystems in the chip separately; an instruction location index file in a specified format, including a first number of instruction streams, so that the operation module performs corresponding operation operations based on the operation descriptors in the instruction stream; and a generated address segment configuration file in a specified format, which is used to indicate the address segment where the processing results of the operation module can be stored.

[0032] According to some embodiments, the simulation result corresponding to at least one operation descriptor is obtained in advance by software simulation. It is understandable that the operation process of each operation module can be simulated by software to verify the functionality of each operation module, that is, to achieve chip subsystem level verification; the collaborative operation process of multiple operation modules can also be simulated by software to verify the functionality of the chip at the system level.

[0033] In one example, the software for simulation receives multiple files in the verification stimulus described above as input, starts simulation in response to the input, and outputs the processing results of the simulation of each operation module to the address segment indicated in the generated address segment configuration file. Thus, by simulating the hardware through software to execute each stage of the task to be verified, the output values ​​of the chip and the software simulation in the same address segment when executing the corresponding steps can be compared to verify the functionality of each operation module.

[0034] Figure 2 FIG. 1 is a schematic diagram showing the overall process of chip verification according to an embodiment of the present disclosure. Figure 2 As shown, the software receives the data file as the verification stimulus as input for calculation simulation, and outputs the simulation result for comparison with the feedback result of the chip. At the hardware verification end, the data file as the verification stimulus is read by the hardware verification platform. Specifically, the data file can be read through a component that is compatible with the file format of the verification stimulus, and the corresponding data file is sent to the chip. The calculation module in the chip performs calculations based on the calculation descriptors contained in the data file and generates corresponding processing results, and outputs the final feedback result, which is compared with the simulation result of the software simulation, so as to complete the verification of the chip.

[0035] According to some embodiments, the chip also includes a scheduling module, and wherein, for each of the multiple operation descriptors included in the instruction stream, enabling at least one of the multiple operation modules to perform data processing for the operation descriptor may include: starting the scheduling module using the instruction stream so that the scheduling module can enable at least one operation module corresponding to the operation descriptor to perform data processing for each of the multiple operation descriptors included in the instruction stream.

[0036] Therefore, the scheduling module is started to send multiple operation descriptors in the instruction stream to corresponding operation modules, so that the operation modules corresponding to each operation descriptor perform operations and data processing on the operation descriptor.

[0037] According to some embodiments, when there is no scheduling module in the chip, the verification component used for verification can also directly enable at least one operation module among the multiple operation modules at the subsystem level to be verified to perform data processing for each of the multiple operation descriptors included in the instruction stream.

[0038] According to some embodiments, step S102-2 includes: enabling the scheduling module to feedback an abort message in response to the instruction stream executing to the abort descriptor; and in response to receiving the abort message, determining a feedback result corresponding to at least one operation descriptor in the instruction stream that is located before the abort descriptor.

[0039] The feedback result corresponding to at least one operation descriptor before the abort descriptor is recorded by triggering the abort descriptor, and the feedback result is written into the address segment indicated in the generated address segment configuration file. In one example, the feedback result can be an intermediate result obtained by the at least one operation module performing the operation.

[0040] According to some embodiments, each of a plurality of operation descriptors includes a first address identifier, and the method further includes: before performing a verification operation on any one of a first number of instruction streams, storing the data to be processed in a target storage space; and wherein, for each of the plurality of operation descriptors included in the instruction stream, enabling at least one of the plurality of operation modules to perform data processing for the operation descriptor includes: enabling at least one operation module to read a portion of the data to be processed corresponding to the operation descriptor in the data to be processed from a storage address corresponding to the first address identifier of the operation descriptor in the target storage space; and enabling at least one operation module to perform data processing for the operation descriptor using the portion of the data to be processed corresponding to the operation descriptor.

[0041] It is understandable that the above-mentioned data to be processed is a raw data file with a specified format, which is used to initialize the memory when performing system-level verification on the chip system, and to initialize the chip memory simulated by the chip verification platform when verifying the subsystems in the chip separately. After writing the data to be processed into the memory, the operation module can read the data from the memory for the corresponding operation descriptor, perform the corresponding operation function, and write the result of the operation back to the specified address segment in the memory.

[0042] According to some embodiments, the operation descriptor corresponding to the operation module also includes: a field indicating the address and length of the kernel of the operation module stored in the memory; a field indicating the number of cores required by the kernel of the operation module; and a field indicating the address of the parameters of the kernel of the operation module. Thus, the scheduling module can send the operation descriptor to the corresponding operation module according to the fields in the operation descriptor, and the operation module configures resources and reads data according to the above fields, and completes its corresponding operation function.

[0043] According to some embodiments, each of at least one abort descriptor includes a second address identifier, which can be used to indicate the storage address in the target storage space of the processing result corresponding to each of the at least one operation descriptor located before the abort descriptor in the instruction stream; and wherein, in response to the instruction stream executing to the abort descriptor, determining the feedback result corresponding to at least one operation descriptor located before the abort descriptor in the instruction stream includes: in response to the instruction stream executing to the abort descriptor, reading the processing result corresponding to each of the at least one operation descriptor from the storage address corresponding to the second address identifier of the abort descriptor in the target storage space; and determining the feedback result corresponding to the at least one operation descriptor based on the processing result corresponding to each of the at least one operation descriptor.

[0044] It can be understood that the second address identifier corresponds to the address segment indicated in the generated address segment configuration file described above, and the operation module writes its processing result corresponding to the operation descriptor into the address segment indicated in the generated address segment configuration file. The processing result can be the intermediate result obtained by the operation module during the execution of the operation. This intermediate result can be used to determine the final operation result, that is, the feedback result corresponding to the operation descriptor, and the feedback result is used to compare with the corresponding result in the software simulation.

[0045] According to some embodiments, the target storage space includes a storage space located in the chip. When performing system-level verification on the chip, the original data file needs to be written into the memory of the chip before the scheduling module schedules the instruction stream, so that the memory data can be read when the computing module performs the computing function.

[0046] According to some embodiments, the target storage space also includes a storage space used by a hardware verification platform (e.g., a UVM platform) to simulate chip memory. Accordingly, when performing subsystem-level verification on a chip, the original data file needs to be written into the chip memory simulated by the hardware verification platform, and then the verification platform sends the instruction stream to the operation module corresponding to the operation descriptor, so that the operation module reads data in the simulated chip memory when performing the operation function.

[0047] According to some embodiments, the plurality of operation modules include at least two categories of operation modules, each of the plurality of operation descriptors includes a category identifier, and wherein, for each of the plurality of operation descriptors included in the instruction stream, enabling at least one of the plurality of operation modules to perform data processing for the operation descriptor to obtain a processing result corresponding to the operation descriptor includes: enabling at least one operation module of the same category in the plurality of operation modules to perform data processing for the operation descriptor, wherein the category of at least one operation module corresponds to the category identifier of the operation descriptor. Exemplarily, the category identifier included in the operation descriptor may indicate the type of the operation module that executes the operation descriptor, and at the same time, an instruction stream may include operation descriptors indicating multiple types of operation modules.

[0048] According to some embodiments, the first number is an arbitrary integer not less than 2, there are associated first instruction streams and second instruction streams in the first number of instruction streams, the first instruction stream includes a pause instruction, and the second instruction stream includes a start identifier; and wherein the verification operation also includes: enabling multiple operation modules to respond to the first instruction stream executing to the pause instruction, suspending data processing for the first instruction stream; and enabling at least one operation module among the multiple operation modules to respond to the second instruction stream executing to the start identifier, starting data processing for the first instruction stream from the next instruction of the pause instruction in the first instruction stream.

[0049] It is understandable that the operations between different operation modules may not be independent of each other. The first operation module may need to receive the calculation results output by the second module as input. In this process, the synchronous and asynchronous coordination of different operation modules in executing operation operations can be achieved through the cooperation between different instruction streams.

[0050] Figure 3 FIG. 1 is a schematic diagram showing an instruction flow according to an embodiment of the present disclosure. Figure 3 As shown, INT represents an interrupt instruction. When verifying the chip, data can be written in response to the interrupt instruction. The written data can be the intermediate result when the operation module performs the operation function. CDNN and XPU are category identifiers contained in the operation descriptor, which respectively indicate two different types of operation modules and can perform different operation functions respectively. WAIT is a pause instruction and RECORD is a start identifier. The two work together to realize the synchronous and asynchronous operations of different operation modules indicated by different instruction streams.

[0051] Figure 4 FIG. 4 shows a flow chart of chip system level verification according to an embodiment of the present disclosure. Figure 4As shown, the method for performing system-level verification on a chip includes: reading a data file as a verification stimulus. Specifically, a verification component can be set on a general verification platform, and the verification component can read a data file with a specific format according to an agreed file format, and then the verification component reads the data file. As mentioned above, the data file used as a verification stimulus may include: an original data file, an instruction location index file, and a generated address segment configuration file. After the verification platform reads the above files, the original data file is first written into the memory of the chip to initialize the memory of the chip. Subsequently, the verification platform starts the scheduling module of the chip to send the operation descriptor in the instruction stream contained in the instruction location index file to the corresponding operation module. The operation module responds to the corresponding operation descriptor, performs the corresponding operation, reads and writes the memory data, and writes the calculation result back to the memory. After the calculation is completed, the scheduling module feeds back an interrupt indicating that the calculation is completed. In response to the calculation completion interrupt, the verification platform reads data from the memory and generates a hardware output file, that is, the calculation result of the chip corresponding to the input verification stimulus. The hardware output file is compared with the result of the software simulation to determine whether the verification result is correct.

[0052] Correspondingly, the chip verification method is also applicable to the subsystem-level verification of the chip, that is, to verify each computing module in the chip. The overall process of chip subsystem verification is similar to the system-level verification of the chip. Unlike the system-level verification, the chip's memory and scheduling module are not included in the verification of the subsystem. Therefore, the verification platform needs to simulate the chip's memory for reading and writing data. At the same time, since the scheduling module is not included in the subsystem, the operation descriptor in the instruction stream can be directly sent to the corresponding subsystem, that is, the computing module, through the verification component set on the verification platform, so as to realize the verification of the subsystem.

[0053] According to another aspect of the present disclosure, a chip verification device is provided, wherein the chip includes a plurality of operation modules. Figure 5As shown, the chip verification device 500 includes: a determination unit 501, configured to determine a first number of instruction streams, wherein each instruction stream in the first number of instruction streams includes multiple operation descriptors and at least one abort descriptor; and an execution unit 502, configured to perform a verification operation on any instruction stream in the first number of instruction streams, and the execution unit at least includes: an enabling subunit 502-1, configured to enable at least one operation module in multiple operation modules to perform the operation descriptor for each operation descriptor in the multiple operation descriptors included in the instruction stream. Data processing to obtain the processing result corresponding to the operation descriptor; a determination subunit 502-2 is configured to determine, in response to the instruction stream executing to the abort descriptor, a feedback result corresponding to at least one operation descriptor located before the abort descriptor in the instruction stream, wherein the feedback result is obtained based on the processing result corresponding to each operation descriptor in the at least one operation descriptor; and a comparison subunit 502-3 is configured to compare the feedback result corresponding to at least one operation descriptor with the simulation result corresponding to at least one operation descriptor to determine the verification result of the chip.

[0054] Thus, the determination unit 501 determines the first number of instruction streams, and the execution unit 502 performs chip verification. By enabling the operation units in the chip to sequentially execute the various operation descriptors in the instruction stream, the collaborative operation mode between the various operation modules of the chip in the real scene can be restored, so that the chip can complete the real computing function, and compare it with the corresponding simulation results to verify the functional correctness of the chip at the system level. At the same time, by enabling each operation module in the chip to execute the corresponding operation descriptor respectively, and comparing the feedback results corresponding to each operation module and the simulation results corresponding to the corresponding operation descriptor respectively, the respective verification of each operation module in the chip is realized to verify the functional correctness of the chip at the subsystem level. Thus, by verifying the functional correctness of the chip at the system level and the functional correctness of the subsystem level, the accuracy of chip verification and the completeness of verification coverage can be effectively improved.

[0055] According to some embodiments, the determination unit 501 may include: a subunit for obtaining a verification stimulus corresponding to the task to be verified, wherein the verification stimulus is a subunit compiled using a compiler corresponding to the chip; and a subunit for determining a first number of instruction streams based on the verification stimulus.

[0056] In one example, the device may write a corresponding verification program in a high-level programming language for the task to be verified, wherein the task to be verified may be, for example, a computing function that can be completed by the chip, and accordingly, the verification program can also implement this computing function.

[0057] According to some embodiments, the device can also use a compiler to compile the verification program written in the above-mentioned high-level programming language to obtain a file in a specified format, namely, a verification stimulus, for chip verification. The verification stimulus includes: a raw data file in a specified format, which is used to initialize the memory when performing system-level verification on the chip system, and when verifying the subsystems in the chip separately, it is used to initialize the chip memory simulated by the chip verification platform; an instruction location index file in a specified format, including a first number of instruction streams, so that the operation module performs corresponding operation operations based on the operation descriptors in the instruction stream; and a generated address segment configuration file in a specified format, which is used to indicate the address segment where the processing results of the operation module can be stored.

[0058] According to some embodiments, the simulation result corresponding to at least one operation descriptor is obtained in advance by software simulation. It is understandable that the device can use software to simulate the operation process of each operation module separately to verify the functionality of each operation module, that is, to achieve chip subsystem level verification; it can also use software to simulate the collaborative operation process of multiple operation modules to verify the functionality of the chip at the system level.

[0059] In one example, the software for simulation receives multiple data files in the verification stimulus described above as input, starts simulation in response to the input, and outputs the processing results of the simulation of each operation module to the address segment indicated in the generated address segment configuration file. Thus, the output values ​​of the chip and software simulation in the same address segment can be compared to verify the functionality of each operation module.

[0060] According to some embodiments, the chip also includes a scheduling module, and wherein the enabling sub-unit 502-1 includes: a sub-unit for starting the scheduling module using the instruction stream so that the scheduling module can enable at least one operation module corresponding to the operation descriptor to perform data processing for each of the multiple operation descriptors included in the instruction stream.

[0061] Therefore, the scheduling module is started to send multiple operation descriptors in the instruction stream to corresponding operation modules, so that the operation modules corresponding to each operation descriptor perform operations and data processing on the operation descriptor.

[0062] According to some embodiments, the determination subunit 502-2 includes: a subunit for enabling the scheduling module to feedback an abort message in response to the instruction stream executing to the abort descriptor; and a subunit for determining, in response to receiving the abort message, a feedback result corresponding to at least one operation descriptor in the instruction stream that is located before the abort descriptor.

[0063] According to some embodiments, each of a plurality of operation descriptors includes a first address identifier, and the device further includes: a write unit configured to store the data to be processed in a target storage space before performing a verification operation on any one of a first number of instruction streams; and wherein the enabling sub-unit includes: a sub-unit for enabling at least one operation module to read a portion of the data to be processed corresponding to the operation descriptor in the data to be processed from a storage address in the target storage space corresponding to the first address identifier of the operation descriptor; and a sub-unit for enabling at least one operation module to perform data processing for the operation descriptor using the portion of the data to be processed corresponding to the operation descriptor.

[0064] It is understandable that the above-mentioned data to be processed is a raw data file with a specified format, which is used to initialize the memory when performing system-level verification on the chip system, and to initialize the chip memory simulated by the chip verification platform when verifying the subsystems in the chip separately. After writing the data to be processed into the memory, the operation module can read the data from the memory for the corresponding operation descriptor, perform the corresponding operation function, and write the result of the operation back to the specified address segment in the memory.

[0065] According to some embodiments, the operation descriptor corresponding to the operation module also includes: a field indicating the address and length of the kernel of the operation module stored in the memory; a field indicating the number of cores required by the kernel of the operation module; and a field indicating the address of the parameters of the kernel of the operation module. Thus, the scheduling module can send the operation descriptor to the corresponding operation module according to the fields in the operation descriptor, and the operation module configures resources and reads data according to the above fields, and completes its corresponding operation function.

[0066] According to some embodiments, each of at least one abort descriptor includes a second address identifier, which can be used to indicate the storage address in the target storage space of the processing result corresponding to each of at least one operation descriptor located before the abort descriptor in the instruction stream; and wherein the determination subunit includes: a subunit for reading the processing result corresponding to each of the at least one operation descriptor from the storage address corresponding to the second address identifier of the abort descriptor in the target storage space in response to the instruction stream executing to the abort descriptor; and a subunit for determining the feedback result corresponding to at least one operation descriptor based on the processing result corresponding to each of the at least one operation descriptor.

[0067] It can be understood that the second address identifier corresponds to the address segment indicated in the generated address segment configuration file described above, and the operation module writes its processing result corresponding to the operation descriptor into the address segment indicated in the generated address segment configuration file. The processing result can be the intermediate result obtained by the operation module during the execution of the operation. This intermediate result can be used to determine the final operation result, that is, the feedback result corresponding to the operation descriptor, and the feedback result is used to compare with the corresponding result in the software simulation.

[0068] According to some embodiments, the target storage space includes a storage space located in the chip. When performing system-level verification on the chip, the original data file needs to be written into the memory of the chip before the scheduling module schedules the instruction stream, so that the memory data can be read when the computing module performs the computing function.

[0069] According to some embodiments, the target storage space also includes a storage space used by a hardware verification platform (e.g., a UVM platform) to simulate chip memory. Accordingly, when performing subsystem-level verification on a chip, the original data file needs to be written into the chip memory simulated by the hardware verification platform, and then the verification platform sends the instruction stream to the operation module corresponding to the operation descriptor, so that the operation module reads data in the simulated chip memory when performing the operation function.

[0070] According to some embodiments, the plurality of operation modules include at least two types of operation modules, each of the plurality of operation descriptors includes a category identifier, and wherein the enabling subunit includes: a subunit for enabling at least one operation module of the same category among the plurality of operation modules to perform data processing for the operation descriptor, wherein the category of at least one operation module corresponds to the category identifier of the operation descriptor. Exemplarily, the category identifier included in the operation descriptor may indicate the type of the operation module that executes the operation descriptor, and at the same time, an instruction stream may include operation descriptors indicating multiple types of operation modules.

[0071] According to some embodiments, the first number is an arbitrary integer not less than 2, there are associated first and second instruction streams in the first number of instruction streams, the first instruction stream includes a pause instruction, and the second instruction stream includes a start mark; and wherein the execution unit further includes: a subunit for enabling multiple operation modules to respond to the first instruction stream to execute to the pause instruction and suspend data processing for the first instruction stream; and a subunit for enabling at least one operation module among the multiple operation modules to respond to the second instruction stream to execute to the start mark, and start data processing for the first instruction stream from the next instruction of the pause instruction in the first instruction stream. It can be understood that the operations between different operation modules may not be independent of each other, and the first operation module may need to receive the calculation result output by the second module as input. In this process, the coordination of synchronization and asynchrony of different operation modules in executing operation operations can be achieved through the cooperation between different instruction streams.

[0072] According to an embodiment of the present disclosure, an electronic device, a readable storage medium and a computer program product are also provided.

[0073] According to another aspect of the present disclosure, an electronic device is also provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the above methods.

[0074] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is further provided, wherein the computer instructions are used to enable the computer to execute any one of the above methods.

[0075] According to another aspect of the present disclosure, a computer program product is further provided, including a computer program, wherein the computer program implements any one of the above methods when executed by a processor.

[0076] refer to Figure 6 , a block diagram of an electronic device 600 that can be used as a server or client of the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0077] like Figure 6 As shown, the device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the device 600 can also be stored. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0078] Multiple components in the device 600 are connected to the I / O interface 805, including: an input unit 606, an output unit 607, a storage unit 608, and a communication unit 609. The input unit 606 can be any type of device that can input information to the device 600. The input unit 606 can receive input digital or character information and generate key signal input related to user settings and / or function control of the electronic device, and can include but is not limited to a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and / or a remote controller. The output unit 607 can be any type of device that can present information, and can include but is not limited to a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 608 can include but is not limited to a disk, an optical disk. The communication unit 609 allows the device 600 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and can include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a Bluetooth™ device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0079] The computing unit 601 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 601 performs the various methods and processes described above, such as a chip verification method. For example, in some embodiments, the chip verification method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the chip verification method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the chip verification method in any other appropriate manner (e.g., by means of firmware).

[0080] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0081] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0082] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0083] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0084] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0085] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0086] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0087] Although the embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the above-mentioned methods, systems and devices are merely exemplary embodiments or examples, and the scope of the present invention is not limited by these embodiments or examples, but only by the claims after authorization and their equivalent scope. Various elements in the embodiments or examples can be omitted or replaced by their equivalent elements. In addition, each step can be performed in an order different from that described in the present disclosure. Further, the various elements in the embodiments or examples can be combined in various ways. It is important that with the evolution of technology, many elements described herein can be replaced by equivalent elements that appear after the present disclosure.

Claims

1. A chip verification method, wherein: The chip includes a plurality of computing modules, and the method includes: Determine a first number of instruction streams, wherein each instruction stream in the first number of instruction streams includes a plurality of operation descriptors and at least one abort descriptor, wherein each operation descriptor indicates a sub-instruction stream consisting of a plurality of instructions, and each abort descriptor indicates a trigger operation of a feedback result corresponding to at least one operation descriptor before the abort descriptor; and For any one instruction stream of the first number of instruction streams, a verification operation is performed, where the verification operation at least includes: For each operation descriptor among the multiple operation descriptors included in the instruction stream, enabling at least one operation module among the multiple operation modules to perform data processing for the operation descriptor to obtain a processing result corresponding to the operation descriptor; In response to the instruction stream being executed to the abort descriptor, determining a feedback result corresponding to at least one operation descriptor located before the abort descriptor in the instruction stream, wherein the feedback result is obtained according to a processing result corresponding to each operation descriptor in the at least one operation descriptor; and The feedback result corresponding to the at least one operation descriptor is compared with the simulation result corresponding to the at least one operation descriptor to determine a verification result of the chip.

2. The method according to claim 1, wherein: The chip also includes a scheduling module. And wherein, for each of the multiple operation descriptors included in the instruction stream, enabling at least one operation module among the multiple operation modules to perform data processing for the operation descriptor comprises: The scheduling module is started by using the instruction stream, so that the scheduling module can enable at least one operation module corresponding to each operation descriptor of multiple operation descriptors included in the instruction stream to perform data processing for the operation descriptor.

3. The method according to claim 2, wherein: In response to the instruction stream being executed to the abort descriptor, determining a feedback result corresponding to at least one operation descriptor located before the abort descriptor in the instruction stream comprises: enabling the scheduling module to feedback an abort message in response to the instruction stream executing to the abort descriptor; and In response to receiving the abort message, a feedback result corresponding to at least one operation descriptor located before the abort descriptor in the instruction stream is determined.

4. The method according to any one of claims 1 to 3, wherein: Each of the plurality of operation descriptors includes a first address identifier, and the method further includes: Before performing the verification operation on any one of the first number of instruction streams, storing the data to be processed in the target storage space; And wherein, for each of the multiple operation descriptors included in the instruction stream, enabling at least one operation module among the multiple operation modules to perform data processing for the operation descriptor comprises: enabling the at least one operation module to read a portion of the data to be processed corresponding to the operation descriptor in the data to be processed from a storage address corresponding to the first address identifier of the operation descriptor in the target storage space; and The at least one operation module is enabled to perform data processing for the operation descriptor using the portion of the to-be-processed data corresponding to the operation descriptor.

5. The method according to claim 4, wherein: Each of the at least one abort descriptor comprises a second address identifier, and the second address identifier can be used to indicate a storage address in the target storage space of a processing result corresponding to each of the at least one operation descriptor located before the abort descriptor in the instruction stream; And wherein, in response to the instruction stream being executed to the abort descriptor, determining the feedback result corresponding to at least one operation descriptor located before the abort descriptor in the instruction stream comprises: In response to the instruction stream executing to the abort descriptor, reading a processing result corresponding to each of the at least one operation descriptor from a storage address in the target storage space corresponding to the second address identifier of the abort descriptor; and According to the processing result corresponding to each operation descriptor in the at least one operation descriptor, a feedback result corresponding to the at least one operation descriptor is determined.

6. The method according to claim 4, wherein: The target storage space includes a storage space located in the chip.

7. The method according to any one of claims 1 to 3, wherein: The plurality of operation modules include at least two types of operation modules, and each of the plurality of operation descriptors includes a category identifier. And wherein, for each of the multiple operation descriptors included in the instruction stream, enabling at least one operation module among the multiple operation modules to perform data processing for the operation descriptor to obtain a processing result corresponding to the operation descriptor includes: At least one operation module of the same category among the multiple operation modules is enabled to perform data processing for the operation descriptor, wherein the category of the at least one operation module corresponds to the category identifier of the operation descriptor.

8. The method according to any one of claims 1 to 3, wherein: The first number is an arbitrary integer not less than 2, the first number of instruction streams includes a first instruction stream and a second instruction stream that are associated, the first instruction stream includes a pause instruction, and the second instruction stream includes a start flag; And wherein, the verification operation further includes: enabling the plurality of operation modules to suspend data processing for the first instruction stream in response to the first instruction stream executing the suspend instruction; and At least one of the plurality of operation modules is enabled to start data processing for the first instruction stream from an instruction next to the pause instruction in the first instruction stream in response to the second instruction stream executing to the start identifier.

9. The method according to any one of claims 1 to 3, wherein: Determining the first number of instruction streams includes: Obtaining a verification stimulus corresponding to the task to be verified, wherein the verification stimulus is compiled using a compiler corresponding to the chip; and Based on the verification stimulus, the first number of instruction streams is determined.

10. The method according to any one of claims 1 to 3, wherein: The simulation result corresponding to the at least one operation descriptor is obtained in advance by using software simulation.

11. A chip verification device, wherein: The chip includes a plurality of computing modules, and the device includes: a determining unit configured to determine a first number of instruction streams, wherein each instruction stream in the first number of instruction streams includes a plurality of operation descriptors and at least one abort descriptor, wherein each operation descriptor indicates a sub-instruction stream consisting of a plurality of instructions, and each abort descriptor indicates a triggering operation of a feedback result corresponding to at least one operation descriptor before the abort descriptor; and an execution unit, configured to perform a verification operation on any one of the first number of instruction streams, the execution unit comprising at least: an enabling subunit, configured to enable, for each of the plurality of operation descriptors included in the instruction stream, at least one operation module among the plurality of operation modules to perform data processing for the operation descriptor, so as to obtain a processing result corresponding to the operation descriptor; a determining subunit configured to determine, in response to the instruction stream being executed to the abort descriptor, a feedback result corresponding to at least one operation descriptor located before the abort descriptor in the instruction stream, wherein the feedback result is obtained according to a processing result corresponding to each operation descriptor in the at least one operation descriptor; and The comparison subunit is configured to compare the feedback result corresponding to the at least one operation descriptor with the simulation result corresponding to the at least one operation descriptor to determine the verification result of the chip.

12. The device according to claim 11, wherein The chip also includes a scheduling module. And wherein, the enabling subunit includes: The subunit is used to start the scheduling module by using the instruction stream, so that the scheduling module can enable at least one operation module corresponding to each operation descriptor of multiple operation descriptors included in the instruction stream to execute data processing for the operation descriptor.

13. The device according to claim 12, wherein: The determining subunit comprises: a subunit for enabling the scheduling module to feedback an abort message in response to the instruction stream executing to the abort descriptor; and A subunit for determining, in response to receiving the abort message, a feedback result corresponding to at least one operation descriptor located before the abort descriptor in the instruction stream.

14. The device according to any one of claims 11 to 13, wherein: Each of the plurality of operation descriptors includes a first address identifier, and the device further includes: A writing unit is configured to store the data to be processed into a target storage space before performing a verification operation on any one of the first number of instruction streams; And wherein, the enabling subunit includes: for enabling the at least one operation module to read a subunit of a portion of the data to be processed corresponding to the operation descriptor in the data to be processed from a storage address corresponding to the first address identifier of the operation descriptor in the target storage space; and A subunit for enabling the at least one operation module to use the portion of the to-be-processed data corresponding to the operation descriptor to perform data processing for the operation descriptor.

15. The device according to claim 14, wherein: Each of the at least one abort descriptor comprises a second address identifier, and the second address identifier can be used to indicate a storage address in the target storage space of a processing result corresponding to each of the at least one operation descriptor located before the abort descriptor in the instruction stream; And wherein, the determining subunit includes: a subunit for reading, in response to the instruction stream executing to the abort descriptor, a processing result corresponding to each of the at least one operation descriptor from a storage address in the target storage space corresponding to the second address identifier of the abort descriptor; and A subunit configured to determine a feedback result corresponding to the at least one operation descriptor according to a processing result corresponding to each of the at least one operation descriptor.

16. The device according to claim 14, wherein: The target storage space includes a storage space located in the chip.

17. The device according to any one of claims 11 to 13, wherein: The plurality of operation modules include at least two types of operation modules, and each of the plurality of operation descriptors includes a category identifier. And wherein, the enabling subunit includes: A subunit for enabling at least one operation module of the same category among the multiple operation modules to perform data processing for the operation descriptor, wherein the category of the at least one operation module corresponds to the category identifier of the operation descriptor.

18. The device according to any one of claims 11 to 13, wherein: The first number is an arbitrary integer not less than 2, the first number of instruction streams includes a first instruction stream and a second instruction stream that are associated, the first instruction stream includes a pause instruction, and the second instruction stream includes a start flag; And wherein, the execution unit further includes: A subunit configured to enable the plurality of operation modules to suspend data processing for the first instruction stream in response to the first instruction stream executing the suspend instruction; and A subunit for enabling at least one of the plurality of operation modules to start data processing for the first instruction stream from the next instruction of the pause instruction in the first instruction stream in response to the second instruction stream executing to the start identifier.

19. The device according to any one of claims 11 to 13, wherein: The determining unit comprises: Used to obtain a verification stimulus corresponding to the task to be verified, wherein the verification stimulus is a subunit compiled using a compiler corresponding to the chip; and The method is configured to determine the first number of subunits of the instruction stream based on the verification stimulus.

20. The device according to any one of claims 11 to 13, wherein: The simulation result corresponding to the at least one operation descriptor is obtained in advance by using software simulation.

21. An electronic device comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; in The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 10.

22. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-10.

23. A computer program product comprising a computer program, wherein: When the computer program is executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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