Three-dimensional memory and methods of making the same

Abstract

The present application relates to a kind of three-dimensional memory and its manufacturing method, the manufacturing method of the three-dimensional memory includes: forming first stack structure on substrate;Form first opening on the surface of first stack structure away from substrate;First opening is used as alignment mark to etch first stack structure, form first channel hole passing through first stack structure;Form sacrificial material layer in first channel hole, and form support layer in first opening;Form second stack structure on first stack structure, sacrificial material layer and support layer;Form second opening passing through second stack structure, second opening exposes support layer;Support layer is removed via second opening, so that, can avoid the problem that the upper and lower film layers of first opening are easily affected by stress from support layer in first opening due to the existence of first opening providing alignment mark on first stack structure, improve the reliability of three-dimensional memory.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor technology, and more specifically to a three-dimensional memory and its fabrication method. [Background Technology]

[0002] With the development of technology, the semiconductor industry is constantly seeking new production methods to enable each memory die in memory devices to have a greater number of memory cells. Among them, 3D NAND (three-dimensional NAND gate) memory has become a cutting-edge and highly promising memory technology due to its advantages such as high storage density and low cost.

[0003] Currently, in 3D NAND flash memory, a vertical stacking of multiple memory cells is generally used to achieve higher storage capacity in a smaller space, thereby improving the storage density and capacity of 3D NAND flash memory. A 3D NAND flash memory includes a substrate, a lower stack structure and an upper stack structure stacked on the substrate, and a channel structure that passes through the upper stack structure and the lower stack structure from top to bottom.

[0004] In existing 3D NAND memory fabrication processes, before forming the upper stack structure, openings are typically formed on the lower stack structure to provide alignment marks for subsequent process steps. However, the presence of these openings makes the upper and lower film layers susceptible to stress and deformation, thus affecting the reliability of the 3D NAND memory. [Summary of the Invention]

[0005] The purpose of this invention is to provide a three-dimensional memory and its manufacturing method, so as to avoid the problem that the upper and lower film layers of the opening provided with alignment marks on the lower stack structure are easily affected by stress and deformed, thereby improving the reliability of the three-dimensional memory.

[0006] To address the aforementioned problems, the present invention provides a method for fabricating a three-dimensional memory. The method includes: forming a first stack structure on a substrate; forming a first opening on a surface of the first stack structure facing away from the substrate; etching the first stack structure using the first opening as an alignment mark to form a first channel hole penetrating the first stack structure; forming a sacrificial material layer in the first channel hole and a support layer in the first opening; forming a second stack structure on the first stack structure, the sacrificial material layer, and the support layer; forming a second opening penetrating the second stack structure, the second opening exposing the support layer; and removing the support layer through the second opening.

[0007] Specifically, etching the first stacked structure using the first opening as an alignment mark to form a first channel hole penetrating the first stacked structure includes: sequentially forming a hard mask layer and a photoresist layer on the first stacked structure; partially recessing the hard mask layer and photoresist layer into the first opening along the direction towards the substrate; and forming a first groove on the surface of the hard mask layer and photoresist layer away from the substrate; providing a photomask and aligning the alignment mark on the photomask with the first groove; exposing and developing the photoresist layer according to the aligned photomask to obtain a patterned photoresist layer; etching the hard mask layer according to the patterned photoresist layer to obtain a patterned hard mask layer; and etching the first stacked structure according to the patterned hard mask layer to form a first channel hole penetrating the first stacked structure.

[0008] Before forming the first stack structure on the substrate, the method further includes: forming a third opening on the substrate, wherein a portion of the first stack structure is recessed into the third opening in the direction toward the substrate, and forming a second groove on the surface of the first stack structure away from the substrate; forming the first opening on the surface of the first stack structure away from the substrate specifically includes: etching the first stack structure with the second groove as an alignment mark to form the first opening, wherein the first opening extends in a direction perpendicular to the substrate, and the top end of the first opening is located in the first stack structure and does not penetrate the first stack structure.

[0009] The material of the support layer is the same as that of the sacrificial material layer.

[0010] The substrate includes a core region and a step region connected in a direction parallel to the substrate, and an edge region connected to the core region and / or the step region, wherein the orthographic projection of the first opening on the substrate is located within the edge region.

[0011] Specifically, forming a second opening through the second stack structure includes: forming a fourth opening on the surface of the second stack structure away from the substrate; and etching the second stack structure using the fourth opening as an alignment mark to form a second opening through the second stack structure.

[0012] The method for fabricating a three-dimensional memory further includes: forming a second channel hole through a second stack structure, the second channel hole exposing a sacrificial material layer; removing the sacrificial material layer through the second channel hole; and after removing the support layer and the sacrificial material layer, further including: forming a channel structure in the first channel hole and the second channel hole, as well as the first opening and the second opening.

[0013] The process includes, after removing the support layer, forming a dielectric layer in the first opening and the second opening.

[0014] To address the aforementioned problems, the present invention also provides a three-dimensional memory, comprising: a substrate; a first stack structure and a second stack structure stacked in a direction perpendicular to the substrate; a channel structure penetrating the first stack structure and the second stack structure; a first opening located on the first stack structure, the first opening extending in a direction perpendicular to the substrate, the top end of the first opening being located in the first stack structure and not penetrating the first stack structure; and a second opening penetrating the second stack structure, the second opening being connected to the first opening.

[0015] The substrate includes a core region and a step region connected in a direction parallel to the substrate, and an edge region connected to the core region and / or the step region, wherein the orthographic projection of the first opening on the substrate is located within the edge region.

[0016] The three-dimensional memory further includes a third opening on the substrate, and a portion of the first stack structure is recessed into the third opening in the direction toward the substrate, while a second groove is formed on the surface of the first stack structure away from the substrate.

[0017] The three-dimensional memory further includes a fourth opening located on the second stack structure, the fourth opening extending in a direction perpendicular to the substrate, the top end of the fourth opening being located in the second stack structure but not penetrating the second stack structure.

[0018] The three-dimensional memory also includes a dielectric layer located in the first opening and the second opening.

[0019] The three-dimensional memory also includes a support structure located in the first opening and the second opening, the support structure having the same structure as the channel structure.

[0020] The beneficial effects of this invention are as follows: Unlike the prior art, the three-dimensional memory and its fabrication method provided by this invention form a first stack structure on a substrate and a first opening on the surface of the first stack structure facing away from the substrate. Then, the first stack structure is etched with the first opening as an alignment mark to form a first channel hole through the first stack structure. Subsequently, a sacrificial material layer is formed in the first channel hole, and a support layer is formed in the first opening. Then, a second stack structure is formed on the first stack structure, the sacrificial material layer, and the support layer, and a second opening is formed through the second stack structure. The second opening exposes the support layer, and then the support layer is removed through the second opening. Thus, the presence of the first opening with alignment marks on the first stack structure can avoid the deformation of the upper and lower film layers of the first opening due to the stress from the support layer inside the first opening, which could lead to upward lifting, downward descent, or even peeling. This improves the reliability of the three-dimensional memory. [Attached Image Description]

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating the method for fabricating a three-dimensional memory provided in an embodiment of the present invention;

[0023] Figures 2a-2p This is a cross-sectional structural schematic diagram corresponding to the manufacturing process of the three-dimensional memory provided in the embodiments of the present invention.

Detailed Implementation Methods

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Furthermore, the directional terms used in this invention, such as [up], [down], [front], [back], [left], [right], [inside], [outside], and [side], are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding this invention, and not for limiting it. In the various figures, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the figures are not drawn to scale. Additionally, some well-known parts may not be shown in the figures.

[0026] This invention can be presented in various forms, some of which will be described below.

[0027] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the present invention. The specific process of the method for fabricating the three-dimensional memory is as follows:

[0028] Step S11: Form the first stack structure on the substrate.

[0029] The cross-sectional structure diagram after step S11 is shown below. Figure 2a As shown.

[0030] The substrate 11 can be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). The first stack structure 12 may include multiple alternating layers of a gate sacrificial layer 121 and a gate insulating layer 122 disposed in a direction Z perpendicular to the substrate 11. In specific implementations, methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and laser-assisted deposition can be used to form the gate sacrificial layer 121 and the gate insulating layer 122 of the first stack structure 12 on the substrate 11.

[0031] In the first stack structure 12, the gate sacrificial layer 121 can be made of silicon nitride, and the gate insulating layer 122 can be made of silicon oxide, thereby forming a silicon nitride / silicon oxide stack structure. In subsequent steps, the gate sacrificial layer 121 will be replaced by a replacement process and a conductive material (e.g., tungsten) will be filled in the same position to form a gate layer.

[0032] In a three-dimensional memory, the number of layers of the first stack structure 12 determines the number of memory cells it contains in the vertical direction (direction Z perpendicular to the substrate 11). For example, the number of layers of the first stack structure 12 can be 32, 64, 96, 128, etc., and the more layers the first stack structure 12 has, the higher the integration of the corresponding three-dimensional memory.

[0033] Specifically, the substrate 11 may include a device region C1 and an edge region C2 connected in a direction parallel to the substrate 11 (e.g., a first lateral direction X). The device region C1 may include a core region and a step region connected in the direction parallel to the substrate 11, and the edge region C2 may be connected to the core region and / or the step region. It is understood that the step region of the substrate 11 serves as an electrical connection region for providing word lines (gate layers), and can be used to form virtual channel structures and word line contacts in subsequent process steps. The core region of the substrate 11 can be used to form channel structures in subsequent process steps. The edge region C2 of the substrate 11 can be used to form scribe lines and provide electrical connection regions for peripheral circuits in subsequent process steps.

[0034] Step S12: Form a first opening on the surface of the first stack structure away from the substrate.

[0035] The structural diagram after step S12 is as follows: Figure 2b As shown.

[0036] The first opening 13 serves as an alignment mark during the subsequent etching process to form a channel hole penetrating the first stack structure 12. Specifically, the first opening 13 may extend in a direction Z perpendicular to the substrate 11, and the top end of the first opening 13 is located in the first stack structure 12 but does not penetrate the first stack structure 12. Specifically, the first opening 13 may be groove-shaped, and its cross-sectional shape may be a geometric shape such as a circle, square, rectangle, number shape, or letter shape.

[0037] It should be noted that the inventors have discovered that, according to existing 3D memory fabrication methods, the substrate typically has multiple zero marks for positioning in subsequent processing. However, the etching process for forming through-hole channels in the stacked structure requires the use of a hard mask layer. Furthermore, the relatively thick hard mask layer can obscure the zero marks on the substrate, making it impossible to accurately position the through-holes during the photolithography process.

[0038] Furthermore, it is understood that, compared to the scheme of using the zero-layer mark on the substrate as the alignment mark for etching to form the channel hole, this embodiment provides a first opening corresponding to the zero-layer mark on the substrate on the upper surface of the stack structure before covering the hard mask. This allows the position of the first opening to be conformally transmitted to the upper surface of the hard mask after covering the hard mask, thus forming a groove on the upper surface of the hard mask. In this way, during the etching process to form the channel hole through the stack structure, the problem of the photolithography process being unable to accurately locate the channel hole due to the excessive thickness of the hard mask layer that needs to be set on the upper surface of the stack structure can be effectively avoided.

[0039] In one specific embodiment, the orthogonal projection of the first opening 13 onto the substrate 11 can be located within the edge region C2 of the substrate 11 to avoid the first opening 13 occupying the storage space of the three-dimensional memory. Specifically, an anisotropic etching process (e.g., dry etching process) or an isotropic etching process (e.g., wet etching process) can be used to etch the first stack structure 12 located on the edge region C2 of the substrate 11 from top to bottom, forming the first opening 13 extending in the direction Z perpendicular to the substrate 11 and not penetrating the first stack structure 12.

[0040] Step S13: Etch the first stack structure with the first opening as the alignment mark to form a first channel hole through the first stack structure.

[0041] Specifically, step S13 can include:

[0042] Step S131: A first hard mask layer and a first photoresist layer are sequentially formed on the first stack structure. A portion of the first hard mask layer and the first photoresist layer is recessed into the first opening along the direction toward the substrate, and a first groove is formed on the surface of the first hard mask layer and the first photoresist layer away from the substrate.

[0043] The structural diagram after step S131 is as follows: Figure 2c As shown.

[0044] The first hard mask layer 14 and the first photoresist layer 15 are both conformally aligned with the surface of the first stacked structure 12 away from the substrate 11 (i.e., the upper surface), so that the first opening 13 located on the upper surface of the first stacked structure 12 is replicated on the surface of the first hard mask layer 14 and the first photoresist layer 15 away from the substrate 11 (i.e., the upper surface), thereby obtaining the first groove 16 located on the upper surface of the first hard mask layer 14 and the first photoresist layer 15.

[0045] Step S132: Provide a first photomask and align the alignment marks on the first photomask with the first groove.

[0046] Step S133: Expose and develop the first photoresist layer according to the aligned first photomask to obtain a patterned first photoresist layer.

[0047] The structural diagram after step S133 is as follows: Figure 2d As shown.

[0048] After exposure and development are completed, the pattern on the first photomask is transferred to the first photoresist layer 15, and the first photomask is removed after exposure and development are completed to facilitate its reuse. The patterned first photoresist layer 15 may include a first opening pattern, and the shape of the first opening pattern may be the same as the cross-sectional shape of the first channel hole to be formed in subsequent processes.

[0049] Step S134: Etch the first hard mask layer according to the patterned first photoresist layer to obtain the patterned first hard mask layer.

[0050] The structural diagram after step S134 is as follows: Figure 2e As shown.

[0051] The patterned first hard mask layer 14 may include a second opening pattern, and the shape of the second opening pattern may be the same as the first opening pattern on the patterned first photoresist layer 15. Furthermore, in specific implementations, an anisotropic etching process can be used, for example, a dry etching process (such as plasma etching, reactive ion etching, etc.), to etch away the first hard mask layer 14 exposed through the first opening pattern on the patterned first photoresist layer 15, thereby obtaining the patterned first hard mask layer 14.

[0052] Step S135: Etch the first stack structure according to the patterned first hard mask layer to form a first channel hole through the first stack structure.

[0053] The structural diagram after step S135 is as follows: Figure 2f As shown.

[0054] Specifically, the first stack structure 12 exposed by the second opening pattern on the patterned first hard mask layer 14 can be removed by etching from top to bottom, forming a first channel hole 17 that penetrates the first stack structure 12 and extends to the substrate 11, thereby exposing a portion of the substrate 11. In one specific embodiment, as... Figure 2f As shown, the first channel hole 17 can also penetrate the first stack structure 12 and extend into the interior of the substrate 11 to form a groove 11A on the substrate 11, thereby achieving sufficient etching to ensure that the substrate 11 can be exposed through the first channel hole 17. This also helps to increase the support effect of the channel structure formed in the first channel hole 17 on the first stack structure 12 in subsequent processes. Specifically, the first channel hole 17 extends into the interior of the substrate 11, and the bottom of the corresponding channel structure also extends into the interior of the substrate 11. Therefore, when there is a void region inside or below the first stack structure 12 (for example, a void region formed after removing the gate sacrificial layer 121), the channel structure can provide more effective support to the first stack structure 12, thereby reducing the problem of partial collapse or complete peeling off of the film layer in the first stack structure 12.

[0055] Furthermore, it is understood that during the etching process to form the first channel hole 17, the patterned first hard mask layer 14 has a certain etching selectivity relative to the first stack structure 12. The patterned first hard mask layer 14 and the first stack structure 12 can react with the etchant and be consumed simultaneously. Moreover, the thickness of the patterned first hard mask layer 14 should be large enough to ensure that it still has a certain thickness when the etching is completed.

[0056] In the above embodiment, after forming the first channel hole 17, the remaining first photoresist layer 15 and first hard mask layer 14 on the first stack structure 12 can be removed by dissolving or ashing in a solvent, so that the surface of the back substrate 11 of the first stack structure 12 and the first opening 13 located on the surface of the back substrate 11 of the first stack structure 12 are re-exposed.

[0057] Furthermore, it is understood that the method for forming the first channel hole 17 described above can also be modified in a variant embodiment by directly using a mask with alignment marks and an opening pattern to etch away the first stack structure 12 exposed through the opening pattern on the mask to form the first channel hole 17.

[0058] In this embodiment, during the etching process to form the first channel hole 17, the mask alignment is achieved by utilizing the first opening 13 on the upper surface of the first stack structure 12. Compared with the prior art scheme of using the zero-layer mark on the upper surface of the substrate to achieve mask alignment, this can effectively avoid the problem of large mask alignment error caused by the excessive thickness of the first hard mask layer 14 on the upper surface of the first stack structure 12.

[0059] Step S14: A sacrificial material layer is formed in the first channel hole, and a support layer is formed in the first opening.

[0060] The structural diagram after step S14 is as follows: Figure 2g As shown.

[0061] The material of the support layer 18 can be the same as or different from that of the sacrificial material layer 19. The materials of both the support layer 18 and the sacrificial material layer 19 can be any one of polycrystalline silicon, carbon, and tungsten.

[0062] Specifically, sacrificial material can be simultaneously deposited and filled in the first channel hole 17 and the first opening 13, and a chemical mechanical polishing process can be used to remove the sacrificial material located outside the first channel hole 17 and the first opening 13, to obtain a sacrificial material layer 19 in the first channel hole 17 and a support layer 18 in the first opening 13. The sacrificial material can be any one of polysilicon, carbon, and tungsten. Thus, after the sacrificial material fills the first channel hole 17 and the first opening 13, the first stack structure 12 can obtain a complete structural surface for subsequent formation of the second stack structure.

[0063] It is understandable that, compared to the approach of not filling the first opening 13 after forming the first channel hole 17, that is, not forming the support layer 18 in the first opening 13, this embodiment can effectively reduce the stress effect of the first opening 13 on the upper and lower film layers by forming the support layer 18 in the first opening 13 after forming the first channel hole 17.

[0064] In one specific embodiment, the material of the support layer 18 can be carbon. Furthermore, the inventors have found that, compared to using a support layer 18 made of common oxides or polycrystalline silicon, using a support layer 18 made of carbon material can further reduce the stress effect of the first opening 13 on its upper and lower film layers and effectively reduce costs. Moreover, carbon has the advantage of being easy to remove.

[0065] In an alternative embodiment, the first channel hole 17 and the first opening 13 may be filled in different process steps, that is, the sacrificial material layer 19 and the support layer 18 may be formed through different process steps.

[0066] Step S15: Form a second stack structure on the first stack structure, the sacrificial material layer, and the support layer.

[0067] The structural diagram after step S15 is as follows: Figure 2h As shown.

[0068] The second stack structure 20 may include multiple alternating layers of a gate sacrificial layer 201 and a gate insulating layer 202 disposed in a direction Z perpendicular to the substrate 11. Furthermore, the method for forming the second stack structure 20 may be the same as the method for forming the first stack structure 12 described above, and therefore will not be repeated here.

[0069] Step S16: Form a second opening through the second stack structure, the second opening exposing the support layer.

[0070] The structural diagram after step S16 is as follows: Figure 2j As shown.

[0071] Specifically, a second opening 21 can be formed by etching the second stack structure 20 from top to bottom, extending through the second stack structure 20 and reaching the surface of the first stack structure 12. The second opening 21 can communicate with the first opening 13, and the bottom of the second opening 21 can expose the top surface of the support layer 18 in the first opening 13.

[0072] In some embodiments, after the second stack structure 20 is formed on the first stack structure 12, the sacrificial material layer 19, and the support layer 18, as Figure 2iAs shown, a second channel hole 22 can also be formed through the second stack structure 20, exposing the sacrificial material layer 19. Furthermore, in specific implementations, the second channel hole 22 and the second opening 21 can be formed in the same etching process. Accordingly, step S16 can specifically involve forming both the second opening 21 and the second channel hole 22 through the second stack structure 20. That is, during the etching process of the second stack structure 20 to form the second opening 21, the second channel hole 22 is also formed by etching the second stack structure 20.

[0073] In one specific embodiment, such as Figure 2j and Figure 2k As shown, step S16 above can specifically include:

[0074] Step S161: A fourth opening 9 is formed on the surface of the second stack structure 20 away from the substrate 11.

[0075] Step S162: Etch the second stack structure 20 with the fourth opening 9 as the alignment mark to form a second opening 21 that penetrates the second stack structure 20.

[0076] Specifically, step S162 can include:

[0077] Step S1-1: A second hard mask layer 8 and a second photoresist layer 7 are sequentially formed on the second stack structure 20. A portion of the second hard mask layer 8 and the second photoresist layer 7 is recessed into the fourth opening 9 along the direction toward the substrate 11, and a third groove 6 is formed on the surface of the second hard mask layer 8 and the second photoresist layer 7 away from the substrate 11.

[0078] Step S1-2: Provide a second photomask and align the alignment marks on the second photomask with the third groove 6.

[0079] Step S1-3: Expose and develop the second photoresist layer 7 according to the aligned second photomask to obtain the patterned second photoresist layer 7.

[0080] Step S1-4: Etch the second hard mask layer 8 according to the patterned second photoresist layer 7 to obtain the patterned second hard mask layer 8.

[0081] Step S1-5: Etch the second stack structure 20 according to the patterned second hard mask layer 8 to form a second opening 21 through the second stack structure 20.

[0082] It should be noted that the above Figure 2j and Figure 2kThese are schematic diagrams showing the structures after steps S1-4 and S1-5 are completed, respectively. Furthermore, in some embodiments, during the etching of the second stack structure 20 to form the second opening 21, the second channel hole 22 is also formed simultaneously by etching the second stack structure 20.

[0083] Furthermore, in specific implementation, the specific implementation methods of steps S161, S162, S1-1, S1-2, S1-3, S1-4, and S1-5 can respectively refer to the specific implementation methods of steps S12, S13, S131, S132, S133, S134, and S135 in the preceding steps. Only steps S12, S13, S131, S132, S133, S134, and S135 need to be modified. The first opening 13, the first stack structure 12, the first hard mask layer 14, the first photoresist layer 15, the first photomask, the first groove 16, and the first channel hole 17 are replaced with the fourth opening 9, the second stack structure 20, the second hard mask layer 8, the second photoresist layer 7, the second photomask, the third groove 6, and the second opening 21, respectively. This yields the specific implementations of steps S161, S162, S1-1, S1-2, S1-3, S1-4, and S1-5, which will not be elaborated further.

[0084] Step S17: Remove the support layer through the second opening.

[0085] The structural diagram after step S17 is as follows: Figure 2l As shown.

[0086] After the support layer 18 is removed, the inner wall of the first opening 13 in the first stack structure 12 will be re-exposed.

[0087] Specifically, the support layer 18 can be removed by an ashing process. For example, the support layer 18 can be made of carbon material, and the carbon material support layer 18 can be removed by an ashing process. Furthermore, in one embodiment, a selective etchant can be used to selectively remove the support layer 18 relative to the first stack structure 12 and the second stack structure 20 via the second opening 21.

[0088] In some embodiments, such as Figure 2lAs shown, after forming the second opening 21 and the second channel hole 22 penetrating the second stack structure 20, the sacrificial material layer 19 can be removed through the second channel hole 22. Furthermore, in specific implementations, the sacrificial material layer 19 and the support layer 18 can be removed through the same process step (e.g., an ashing process step), effectively shortening the process flow. Accordingly, step S17 can specifically be: removing the support layer 18 through the second opening 21 and removing the sacrificial material layer 19 through the second channel hole 22. That is, during the removal of the support layer 18 located in the first opening 13, the sacrificial material layer 19 located in the first channel hole 17 is also removed simultaneously.

[0089] It should be noted that the inventors have discovered that, compared to the solution of not removing the support layer 18, this embodiment, by removing the support layer 18, can avoid the support layer 18 (for example, the support layer 18 made of carbon material) from easily deforming under high temperature during the subsequent annealing process, which would cause the upper and lower film structures of the support layer 18 to rise or fall, or even peel off, thus helping to reduce product defects.

[0090] In some embodiments, after removing the support layer 18, that is, after step S17, the process may further include:

[0091] Step A: Form a dielectric layer in the first opening and the second opening.

[0092] The structural diagram after step A is completed is as follows: Figure 2m As shown.

[0093] The dielectric layer 10 can be made of insulating materials such as silicon oxide. Specifically, insulating materials such as silicon oxide can be filled into the first opening 13 and the second opening 21 to form the dielectric layer 10.

[0094] In some embodiments, after removing the support layer 18 and the sacrificial material layer 19, as Figure 2n As shown, a channel structure 23 can be formed in the first channel hole 17 and the second channel hole 22. In order to improve the stability of the overall structure, the first opening 13 and the second opening 21 can also be filled. For example, the first opening 13 and the second opening 21 can be filled with an insulating material such as silicon oxide.

[0095] In some embodiments, in order to reduce process steps, such as Figure 2o As shown, while forming the channel structure 23 in the first channel hole 17 and the second channel hole 22, the channel structure 23 can also be formed in the first opening 13 and the second opening 21, so that the channel structure 23 can be formed and the first opening 13 and the second opening 21 can be filled in one process step.

[0096] Specifically, physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser-assisted deposition, and other methods can be used to sequentially deposit a storage functional layer and a channel layer on the inner walls of the first channel hole 17 and the second channel hole 22, as well as the inner walls of the first opening 13 and the second opening 21. A dielectric material (e.g., silicon oxide) is then filled into the first channel hole 17 and the second channel hole 22, and the first opening 13 and the second opening 21, to form an insulating filling layer. This results in a channel structure 23 with an insulating filling layer, a channel layer, and a storage functional layer located in the first channel hole 17 and the second channel hole 22, and a channel structure 23 with an insulating filling layer, a channel layer, and a storage functional layer located in the first opening 13 and the second opening 21. The aforementioned storage functional layer may include a charge blocking layer, a charge trapping layer, and a tunneling layer sequentially formed on the inner walls of the first channel via 17 and the second channel via 22, as well as on the inner walls of the first opening 13 and the second opening 21. Specifically, the materials of the charge blocking layer, the charge trapping layer, the tunneling layer, and the channel layer may be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, corresponding to the aforementioned channel structure as an "ONOP" structure. Furthermore, it is understood that although the storage functional layer exemplified here uses the ONO structure composed of the first oxide layer, the nitride layer, and the second oxide layer as an example structure, other possible structures are also possible.

[0097] In the above embodiments, before forming the first stack structure 12 on the substrate 11, as follows Figure 2p As shown, the above-mentioned method for manufacturing a three-dimensional memory may further include:

[0098] Step B: A third opening 11B is formed on the substrate 11, a portion of the first stack structure 12 is recessed into the third opening 11B in the direction toward the substrate 11, and a second groove 25 is formed on the surface of the first stack structure 12 away from the substrate 11.

[0099] Accordingly, step S12 can specifically include: etching the first stack structure 12 using the second groove 25 as an alignment mark to form a first opening 13. The first opening 13 extends in a direction perpendicular to the substrate 11, and the top end of the first opening 13 is located in the first stack structure 12 but does not penetrate the first stack structure 12. The third opening 11B is located in the upper surface of the substrate 11 and can extend in a direction Z perpendicular to the substrate 11 without penetrating the substrate 11. Specifically, the orthographic projection of the third opening 11B on the substrate 11 can be located within the edge region C2 of the substrate 11 to avoid the third opening 11B occupying the storage space of the three-dimensional memory.

[0100] Specifically, the third opening 11B can be in the shape of a groove, and its cross-sectional shape can be a geometric shape such as a circle, square, rectangle, number shape, or letter shape. Furthermore, each gate sacrificial layer 121 and gate insulating layer 122 in the first stack structure 12 is conformally fitted to the upper surface of the substrate 11 to replicate the pattern of the third opening 11B onto the upper surface of the first stack structure 12, thereby obtaining the second groove 25 located on the upper surface of the first stack structure 12.

[0101] It should be noted that, in some alternative embodiments, the substrate 11 may also include a zero-layer mark, and the first opening 13 may also be formed by etching the first stack structure 12 with the zero-layer mark of the substrate 11 as an alignment mark.

[0102] In some specific embodiments, after forming the above-described channel structure 23, the following may also be included:

[0103] Step S18: Form a gate slit that passes through the second stack structure 20 and the first stack structure 12 from top to bottom.

[0104] For example, the second stack structure 20 and the first stack structure 12 can be etched sequentially from top to bottom to form a gate line gap that runs through the first stack structure 12 and the second stack structure 20.

[0105] Step S19: Replace the gate sacrificial layer 121 of the first stack structure 12 and the gate sacrificial layer 201 of the second stack structure 20 with gate layers through the gate line gaps.

[0106] For example, the gate sacrificial layer 121 of the first stacked structure 12 and the gate sacrificial layer 201 of the second stacked structure 20 can be replaced by a replacement process, and conductive material (e.g., tungsten) can be filled in the same position to form the gate layer of the first stacked structure 12 and the gate layer of the second stacked structure 20.

[0107] In some embodiments, after S10, the gate layer obtained by replacement can be etched through the gate line gap to form a gap between the gate layer and the gate line gap. In subsequent processes, when the gate line gap is filled with insulating and / or conductive materials, the gap between the gate layer and the gate line gap is also filled with insulating and / or conductive materials.

[0108] Furthermore, following step S19 above, the following may also be included:

[0109] Step S20: Form a grid line slot structure in the grid line slots.

[0110] Specifically, a gate line slot structure can be formed by filling the gate line slots with an insulating material (e.g., an insulating material with a high dielectric constant such as silicon oxide, silicon nitride, or silicon oxynitride). In some alternative embodiments, a gate line slot structure with a common source electrode can also be obtained by filling the gate line slots with an insulating material (e.g., silicon oxide) as an insulating layer and a conductive material (e.g., tungsten) as a common source electrode.

[0111] Unlike existing technologies, the three-dimensional memory and its fabrication method provided by this invention form a first stack structure on a substrate and a first opening on the surface of the first stack structure facing away from the substrate. Then, the first stack structure is etched using the first opening as an alignment mark to form a first channel hole penetrating the first stack structure. Subsequently, a sacrificial material layer is formed in the first channel hole, and a support layer is formed in the first opening. Next, a second stack structure is formed on the first stack structure, the sacrificial material layer, and the support layer, and a second opening penetrating the second stack structure is formed. The second opening exposes the support layer, and the support layer is then removed through the second opening. Thus, the presence of the first opening with alignment marks on the first stack structure can avoid the deformation of the upper and lower film layers of the first opening due to stress from the support layer within the first opening, which could lead to upward lifting, downward sliding, or even peeling. This improves the reliability of the three-dimensional memory.

[0112] The three-dimensional memory fabricated according to the above-described method embodiments of the present invention is as follows: Figure 2n and Figure 2o As shown, the three-dimensional memory includes: a substrate 11; a first stack structure 12 and a second stack structure 20 stacked in a direction perpendicular to the substrate 11; a channel structure 23 penetrating the first stack structure 12 and the second stack structure 20; a first opening 13 located on the first stack structure 12, the first opening 13 extending in a direction perpendicular to the substrate 11, the top end of the first opening 13 located in the first stack structure 12 and not penetrating the first stack structure 12; and a second opening 21 penetrating the second stack structure 20, the second opening 21 communicating with the first opening 13.

[0113] In one embodiment, the substrate 11 may include a device region C1 and an edge region C2 connected in a direction parallel to the substrate 11 (e.g., a first lateral direction X). The device region C1 may include a core region and a step region connected in a direction parallel to the substrate 11. The edge region C2 may be specifically connected to the core region and / or the step region in the device region C1, and the orthographic projection of the first opening 13 on the substrate 11 may be located within the edge region C2.

[0114] In one embodiment, the three-dimensional memory may further include a third opening on the substrate 11, and a portion of the first stack structure 12 may be recessed into the third opening in the direction toward the substrate 11, while a second groove is formed on the surface of the first stack structure 12 away from the substrate 11.

[0115] In one embodiment, the three-dimensional memory may further include a fourth opening located on the second stack structure 20, the fourth opening may extend in a direction perpendicular to the substrate, the top end of the fourth opening may be located in the second stack structure and does not penetrate the second stack structure 20.

[0116] In one embodiment, the three-dimensional memory may further include a dielectric layer located in the first opening 13 and the second opening 21.

[0117] In one embodiment, the three-dimensional memory may further include a support structure located in the first opening 13 and the second opening 21 (that is, the channel structure 23 or the dielectric layer 10 located in the first opening 13 and the second opening 21 in the above method embodiment). Specifically, the support structure may have the same structure as the channel structure 23.

[0118] It should be noted that the various structures of the three-dimensional memory in this embodiment can refer to the specific implementation methods described in the above method embodiments, so they will not be repeated here.

[0119] Unlike existing technologies, the three-dimensional memory provided in this embodiment can avoid the problem of deformation caused by stress from the support layer inside the first opening due to the presence of the first opening with alignment marks on the first stack structure, which can lead to upward lifting, downward descent, or even peeling. This improves the reliability of the three-dimensional memory.

[0120] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A first stack structure is formed on the substrate; A first opening is formed on the surface of the first stack structure opposite to the substrate; The first stack structure is etched with the first opening as an alignment mark to form a first channel hole penetrating the first stack structure; A sacrificial material layer is formed in the first channel hole, and a support layer is formed in the first opening; A second stack structure is formed on the first stack structure, the sacrificial material layer, and the support layer; A second opening is formed through the second stack structure, the second opening exposing the support layer; The support layer is removed through the second opening.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The step of etching the first stack structure using the first opening as an alignment mark to form a first channel hole penetrating the first stack structure specifically includes: A hard mask layer and a photoresist layer are sequentially formed on the first stack structure. A portion of the hard mask layer and the photoresist layer are recessed into the first opening along the direction toward the substrate, and a first groove is formed on the surface of the hard mask layer and the photoresist layer away from the substrate. Provide a photomask and align the alignment marks on the photomask with the first groove; The photoresist layer is exposed and developed according to the aligned photomask to obtain the patterned photoresist layer. The hard mask layer is etched according to the patterned photoresist layer to obtain the patterned hard mask layer; The first stack structure is etched according to the patterned hard mask layer to form a first channel hole through the first stack structure.

3. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Prior to forming the first stack structure on the substrate, the method further includes: A third opening is formed on the substrate, a portion of the first stack structure is recessed into the third opening in the direction toward the substrate, and a second groove is formed on the surface of the first stack structure opposite to the substrate. The step of forming a first opening on the surface of the first stack structure opposite to the substrate specifically includes: The first stack structure is etched using the second groove as an alignment mark to form a first opening. The first opening extends in a direction perpendicular to the substrate, and the top end of the first opening is located in the first stack structure but does not penetrate the first stack structure.

4. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The material of the support layer is the same as that of the sacrificial material layer.

5. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The substrate includes a core region and a step region connected in a direction parallel to the substrate, and an edge region connected to the core region and / or the step region, wherein the orthographic projection of the first opening on the substrate is located within the edge region.

6. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The formation of the second opening penetrating the second stack structure specifically includes: A fourth opening is formed on the surface of the second stack structure opposite to the substrate; The second stack structure is etched using the fourth opening as an alignment mark to form a second opening that penetrates the second stack structure.

7. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The method for manufacturing the three-dimensional memory also includes: A second channel hole is formed through the second stack structure, the second channel hole exposing the sacrificial material layer; The sacrificial material layer is removed via the second channel hole; After removing the support layer and the sacrificial material layer, the process further includes: A channel structure is formed in the first channel hole and the second channel hole, as well as in the first opening and the second opening.

8. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, After removing the support layer, the process also includes: A dielectric layer is formed in the first opening and the second opening.

9. A three-dimensional memory, characterized in that, include: Substrate; A first stack structure and a second stack structure are stacked in a direction perpendicular to the substrate; A channel structure that runs through the first stack structure and the second stack structure; A first opening located on the first stack structure, the first opening extending in a direction perpendicular to the substrate, the first opening being an alignment mark, the top end of the first opening being located in the first stack structure and not penetrating the first stack structure; A second opening extends through the second stack structure, and the second opening is connected to the first opening.

10. The three-dimensional memory according to claim 9, characterized in that, The substrate includes a core region and a step region connected in a direction parallel to the substrate, and an edge region connected to the core region and / or the step region, wherein the orthographic projection of the first opening on the substrate is located within the edge region.

11. The three-dimensional memory according to claim 9, characterized in that, The three-dimensional memory also includes: A third opening is located on the substrate, and a portion of the first stack structure is recessed into the third opening in the direction toward the substrate, while a second groove is formed on the surface of the first stack structure opposite to the substrate.

12. The three-dimensional memory according to claim 9, characterized in that, The three-dimensional memory also includes: A fourth opening is located on the second stack structure, the fourth opening extends in a direction perpendicular to the substrate, the top end of the fourth opening is located in the second stack structure, and does not penetrate the second stack structure.

13. The three-dimensional memory according to claim 9, characterized in that, The three-dimensional memory also includes: The dielectric layer located in the first opening and the second opening.

14. The three-dimensional memory according to claim 9, characterized in that, The three-dimensional memory also includes: A support structure located in the first opening and the second opening, the support structure having the same structure as the channel structure.

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