Spintronic devices, memory cells, memory arrays, and read / write circuits

Abstract

This disclosure provides a spintronic device for integrated circuit technology, comprising: a bottom electrode; a spin-orbit coupling layer disposed on the bottom electrode; at least one pair of magnetic tunnel junctions disposed on the spin-orbit coupling layer; each magnetic tunnel junction comprising a free layer, a tunneling layer, and a reference layer disposed sequentially from bottom to top; the reference layers of the two magnetic tunnel junctions in each pair of magnetic tunnel junctions having opposite magnetization directions; and a top electrode disposed on the reference layer of each magnetic tunnel junction. This disclosure also discloses a memory cell, a memory array, and a read / write circuit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a spintronic device, a memory cell, a memory array, and a read / write circuit. Background Technology

[0002] Spin-orbit-moment magnetic random access memory (SOT-MRAM) uses a vertical spin current induced by current flowing through a heavy metal layer to flip the magnetization direction of the free layer. Depending on whether the free layer and reference layer are aligned parallel or antiparallel, low-resistivity and high-resistivity states can be achieved. SOT-MRAM also boasts high speed and high durability, enabling in-memory computing applications. However, traditional SOT-MRAM requires in-plane field assistance for flipping, which is detrimental to integration; furthermore, the tunneling magnetoresistivity (TMR) of magnetic tunnel junctions (MTJs) is relatively low, typically only reaching 100%-150%, which means that process variations can lead to a higher probability of misreads. Summary of the Invention

[0003] The main objective of this disclosure is to provide a spintronic device, memory cell, memory array, and read / write circuit with no off-field flipping and high read / write margin.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a spintronic device, comprising:

[0005] Bottom electrode;

[0006] A spin-orbit coupling layer is disposed on the bottom electrode;

[0007] At least one pair of magnetic tunnel junctions are disposed on the spin-orbit coupling layer. Each magnetic tunnel junction includes a free layer, a tunneling layer and a reference layer arranged sequentially from bottom to top. The reference layers of the two magnetic tunnel junctions of each pair of magnetic tunnel junctions are magnetized in opposite directions.

[0008] The top electrode is disposed on the reference layer of each of the magnetic tunnel junctions.

[0009] In one embodiment, each of the magnetic tunnel junctions has a string-like structure.

[0010] In one embodiment, the straight side of each magnetic tunnel junction forms a predetermined angle with the axis of the spin-orbit coupling layer along its length.

[0011] In one embodiment, the bottom electrode includes:

[0012] The first electrode is connected to the first end of the spin-orbit coupling layer;

[0013] The second electrode is connected to the second end of the spin-orbit coupling layer;

[0014] The first and second ends of the spin-orbit coupling layer are arranged opposite to each other.

[0015] In one embodiment, the spin-orbit coupling layer is made of a heavy metal material.

[0016] A second aspect of this disclosure provides a storage unit, including:

[0017] Spintronic devices as described in the first aspect;

[0018] A first transistor includes a first terminal, a second terminal, and a third terminal. The first terminal of the first transistor is connected to one end of the bottom electrode, the second terminal of the first transistor is connected to the write word line, the third terminal of the first transistor is connected to the bit line, and the other end of the bottom electrode is connected to the source line.

[0019] The second transistor includes a first terminal, a second terminal, and a third terminal. The first terminal of the second transistor is connected to the top electrode of one of the pair of magnetic tunnel junctions, the second terminal of the second transistor is connected to the read word line, and the third terminal of the second transistor is connected to the bit line.

[0020] The third transistor includes a first terminal, a second terminal, and a third terminal. The first terminal of the third transistor is connected to the other top electrode in the pair of magnetic tunnel junctions. The second terminal of the third transistor is connected to the read word line, and the third terminal of the third transistor is connected to the inverted bit line.

[0021] A third aspect of this disclosure provides a storage array, comprising: m write lines, m read lines, n source lines, and m rows and n columns of storage units, wherein the storage units are the storage units described in the second aspect of this disclosure, and m and n are both positive integers;

[0022] The bit lines of each of the memory cells located in the same column are connected to the same bit line, and the inverted bit lines of each of the memory cells located in the same column are connected to the same inverted bit line;

[0023] The write lines of each of the storage cells located in the same row are connected to the same write line, and the read lines of each of the storage cells located in the same column are connected to the same read line.

[0024] A fourth aspect of this disclosure provides a read / write circuit, including:

[0025] The storage array as described in the third aspect of the embodiments of this disclosure;

[0026] Bit line decoder for providing bit line operating voltages to the n bit lines and the n inverted bit lines;

[0027] A word line decoder is used to provide word line operating voltage to the m write word lines and the m read word lines;

[0028] A source-line decoder is used to provide bit-line operating voltage and induced current to the n source lines;

[0029] The read operation module is used to read the data stored in the storage array and perform logical operations on the data stored in the storage array.

[0030] In one embodiment, the read operation module includes:

[0031] A current-mode sensitive amplifier includes an input terminal, a reference terminal, and an output terminal. The input terminal of the current-mode sensitive amplifier is connected to the bit line through the bit line decoder, and the reference terminal of the current-mode sensitive amplifier is connected to the inverted bit line through the bit line decoder.

[0032] An adder includes an input terminal and an output terminal, wherein the input terminal of the adder is connected to the output terminal of the current-mode sensitive amplifier;

[0033] The register is connected to the output of the adder.

[0034] In one embodiment, the read / write circuit is used to binarize a neural network.

[0035] As can be seen from the above embodiments of this disclosure, the spintronic device, memory cell, memory array, and read / write circuit provided by this disclosure, on the one hand, can achieve deterministic magnetization reversal driven by unipolar current pulses without an external magnetic field. On the other hand, the reference layer magnetization directions of the two magnetic tunnel junctions in each pair of magnetic tunnel junctions are opposite, ensuring that the two magnetic tunnel junctions are always in opposite resistance states, achieving self-reference and improving read margin. Furthermore, the constructed memory array, combined with external circuitry, can realize matrix-vector multiplication operations. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the structure of a spintronic device provided in an embodiment of the present disclosure;

[0038] Figure 2 A top view of a spintronic device provided in an embodiment of this disclosure;

[0039] Figure 3 Magnetization reversal curve of a spintronic device provided in an embodiment of this disclosure;

[0040] Figure 4 Unipolar pulse synchronous flipping curve of a spintronic device provided in an embodiment of this disclosure;

[0041] Figure 5 A schematic diagram of a storage unit provided in an embodiment of this disclosure;

[0042] Figure 6 A schematic diagram of a storage array provided in an embodiment of this disclosure;

[0043] Figure 7 This is a schematic diagram of a read / write circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0044] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0045] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a spintronic device provided in an embodiment of the present disclosure. The spintronic device includes: bottom electrodes 101 and 104, a spin-orbit coupling layer 102 disposed on the bottom electrodes 101 and 104, at least one pair of magnetic tunnel junctions 103 disposed on the spin-orbit coupling layer 102, each magnetic tunnel junction 103 including a free layer 1031, a tunneling layer 1032 and a reference layer 1033 disposed sequentially from bottom to top, the reference layers 1033 of each pair of magnetic tunnel junctions 103 having opposite magnetization directions, and a top electrode 1034 disposed on the reference layer 1033 of each magnetic tunnel junction 103.

[0046] In one embodiment of this disclosure, the reference layer 1033 and the free layer 1031 are made of one or more ferromagnetic materials such as CoFeB and Co / Pt, which have perpendicular magnetic anisotropy. The spin-orbit coupling layer 102 is composed of one or more heavy metals such as Pt, Ta, and W. The bottom electrodes 101 and 104 and the top electrode 1034 are composed of metals such as Ti / Au, Ti / Pt, Cr / Au, and Ta / CuN. Furthermore, the tunneling layer 1032 is composed of materials such as MgO and Al2O3.

[0047] Please see Figure 2 , Figure 2 This is a top view of a spintronic device provided in an embodiment of the present disclosure.

[0048] In one embodiment of this disclosure, each magnetic tunnel junction 103 has a chordal structure. The straight side of each magnetic tunnel junction 103 forms a predetermined angle with the axis of the spin-orbit coupling layer 102 along its length. The asymmetrical shape of the magnetic tunnel junction 103 induces a certain shape anisotropy. Combined with the DM antisymmetric exchange effect, field-free deterministic flipping of the magnetic tunnel junction 103 can be achieved, and unipolar switching can be realized. When current flows through the spin-orbit coupling layer 102, a vertical spin current is generated due to the spin Hall effect of the heavy metal or the Rashaba effect at the interface, causing the free layer 1031 of the magnetic tunnel junction 103 to flip. Since the magnetization directions of the reference layers 1033 of the two magnetic tunnel junctions 103 are opposite, the two magnetic tunnel junctions 103 always store opposite resistive states.

[0049] In this disclosure, the straight sides of the two magnetic tunnel junctions 103 in a pair of magnetic tunnel junctions form a predetermined angle with the axis of the spin-orbit coupling layer 102 along its length. They can be the same or complementary, and this disclosure does not impose any restrictions on this.

[0050] Please see Figure 3 , Figure 3 This is a magnetization reversal curve of a spintronic device provided in an embodiment of this disclosure. A preset angle is set between a pair of magnetic tunnel junctions 103. The pulses were applied at angles of 45°, 60°, and 90° along the x-axis with a pulse width of 0.5 ns and a density of 2 × 10⁻⁶. 8 A / cm 2 The current pulses enabled the field-free deterministic flipping of a pair of magnetic tunnel junctions 103 synchronously.

[0051] Please see Figure 4 , Figure 4 This is a unipolar pulse synchronous flipping curve of a spintronic device provided in an embodiment of this disclosure. A preset angle is set between a pair of magnetic tunnel junctions 103. At an angle of 45°, four pulses with a width of 0.5 ns and a density of 2 × 10⁻⁶ are continuously applied along the x-axis. 8 A / cm 2 The unipolar current pulse enables the synchronous and repeated switching of the two magnetic tunnel junctions 103. The unipolar current pulse is easy to operate and simplifies the external drive circuit.

[0052] Please see Figure 5 , Figure 5 This is a schematic diagram of a storage unit provided according to an embodiment of the present disclosure. The storage unit includes: as shown in the diagram. Figure 1The spintronic device 604 shown includes: a first transistor 601, comprising a first terminal, a second terminal, and a third terminal; the first terminal of the first transistor is connected to the bottom electrode 101; the second terminal of the first transistor 601 is connected to the write word line WWL; the third terminal of the first transistor 601 is connected to the bit line BL; and the bottom electrode 104 is connected to the source line SL. A second transistor 602, comprising a first terminal, a second terminal, and a third terminal, has its first terminal connected to one of the top electrodes 1034 of a pair of magnetic tunnel junctions 103; its second terminal is connected to the read word line RWL; and its third terminal is connected to the bit line BL. A third transistor 603, comprising a first terminal, a second terminal, and a third terminal, has its first terminal connected to the other top electrode 1034 of a pair of magnetic tunnel junctions 103; its second terminal is connected to the read word line RWL; and its third terminal is connected to the inverted bit line / BL.

[0053] In this embodiment, 601 can be considered as a write control transistor, 602 and 603 as read control transistors, and 604 as a spintronic device. When a read operation is performed, the write word line WWL is pulled low, turning off the first transistor 601, and the read word line RWL is pulled high, turning on the second transistor 602 and the third transistor 603. Simultaneously, the source line SL is grounded, and current flows through the bit line BL and the reverse bit line / BL through a pair of magnetic tunnel junctions 103. The current on the bit line BL and the reverse bit line / BL flows into the current-mode sensitive amplifier CSA, reading the stored state of the spintronic device 604. When a write operation is performed, the write word line WWL is pulled high, turning on the first transistor 601, and the read word line RWL is pulled low, turning off the second transistor 602 and the third transistor 603. Simultaneously, the source line SL is grounded, and the current between the bit line BL and the source line SL flows through the current path of the spin-orbit coupling layer 102, flipping the resistance state of the magnetic tunnel junction 103, thus achieving the writing of the resistance state.

[0054] Please see Figure 6 , Figure 6 This is a schematic diagram of a storage array provided in an embodiment of the present disclosure. The storage array includes: m write word lines, m read word lines, n source lines, and m rows and n columns of storage cells. The storage cells are as follows: Figure 5 The storage cells shown are both positive integers, m and n. The bit lines of each storage cell in the same column are connected to the same bit line, and the inverted bit lines of each storage cell in the same column are connected to the same inverted bit line. The write word lines of each storage cell in the same row are connected to the same write word line, and the read word lines of each storage cell in the same column are connected to the same read word line.

[0055] Please see Figure 7 , Figure 7 This is a schematic diagram of a read / write circuit provided in an embodiment of the present disclosure. The read / write circuit includes:

[0056] like Figure 6 The storage array shown;

[0057] Bit line decoder, used to provide bit line operating voltage to n bit lines and n inverted bit lines;

[0058] A word line decoder is used to provide word line operating voltage to m write word lines and m read word lines;

[0059] Source line decoder, used to provide bit line operating voltage and induced current to n source lines;

[0060] The read operation module is used to read data stored in the storage array and perform logical operations on the data stored in the storage array.

[0061] In this embodiment, at the algorithm level, high and low impedance states are mapped to (+1, 0), respectively. When the current stage input is high, a multiplication result can be output based on the difference in current on bit line BL and the inverted bit line / BL, and then input into the adder and register. When the current stage input is low, no output is generated, i.e., the output is low. Through a series of multiplication and addition operations, matrix-vector multiplication can be implemented for binary neural networks.

[0062] In one embodiment, the read operation module includes: a current-mode sensitive amplifier with an input terminal, a reference terminal, and an output terminal; the input terminal of the current-mode sensitive amplifier is connected to a bit line via a bit line decoder, and the reference terminal of the current-mode sensitive amplifier is connected to an inverted bit line via a bit line decoder; an adder including an input terminal and an output terminal; the input terminal of the adder is connected to the output terminal of the current-mode sensitive amplifier; and a register connected to the output terminal of the adder.

[0063] Alternatively, the reference terminal of the current-mode sensitive amplifier can be connected to the bit line via a bit line decoder, and the input terminal of the current-mode sensitive amplifier can be connected to the inverted bit line via a bit line decoder. This disclosure does not limit this.

[0064] It should be noted that the functional modules in the various embodiments of this disclosure can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0065] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0066] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0067] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0068] The above is a description of a spintronic device, memory cell, memory array, and read / write circuit provided by the present invention. For those skilled in the art, based on the ideas of the embodiments of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A spintronic device, characterized in that, include: Bottom electrode; A spin-orbit coupling layer is disposed on the bottom electrode; At least one pair of magnetic tunnel junctions are disposed on the spin-orbit coupling layer. Each magnetic tunnel junction includes a free layer, a tunneling layer and a reference layer arranged sequentially from bottom to top. Each magnetic tunnel junction has a string-shaped structure. The straight side of each magnetic tunnel junction forms a preset angle with the axis of the spin-orbit coupling layer along its length. The reference layers of the two magnetic tunnel junctions in each pair of magnetic tunnel junctions have opposite magnetization directions. The top electrode is disposed on the reference layer of each of the magnetic tunnel junctions.

2. The spintronic device according to claim 1, characterized in that, The bottom electrode includes: The first electrode is connected to the first end of the spin-orbit coupling layer; The second electrode is connected to the second end of the spin-orbit coupling layer; The first and second ends of the spin-orbit coupling layer are arranged opposite to each other.

3. The spintronic device according to claim 1, characterized in that, The material of the spin-orbit coupling layer is a heavy metal material.

4. A storage unit, characterized in that, include: The spintronic device as described in any one of claims 1 to 3; A first transistor includes a first terminal, a second terminal, and a third terminal. The first terminal of the first transistor is connected to the bottom electrode, the second terminal of the first transistor is connected to the write word line, the third terminal of the first transistor is connected to the bit line, and the bottom electrode is connected to the source line. The second transistor includes a first terminal, a second terminal, and a third terminal. The first terminal of the second transistor is connected to the top electrode of one of the pair of magnetic tunnel junctions, the second terminal of the second transistor is connected to the read word line, and the third terminal of the second transistor is connected to the bit line. The third transistor includes a first terminal, a second terminal, and a third terminal. The first terminal of the third transistor is connected to the other top electrode in the pair of magnetic tunnel junctions. The second terminal of the third transistor is connected to the read word line, and the third terminal of the third transistor is connected to the inverted bit line.

5. A storage array, characterized in that, include: The system comprises m write lines, m read lines, n source lines, and m rows and n columns of storage units, wherein the storage units are as described in claim 4, and m and n are both positive integers. The bit lines of each of the memory cells located in the same column are connected to the same bit line, and the inverted bit lines of each of the memory cells located in the same column are connected to the same inverted bit line; The write lines of each of the storage cells located in the same row are connected to the same write line, and the read lines of each of the storage cells located in the same column are connected to the same read line.

6. A read / write circuit, characterized in that, include: The storage array as described in claim 5; Bit line decoder for providing bit line operating voltages to the n bit lines and the n inverted bit lines; A word line decoder is used to provide word line operating voltage to the m write word lines and the m read word lines; A source-line decoder is used to provide bit-line operating voltage and induced current to the n source lines; The read operation module is used to read the data stored in the storage array and perform logical operations on the data stored in the storage array.

7. The read / write circuit according to claim 6, characterized in that, The read operation module includes: A current-mode sensitive amplifier includes an input terminal, a reference terminal, and an output terminal. The input terminal of the current-mode sensitive amplifier is connected to the bit line through the bit line decoder, and the reference terminal of the current-mode sensitive amplifier is connected to the inverted bit line through the bit line decoder. An adder includes an input terminal and an output terminal, wherein the input terminal of the adder is connected to the output terminal of the current-mode sensitive amplifier; The register is connected to the output of the adder.

8. The read / write circuit according to claim 6 or 7, characterized in that, The read / write circuit is used to binarize the neural network.

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