Waveform construction using data point interpolation

Abstract

A method for constructing a waveform based on N sampled data captured at N consecutive time points, comprising, in part, applying the N sampled data to each of M delayed copies of a filter, K data points at a time, the filter including K taps, thereby generating NxM interpolated data. The waveform is then constructed based on the N sampled data and the NxM interpolated data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 62 / 867,462, filed June 27, 2019, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to communication systems and, more particularly, to systems and methods for constructing waveforms using interpolated data. Background Art

[0004] One technique for generating eye diagrams for binary signaling in a serializer / deserializer (SERDES) involves shifting the timing of the primary data slicer to provide the data necessary to form the eye diagram. Eye diagrams formed using analog-to-digital converter (ADC)-based receivers are inherently destructive because they require shifting and sampling the timing on the primary data path to generate the required statistics. This timing shift makes data samples susceptible to errors when scanning for the edges of the eye pattern in the eye diagram, rendering data samples for the primary data path unusable. During this process, normal link operation ceases.

[0005] According to another technique, additional circuitry (such as an auxiliary clipper with separate timing offset control) is used to generate the data used to form the eye diagram. Using an auxiliary clipper to generate the eye diagram requires equalization of the signal before clipping or sampling. To be non-destructive, such a technique would require a second ADC, a copy of all digital signal processor (DSP) equalization circuitry, and independent timing offset control, resulting in a significant increase in hardware cost. There remains a need for an improved method of forming an eye diagram. Summary of the Invention

[0006] According to one embodiment of the present invention, a method for constructing a waveform based on N sampled data captured at N consecutive time points includes, in part, applying the N sampled data to each of M delayed copies of a filter, K data points at a time, thereby generating N x M interpolated data, the filter including K taps. The waveform is then constructed using the N sampled data and the N x M interpolated data. It will be understood that K, N, and M are integers, and K is less than N.

[0007] In one embodiment, the waveform is an eye diagram that characterizes the quality of the communication link receiver. In one embodiment, the waveform defines an impulse response received by the communication link. In one embodiment, the filter has a finite length and is non-recursive. In one embodiment, the filter has a finite length and is recursive.

[0008] In one embodiment, the N data points are sampled at periodic time intervals. In one embodiment, the delay between the i-th and (i+1)-th delayed copies of the filter is the same as the delay between the (i+1)-th and (i+2)-th delayed copies of the filter. In one embodiment, the method further comprises, in part, storing filter coefficients in a read-only memory, the filter coefficients being associated with each of the delayed copies of the filter. In one embodiment, the N sampled data are composed of 2 Q Level definition, where Q is an integer equal to or greater than 2. In one embodiment, the method further includes, in part, applying the sampled data and the subset of NxM interpolated data to a filter to generate a second set of interpolated data.

[0009] A system configured to construct a waveform based on N sampled data captured at N consecutive time points includes, in part, a data collection unit, a filter having K taps, control logic, and waveform construction logic. The data collection unit is configured to collect the N sampled data. The control logic is configured to cause the filter to receive K data points of the N sampled data into each of M delayed copies of the filter, thereby generating N x M interpolated data. The waveform construction logic is configured to construct the waveform using the N sampled data and the N x M interpolated data. It will be understood that K, N, and M are integers, and K is less than N.

[0010] In one embodiment, the waveform is an eye diagram that characterizes the quality of a communication link receiver. In one embodiment, the waveform defines an impulse response received by the communication link. In one embodiment, the filter has a finite length and is non-recursive. In one embodiment, the filter has a finite length and is recursive. In one embodiment, the delay between the i-th and (i+1)-th delayed copies of the filter is the same as the delay between the (i+1)-th and (i+2)-th delayed copies of the filter.

[0011] In one embodiment, the system further comprises, in part, a read-only memory adapted to store filter coefficients associated with each of the delayed copies of the filter. Q The level is defined as Q, where Q is an integer equal to or greater than 2. In one embodiment, the filter is formed in a silicon substrate.

[0012] According to one embodiment of the present invention, a computer-readable storage medium includes, in part, instructions that, when executed by a processor, cause the processor to: apply N sampled data to each of M delayed copies of a filter, K data at a time, thereby generating N x M interpolated data, where the filter includes K taps. The instructions also cause the processor to construct a waveform using the N sampled data and the N x M interpolated data. It will be understood that K, N, and M are integers, and K is less than N. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of embodiments of the present disclosure. The accompanying drawings are intended to provide knowledge and understanding of the embodiments of the present disclosure and are not intended to limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0014] Figure 1 A Sinc function defining the characteristics of a filter for interpolating data according to one embodiment of the present disclosure is shown.

[0015] Figure 2 Exemplary data captured by the clipper at the receiver of the communication link is shown.

[0016] Figure 3 yes Figure 2 Histogram of the data shown.

[0017] Figure 4 Response characteristics of exemplary filters that may be used to generate timing offset and interpolated data according to one embodiment of the present disclosure are shown.

[0018] Figure 5 According to one embodiment of the present disclosure, Figure 4 The filter interpolates the data.

[0019] Figure 6 According to one embodiment of the present disclosure Figure 5 Histogram of the interpolated data shown in .

[0020] Figure 7 According to one embodiment of the present disclosure Figure 2 An example eye diagram generated from the data shown in .

[0021] Figure 8 Raised cosine functions with different beta parameters for interpolating data are shown according to one embodiment of the present disclosure.

[0022] Figure 9 An embodiment according to the present disclosure is shown Figure 7 The outlines of the areas near the top, middle, and bottom of the eye diagram.

[0023] Figure 10 An embodiment according to the present disclosure is shown Figure 7 A more detailed view of the outlines of the areas near the top, middle, and bottom of the eye diagram.

[0024] Figure 11A is a flow chart for generating an eye diagram according to one embodiment of the present disclosure.

[0025] Figure 11B An embodiment according to the present disclosure is shown Figure 11A A flowchart with more details of the multiple steps of the flowchart.

[0026] Figure 11C Data interpolated using a filter according to one embodiment of the present invention is shown.

[0027] Figure 12 is a simplified high-level block diagram of a receiver configured to provide interpolated data for waveform reconstruction according to one embodiment of the present invention.

[0028] Figure 13 Flowcharts illustrating various processes used during the design and fabrication of integrated circuits according to some embodiments of the present disclosure.

[0029] Figure 14 An abstract diagram is shown of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0030] There remains a need for an improved method for forming an eye diagram. According to embodiments of the present disclosure, systems, methods, and circuit devices for generating eye diagrams are described. In one embodiment, rather than capturing samples at many different points in time, the disclosed embodiments interpolate between data sampled at predefined regular time intervals to "fill in" data that nominally requires additional circuitry to acquire.

[0031] In one embodiment, at least one sample is generated per unit time interval (UI) to generate a complete, high-resolution eye diagram. As further described below, the data at the time points between the UI interval samples is generated by passing the data per unit UI through multiple interpolation processes to generate the eye diagram. Although the following description of the present invention is described with reference to collecting one data sample per UI to generate the eye diagram, it will be understood that embodiments of the present disclosure are equally suitable for using multiple samples per UI or using different numbers of samples at different times, resulting in a non-integer number of samples per UI to generate the eye diagram.

[0032] Embodiments of the present disclosure may be used to generate eye diagrams from data that has or has not been equalized by, for example, a digital signal processor (DSP). Furthermore, in addition to forming eye diagrams, embodiments of the present disclosure may also be used to assess the quality of a communication link by determining vertical blur thickness, horizontal blur thickness, crossover jitter, and many other characteristics of the communication link.

[0033] As described in detail below, embodiments of the present disclosure are adapted to interpolate between data samples collected at regular time intervals by a data sampler of a communication link to generate a data set that enables the creation of an accurate eye diagram. In other words, rather than capturing samples at intermediate points in time, embodiments of the present disclosure interpolate between already captured data samples to "fill in" data that would otherwise require additional circuitry. For example, assume that a clipper is adapted to sample data at regular unit time intervals (UI) of T1, T1+1*UI, T1+2*UI, ..., T1+N*UI. To generate the eye diagram, embodiments of the present disclosure interpolate between samples collected at T1, T1+1*UI, T1+2*UI...T1+N*UI to provide accurate estimates of the missing data at T1+1.25*UI, T1+2.25*UI...T1+(N+.25)*UI, rather than collecting data samples at times T1+1.25*UI, T1+2.25*UI...T1+(N+.25)*UI by, for example, a 1 / 4UI shift clipper. As used herein, the terms interpolation and fractional delay are considered interchangeable.

[0034] In one embodiment, data interpolation is performed using a finite length digital filter whose coefficients are stored in a storage medium such as an on-chip read-only memory (ROM).

[0035] Assume that the interpolation is performed by shifting the delay of the filter by the amount D. The Z-domain delay can be written as a discrete time Fourier transform (DTFT):

[0036] z=e -jω (1)

[0037] Where ω=2πfT, and T represents the sampling interval.

[0038] The delayed DTFT can be written as:

[0039] H(e jω )=e -jω D (2)

[0040] The inverse DTFT can be calculated as follows:

[0041]

[0042] Expression (3) can also be written as:

[0043]

[0044] It is understood that D is a fraction of UI. In one embodiment, to ensure infinite length, when and when it is zero elsewhere, the coefficient of h(n) is defined by sinc(nD).

[0045] Figure 1 A curve defined by the sinc(nD) function representing a filter comprising 11 taps is shown. The points indicated by solid circles on curve 10 occur at the corresponding time intervals -5*UI, -4*UI, -3*UI, -2*UI, -UI, 0UI, 2*UI, 3*UI, 4*UI, and 5*UI, respectively. If the filter coefficients are selected so that the sinc function is shifted by 0.3*UI time units, curve 12 is obtained, so that the points indicated by solid circles are sampled at the respective time intervals -5*UI, -4*UI, -3*UI, -2*UI, -UI, 0UI, 2*UI, 3*UI, 4*UI, and 5*UI.

[0046] from Figure 1 As can be seen, the function sinc(nD) has oscillating and decaying tap values ​​in which the side lobes decay slowly. In some embodiments, relatively long filters are used for interpolation. It will be appreciated that the intervals over which the interpolation process is applied need not be limited to 1 UI. Any integer multiple of UI, fractions of UI, or integer multiples other than fractions of UI may be used over a shorter or wider range. It will also be appreciated that the range over which interpolation is performed need not be symmetrical nor need it include a time point defined by zero.

[0047] Assume the filter has K taps. Further assume we want M delay quantization steps per UI. Delay quantization determines the horizontal resolution of the eye diagram. As you can see, a larger value for M results in a greater number of interpolations, leading to more and finer details in the eye diagram.

[0048] Thus, for a filter with K taps and M quantization steps per UI, the filter defined above by h(n) requires K*M coefficients. To perform a shift of delay amount D, K samples of h(1+D), h(M+1+D), h(2*M+1+D), ... are selected as filter coefficients. By varying the filter taps, different delays can be achieved.

[0049] For example, the clipper generates 1000 data points sampled at regular time intervals, which are separated by 1 UI. As described above, according to an embodiment of the present disclosure, it is desired to determine data at 0.25 UI, 0.5 UI, and 0.75 UI by interpolation. It is also desired that the selected filter has 13 taps. To this end, the filter function is delayed by 0.25 UI to generate associated filter coefficients for the 13 taps. The filter coefficients associated with the 0.25 UI delay are then applied to 13 of the 1000 data points at a time to generate the 1000 data points generated by the first set of filters. The 1000 points generated by the first set of filters are then interpolated to generate data at 0.25 UI. Next, the filter function is delayed by 0.5 UI to generate another set of filter coefficients, which are applied to 13 of the 1000 samples at a time to generate 1000 data points generated by the second set of filters. The 1000 points generated by the second set of filters are then interpolated to generate data at 0.5 UI. Next, the filter function is delayed by 0.75 UI to generate another set of filter coefficients, which are applied to 13 data points in the 1000 samples at a time to generate the 1000 sample points generated by the third set of filters. The 1000 points generated by the third set of filters are then interpolated to generate the data at 0.75 UI.

[0050] Since the filter function and its characteristics are known in advance, the filter coefficients for each desired delay value can also be pre-generated and stored in a memory such as a ROM. Specifying the delay amount provides the address where the corresponding filter coefficients are stored. The horizontal resolution of the eye diagram can be changed by selecting the time delay for the interpolation process. The step size between the time delays can be uniform or non-uniform. The data samples can be provided by an ADC or any other suitable circuit device.

[0051] According to one embodiment, an eye diagram can be generated as described below. First, a set of data samples are collected and stored in a storage array, such as a static random access memory (SRAM) that can be on-chip or off-chip. Next, a desired time is selected for the interpolation process. The captured data is then passed through an interpolation process to generate a set of time-shifted interpolated data samples representing the signal at the desired time. Thereafter, a histogram of the data samples from the data samples so generated is stored in a matrix column corresponding to the desired time. The histogram is the distribution of voltage samples at the desired time point. The voltage samples are stored in the matrix rows. The above process is then repeated until data covering the desired time points for the selected time interval is generated. The data in the matrix columns and rows indicating time and voltage, respectively, is then used to generate an eye diagram. It will be understood that embodiments of the present disclosure are also suitable for non-uniform sampling to provide more detail in certain areas of the eye diagram.

[0052] In one embodiment, the interpolation process can be performed by a class of filters commonly referred to as fractional delay filters (FDFs). Such filters can be implemented in a variety of forms, such as finite impulse response (FIR), Farrow structures, or polyphase representations. It will be appreciated that embodiments of the present disclosure are not limited to any particular type of filter.

[0053] In one embodiment, the FDF is used to generate an oversampled copy of the interpolation filter function (i.e., M samples per UI), which is characterized by a truncated sinc or raised cosine filter function spanning an N*UI range. The oversampling of the filter defines the interpolation step size. Interpolation includes selecting K M-spaced taps to filter the data. For example, the first interpolation filter may include filter taps 1, M+1, 2*M+1... In order to interpolate at a 1 / M*UI time interval, the captured data will be filtered using a filter that includes filter taps 2, M+2, 2*M+2... Repeat this process until the desired interval is covered.

[0054] According to another embodiment, to scan the eye using the FDF, a single interpolation filter can be used that interpolates the desired time step. In such an embodiment, a first set of interpolated data is generated by filtering the captured data. A second set of interpolated data is generated by filtering the first set of interpolated data using the same filter and the same filter coefficients. Thus, the second set of interpolated data is delayed by one time step from the first set of interpolated data, or by two time steps from the initially captured data. This process can be repeated until the entire time interval used for interpolation has been covered.

[0055] In another embodiment, the interpolation process can be implemented algebraically, such as by using Lagrange interpolation or spline interpolation. For example, a polynomial function can be used to perform the interpolation. The interpolation point changes as the polynomial coefficients change. It will be appreciated that any interpolation technique can be used to form the eye diagram according to embodiments of the present disclosure.

[0056] Figure 2 4-level pulse amplitude modulation (PAM4) data captured by a clipper and quantized by an exemplary multi-bit ADC is shown. Four expected signal levels can be seen near ±10 and ±30 millivolts. Figure 3 yes Figure 2 Histogram of the data shown in . Figure 4 The response characteristic of an exemplary filter that can be used to generate timing offsets (delays) with a granularity of 1 / 64 of a UI is shown - that is, the filter has 64 taps per UI and spans 12 UIs. The filter characteristic is rounded to The raised cosine function is limited.

[0057] Figure 5 Shown Figure 4 The subset of filter coefficients that will be used to define the delay by UI 20 / 64. If UI 32 / 64 is defined as the zero time point, the shift corresponds to UI 12 / 64. Figure 6 is a histogram of the interpolated data samples at a time offset of -12 / 64 from the center. Figure 7 is based on Figure 2 An example of an eye diagram created from the data shown, and using the interpolation process across 1UI as described above and referring to Figures 2 to 6 Further shown.

[0058] As mentioned above, in some embodiments, a raised cosine filter function is used for interpolation defined as follows:

[0059] otherwise

[0060] like Figure 4 As shown, the raised cosine filter includes a rounding parameter β, which determines how quickly the side lobes disappear. Figure 8 Curves 310, 320, 330 and 340 illustrate the raised cosine functions defined above for parameter values ​​of 0, 0.25, 0.5 and 1, respectively. In one example, a rounding parameter β value of 0.8 is used.

[0061] In addition to generating eye diagrams, embodiments of the present disclosure may be used to generate measurements of eye height and eye width from a matrix storing eye diagram data. Figure 9 The diamond curves 410, 420 and 430 show the confidence level of 97% and the bit error rate of 1e-4.028 respectively. Figure 7 Contours of the areas near the top, middle, and bottom of the eye diagram are shown. Confidence levels and bit error rates are based on the number of points captured to generate the eye diagram. In some embodiments, eye height can be calculated at each interpolated point along the x-axis to create a more detailed view of the inner eye contour. Figure 10 Curves 510, 520, and 530 respectively show the results at a 97% confidence level and a bit error rate of 1e-4.028as when the eye height is calculated at each interpolated point along the x-axis. Figure 7 Contours of the areas near the top, middle, and bottom of the eye diagram are shown. The confidence level and bit error rate are based on the number of points captured to generate the eye diagram.

[0062] Figure 11AFIG6 is a flowchart 600 for generating an eye diagram according to one embodiment of the present disclosure. At 602, a time offset (time_offset) defined by an initial time (time_init), a time step (time-step), and an end time (time_end) is defined. At 604, an interpolation process is selected. At 608, the interpolation process is performed using the data set collected at 606 and the time offset defined at 602.

[0063] At 610, a histogram of the interpolated data is generated and stored in memory corresponding to the columns of the matrix (eye_matrix) defined by the time offset. At 612, the time offset is compared to the end time. If the time offset is less than the end time, the process moves to 602 to increase the time step and repeat the interpolation. If the time offset is not less than the end time, the process is terminated.

[0064] Figure 11B yes Figure 11A A more detailed view of the flowchart shown. At 1102, N data points sampled at different times are captured. The times at which the samples are captured may or may not occur at the end of a regular time interval. At 1104, the N data samples are then applied, K data points at a time, to a filter having K taps and shifted by a first delay to generate a first set of N interpolated data. Next, at 1106, the filter delay shift is increased. At 1108, the N data samples are applied, K data points at a time, to the delay-shifted filter to generate another set of N interpolated data. If, at 1110, a determination is made that the filter has been shifted by all desired delays, the set of N interpolated data is used along with the sampled data to generate an eye diagram. At 1110, if it is determined that the filter has not been shifted by all desired delays, the process returns to 1106 and is repeated.

[0065] Figure 11C Seven exemplary data samples 22, 24, 26, 28, 30, 32, and 34 captured from analog waveform 80 are shown, identified by circles. According to one exemplary embodiment, a filter having three taps is used to generate interpolated data, identified by triangles. Arrows C1, C2, and C3 represent the filter coefficients applied to data samples 22, 24, and 26 to generate interpolated data 40. The length of the arrows represents the relative weighting of the filter coefficients. Similarly, arrows C4, C5, and C6 represent the filter coefficients applied to data samples 28, 30, and 32 to generate interpolated data 42. It will be appreciated that the remaining interpolated data is generated in the same manner.

[0066] Figure 12FIG. 800 is a simplified high-level block diagram of a receiver 800 according to one embodiment of the present disclosure, the receiver 800 being configured to provide interpolated data for generating, for example, an eye diagram, impulse response, etc. Data received by the receiver is delivered to an analog processing unit 802, the analog processing unit being adapted to provide functions such as impedance matching, signal equalization, and variable gain amplification, or to pass the received signal to an analog-to-digital converter (ADC) 804. The analog-to-digital converter (ADC) 804 is adapted to convert the analog output signal of the analog processing unit 802 into a digital signal using a clock signal supplied by a clock source 806.

[0067] The digital signal processor (DSP) 806 is adapted to perform one or more of digital equalization, feedforward equalization, and decision feedback equalization and other functions on the data samples supplied by the ADC 804 using the clock signal supplied by the clock source 806. The clock recovery unit 810 is adapted to recover a clock signal from the data supplied by the DSP 806 and supply the recovered clock signal to the clock source 806 for synchronization. The data supplied by the DSP 806 can be sent to the upper layer of the communication link via an interface 812.

[0068] The data sampled by the ADC 804 is also delivered to a data collection unit 852 of a waveform reconstruction unit 850. The data collection unit 852 can be a static random access memory (SRAM) or any other data storage medium. The control logic 854 is adapted to select filter coefficients associated with a given time offset and cause the filter 856 to filter the data stored in the data collection unit 852 using the selected filter coefficients to generate interpolated data. For each time offset, the waveform reconstruction logic 858 is adapted to generate a histogram based on the interpolated data when indicated by the control logic 803 to create an eye diagram 86o. The waveform reconstruction logic 858 is adapted to generate an impulse response based on the interpolated data for each offset when so indicated by the control logic 803.

[0069] In one embodiment, where interpolation is performed by a filter having a response characteristic h(n) of K*M tap lengths to generate an eye diagram, an initial timing offset D is first defined. A subset of the filter coefficients can be generated for K sub-samples by time shifting as described above. Accordingly, D has a range defined by 0 <= D < M. Then the data is filtered using one of M interpolation filters, each of the interpolation filters including K samples at h(1+D), h(2+D), h(3+D),... h(K+D). Next, a probability density function is generated for the eye diagram at the timing offset D. Thereafter, D is incremented by one time step and the process is repeated.

[0070] In some embodiments, before or after applying digital signal processing (DSP) operations in the receiver, interpolation can be used to form a densely sampled impulse response for the channel. The impulse response can then be plotted and / or analyzed to determine channel quality and equalization effectiveness. The impulse response can be generated by using a filter with a tap interval equal to the interpolation interval and adjusting the filter using a technique called system identification. To this end, the transmitted data symbols (ideal symbols) are first recovered from the captured data. The filter is then adjusted so that when the ideal samples are applied to the adjusted filter, the output of the filter matches the captured data. Therefore, the adjusted filter becomes a channel model from the transmitter to the receiver. This filter does not need to have a set length and is not limited by the method of performing interpolation.

[0071] According to another embodiment, the impulse response is obtained from the correlation between what is considered to be the current time sample and an earlier or later sample. Without interpolation, the granularity of the impulse response is limited to 1 point per UI. With interpolation, as described herein, the granularity of the impulse response can be increased by a factor of M, where M is the oversampling rate of the interpolation filter. A finer-grained impulse response can be equivalently obtained by first obtaining a 1-point per UI impulse response and convolving that response with a full (K*M) interpolation filter.

[0072] In one embodiment, the impulse responses generated as described above are used to generate a noise-free eye diagram to account for only intersymbol interference. This can be achieved by passing an ideal data symbol through one of the high-resolution impulse responses generated as described above. Using the recovered symbols mentioned above, the impact of jitter and noise on the received signal quality can be determined. In one embodiment, as described above, this can be achieved by comparing (e.g., by superposition, differentiation, etc.) a reconstructed analog waveform generated from the data capture with an analog waveform constructed from the impulse responses and recovered symbols.

[0073] In one embodiment, the data capture can be masked to retrieve specific bit patterns (e.g., individual bits or Nyquist patterns). This masking can be done on the die, where only the desired bits are collected. Masking can also be performed by filtering the captured data and creating a histogram using only the desired bits.

[0074] Figure 14A set of example processes 700 used during the design, verification, and manufacture of an article of manufacture, such as an integrated circuit, is illustrated to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term "EDA" stands for the term "electronic design automation." The processes begin by creating a product concept 710 using information provided by a designer, which is transformed to create a manufactured product using a set of EDA processes 712. When the design is complete, the design is taped out 734, which means that the artwork (e.g., geometric pattern) of the integrated circuit is sent to manufacturing equipment to produce a mask set, which is then used to manufacture the integrated circuit. After tapeout, the semiconductor die is manufactured 736, and packaging and assembly processes 738 are performed to produce the completed integrated circuit 740.

[0075] The specification of a circuit or electronic structure can range from low-level transistor material layout to high-level description languages. High levels of abstraction can be used to design circuits and systems using hardware description languages ​​("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be converted to a logic-level register transfer level ("RTL") description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of abstraction adds more useful detail to the design description, for example, more detail about the modules that comprise the description. Abstract descriptions at lower levels of abstraction can be computer-generated, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of abstraction that is used to specify a more detailed description is SPICE, which is used for detailed descriptions of circuits with many analog components. The descriptions at each level of abstraction can be used by the corresponding tools for that layer (e.g., formal verification tools). The design process can use Figure 14 The sequence depicted in the .description of the process is enabled by an EDA product (or tool).

[0076] During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0077] During logic design and functional verification 716, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, components of a circuit can be verified to generate outputs that match the requirements of the specifications of the circuit or system being designed. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, specialized systems of components called "emulators" or "prototyping systems" are used to accelerate functional verification.

[0078] During synthesis and design for testing 718, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit operates according to the specified design during manufacturing. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the completed integrated circuit can be tested to verify that the integrated circuit meets the specifications.

[0079] During netlist verification 720, the netlist is checked for consistency with timing constraints and correspondence with HDL code.During design planning 722, an overall floorplan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0080] During layout or physical implementation 724, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connecting circuit components through multiple conductors) are performed, and selection of cells from a library to implement specific logic functions can be performed. As used herein, the term "cell" can specify a group of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are implemented as physical structures and implemented in simulations. Parameters, such as size, are specified for the selected cells (based on "standard cells"), and the parameters are made accessible in a database for use by EDA products.

[0081] During analysis and extraction 726, circuit functionality is verified at the layout level, which allows for refinement of the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, and lithography constraints, are correct, and that the circuit functionality matches the HDL design specifications. During resolution enhancement 730, the layout geometry is transformed to improve the fabrication of the circuit design.

[0082] During tape-out, data is created for the production of lithographic masks (after applying lithographic enhancements where appropriate).During mask data preparation 732, the "tape-out" data is used to produce lithographic masks, which are used to produce finished integrated circuits.

[0083] Computer systems (such as Figure 14 The storage subsystem of the computer system 900) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and physical and logical design products that use the libraries.

[0084] Figure 14 An example machine of computer system 900 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0085] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Furthermore, while a single machine is shown, the term "machine" should also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0086] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

[0087] The processing device 902 represents one or more processors, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 902 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 902 may be configured to execute instructions 926 for performing the operations and steps described herein.

[0088] The computer system 900 may also include a network interface device 908 for communicating over a network 920. The computer system 900 may also include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generating device 916 (e.g., a speaker), a graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

[0089] The data storage device 918 may include a machine-readable storage medium 924 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methodologies or functionality described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during execution by the computer system 900, with the main memory 904 and the processing device 902 also constituting machine-readable storage media.

[0090] In some implementations, the instructions 926 include instructions for implementing functionality corresponding to the present disclosure. Although the machine-readable storage medium 924 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine and processing device 902 to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0091] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. These operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0092] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise stated, as will be apparent from this disclosure, it should be understood that throughout this specification certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0093] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or the apparatus may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0094] The algorithms and displays proposed herein are not inherently related to any particular computer or other device. Various other systems can be used together with the programs taught herein, or it may prove convenient to construct more specialized equipment to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be understood that various programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0095] The present disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0096] In the foregoing disclosure, the implementation of the present disclosure has been described with reference to its specific example implementation. It is apparent that various modifications may be made to these implementations without departing from the scope of the embodiments of the present disclosure as set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the accompanying drawings, and identical elements are marked with the same numerals. Therefore, the present disclosure and the accompanying drawings should be considered in an illustrative rather than a restrictive sense.

Claims

1. A method for constructing a waveform based on N sampled data captured at N consecutive time points, the method comprising: applying K data of the N sampled data at a time to each of M delayed copies of a filter, thereby generating N×M interpolated data, the filter comprising K taps, wherein values ​​of the K taps associated with the i-th delayed copy of the filter are determined by shifting a function characterizing the filter by a delay between the i-th delayed copy of the filter and the i-1-th delayed copy of the filter, where i is an integer ranging from 1 to M; and The waveform is constructed using the N sample data and the N×M interpolated data, where K, N, and M are integers, and where K is less than N.

2. The method of claim 1, wherein the waveform is an eye diagram, the eye diagram characterizing the quality of a communication link receiver.

3. The method of claim 1, wherein the waveform defines an impulse response received by a communication link. The method of claim 1 , wherein the filter has a finite length and is non-recursive. The method of claim 1 , wherein the filter has a finite length and is recursive. The method according to claim 1 , wherein the N sampled data are sampled at periodic time intervals.

7. The method of claim 1, wherein the delay between the i-th delayed copy and the (i+1)-th delayed copy of the filter is the same as the delay between the (i+1)-th delayed copy and the (i+2)-th delayed copy of the filter.

8. The method according to claim 1, further comprising: Filter coefficients are stored in read-only memory, the filter coefficients being associated with each of the delayed copies of the filter.

9. The method according to claim 1, wherein the N sample data are composed of 2 Q Level definition, where Q is an integer equal to or greater than 2.

10. The method according to claim 1, further comprising: The sampled data and the subset of the NxM interpolated data are applied to the filter to generate a second set of interpolated data.

11. A system configured to construct a waveform from N sampled data captured at N consecutive time points, the system comprising: A data collection unit, adapted to collect the N sampled data; A filter including K taps; control logic configured to cause the filter to receive K data points of the N sampled data at a time into each of M delayed copies of the filter, thereby generating N×M interpolated data, wherein values ​​of the K taps associated with the i-th delayed copy of the filter are determined by shifting a function characterizing the filter by a delay between the i-th delayed copy of the filter and the i-1-th delayed copy of the filter, where i is an integer ranging from 1 to M; as well as The waveform construction logic is configured to construct the waveform using the N sampled data and the N×M interpolated data, wherein K, N, and M are integers, and wherein K is less than N.

12. The system of claim 11, wherein the waveform is an eye diagram, the eye diagram characterizing the quality of a communication link receiver.

13. The system of claim 11, wherein the waveform defines an impulse response received by a communication link.

14. The system of claim 11, wherein the filter has a finite length and is non-recursive.

15. The system of claim 11, wherein the filter has a finite length and is recursive.

16. The system of claim 11, wherein the delay between the i-th delayed copy and the (i+1)-th delayed copy of the filter is the same as the delay between the (i+1)-th delayed copy and the (i+2)-th delayed copy of the filter.

17. The system of claim 11, further comprising: A read-only memory is adapted to store filter coefficients associated with each of the delayed copies of the filter.

18. The system according to claim 11, wherein the N sample data are composed of 2 Q Level definition, where Q is an integer equal to or greater than 2.

19. The system of claim 11, wherein the filter is formed in a silicon substrate.

20. A computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to: applying K data of N sampled data at a time to each of M delayed copies of a filter, thereby generating N×M interpolated data, the filter comprising K taps, wherein values ​​of the K taps associated with the i-th delayed copy of the filter are determined by shifting a function characterizing the filter by a delay between the i-th delayed copy of the filter and the i-1-th delayed copy of the filter, where i is an integer ranging from 1 to M; and A waveform is constructed using the N sampled data and the N×M interpolated data, where K, N, and M are integers, and where K is less than N.

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