A method and system for improving system IOPS

Abstract

The present invention discloses a method and a system for improving the system IOPS. Among them, the method includes: adopting a mode of an 8-core central processing unit for the solid-state drive system, each central processing unit corresponding to a memory flash channel, and each memory flash channel operating independently without being affected by the operations of other memory flash channels. At the same time, the 8-core central processing units can cooperate when needed. And in the random access mode, the solid-state drive system automatically evenly distributes the current input / output access operations to each central processing unit, and reads data from the memory flash or writes user data according to the current input / output access operations evenly distributed to each central processing unit. By the above method, it is possible to improve the performance of the number of read and write operations per second for random access of the solid-state drive, enabling the solid-state drive system to fully utilize the performance of the hardware in the random access mode and reach the maximum speed of the solid-state drive system.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly to a method and a system for improving the system IOPS. Background Art

[0002] In current society, people have higher and higher requirements for the response speed of human-computer interactive devices. It is becoming increasingly intolerable that when a device is clicked or operated and then gets stuck in operation without quickly giving the user a result, which will cause extremely poor user experience. For example, when a user logs in to or operates an APP (Application), a large amount of data needs to be queried from a database subsequently, as well as secondary, tertiary data queries, calculations, and merges extended from the data.

[0003] For example, for a Weibo-type APP, the amount of content shown to customers each time is much smaller than the home page of a portal website, but the response speed of the Weibo APP is much slower than that of the portal website. The reason is primarily the IOPS (Input / Output Operations Per Second) response speed of the memory.

[0004] In related technologies, in a traditional mechanical hard disk, due to the seek time of the read / write head (i.e., the time required for the head to move from one track of the disk to another track and wait for the starting data bit of the target track to rotate to directly below the head) being restricted by the mechanical structure and unable to be further improved, if the system has a large number of random IO (Input / Output) operations, the read / write response for each small piece of data needs to wait for the seek time of the head, resulting in very slow access. For example, the continuous read / write speed of a mechanical hard disk can generally reach 100MB / S (megabytes per second), but the seek time is at least 3 milliseconds, and at most only 330 random accesses can be performed per second. Usually, each access only operates on 4KB (Kilobyte) of data, and the total bandwidth is only 4KB * 330 = 1.3MB / S, which has a huge difference from the speed of 100MB / S. The intuitive feeling of the user's operation is that the system reacts too slowly.

[0005] With the development of technology, Solid State Disk (SSD) has emerged, with a significant improvement in IOPS, from 330 times per second before to 10,000, 50,000, or even 100,000 times per second now. However, the existing solid state drive system designs the IOPS index based on a 4KB access volume. That is, in the random read / write mode, the total speed is 100,000 * 4KB = 400MB / S, which is far from the sequential access speed of 3000MB / S of the solid state drive. This results in mediocre performance in terms of the number of read / write operations per second in the random access of the solid state drive, preventing the solid state drive system from fully leveraging the hardware performance in the random access mode and not achieving the maximum speed of the solid state drive system. Summary of the Invention

[0006] In view of this, the object of the present invention is to provide a method and system for improving system IOPS, which can improve the performance of the number of read / write operations per second in the random access of the solid state drive, enabling the solid state drive system to fully utilize the hardware performance in the random access mode and reach the maximum speed of the solid state drive system.

[0007] According to one aspect of the present invention, there is provided a method for improving system IOPS, including:

[0008] Adopting a mode of an 8-core central processing unit for the solid state drive system, each central processing unit corresponding to a memory channel, each memory channel operating independently without being affected by the operations of other memory channels, and the 8-core central processing units being able to cooperate when needed; in the random access mode, automatically evenly distributing the current input / output access operations to each central processing unit by the solid state drive system; and reading data from the memory or writing user data according to the current input / output access operations evenly distributed to each central processing unit.

[0009] Among them, the step of adopting a mode of an 8-core central processing unit for the solid state drive system, each central processing unit corresponding to a memory channel, each memory channel operating independently without being affected by the operations of other memory channels, and the 8-core central processing units being able to cooperate when needed includes: adopting a distributed design mode, adopting a mode of an 8-core central processing unit for the solid state drive system, each central processing unit corresponding to a memory channel, each memory channel operating independently without being affected by the operations of other memory channels, and the 8-core central processing units being able to cooperate when needed.

[0010] Among them, when in the random access mode, the solid-state drive system automatically distributes the current input / output access operations evenly to each central processing unit, including: when in the random access mode, in a manner of distributing according to the address range responsible for the memory bus by the access address associated with the current input / output access operation, the solid-state drive system automatically distributes the current input / output access operations evenly to each central processing unit.

[0011] Among them, reading data from the memory or writing user data according to the current input / output access operations evenly distributed to each central processing unit includes: according to the current input / output access operations evenly distributed to each central processing unit, each central processing unit decodes the access instructions associated with the current input / output access operations, and through flash translation layer conversion, obtains the actual memory access address, and reads data from the actual memory or writes user data.

[0012] Among them, after reading data from the memory or writing user data according to the current input / output access operations evenly distributed to each central processing unit, it further includes: taking into account the read and write operations of sequential large data, through the coordinated work of the 8 central processing units, jointly performing parallel decoding and address conversion on the access to the large data and parallel reading and writing of the memory.

[0013] According to another aspect of the present invention, there is provided a system for improving system IOPS, including: a designer, a distributor, and a reader / writer; the designer is used to adopt a mode of 8 small-core central processing units for the solid-state drive system, each central processing unit corresponds to a memory channel, and each memory channel operates independently without being affected by the operations of other memory channels, and at the same time, the 8 small-core central processing units can cooperate when needed; the distributor is used to, when in the random access mode, automatically distribute the current input / output access operations evenly to each central processing unit through the solid-state drive system; the reader / writer is used to read data from the memory or write user data according to the current input / output access operations evenly distributed to each central processing unit.

[0014] Among them, the designer is specifically used for: adopting a distributed design mode, adopting a mode of 8 small-core central processing units for the solid-state drive system, each central processing unit corresponds to a memory channel, and each memory channel operates independently without being affected by the operations of other memory channels, and at the same time, the 8 small-core central processing units can cooperate when needed.

[0015] Among them, the dispenser is specifically configured to: in the random access mode, in a manner of allocating according to the address range responsible for the memory bus by the access address associated with the current input / output access operation, automatically allocate the current input / output access operation to each central processing unit by the solid-state drive system.

[0016] Among them, the reader / writer is specifically configured to: according to the current input / output access operation evenly allocated to each central processing unit, decode the access instruction associated with the current input / output access operation through each central processing unit, and after conversion by the flash translation layer, obtain the actual memory access address, and read data from the actual memory or write user data.

[0017] Among them, the system for improving system IOPS further includes: a coordinator; the coordinator is used to take into account the read / write operations of sequential large data, and through the coordinated work of the 8 central processing units, perform parallel decoding, address conversion, and parallel read / write of the memory for the access to the large data together.

[0018] According to another aspect of the present invention, there is provided a computer device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method for improving system IOPS as described in any one of the above.

[0019] According to still another aspect of the present invention, there is provided a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the method for improving system IOPS as described in any one of the above is implemented.

[0020] It can be found that the above solution can adopt a mode of 8 small-core central processing units (CPUs) for the solid-state drive system. Each central processing unit (CPU) corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, the 8 small-core central processing units (CPUs) can cooperate when needed, and in the random access mode, the current input / output (IO) access operation can be automatically evenly allocated to each central processing unit (CPU) by the solid-state drive system, and according to the current input / output (IO) access operation evenly allocated to each central processing unit (CPU), data can be read from the memory flash or user data can be written, which can achieve the performance of improving the number of read / write operations per second for random access of the solid-state drive, enabling the solid-state drive system to fully utilize the performance of the hardware in the random access mode and reach the maximum speed of the solid-state drive system.

[0021] Furthermore, the above solution can adopt a distributed design pattern, using a mode of 8 small-core central processing units (CPUs) for the solid-state drive system. Each central processing unit (CPU) corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, the 8 small-core central processing units (CPUs) can cooperate when needed. The advantage of this is that the solid-state drive system can complete large-data-volume burst tasks.

[0022] Furthermore, in the above solution, in the random access mode, the access addresses associated with the current input / output (I / O) access operations can be used to allocate the address range responsible for the memory flash bus. In this way, the solid-state drive system automatically distributes the current input / output (I / O) access operations evenly to each central processing unit (CPU). The advantage of this is that in the random access model, with a unit of 4KB (kilobyte) data bits, the data volume is not large, and each central processing unit (CPU) is sufficient to handle it.

[0023] Furthermore, in the above solution, based on the current input / output (I / O) access operations evenly distributed to each central processing unit (CPU), each central processing unit (CPU) decodes the access instructions associated with the current input / output (I / O) access operations. After conversion by the FTL (Flash Translation Layer), the actual memory flash access address is obtained, and data is read from or user data is written to the actual memory flash. The advantage of this is that the previous method of relying on a single central processing unit (CPU) for decoding and then reading and writing the memory flash has been changed to the current method where the 8 central processing units (CPUs) perform parallel computing decoding, parallel memory flash operations, and system data transmission. The speed of reading and writing operations per second (IOPS) has increased from the previous 400 megabytes per second to 400 * 8 = 3000 megabytes per second, maximizing the utilization of hardware performance. The response speed has increased from the previous 100,000 times per second to 100,000 * 8 = 800,000 times per second. It can improve the performance of the number of random read and write operations per second of the solid-state drive, enabling the solid-state drive system to fully utilize the hardware performance in the random access mode and reach the maximum speed of the solid-state drive system.

[0024] Furthermore, the above solution can take into account the sequential read and write operations of large data. Through the coordinated work of the 8 central processing units (CPUs), they jointly perform parallel decoding, address conversion, and parallel reading and writing of the memory flash for the access to the large data. The advantage of this is that the solid-state drive system can complete large-data-volume burst tasks without sacrificing the performance of large data. Description of the Drawings

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0026] Figure 1 is a schematic flowchart of an embodiment of the method for the present invention to improve the system IOPS;

[0027] Figure 2 is a schematic flowchart of another embodiment of the method for the present invention to improve the system IOPS;

[0028] Figure 3 is a schematic structural diagram of an embodiment of the system for the present invention to improve the system IOPS;

[0029] Figure 4 is a schematic structural diagram of another embodiment of the system for the present invention to improve the system IOPS;

[0030] Figure 5 is a schematic structural diagram of an embodiment of the computer device of the present invention. Detailed implementation manners

[0031] The following will further describe the present invention in detail in conjunction with the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are only used to illustrate the present invention, but do not limit the scope of the present invention. Similarly, the following embodiments are only partial embodiments of the present invention rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0032] The present invention provides a method for improving the system IOPS, which can improve the performance of the number of read and write operations per second for random access of solid-state drives, enabling the solid-state drive system to fully utilize the performance of the hardware in the random access mode and reach the maximum speed of the solid-state drive system.

[0033] Please refer to Figure 1 , Figure 1 is a schematic flowchart of an embodiment of the method for the present invention to improve the system IOPS. It should be noted that if there are substantially the same results, the method of the present invention is not limited to Figure 1 the process sequence shown. As Figure 1 shown, the method includes the following steps:

[0034] S101: Adopt a mode of using 8 small-core central processing units (CPUs) for the solid-state drive system. Each central processing unit (CPU) corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, the 8 small-core central processing units (CPUs) can cooperate when needed.

[0035] Among them, the mode of using 8 small-core central processing units (CPUs) for the solid-state drive system, where each central processing unit (CPU) corresponds to a memory flash channel, each memory flash channel operates independently without being affected by the operations of other memory flash channels, and at the same time the 8 small-core central processing units (CPUs) can cooperate when needed, may include:

[0036] Adopt a distributed design mode. For the solid-state drive system, use a mode of 8 small-core central processing units (CPUs). Each central processing unit (CPU) corresponds to a memory flash channel, each memory flash channel operates independently without being affected by the operations of other memory flash channels, and at the same time the 8 small-core central processing units (CPUs) can cooperate when needed. The advantage of this is that the solid-state drive system can complete large-volume burst tasks.

[0037] S102: In the random access mode, the solid-state drive system automatically distributes the current input / output (IO) access operations evenly to each central processing unit (CPU).

[0038] Among them, in the random access mode, the solid-state drive system automatically distributing the current input / output (IO) access operations evenly to each central processing unit (CPU) may include:

[0039] In the random access mode, in the way of distributing according to the address range responsible for the memory flash bus by the access address associated with the current input / output (IO) access operation, the solid-state drive system automatically distributes the current input / output (IO) access operations evenly to each central processing unit (CPU). The advantage of this is that since in the random access model, it is in units of 4KB (kilobyte) data bits and the data volume is not large, each central processing unit (CPU) is sufficient to handle it.

[0040] S103: Read data from the memory flash or write user data according to the current input / output (IO) access operations evenly distributed to each central processing unit (CPU).

[0041] Among them, reading data from the memory flash or writing user data according to the current input / output (IO) access operations evenly distributed to each central processing unit (CPU) may include:

[0042] According to the current input / output (I / O) access operations evenly distributed to each central processing unit (CPU), each CPU decodes the access instructions associated with the current I / O access operations. After conversion by the FTL (Flash Translation Layer), the actual memory flash access address is obtained, and data is read from or user data is written to the actual memory flash. The advantage is that the original method, which relied on one CPU for decoding and then reading and writing to the memory flash, has now changed to 8 CPUs performing parallel computing decoding, parallel memory flash operations, and system data transmission. The I / O operations per second (IOPS) speed has increased from 400 megabytes per second to 400 * 8 = 3200 megabytes per second, maximizing the utilization of hardware performance. The response speed has increased from 100,000 times per second to 100,000 * 8 = 800,000 times per second, enabling the performance of the number of random read and write operations per second of the solid-state drive to be improved. In the random access mode, the solid-state drive system can fully utilize the hardware performance and reach the maximum speed of the solid-state drive system.

[0043] Among them, after reading data from or writing user data to the memory flash according to the current I / O access operations evenly distributed to each CPU, it may further include:

[0044] Taking into account the sequential read and write operations of large data, the 8 CPUs work together to perform parallel decoding, address conversion, and parallel read and write to the memory flash for the access of the large data. The advantage is that the solid-state drive system can complete large data volume burst tasks without sacrificing the performance of large data.

[0045] It should be noted that there is an error in the calculation in the original text. 400 * 8 = 3200, not 3000. The translation has been corrected accordingly.It can be found that in this embodiment, an SSD system can adopt a mode with 8 small-core central processing units (CPUs). Each CPU corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, the 8 small-core CPUs can cooperate when needed. And in the random access mode, the SSD system can automatically evenly distribute the current input / output (I / O) access operations to each CPU. Also, based on the current I / O access operations evenly distributed to each CPU, data can be read from the memory flash or user data can be written, which can improve the performance of the number of read and write operations per second for random access of the SSD, enabling the SSD system to fully utilize the performance of the hardware in the random access mode and reach the maximum speed of the SSD system.

[0046] Furthermore, in this embodiment, a distributed design mode can be adopted. The SSD system adopts a mode with 8 small-core CPUs. Each CPU corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, the 8 small-core CPUs can cooperate when needed. The advantage of this is that the SSD system can complete large-volume burst tasks.

[0047] Furthermore, in this embodiment, in the random access mode, in a way of distributing according to the address range responsible for the memory flash bus by the access address associated with the current I / O access operation, the SSD system can automatically evenly distribute the current I / O access operations to each CPU. The advantage of this is that since in the random access model, the data volume is in units of 4KB (kilobytes) and is not large, each CPU is sufficient to handle it.

[0048] Further, in this embodiment, based on the current input / output (I / O) access operations evenly distributed to each central processing unit (CPU), each CPU decodes the access instructions associated with the current I / O access operations. After conversion by the FTL (Flash Translation Layer), the actual memory flash access address is obtained, and data is read from or user data is written to the actual memory flash. The advantage of this is that instead of relying on a single CPU for decoding and then reading and writing to the memory flash as before, now the 8 CPUs perform parallel computing decoding, parallel memory flash operations, and system data transmission. The I / O operations per second (IOPS) speed has increased from 400 megabytes per second to 400 * 8 = 3000 megabytes per second, maximizing the utilization of hardware performance. The response speed has increased from 100,000 times per second to 100,000 * 8 = 800,000 times, enabling the performance of the number of read and write operations per second in random access of the solid-state drive to be improved. In the random access mode, the solid-state drive system can fully utilize the hardware performance and reach the maximum speed of the solid-state drive system.

[0049] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of another embodiment of the method for the present invention to improve system IOPS. In this embodiment, the method includes the following steps:

[0050] S201: Adopt a mode of 8 small-core central processing units (CPUs) for the solid-state drive system. Each CPU corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, the 8 small-core CPUs can cooperate when needed.

[0051] It can be as described in S101 above and will not be elaborated here.

[0052] S202: In the random access mode, the solid-state drive system automatically distributes the current input / output (I / O) access operations evenly to each CPU.

[0053] It can be as described in S102 above and will not be elaborated here.

[0054] S203: Based on the current input / output (I / O) access operations evenly distributed to each CPU, read data from the memory flash or write user data.

[0055] It can be as described in S103 above and will not be elaborated here.

[0056] S204: Take into account the read and write operations of sequential big data. Through the coordination of these 8 central processing units (CPUs), they jointly perform parallel decoding, address conversion, and parallel read and write of the memory flash for the access to this big data.

[0057] It can be found that in this embodiment, the read and write operations of sequential big data can be taken into account. Through the coordination of these 8 central processing units (CPUs), they jointly perform parallel decoding, address conversion, and parallel read and write of the memory flash for the access to this big data. The advantage of this is that without sacrificing the performance of big data, the solid-state drive system can complete burst tasks with a large amount of data.

[0058] The present invention also provides a system for improving the system IOPS, which can achieve the performance of improving the number of read and write operations per second for random access of the solid-state drive, enabling the solid-state drive system to fully utilize the performance of the hardware in the random access mode and reach the maximum speed of the solid-state drive system.

[0059] Please refer to Figure 3 , Figure 3 , which is a schematic structural diagram of an embodiment of the system for improving the system IOPS of the present invention. In this embodiment, the system 30 for improving the system IOPS includes a designer 31, a distributor 32, and a reader / writer 33.

[0060] The designer 31 is used to adopt a mode of 8 small-core central processing units (CPUs) for the solid-state drive system. Each central processing unit (CPU) corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, these 8 small-core central processing units (CPUs) can cooperate when needed.

[0061] The distributor 32 is used to automatically evenly distribute the current input / output (IO) access operations to each central processing unit (CPU) through the solid-state drive system in the random access mode.

[0062] The reader / writer 33 is used to read data from the memory flash or write user data according to the current input / output (IO) access operations evenly distributed to each central processing unit (CPU).

[0063] Optionally, the designer 31 can be specifically used for:

[0064] Adopt a distributed design mode, and adopt a mode of 8 small-core central processing units (CPUs) for the solid-state drive system. Each central processing unit (CPU) corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, these 8 small-core central processing units (CPUs) can cooperate when needed.

[0065] Optionally, the dispenser 32 can be specifically used for:

[0066] In the random access mode, in a manner of allocating the address range responsible for the memory flash bus according to the access address associated with the current input / output (IO) access operation, the solid-state drive system automatically evenly distributes the current input / output (IO) access operation to each central processing unit (CPU).

[0067] Optionally, the reader / writer 33 can be specifically used for:

[0068] According to the current input / output (IO) access operation evenly distributed to each central processing unit (CPU), each central processing unit (CPU) decodes the access instruction associated with the current input / output (IO) access operation, and through Flash Translation Layer (FTL) conversion, obtains the actual memory flash access address, and reads data from the actual memory flash or writes user data.

[0069] Please refer to Figure 4 , Figure 4 FIG. is a schematic structural diagram of another embodiment of the system for improving the system IOPS of the present invention. Different from the previous embodiment, the system 40 for improving the system IOPS of this embodiment further includes a coordinator 41.

[0070] The coordinator 41 is used to take into account the read and write operations of sequential large data, and through the coordinated work of the 8 central processing units (CPUs), jointly perform parallel decoding and address conversion of the access to the large data and parallel read and write of the memory flash.

[0071] Each unit module of the system 30 / 40 for improving the system IOPS can respectively execute the corresponding steps in the above method embodiments, so the unit modules will not be described in detail here. For details, please refer to the description of the corresponding steps above.

[0072] The present invention further provides a computer device, as Figure 5 shown, including: at least one processor 51; and a memory 52 communicatively connected to the at least one processor 51; wherein, the memory 52 stores instructions executable by the at least one processor 51, and the instructions are executed by the at least one processor 51 so that the at least one processor 51 can execute the method for improving the system IOPS described above.

[0073] Among them, the memory 52 and the processor 51 are connected in a bus manner. The bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors 51 and the memory 52 together. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, etc., which are well known in the art, so they will not be further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a component or multiple components, such as multiple receivers and transmitters, and provides a unit for communicating with various other devices on the transmission medium. The data processed by the processor 51 is transmitted on the wireless medium through the antenna. Further, the antenna also receives data and transmits the data to the processor 51.

[0074] The processor 51 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management, and other control functions. The memory 52 can be used to store data used by the processor 51 when executing operations.

[0075] The present invention further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the above method embodiments are implemented.

[0076] It can be found that in the above solution, the solid-state drive system can adopt a mode of 8 small-core central processing units (CPUs). Each central processing unit (CPU) corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, the 8 small-core central processing units (CPUs) can cooperate when needed. And in the random access mode, the solid-state drive system can automatically evenly distribute the current input / output (IO) access operations to each central processing unit (CPU), and can read data from the memory flash or write user data according to the current input / output (IO) access operations evenly distributed to each central processing unit (CPU), which can improve the performance of the number of read and write operations per second of the random access of the solid-state drive, enable the solid-state drive system to fully utilize the performance of the hardware in the random access mode, and can reach the maximum speed of the solid-state drive system.

[0077] Furthermore, in the above solution, a distributed design mode can be adopted. The solid-state drive system adopts a mode of 8 small-core central processing units (CPUs). Each central processing unit (CPU) corresponds to a memory flash channel, and each memory flash channel operates independently without being affected by the operations of other memory flash channels. At the same time, the 8 small-core central processing units (CPUs) can cooperate when needed. The advantage of this is that the solid-state drive system can complete large-data-volume burst tasks.

[0078] Furthermore, in the above solution, in the random access mode, the access addresses associated with the current input / output (I / O) access operations can be used to allocate the address range responsible for the memory flash bus. In this way, the solid-state drive (SSD) system can automatically evenly distribute the current I / O access operations to each central processing unit (CPU). The advantage is that in the random access model, since the data unit is 4KB (kilobytes), the data volume is not large, which enables each CPU to handle it adequately.

[0079] Furthermore, in the above solution, based on the current I / O access operations evenly distributed to each CPU, each CPU can decode the access instructions associated with the current I / O access operations. After conversion through the Flash Translation Layer (FTL), the actual memory flash access address can be obtained, and data can be read from or user data can be written to the actual memory flash. The advantage is that the previous method of relying on a single CPU for decoding and then reading and writing the memory flash has now changed to parallel computing decoding by 8 CPUs, parallel memory flash operations, and system data transmission. The input / output operations per second (IOPS) speed has increased from 400 megabytes per second to 400 * 8 = 3000 megabytes per second, maximizing the utilization of hardware performance. The response speed has increased from 100,000 times per second to 100,000 * 8 = 800,000 times per second. This can improve the performance of the SSD's random access IOPS, allowing the SSD system to fully utilize hardware performance in the random access mode and reach the maximum speed of the SSD system.

[0080] Furthermore, in the above solution, the sequential large data read and write operations can be taken into account. Through the coordinated work of the 8 CPUs, they can jointly perform parallel decoding, address conversion, and parallel reading and writing of the memory flash for the large data access. The advantage is that the SSD system can complete large data volume burst tasks without sacrificing the performance of large data.

[0081] In several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0082] The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0083] In addition, each functional unit in various embodiments of the present invention can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0084] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0085] The above are only partial embodiments of the present invention and do not limit the protection scope of the present invention. Any equivalent device or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A method for improving system IOPS, characterized in that Including: Adopting a mode of an 8-core central processing unit for the solid-state drive system, each central processing unit corresponding to a memory channel, each memory channel operating independently without being affected by the operations of other memory channels, and at the same time, the 8-core central processing units can cooperate when needed; In the random access mode, automatically distributing the current input / output access operations to each of the central processing units by the solid-state drive system; Reading data from the memory or writing user data according to the current input / output access operations evenly distributed to each of the central processing units.

2. The method for improving system IOPS according to claim 1, wherein The mode of adopting an 8-core central processing unit for the solid-state drive system, each central processing unit corresponding to a memory channel, each memory channel operating independently without being affected by the operations of other memory channels, and at the same time, the 8-core central processing units can cooperate when needed, includes: Adopting a distributed design mode, adopting a mode of an 8-core central processing unit for the solid-state drive system, each central processing unit corresponding to a memory channel, each memory channel operating independently without being affected by the operations of other memory channels, and at the same time, the 8-core central processing units can cooperate when needed.

3. The method for improving the system IOPS according to claim 1, wherein The step of, in the random access mode, automatically distributing the current input / output access operations to each of the central processing units by the solid-state drive system, includes: In the random access mode, in a manner of distributing according to the address range responsible for the memory bus by the access address associated with the current input / output access operation, automatically distributing the current input / output access operations to each of the central processing units by the solid-state drive system.

4. The method for improving the system IOPS according to claim 1, wherein The step of reading data from the memory or writing user data according to the current input / output access operations evenly distributed to each of the central processing units, includes: According to the current input / output access operations evenly distributed to each of the central processing units, decoding the access instructions associated with the current input / output access operations by each of the central processing units, and through flash translation layer conversion, obtaining the actual memory access address, and reading data from the actual memory or writing user data.

5. The method for improving the system IOPS according to claim 1, wherein After the step of reading data from the memory or writing user data according to the current input / output access operations evenly distributed to each of the central processing units, it further includes: Taking into account the read and write operations of sequential large data, coordinating the work of the 8 central processing units to perform parallel decoding, address conversion, and parallel reading and writing of the memory for the access to the large data together.

6. A system for improving system IOPS, characterized in that, Including: A designer, a distributor, and a reader / writer; The designer is used to adopt a mode of an 8-core central processing unit for the solid-state drive system, each central processing unit corresponding to a memory channel, each memory channel operating independently without being affected by the operations of other memory channels, and at the same time, the 8-core central processing units can cooperate when needed; The distributor is used to, in the random access mode, automatically distribute the current input / output access operations to each of the central processing units by the solid-state drive system; The reader / writer is used to read data from the memory or write user data according to the current input / output access operations evenly distributed to each central processing unit.

7. The system for improving the system IOPS according to claim 6, wherein The designer is specifically used for: Adopting a distributed design pattern, the solid-state drive system adopts a mode of 8 small-core central processing units. Each central processing unit corresponds to a memory channel, and each memory channel operates independently without being affected by the operations of other memory channels. At the same time, the 8 small-core central processing units can cooperate when needed.

8. The system for improving system IOPS according to claim 6, wherein The allocator is specifically used for: In the random access mode, in the way of distributing according to the address range responsible for the memory bus by the access address associated with the current input / output access operation, the current input / output access operation is automatically evenly distributed to each central processing unit through the solid-state drive system.

9. The system for improving system IOPS according to claim 6, wherein The reader / writer is specifically used for: According to the current input / output access operations evenly distributed to each central processing unit, each central processing unit decodes the access instructions associated with the current input / output access operation, and through the flash translation layer conversion, obtains the actual memory access address, and reads data from the actual memory or writes user data.

10. The system for improving system IOPS according to claim 6, wherein The system for improving system IOPS further includes: A coordinator; The coordinator is used to take into account the read and write operations of sequential large data. Through the coordinated work of the 8 central processing units, the access to the large data is decoded and address-converted in parallel and the memory is read and written in parallel.

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