Deadlock loop detection method, device, electronic device and storage medium

Abstract

A method, apparatus, electronic device, and computer-readable storage medium for detecting deadlock loops in a network-on-chip (NOC). The NOC includes multiple routing nodes and multiple devices. The method comprises: determining multiple access paths between the multiple devices, each of the multiple access paths including a master device selected from one of the multiple devices, a slave device selected from one of the multiple devices, and at least one routing node from multiple routing nodes for connecting the master and slave devices; superimposing the multiple access paths and identifying multiple valid routing nodes from the multiple routing nodes, wherein each of the multiple valid routing nodes in the multiple access paths is used to receive data from one of the multiple routing nodes and also to send data to one of the multiple routing nodes; and detecting whether a deadlock loop is caused by the multiple access paths based on the multiple valid routing nodes. This method can reduce the time overhead of detecting whether the multiple access paths cause a deadlock loop, thereby improving detection efficiency.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method, apparatus, electronic device, and computer-readable storage medium for detecting a deadlock loop in an on-chip network. Background Art

[0002] As the number of cores in processor chips continues to increase, systems-on-chip (SoCs) are trending from multi-core to many-core. Recently, processor chips with up to 1,000 cores have been developed. In such large-scale many-core systems, global interconnects can lead to severe on-chip synchronization errors, unpredictable communication latency, and significant power consumption. To alleviate these challenges, the concept of Network-on-Chip (NoC) has been proposed. NoCs can replace traditional bus or point-to-point interconnects, becoming a new on-chip communication architecture. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a method for detecting a deadlock loop in an on-chip network, where the on-chip network includes multiple routing nodes and multiple devices. The method includes: determining multiple access paths between the multiple devices, each of the multiple access paths including a master device selected from one of the multiple devices, a slave device selected from one of the multiple devices, and at least one routing node from the multiple routing nodes for connecting the master device and the slave device; superimposing the multiple access paths and identifying multiple valid routing nodes from the multiple routing nodes, where each of the multiple valid routing nodes in the multiple access paths is used to receive data from one of the multiple routing nodes and also to send data to one of the multiple routing nodes; and detecting whether a deadlock loop is caused by the multiple access paths based on the multiple valid routing nodes.

[0004] For example, in the detection method provided in an embodiment of the present disclosure, based on the multiple valid routing nodes, detecting whether the deadlock loop is caused by the multiple access paths includes: determining the valid transmission segments between the multiple valid routing nodes according to the superposition results obtained by superimposing the multiple access paths, wherein each access path includes at least one transmission segment, and the valid transmission segment is a transmission segment for connecting two valid routing nodes; and based on the valid transmission segments, detecting whether the deadlock loop is caused by the multiple access paths.

[0005] For example, in the detection method provided in one embodiment of the present disclosure, based on the valid transmission segment, detecting whether the deadlock loop is caused by the multiple access paths includes: determining multiple target access paths with the same valid transmission segment among the multiple access paths; merging the multiple target access paths to obtain an access path graph; and based on the access path graph, detecting whether the deadlock loop is caused by the multiple target access paths.

[0006] For example, in the detection method provided in one embodiment of the present disclosure, the multiple target access paths having the same valid transmission segment among the multiple access paths are determined, including: for each selected access path, searching whether there is at least one valid transmission segment in the selected access path that exists in other access paths; and in response to the existence of at least one valid transmission segment in the selected access path that exists in the other access paths, determining that the selected access path is the target access path.

[0007] For example, in the detection method provided in one embodiment of the present disclosure, for each selected access path, a search is performed to determine whether at least one valid transmission segment in the selected access path exists in other access paths, including: based on each selected access path, determining an access path set for each valid transmission segment in the selected access path, wherein the elements in the access path set are the individual access paths containing the valid transmission segments; and in response to the presence of multiple elements in the access path set for at least one valid transmission segment in the selected access path, determining that the at least one valid transmission segment exists in other access paths.

[0008] For example, in the detection method provided in an embodiment of the present disclosure, based on the access path graph, detecting whether the deadlock loop is caused by the multiple target access paths includes: determining the next-level routing node of each valid routing node in the access path graph, wherein the next-level routing node is a routing node adjacent to the valid routing node, and the valid routing node is used to send data to the next-level routing node; determining a first number of the next-level routing nodes of all valid routing nodes in the access path graph that are of the type of valid routing nodes; determining a second number of all valid routing nodes in the access path graph; and in response to the first number being equal to the second number, determining that the multiple target access paths can cause the deadlock loop.

[0009] For example, in the detection method provided in an embodiment of the present disclosure, the first number of valid routing nodes in the next-level routing nodes of all valid routing nodes in the access path graph is determined, including: in response to the type of the next-level routing node of each valid routing node in the access path graph being a valid routing node, adding the next-level routing node to the next-level node set, thereby obtaining the next-level node set of each valid routing node; merging the elements in the next-level node set of each valid routing node to obtain a final set; and taking the number of elements in the final set as the first number.

[0010] For example, in the detection method provided in an embodiment of the present disclosure, the multiple access paths are superimposed, and the multiple valid routing nodes among the multiple routing nodes are identified, including: superimposing the multiple access paths to obtain a superposition result; for each routing node in the superposition result, determining whether the routing node is used to receive data from one of the multiple routing nodes and to send data to one of the multiple routing nodes; and in response to the routing node being used to receive data from one of the multiple routing nodes and to send data to one of the multiple routing nodes, determining that the routing node belongs to the multiple valid routing nodes.

[0011] For example, in the detection method provided in an embodiment of the present disclosure, there are multiple access path graphs, and based on the access path graphs, detecting whether the deadlock loop is caused by the multiple target access paths includes: based on each access path graph, detecting whether the deadlock loop is caused by the multiple target access paths in each access path graph.

[0012] For example, in the detection method provided in one embodiment of the present disclosure, the valid transmission segment between the multiple valid routing nodes is determined based on the superposition result obtained by superimposing the multiple access paths, including: determining the access path subgraph of each of the multiple access paths based on the superposition result obtained by superimposing the multiple access paths; and analyzing each of the access path subgraphs to obtain the valid transmission segment between the multiple valid routing nodes.

[0013] For example, in the detection method provided in an embodiment of the present disclosure, it also includes obtaining routing information of the on-chip network; determining the multiple access paths between the multiple devices, including: determining the multiple access paths between the multiple devices based on the routing information.

[0014] At least one embodiment of the present disclosure provides a detection device for a deadlock loop in an on-chip network, where the on-chip network includes multiple routing nodes and multiple devices, including: a path determination unit, configured to determine multiple access paths between the multiple devices, each of the multiple access paths including a master device selected from one of the multiple devices, a slave device selected from one of the multiple devices, and at least one routing node among the multiple routing nodes for connecting the master device and the slave device; an identification unit, configured to superimpose the multiple access paths and identify multiple valid routing nodes among the multiple routing nodes, wherein, among the multiple access paths, the valid routing node is used to receive data from one of the multiple routing nodes and also to send data to one of the multiple routing nodes; and a detection unit, configured to detect, based on the multiple valid routing nodes, whether the deadlock loop is caused by the multiple access paths.

[0015] For example, in the detection device provided in one embodiment of the present disclosure, the detection unit includes: an effective transmission segment determination subunit, configured to determine the effective transmission segments between the multiple effective routing nodes based on the superposition results obtained by superimposing the multiple access paths, each access path includes at least one transmission segment, and the transmission segment used to connect two valid routing nodes is the effective transmission segment; and a deadlock detection subunit, configured to detect whether the deadlock loop is caused by the multiple access paths based on the effective transmission segments.

[0016] For example, in the detection device provided in one embodiment of the present disclosure, the deadlock detection subunit includes: a target path determination subunit, configured to determine multiple target access paths with the same valid transmission segment among the multiple access paths; a merging subunit, configured to merge the multiple target access paths to obtain an access path graph; and a deadlock loop detection subunit, configured to detect whether the deadlock loop is caused by the multiple target access paths based on the access path graph.

[0017] For example, in the detection device provided in one embodiment of the present disclosure, the target path determination subunit includes: a search subunit, configured to search, for each selected access path, whether there is at least one valid transmission segment in the selected access path that exists in other access paths; and a target determination subunit, configured to determine that the selected access path is the target access path in response to the existence of at least one valid transmission segment in the selected access path that exists in the other access paths.

[0018] For example, in the detection device provided in one embodiment of the present disclosure, the search subunit includes: a path set determination subunit, configured to determine, based on each selected access path, an access path set of each valid transmission segment in the selected access path, wherein the elements in the access path set are the individual access paths containing the valid transmission segments; and a judgment subunit, configured to determine that, in response to the presence of multiple elements in the access path set of at least one valid transmission segment in the selected access path, the at least one valid transmission segment exists in other access paths.

[0019] For example, in the detection device provided in one embodiment of the present disclosure, the deadlock loop detection subunit includes: a first determination subunit, configured to determine the next-level routing node of each valid routing node in the access path graph, wherein the next-level routing node is a routing node adjacent to the valid routing node, and the valid routing node is used to send data to the next-level routing node; a second determination subunit, configured to determine a first number of the next-level routing nodes of all valid routing nodes in the access path graph that are of the type of valid routing nodes; a third determination subunit, configured to determine a second number of all valid routing nodes in the access path graph; and a fourth determination subunit, configured to determine that, in response to the first number being equal to the second number, the multiple target access paths can cause the deadlock loop.

[0020] For example, in the detection device provided in one embodiment of the present disclosure, the second determination subunit includes: a next-level node set generation subunit, configured to, in response to the type of the next-level routing node of each valid routing node in the access path graph being a valid routing node, add the next-level routing node to the next-level node set, thereby obtaining the next-level node set of each valid routing node; a merging subunit, configured to merge the elements in the next-level node set of each valid routing node to obtain a final set; and a statistical subunit, configured to take the number of elements in the final set as the first number.

[0021] For example, in the detection device provided in one embodiment of the present disclosure, the identification unit includes: a superposition subunit, configured to superimpose the multiple access paths to obtain a superposition result; a fifth determination subunit, configured to determine, for each routing node in the superposition result, whether the routing node is used to receive data from one of the multiple routing nodes and to send data to one of the multiple routing nodes; and a response subunit, configured to determine that the routing node belongs to the multiple valid routing nodes in response to the routing node being used to receive data from one of the multiple routing nodes and to send data to one of the multiple routing nodes.

[0022] For example, in the detection device provided in an embodiment of the present disclosure, the deadlock loop detection subunit includes a loop detection subunit configured to detect, based on each access path graph, whether the deadlock loop is caused by the multiple target access paths in each access path graph.

[0023] For example, in the detection device provided in one embodiment of the present disclosure, the device also includes an acquisition unit configured to acquire routing information of the on-chip network; the path determination unit includes a path determination subunit configured to determine the multiple access paths between the multiple devices based on the routing information.

[0024] At least one embodiment of the present disclosure provides an electronic device, comprising a processor; a memory comprising one or more computer program instructions; wherein the one or more computer program instructions are stored in the memory and, when executed by the processor, implement the detection method for on-chip network deadlock loops provided in any embodiment of the present disclosure.

[0025] At least one embodiment of the present disclosure provides a computer-readable storage medium for storing non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a computer, the method for detecting deadlock loops in an on-chip network provided in any embodiment of the present disclosure can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0027] Figure 1A Shows the basic structure of a NOC system;

[0028] Figure 1B A NOC network topology diagram is shown;

[0029] Figure 1C Shown Figure 1B The deadlock loop formed by the NOC network topology diagram in the diagram;

[0030] Figure 2 A flowchart of a method for detecting a deadlock loop in a network on chip (NOC) according to at least one embodiment of the present disclosure is shown;

[0031] Figure 3A At least one embodiment of the present disclosure provides Figure 2 Flowchart of the method of step S20;

[0032] Figure 3B The network topology diagram after marking the superposition results is shown;

[0033] Figure 4A At least one embodiment of the present disclosure provides Figure 2 Flowchart of the method of step S30;

[0034] Figure 4B Shown Figure 1B The access path subgraph of the master device M;

[0035] Figure 4C Shown Figure 1B The access path subgraph of the master device N in the middle;

[0036] Figure 4DShown Figure 1B The access path subgraph of the master device L in the middle;

[0037] Figure 4E At least one embodiment of the present disclosure provides Figure 4A Flowchart of the method for step S32;

[0038] Figure 5 At least one embodiment of the present disclosure provides Figure 4E Method flow chart of step S321;

[0039] Figure 6 A schematic diagram showing a merge result obtained by merging multiple target access paths provided by at least one embodiment of the present disclosure is shown;

[0040] Figure 7A At least one embodiment of the present disclosure provides Figure 4E Method flow chart of step S323;

[0041] Figure 7B At least one embodiment of the present disclosure provides Figure 7A Method flow chart of step S3232;

[0042] Figure 8 A schematic block diagram of a device for detecting deadlock loops in a network on chip (NOC) according to at least one embodiment of the present disclosure is shown;

[0043] Figure 9A A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0044] Figure 9B A schematic block diagram showing another electronic device provided by at least one embodiment of the present disclosure; and

[0045] Figure 10 A schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0046] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0048] Currently, there's no unified, standardized definition of NoC. One narrow definition defines NoC as a network architecture that enables communication between various modules on a chip, consisting of routing nodes, communication links, and network interfaces (NIs). Another broad definition defines NoC as an entire multiprocessor system on a single chip based on network communication, consisting of processing elements (PEs) and a communication network. Processing elements implement broad computing functions and can be microprocessor cores, storage units, or other functional components. The communication network, similar to the narrow definition of NoC, is responsible for interconnecting the PEs. In this article, NOC is defined in this broad sense.

[0049] Currently, the connectivity and data transmission between modules in a NoC system are primarily achieved through routing nodes (router) through various topological structures, providing transmission channels for each master device (master) to access each slave device (slave). In complex topologies, the overlapping of multiple access paths can form access loops within the NoC topology. If certain routing nodes in this access loop encounter transmission blockage during high-bandwidth data transmission for some reason, the cache within each routing node may be gradually consumed. Furthermore, due to the interdependence between the acquisition and release of cache resources required for packet transmission within each routing node, new cache resources cannot be obtained, resulting in an unresolved packet transmission blockage, a condition known as deadlock.

[0050] Detecting whether the topology structure and transmission path of NOC will form a deadlock loop is an essential step in NoC topology design and routing transmission path optimization.

[0051] Figure 1AShown is the basic structure of a NOC system.

[0052] like Figure 1A As shown, the NOC system includes a master device 1A, a master device 1B, a master device 5A, a routing node 1, a routing node 2, a slave device 1A, a slave device 1B, a slave device 2A, and a slave device 2B.

[0053] like Figure 1A As shown, master device 1A and master device 1B are connected to routing node 1, while master device 5A is connected to routing node 2. In an actual NoC system, these master devices (e.g., master device 1A, master device 1B, and master device 5A) can be CPU cores, direct memory access (DMA), and special algorithm modules, which are responsible for initiating read and write operation requests.

[0054] like Figure 1A As shown, slave devices 1A and 1B are connected to routing node 1, while slave devices 2A and 2B are connected to routing node 2. These slave devices can be input / output (IO) interfaces, storage devices such as double data rate (DDR), and display units. Routing nodes 1 and 2 also have separate ports connected to enable master devices 1A and 1B to access slave devices 2A and 2B. Based on the address information in the read / write request sent by the master device or the address information of the slave device, the routing node determines the output port of the read / write request through calculation or table lookup to ensure that the read / write request reaches the requested slave device. After receiving the read / write request and completing the corresponding operation, the slave device returns the response data and status information to the master device that initiated the read / write request through the routing node. The return route can be the original route or a different route based on the actual application requirements of the system.

[0055] Figure 1B A NOC network topology diagram is shown.

[0056] like Figure 1B As shown in the NOC network topology diagram, the oval icon represents the master device (L, M, N) that initiates data transmission, the circular icon represents the slave device (J, K, P) that receives the transmitted data, and the hexagonal icon, pentagonal icon and square icon in the figure represent router node devices (A, B, C, D, E, F, G, H). The dotted arrow line represents the transmission segment between non-routing nodes, and the solid arrow line represents the transmission segment between routing nodes.

[0057] It is important to understand that although Figure 1BDifferent icons and arrow lines are used to distinguish different devices and different transmission segments, but Figure 1B The different icons are only shown to facilitate understanding of the present disclosure. In actual NOC network topology diagrams, different transmission segments of different devices are often not distinguished.

[0058] For each path among all the paths for each master device to access each slave device, the transmission segment between each two adjacent device nodes (including routing nodes, master devices and slave devices, etc.) is uniquely named or numbered. For example, the transmission segment from M to A in the figure is named L_MA, or numbered 1. It should be noted that the transmission segment has a direction. For example, the transmission segment from H to A in the figure is numbered 13, but the transmission segment from A to H is numbered 14. Through the above method, the transmission segment formed by superimposing multiple access paths, for example Figure 1B The NoC access network topology shown names or numbers the transmission segments between all device nodes.

[0059] Due to the superposition of multiple access paths, the following Figure 1C The access loop shown is from A to E, F, H and then back to A. When some device nodes in the access loop encounter transmission obstruction for some reason during high-bandwidth data transmission, it is easy to cause the deadlock loop described in this article.

[0060] For deadlock detection, a full-path, level-by-level search method can be used. This method essentially superimposes all paths, searches for all routing nodes and their transmission ports, and numbers the transmission segments between each routing node. It then begins a level-by-level search from a routing node and marks the searched transmission segments. If the search reaches a dead end, the search proceeds level by level. If the searched transmission segment has already been marked, it indicates that a deadlock loop has formed in the transmission path.

[0061] Figure 1C Shown Figure 1B The deadlock loop formed by the NOC network topology diagram in .

[0062] like Figure 1C As shown in Figure 2, access paths A_E_F_H and F_H_A_E can lead to a deadlock loop. Figure 1B In the NOC network topology shown, the only nodes that can form a deadlock loop are A, E, F, and H.

[0063] The above-mentioned full-path step-by-step search method needs to search step by step according to the access path and traverse all nodes, resulting in a large amount of time and resources being wasted on invalid searches, slow search speed, and low efficiency.

[0064] At least one embodiment of the present disclosure provides a method, apparatus, electronic device, and computer-readable storage medium for detecting deadlock loops in a network on chip. The network on chip includes multiple routing nodes and multiple devices, and the method includes: determining multiple access paths between the multiple devices, each of the multiple access paths including a master device selected from one of the multiple devices, a slave device selected from one of the multiple devices, and at least one routing node from the multiple routing nodes for connecting the master device and the slave device; superimposing the multiple access paths, and identifying multiple valid routing nodes from the multiple routing nodes, wherein each of the multiple valid routing nodes in the multiple access paths is used to receive data from one of the multiple routing nodes and also to send data to one of the multiple routing nodes; and detecting whether a deadlock loop is caused by the multiple access paths based on the multiple valid routing nodes. This method can reduce the time overhead of detecting whether the multiple access paths cause a deadlock loop and improve detection efficiency.

[0065] Figure 2 A flowchart of a method for detecting a deadlock loop in an on-chip network provided by at least one embodiment of the present disclosure is shown.

[0066] like Figure 2 As shown, the method may include steps S10 to S30.

[0067] Step S10: Determine multiple access paths between multiple devices.

[0068] Step S20: Overlay multiple access paths and identify multiple valid routing nodes among the multiple routing nodes.

[0069] Step S30: Based on multiple valid routing nodes, detect whether a deadlock loop is caused by multiple access paths.

[0070] The detection method can identify multiple valid routing nodes from multiple access paths, and detect whether a deadlock loop is caused by multiple access paths based on multiple valid routing nodes, thereby eliminating the interference of invalid routing nodes that will not cause deadlock loops in multiple access paths on the detection of deadlock loops, thereby reducing the time and resource overhead on invalid searches, achieving the technical effect of improving detection efficiency and saving detection time and resources.

[0071] In some embodiments of the present disclosure, a network on chip includes a plurality of routing nodes and a plurality of devices.

[0072] For step S10, the plurality of devices may include at least one master device and at least one slave device. Each of the plurality of access paths includes a master device selected from one of the plurality of devices, a slave device selected from one of the plurality of devices, and at least one routing node for connecting the master device and the slave device from the plurality of routing nodes. For example, in Figure 1BIn the NOC network topology diagram shown, the multiple access paths may include an access path for the master device M to access the slave device K, an access path for the master device L to access the slave device J, and the like.

[0073] like Figure 2 As shown, the detection method includes steps S10 to S30 and further includes step S40. Step S40 can be performed before step S10, for example.

[0074] Step S40: Obtain routing information of the on-chip network.

[0075] In this embodiment, step S10 may be to determine multiple access paths between multiple devices based on routing information.

[0076] Routing information includes the access path for each master device to access each slave device in the network on chip. Therefore, by reading the routing information of the network on chip, multiple access paths to the network on chip can be obtained. For example, the routing information can be a routing table that records the access path for each master device to access each slave device.

[0077] For example, in Figure 1B The routing information of the NOC network topology diagram shown includes: the access path for the master device M to access the slave device K is MABCK, the access path for the master device M to access the slave device J is MAHJ, and the other access paths are as follows: Figure 1B As shown, not listed here one by one.

[0078] For step S20, for example, multiple access paths recorded in the routing information are superimposed to obtain Figure 1B The NOC network topology diagram is shown.

[0079] In step S20, in the plurality of access paths, each of the plurality of valid routing nodes is used to receive data from one of the plurality of routing nodes and is also used to send data to one of the plurality of routing nodes.

[0080] The inventors of this disclosure have discovered that routing nodes that can actually cause deadlock loops have a characteristic: these routing nodes are used to both receive data from one of the multiple routing nodes and send data to one of the multiple routing nodes. In this disclosure, routing nodes that meet the above characteristics are referred to as valid routing nodes, also known as cascaded routing nodes. That is, valid routing nodes are both the receiving end of the routing node at the previous level and the sending end of the routing node at the next level. For example, Figure 1B The routing nodes E, F, H, A and B in the diagram are used to receive data from one of the multiple routing nodes and to send data to one of the multiple routing nodes. Therefore, the routing nodes E, F, H, A and B are called valid routing nodes.

[0081] In this disclosure, routing nodes that cannot function as both receivers and transmitters are referred to as invalid routing nodes or non-cascade routing nodes. For example, routing nodes C, D, and G are only receivers for receiving data from other routing nodes or transmitters for sending data to other routing nodes, but cannot function as both transmitters and receivers. Therefore, routing nodes C, D, and G are invalid routing nodes.

[0082] Figure 3A At least one embodiment of the present disclosure provides Figure 2 Flowchart of the method for step S20 in FIG.

[0083] like Figure 3A As shown, the above step S20 may include steps S21 to S23.

[0084] Step S21: superimpose multiple access paths to obtain a superposition result.

[0085] For example, the overlay result can be a network topology map.

[0086] For example, based on overlapping device nodes (including routing nodes, master devices, slave devices, etc.) in the multiple access paths, the multiple access paths are combined into a network topology graph.

[0087] Step S22: for each routing node in the superposition result, determine whether the routing node is used to receive data from one of the plurality of routing nodes and to send data to one of the plurality of routing nodes.

[0088] For example, for each routing node in the network topology graph, it is determined whether the routing node is used to receive data from a routing node adjacent to and connected to the routing node, and whether the routing node is used to send data to another routing node adjacent to and connected to the routing node.

[0089] For example, determine Figure 1B Whether each routing node (A, B, C, D, E, F, G, H) in the network topology diagram shown is used to receive data from one of the multiple routing nodes and to send data to one of the multiple routing nodes.

[0090] Step S23: In response to the routing node being used to receive data from one of the plurality of routing nodes and being used to send data to one of the plurality of routing nodes, determining that the routing node belongs to a plurality of valid routing nodes.

[0091] For example, if routing node E is used to receive data from routing node A and routing node D and to send data to routing node F, then routing node E is a valid routing node. For another example, if routing node A is used to receive data from routing node H and to send data to routing node B or routing node H, then routing node A is a valid routing node. Similarly, routing node B, routing node F, and routing node H are also valid routing nodes.

[0092] For example, routing node C is only used to receive data from routing node D and routing node B, routing node D is only used to send data to routing node C and routing node E, and routing node G is only used to send data to routing node F. Therefore, routing node C, routing node D, and routing node G are invalid routing nodes.

[0093] In some embodiments of the present disclosure, Figure 3A shown Figure 2 In addition to steps S21 to S23 , the method of step S20 may further include: marking the superposition result according to the identified multiple valid routing nodes, so as to detect a deadlock loop based on the multiple valid routing nodes.

[0094] For example, valid routing nodes are marked by marking icons. The marking icons can be easily distinguished icons of any shape, color, etc.

[0095] Figure 3B The network topology diagram after marking the overlay results is shown.

[0096] like Figure 3B As shown, the hollow dashed icons represent the master or slave devices of the access path. They are not routing nodes and will not form a deadlock loop, such as device nodes L, M, N, P, J, and K in the figure. The hollow solid line icons represent routing nodes that only serve as receivers or transmitters. These routing nodes do not have the functions of both transmitters and receivers, so they do not have the ability to form a routing deadlock loop. They are also referred to as invalid routing nodes as mentioned above. Valid routing nodes that can form a routing deadlock loop are shown in the solid line icons, including routing nodes A, B, E, F, and H.

[0097] Figure 4A At least one embodiment of the present disclosure provides Figure 2 Flowchart of the method for step S30 in FIG.

[0098] like Figure 4A As shown, step S30 may include step S31 and step S32.

[0099] Step S31: Determine valid transmission segments between multiple valid routing nodes based on a superposition result obtained by superimposing multiple access paths. Each access path includes at least one transmission segment. A valid transmission segment is a transmission segment used to connect two valid routing nodes.

[0100] Step S32: Based on the valid transmission segment, detect whether a deadlock loop is caused by multiple access paths.

[0101] For step S31 , for example, the superposition result is directly analyzed, thereby searching for the valid transmission segment directly from the superposition result.

[0102] In other embodiments of the present disclosure, an access path subgraph of each access path is determined based on a superposition result obtained by superimposing multiple access paths, and each access path subgraph is analyzed to obtain a valid transmission segment in each access path subgraph.

[0103] The access path subgraph can be labeled with the valid routing nodes, so that the valid transmission segments in each access path subgraph can be determined based on the valid routing node labels. This allows for quick, simple, and accurate retrieval of valid transmission segments.

[0104] Figure 4B Shown Figure 1B The access path subgraph of the master device M; Figure 4C Shown Figure 1B The access path subgraph of the master device N in the middle; Figure 4D Shown Figure 1B The access path subgraph of the main device L in .

[0105] For example, for Figure 1B In the network topology shown in the figure, the master device M needs to access the slave devices K, J and P. Therefore, Figure 4B As shown, in the access path subgraph of the master device M, the master device M includes three access paths, which are used to access the slave device K, the slave device J, and the slave device P, respectively.

[0106] Similarly, master device N needs to access slave devices K and J. Therefore, if Figure 4C As shown in the access path subgraph of the master device N, the master device N has two access paths, which are used to access the slave device K and the slave device J. The master device L needs to access the slave device K, the slave device J, and the slave device P. Therefore, Figure 4D As shown, in the access path subgraph of the master device L, the master device L includes three access paths, which are used to access the slave device K, the slave device J, and the slave device P, respectively.

[0107] After obtaining the access path subgraph for each access path, the transmission segments in each access path subgraph can be marked to facilitate analysis of each access path subgraph, thereby obtaining valid transmission segments in each access path subgraph. For example, valid transmission segments can be distinguished and marked based on the two routing nodes of the transmission segment and the direction of transmission. For example, the transmission segment from routing node A to routing node B is marked as L_AB, the transmission segment from routing node B to routing node A is marked as L_BA, and the transmission segment from routing node F to routing node H is marked as L_FH.

[0108] For example, in the access path P1 from the master device M to the slave device K in the access path subgraph of the master device M, the transmission segment L_AB connects two valid routing nodes A and B. Therefore, the transmission segment L_AB is a valid routing transmission segment.

[0109] For another example, in the access path subgraph of the master device N, in the access path P4 from the master device N to the slave device K, there is no transmission segment connecting two valid routing nodes, and therefore there is no valid routing transmission segment in the access path P4.

[0110] Regarding step S32, the inventors of the present disclosure have found that only access paths of common transmission segments can form a deadlock loop. Figure 1B In the scenario shown, although access paths E_F_H and H_A_E share a common routing node, these two access paths do not form a deadlock loop. However, access paths A_E_F_H and F_H_A_E share a common transmission segment, allowing them to be merged into a single access path, potentially forming a deadlock loop. Based on this, at least one embodiment of the present disclosure provides a method for detecting whether a deadlock loop is caused by multiple access paths based on valid transmission segments.

[0111] Figure 4E At least one embodiment of the present disclosure provides Figure 4A Flowchart of the method for step S32 in FIG.

[0112] like Figure 4E As shown, step S32 may include steps S321 to S323.

[0113] Step S321: Determine multiple target access paths having the same valid transmission segment among the multiple access paths.

[0114] Step S322: Merge multiple target access paths to obtain an access path graph.

[0115] Step S323: Based on the access path graph, detect whether a deadlock loop is caused by multiple target access paths.

[0116] This method not only eliminates the interference of invalid routing nodes, but also merges target access paths with the same valid transmission segments, thereby screening out transmission segments that are unlikely to produce deadlock loops, further significantly reducing the number of routing nodes that need to be analyzed and improving detection efficiency.

[0117] For step S321, for example, each valid transmission segment is traversed to determine in which access paths the valid transmission segment exists. If the valid transmission segment exists in at least two access paths, the access path where the valid transmission segment exists is the target access path.

[0118] For example, in Figures 4B-4D In the scenario shown, the valid transmission segment L_AB exists in the access path P1 and the access path P8, and the access path P1 and the access path P8 are both target access paths.

[0119] For example, in Figures 4B-4D In the scenario shown, the access path P4 and the access path P6 do not have a common (or repeated) valid transmission segment, so the access path P4 and the access path P6 are not target access paths.

[0120] Figure 5 At least one embodiment of the present disclosure provides Figure 4E Flowchart of the method for step S321 in FIG.

[0121] like Figure 5 As shown, step S321 includes step S3211 and step S3212.

[0122] Step S3211: For each selected access path, search whether there is at least one valid transmission segment in the selected access path that exists in other access paths.

[0123] For example, the selected access path is an access path with a valid transmission segment. Figures 4B-4D The access paths P1, P2, P3, P5, P7 and P8 can be selected as access paths.

[0124] For example, each selected access path is traversed to determine whether each valid transmission segment in the selected access path exists in other access paths.

[0125] For example, the selected access path is P3, which includes a valid transmission segment L_AE and a valid transmission segment L_EF. Only access path P3 contains the valid transmission segment L_AE; no other access paths contain the valid transmission segment L_AE. However, the valid transmission segment L_EF exists not only in access path P3 but also in access path P5.

[0126] For another example, the selected access path is P2, and the selected access path P2 includes a valid transmission segment L_AH. Only the selected access path P2 has the valid transmission segment L_AH, that is, no other access paths include the valid transmission segment L_AH.

[0127] In some embodiments of the present disclosure, step S3211 may include: determining, based on each selected access path, an access path set for each valid transmission segment in the selected access path, where the elements in the access path set are the access paths containing the valid transmission segments; and, in response to the presence of multiple elements in the access path set for at least one valid transmission segment in the selected access path, determining whether the at least one valid transmission segment exists in other access paths. This method can accurately and quickly determine whether each valid transmission segment exists in multiple access paths.

[0128] For example, for a valid transmission segment L_FH, if access paths P5, P7, and P8 all include it, then an access path set L_FH = {P5, P7, P8} can be established. Similarly, according to this rule, an access path set can be established for each valid transmission segment between valid routing nodes. If there are multiple elements in the access path set, it is determined that the valid transmission segment exists in multiple access paths, that is, it is determined that at least one valid transmission segment also exists in other access paths. In some embodiments of the present disclosure, the access path set can be represented by an array.

[0129] In some embodiments of the present disclosure, if a valid transmission segment in a currently selected access path has already been determined in an access path set in a previously selected access path, then the valid transmission segment in the currently selected access path may be skipped to further improve detection efficiency.

[0130] Step S3212: In response to at least one valid transmission segment in the selected access path existing in other access paths, determine that the selected access path is the target access path.

[0131] For example, since the selected access path P3 has at least one valid transmission segment (ie, valid transmission segment L_EF) existing in another access path (ie, access path P5), the selected access path P3 is the target access path.

[0132] For another example, since all valid transmission segments in the selected access path P2 do not exist in other access paths, the access path P2 is not the target access path.

[0133] Of course, those skilled in the art can also determine the target access path in other feasible ways, not limited to Figure 5 The method shown.

[0134] For step S322, for example, if access paths P1, P3, P5, P7, and P8 are target access paths having the same transmission segment, the target access paths P1, P3, P5, P7, and P8 are merged to obtain an access path graph.

[0135] Figure 6 A schematic diagram illustrating a merging result obtained by merging multiple target access paths provided by at least one embodiment of the present disclosure is shown.

[0136] like Figure 6 As shown, the merge result 600 includes the access path graph 610 , the access path P2 , and the access path P4 .

[0137] The access path graph 610 is obtained by merging access paths P1, P3, P5, P7, and P8. Access paths P2 and P4 cannot be merged with other access paths.

[0138] As described above, since only access paths with a common transmission segment may cause a deadlock loop, when detecting whether multiple access paths cause a deadlock loop, it is only necessary to determine whether the access path graph 610 causes a deadlock loop, without considering access paths P2 and P4.

[0139] In step S323, it is determined whether the access path graph 610 causes a deadlock loop. If the access path graph 610 can cause a deadlock loop, then multiple access paths can cause a deadlock loop.

[0140] In some embodiments of the present disclosure, there are multiple access path graphs. Step S323 includes: detecting, based on each access path graph, whether a deadlock loop is caused by multiple target access paths in each access path graph.

[0141] For example, after merging multiple target access paths in step S322 to obtain multiple access path graphs, each access path graph is analyzed separately to detect whether a deadlock loop is caused by the multiple target access paths in each access path graph.

[0142] For example, assuming that there is another access path P9, and the access path P9 and the access path P4 can be merged into another access path graph, the merging result of step S322 includes two access path graphs. Then, in step S323, the access path graph 610 and the other access path graph obtained by merging the access path P9 and the access path P4 are analyzed respectively to detect whether a deadlock loop is caused by multiple target access paths.

[0143] Figure 7A At least one embodiment of the present disclosure provides Figure 4E Flowchart of the method for step S323 in FIG.

[0144] like Figure 7A As shown, step S323 may include steps S3231 to S3234.

[0145] Step S3231: Determine the next level routing node of each valid routing node in the access path graph. The next level routing node is a routing node adjacent to the valid routing node, and the valid routing node is used to send data to the next level routing node.

[0146] Step S3232: Determine a first number of valid routing nodes among the next-level routing nodes of all valid routing nodes in the access path graph.

[0147] Step S3233: Determine the second number of all valid routing nodes in the access path graph.

[0148] Step S3234: In response to the first number being equal to the second number, determining that the plurality of target access paths can lead to a deadlock loop.

[0149] This method can conclude whether a deadlock loop exists by calculating whether the number of valid routing nodes is equal to the number of valid routing nodes in the next level of routing nodes, without the need for repeated level-by-level searches, which greatly reduces the detection time.

[0150] For step S3231, for example, as described above, all valid routing nodes in access path graph 610 include routing node A, routing node B, routing node E, routing node F, and routing node H.

[0151] A next-level routing node is, for example, a routing node adjacent to an active routing node and configured to receive data from the active routing node. For example, the next-level routing nodes of active routing node A include routing node B and routing node E. For example, the next-level routing nodes of active routing node B include routing node C.

[0152] Regarding step S3232, in some embodiments of the present disclosure, for example, the next-level routing nodes of each valid routing node may be formed into a next-level routing node set. Then, for each next-level routing node set, each routing node in the next-level routing node set is identified to determine whether the routing node is a valid routing node. If the routing node is not a valid routing node, the routing node is deleted from the next-level routing node set, thereby obtaining a next-level node set. Next, the total number of elements in all next-level node sets is counted to obtain a first number.

[0153] Figure 7B At least one embodiment of the present disclosure provides Figure 7A Flowchart of the method for step S3232 in FIG.

[0154] like Figure 7B As shown, the method includes steps S701 to S703.

[0155] Step S701: In response to the type of the next-level routing node of each valid routing node in the access path graph being a valid routing node, the next-level routing node is added to the next-level node set, thereby obtaining the next-level node set of each valid routing node.

[0156] Step S702: Merge the elements in the next-level node set of each valid routing node to obtain a final set.

[0157] Step S703: The number of elements in the final set is taken as the first number.

[0158] For step S701, for example, the next-level routing node of each valid routing node is analyzed to determine whether the next-level routing node is a valid routing node, or the marking icon of the next-level routing node is directly read. If the marking icon is a marking icon of a valid routing node (for example, a hexagonal icon), the next-level routing node is determined to be a valid routing node.

[0159] For example, if the next-level valid routing nodes of routing node A are B and E, then the next-level node set of routing node A is {B, E}. If there is no valid routing node in the next level of valid routing node B, then the next-level node set of valid routing node B is empty. If the next-level valid routing node of valid routing node E is F, then the next-level node set of routing node E is {F}. Similarly, the next-level node set of valid routing node F can be determined to be {H}, and the next-level node set of valid routing node H can be determined to be {A}.

[0160] For step S702, for example, the valid routing nodes of the merged access path 610 are A, B, E, F, and H, a total of 5 routing nodes. The next-level node sets of these 5 nodes are {B, E}, {}, {F}, {H}, and {A}, respectively. After merging the array elements in all the next-level node sets, the final set Z = {B, E, F, H, A} is obtained.

[0161] For step S703 , for example, the final set Z={B, E, F, H, A} has 5 elements, so the first quantity is 5.

[0162] For step S3233, for example, as described above, all valid routing nodes in the access path graph 610 are A, B, E, F, and H, which are five routing nodes in total. Therefore, the second number is five.

[0163] In step S3234, if the first number is equal to the second number, it is determined that the multiple target access paths can cause a deadlock loop.

[0164] By analyzing the network topology, the inventors discovered that the number of valid routing nodes in an access path graph with a deadlock loop is equal to the number of elements in the node set next to the valid routing node. Specifically, assuming that there are n valid routing nodes in the merged access path, if a routing deadlock loop exists, the number of elements in the node set next to the valid routing node is also n. If there is no loop, the number of elements in the node set next to the valid routing node is less than n. n is an integer greater than 0.

[0165] by Figure 6 For example, the second number of valid routing nodes in the merged access path graph 610 is 5, and the first number is 5. Therefore, a routing deadlock loop exists in access path graph 610. In access path P2, valid routing nodes A and H are valid. A's next-level node set is {H}, and routing node H has no next-level routing nodes, so its next-level node set is empty. Therefore, the number of valid routing nodes is 2, but the number of elements in the next-level node set is 1. Therefore, there is no routing deadlock loop in access path P2.

[0166] Figure 8 A schematic block diagram of a device 800 for detecting deadlock loops in a network on chip (NOC) according to at least one embodiment of the present disclosure is shown.

[0167] For example, Figure 8 As shown, the detection apparatus 800 includes a path determination unit 810, an identification unit 820, and a detection unit 830. The network on chip includes a plurality of routing nodes and a plurality of devices.

[0168] The path determination unit 810 is configured to determine multiple access paths between the multiple devices, each of the multiple access paths including a master device selected from one of the multiple devices, a slave device selected from one of the multiple devices, and at least one routing node from the multiple routing nodes for connecting the master device and the slave device.

[0169] The path determination unit 810 may, for example, execute Figure 2 Step S10 is described.

[0170] The identification unit 820 is configured to superimpose the multiple access paths and identify multiple valid routing nodes among the multiple routing nodes, wherein, in the multiple access paths, the valid routing node is used to receive data from one of the multiple routing nodes and also to send data to one of the multiple routing nodes.

[0171] The identification unit 820 may, for example, execute Figure 2 Step S20 is described.

[0172] The detection unit 830 is configured to detect, based on the multiple valid routing nodes, whether the multiple access paths cause the deadlock loop.

[0173] The detection unit 830 may, for example, perform Figure 2 Step S30 is described.

[0174] The detection device 800 can reduce the time overhead of detecting whether multiple access paths lead to deadlock loops, thereby improving detection efficiency.

[0175] For example, in a detection device provided in an embodiment of the present disclosure, the detection unit includes a valid transmission segment determination subunit and a deadlock detection subunit. The valid transmission segment determination subunit is configured to determine valid transmission segments between the multiple valid routing nodes based on a superposition result obtained by superimposing the multiple access paths, where each access path includes at least one transmission segment, and a transmission segment connecting two valid routing nodes is a valid transmission segment. The deadlock detection subunit is configured to detect whether the multiple access paths cause the deadlock loop based on the valid transmission segments.

[0176] For example, in a detection device provided in an embodiment of the present disclosure, a deadlock detection subunit includes: a target path determination subunit, a merging subunit, and a deadlock loop detection subunit. The target path determination subunit is configured to determine multiple target access paths having the same valid transmission segment among the multiple access paths. The merging subunit is configured to merge the multiple target access paths to obtain an access path graph. The deadlock loop detection subunit is configured to detect, based on the access path graph, whether the deadlock loop is caused by the multiple target access paths.

[0177] For example, in a detection device provided in an embodiment of the present disclosure, a target path determination subunit includes: a search subunit and a target determination subunit. The search subunit is configured to search, for each selected access path, whether at least one valid transmission segment in the selected access path exists in another access path. The target determination subunit is configured to determine that the selected access path is a target access path in response to at least one valid transmission segment in the selected access path existing in another access path.

[0178] For example, in a detection device provided in an embodiment of the present disclosure, the search subunit includes a path set determination subunit and a judgment subunit. The path set determination subunit is configured to determine, based on each selected access path, an access path set for each valid transmission segment in the selected access path, where the elements in the access path set are the access paths that contain the valid transmission segments. The judgment subunit is configured to, in response to the presence of multiple elements in the access path set for at least one valid transmission segment in the selected access path, determine that the at least one valid transmission segment exists in other access paths.

[0179] For example, in the detection device provided in an embodiment of the present disclosure, the deadlock loop detection subunit includes: a first determination subunit, a second determination subunit, a third determination subunit, and a fourth determination subunit. The first determination subunit is configured to determine the next-level routing node of each valid routing node in the access path graph, the next-level routing node being a routing node adjacent to the valid routing node, and the valid routing node is used to send data to the next-level routing node. The second determination subunit is configured to determine a first number of the next-level routing nodes of all valid routing nodes in the access path graph that are of the type of valid routing nodes. The third determination subunit is configured to determine a second number of all valid routing nodes in the access path graph. The fourth determination subunit is configured to determine, in response to the first number being equal to the second number, that the multiple target access paths can cause the deadlock loop.

[0180] For example, in the detection device provided in one embodiment of the present disclosure, the second determination subunit includes a next-level node set generation subunit, a merging subunit, and a statistical subunit. The next-level node set generation subunit is configured to, in response to the type of the next-level routing node of each valid routing node in the access path graph being a valid routing node, add the next-level routing node to the next-level node set, thereby obtaining the next-level node set of each valid routing node. The merging subunit is configured to merge the elements in the next-level node set of each valid routing node to obtain a final set. The statistical subunit is configured to use the number of elements in the final set as the first number.

[0181] For example, in a detection device provided in an embodiment of the present disclosure, the identification unit includes a superposition subunit, a fifth determination subunit, and a response subunit. The superposition subunit is configured to superimpose the multiple access paths to obtain a superposition result. The fifth determination subunit is configured to determine, for each routing node in the superposition result, whether the routing node is used to receive data from one of the multiple routing nodes and to send data to one of the multiple routing nodes. The response subunit is configured to determine that the routing node belongs to the multiple valid routing nodes in response to the routing node being used to receive data from one of the multiple routing nodes and to send data to one of the multiple routing nodes.

[0182] For example, in the detection device provided in an embodiment of the present disclosure, the deadlock loop detection subunit includes a loop detection subunit configured to detect, based on each access path graph, whether the deadlock loop is caused by the multiple target access paths in each access path graph.

[0183] For example, in a detection device provided in an embodiment of the present disclosure, the device further includes an acquisition unit configured to acquire routing information of the on-chip network. The path determination unit includes a path determination subunit configured to determine the multiple access paths between the multiple devices based on the routing information.

[0184] For example, the path determination unit 810, the identification unit 820, and the detection unit 830 may be hardware, software, firmware, or any feasible combination thereof. For example, the path determination unit 810, the identification unit 820, and the detection unit 830 may be dedicated or general-purpose circuits, chips, or devices, or may be a combination of a processor and memory. The embodiments of the present disclosure do not limit the specific implementation of each of the above units.

[0185] It should be noted that, in the embodiment of the present disclosure, each unit of the detection device 800 corresponds to each step of the aforementioned detection method. For the specific functions of the detection device 800, reference can be made to the relevant description of the detection method, which will not be repeated here. Figure 8 The components and structures of the detection device 8000 shown are merely exemplary and non-limiting. The detection device 800 may further include other components and structures as needed.

[0186] At least one embodiment of the present disclosure further provides an electronic device comprising a processor and a memory, wherein the memory includes one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the above-described detection method. This electronic device can reduce the time overhead of detecting whether multiple access paths result in a deadlock loop, thereby improving detection efficiency.

[0187] Figure 9A This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 9A As shown, the electronic device 900 includes a processor 910 and a memory 920. The memory 920 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 910 is used to execute the non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by the processor 910, one or more steps in the detection method described above can be performed. The memory 920 and the processor 910 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0188] For example, the processor 910 may be a central processing unit (CPU), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X96 or ARM architecture. The processor 910 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 900 to perform desired functions.

[0189] For example, the memory 920 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 910 may execute one or more computer program modules to implement various functions of the electronic device 900. Various applications and various data, as well as various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0190] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 900 can be referred to the description of the detection method above, and will not be repeated here.

[0191] Figure 9B This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 1000 is suitable for implementing the detection method provided in the embodiments of the present disclosure. The electronic device 1000 may be a terminal device, etc. It should be noted that, Figure 9B The electronic device 1000 shown is merely an example and does not limit the functions and scope of use of the embodiments of the present disclosure.

[0192] like Figure 9B As shown, the electronic device 1000 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1010, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1020 or a program loaded from a storage device 1080 into a random access memory (RAM) 1030. Various programs and data required for the operation of the electronic device 1000 are also stored in the RAM 1030. The processing device 1010, the ROM 1020, and the RAM 1030 are connected to each other via a bus 1040. An input / output (I / O) interface 1050 is also connected to the bus 1040.

[0193] Typically, the following devices may be connected to the I / O interface 1050: an input device 1060 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1070 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1080 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1090. The communication device 1090 may allow the electronic device 1000 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 9B The electronic device 1000 is shown as having various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 1000 may alternatively implement or possess more or fewer devices.

[0194] For example, according to an embodiment of the present disclosure, the above-mentioned detection method can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the above-mentioned detection method. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 1090, or installed from the storage device 1080, or installed from the ROM 1020. When the computer program is executed by the processing device 1010, the functions defined in the detection method provided in the embodiment of the present disclosure can be implemented.

[0195] At least one embodiment of the present disclosure further provides a computer-readable storage medium for storing non-transitory computer-readable instructions. When executed by a computer, the non-transitory computer-readable instructions can implement the aforementioned detection method. Using this computer-readable storage medium can reduce the time overhead of detecting whether multiple access paths result in deadlock loops, thereby improving detection efficiency.

[0196] Figure 10 A schematic diagram of a storage medium provided in some embodiments of the present disclosure. Figure 10 As shown, the storage medium 1100 is used to store non-transitory computer-readable instructions 1110. For example, when the non-transitory computer-readable instructions 1110 are executed by a computer, one or more steps in the detection method described above may be performed.

[0197] For example, the storage medium 1100 may be applied to the electronic device 900. Figure 9A The memory 920 in the electronic device 900 is shown. For example, the description of the storage medium 1100 can be referred to Figure 9A The corresponding description of the memory 920 in the electronic device 900 is not repeated here.

[0198] There are a few points to note:

[0199] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0200] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0201] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for detecting deadlock loops in a network on chip, wherein: The network on chip includes a plurality of routing nodes and a plurality of devices, and the method includes: Determining a plurality of access paths between the plurality of devices, wherein each of the plurality of access paths includes a master device selected from one of the plurality of devices, a slave device selected from one of the plurality of devices, and at least one routing node among the plurality of routing nodes for connecting the master device and the slave device; overlaying the plurality of access paths and identifying a plurality of valid routing nodes among the plurality of routing nodes, wherein, in the plurality of access paths, the plurality of valid routing nodes are each configured to receive data from one of the plurality of routing nodes and also to send data to one of the plurality of routing nodes; and Based on the multiple valid routing nodes, detecting whether the multiple access paths cause the deadlock loop, Wherein, based on the multiple valid routing nodes, detecting whether the multiple access paths cause the deadlock loop includes: Determining valid transmission segments between the multiple valid routing nodes based on a superposition result obtained by superimposing the multiple access paths, wherein each access path includes at least one transmission segment, and the valid transmission segment is a transmission segment for connecting two valid routing nodes; and Based on the valid transmission segment, detecting whether the deadlock loop is caused by the multiple access paths, Detecting, based on the valid transmission segment, whether the deadlock loop is caused by the multiple access paths includes: determining a plurality of target access paths having the same valid transmission segment among the plurality of access paths; Merging the multiple target access paths to obtain an access path graph; Based on the access path graph, it is detected whether the deadlock loop is caused by the multiple target access paths.

2. The method according to claim 1, wherein Determining the plurality of target access paths having the same valid transmission segment among the plurality of access paths includes: For each selected access path, searching whether at least one valid transmission segment in the selected access path exists in other access paths; and In response to at least one valid transmission segment in the selected access path existing in the other access paths, the selected access path is determined to be the target access path.

3. The method according to claim 2, wherein: For each selected access path, searching whether at least one valid transmission segment in the selected access path exists in other access paths includes: Based on each selected access path, determining an access path set for each valid transmission segment in the selected access path, wherein an element in the access path set is each access path containing the valid transmission segment; and In response to the presence of a plurality of elements in the access path set of at least one valid transmission segment in the selected access path, it is determined that the at least one valid transmission segment exists in other access paths.

4. The method according to claim 1, wherein Detecting, based on the access path graph, whether the deadlock loop is caused by the multiple target access paths includes: Determining a next-level routing node for each valid routing node in the access path graph, wherein the next-level routing node is a routing node adjacent to the valid routing node, and the valid routing node is used to send data to the next-level routing node; Determine a first number of valid routing nodes among the next-level routing nodes of all valid routing nodes in the access path graph; Determining a second number of all valid routing nodes in the access path graph; and In response to the first number being equal to the second number, it is determined that the plurality of target access paths can cause the deadlock loop.

5. The method according to claim 4, wherein Determining a first number of valid routing nodes among the next-level routing nodes of all valid routing nodes in the access path graph includes: In response to the type of the next-level routing node of each valid routing node in the access path graph being a valid routing node, adding the next-level routing node to the next-level node set, thereby obtaining a next-level node set of each valid routing node; Merging the elements in the next-level node set of each valid routing node to obtain a final set; and The number of elements in the final set is taken as the first number.

6. The method according to claim 1, wherein Superimposing the plurality of access paths and identifying the plurality of valid routing nodes among the plurality of routing nodes comprises: superimposing the multiple access paths to obtain a superposition result; For each routing node in the superposition result, determining whether the routing node is used to receive data from one of the plurality of routing nodes and to send data to one of the plurality of routing nodes; and In response to the routing node being operable to receive data from one of the plurality of routing nodes and to transmit data to one of the plurality of routing nodes, it is determined that the routing node belongs to the plurality of valid routing nodes.

7. The method according to claim 1, wherein There are multiple access path graphs. Detecting, based on the access path graph, whether the deadlock loop is caused by the multiple target access paths includes: Based on each access path graph, it is detected whether the deadlock loop is caused by the multiple target access paths in each access path graph.

8. The method according to claim 1, wherein Determining the valid transmission segments between the multiple valid routing nodes according to a superposition result obtained by superimposing the multiple access paths includes: determining an access path subgraph for each of the plurality of access paths according to a superposition result obtained by superimposing the plurality of access paths; Each of the access path subgraphs is analyzed to obtain the valid transmission segments between the multiple valid routing nodes.

9. The method according to claim 1, further comprising: Obtaining routing information of the on-chip network; Determining the plurality of access paths between the plurality of devices includes: Based on the routing information, the multiple access paths between the multiple devices are determined.

10. A device for detecting deadlock loops in a network on chip, wherein: The network on chip includes multiple routing nodes and multiple devices, and the apparatus includes: a path determination unit configured to determine a plurality of access paths between the plurality of devices, wherein each of the plurality of access paths includes a master device selected from one of the plurality of devices, a slave device selected from one of the plurality of devices, and at least one routing node among the plurality of routing nodes for connecting the master device and the slave device; an identification unit configured to superimpose the plurality of access paths and identify a plurality of valid routing nodes among the plurality of routing nodes, wherein, in the plurality of access paths, each of the plurality of valid routing nodes is used to receive data from one of the plurality of routing nodes and is also used to send data to one of the plurality of routing nodes; and a detection unit configured to detect, based on the multiple valid routing nodes, whether the multiple access paths cause the deadlock loop; Wherein, the detection unit includes: an effective transmission segment determination subunit, configured to determine effective transmission segments between the multiple effective routing nodes based on a superposition result obtained by superimposing the multiple access paths, wherein each access path includes at least one transmission segment, and the effective transmission segment is a transmission segment for connecting two effective routing nodes; and a deadlock detection subunit configured to detect, based on the valid transmission segment, whether the deadlock loop is caused by the multiple access paths; The deadlock detection subunit includes: a target path determination subunit, configured to determine a plurality of target access paths having the same valid transmission segment among the plurality of access paths; a merging subunit, configured to merge the multiple target access paths to obtain an access path graph; The deadlock loop detection subunit is configured to detect, based on the access path graph, whether the deadlock loop is caused by the multiple target access paths.

11. An electronic device comprising: processor; a memory comprising one or more computer program instructions; The one or more computer program instructions are stored in the memory and, when executed by the processor, implement the method for detecting a deadlock loop in an on-chip network according to any one of claims 1 to 9.

12. A computer-readable storage medium non-transitorily storing computer-readable instructions, wherein: When the computer-readable instructions are executed by a processor, the method for detecting a deadlock loop in an on-chip network according to any one of claims 1 to 9 is implemented.

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