A method, system, storage medium and device for controlling the construction of a page linked list

Abstract

The present invention provides a method for constructing a control page linked list, characterized in that it includes the following steps: constructing a common control page to include a 128-byte control page header area, a control block storage area of ​​several bytes, a 64-byte data cache pointer area and a 64-byte original NVMe management and IO instruction backup area; and constructing a chained control page to include a 64-byte control page header area and a control block storage area of ​​several bytes, wherein the control page header area of ​​the common control page includes an 8-byte address pointer pointing to the next chained control page, the control page header area of ​​the chained control page includes three 8-byte chain pointers, which respectively point to the first common control page, the previous control page, and the next chained control page, and the common control page and the chained control page constituting the control page linked list are the same size.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, system, storage medium and device for constructing a control page linked list based on a general computing acceleration architecture. Background Art

[0002] With the rise of computational storage technology in recent years, the computational storage architecture reduces the corresponding data movement operations by offloading data calculations from the host CPU to the data processing acceleration unit close to the storage unit, thereby releasing system performance as much as possible.

[0003] Computational storage introduces three product forms: computational storage processor (CSP), computational storage drive (CSD) and computational storage array (CSA), and expects to redefine the architecture to achieve

[0004] Reduce CPU usage;

[0005] Reduce network and DDR bandwidth consumption;

[0006] Reduce system power consumption;

[0007] Supports potentially large-scale parallel computing processing, etc.

[0008] The core idea of ​​the Universal Computing Acceleration Architecture (UAA) is to optimize the software and hardware interface division through micro-architecture innovation and microcode-driven approach, while taking into account the high performance of hardware execution and maintaining the high flexibility and scalability of software programmability. In the architecture definition of UAA, the size of the control page (hereinafter sometimes referred to as "CP") can be 512 bytes, 1024 bytes or 2048 bytes. In addition to the CP header, data cache and original host IO instruction backup, the remaining space is used to store the control block (hereinafter sometimes referred to as "CB"), see Figure 6 All CPs are placed in a continuous memory space, thus forming a CP resource pool. In addition, in order to facilitate the management of the CP resource pool, the CP granularity in a single resource pool needs to be consistent, that is, only one CP size can be selected.

[0009] The size of CB can be 16 bytes, 32 bytes, 64 bytes and 128 bytes depending on the application engine type. In this way, the number of CBs that can be carried in a single CP is determined by the size of the CP and the size of the CB. In some complex application scenarios, if the lengths of the CB chains corresponding to different types of IO are too different, the selection of the CP size will cause certain difficulties. If it is too small, it will not be able to carry a long CB chain; on the contrary, if the granularity of the CP is too large, it will cause a certain waste of CP resources. Summary of the invention

[0010] In view of this, the purpose of the present invention is to propose a method, system, storage medium and device for constructing a control page linked list based on a general computing acceleration architecture, so as to solve the shortcomings of the existing control page construction method and system.

[0011] Based on the above purpose, the present invention provides a method for constructing a control page linked list based on a general computing acceleration architecture, comprising the following steps:

[0012] Constructing a common control page to include a 128-byte control page header area, a control block storage area of ​​several bytes, a 64-byte data cache pointer area, and a 64-byte original NVMe (non-volatile memory host controller interface specification) management and IO instruction backup area; and

[0013] Construct a chain control page that includes a 64-byte control page header area and several bytes of control block storage area.

[0014] The control page header area of ​​the common control page includes an 8-byte address pointer pointing to the next chain control page.

[0015] The control page header area of ​​the chain control page includes three 8-byte chain pointers, which point to the first common control page, the previous control page, and the next chain control page respectively, and

[0016] The common control pages and the chained control pages constituting the control page chain list have the same size.

[0017] In some embodiments, the control page header area of ​​the ordinary control page also includes: 8 bytes of control page attributes, which are used to identify the type of control page, and identify whether the control page is located in the control page linked list, and its position in the linked list; 8 bytes of the current control page serial number, which is specified when the control page is created; 8 bytes of NVMe queue related information, which includes a 2-byte completion queue ID, a 2-byte submission queue ID, and a 4-byte training queue header information; a 4-byte timestamp, which is used to record the key time nodes in the execution process of the ordinary control page; and 64 bytes of firmware reserved space.

[0018] In some embodiments, the control page header area of ​​the linked control page also includes: an 8-byte control page attribute, which is used to identify the type of the control page, and whether the control page is located in the control page linked list, and its position in the linked list; and 4 8-byte timestamps, which are used to record key time nodes during the execution of the linked control page.

[0019] In some embodiments, the sizes of the common control page and the chain control page are 512 bytes, 1K bytes or 2K bytes respectively, the size of the control block storage area of ​​the common control page is correspondingly 256 bytes, 768 bytes or 1792 bytes, and the size of the control block storage area of ​​the chain control page is correspondingly 448 bytes, 960 bytes or 1984 bytes. The size of the control block is 16 bytes, 32 bytes, 64 bytes or 128 bytes.

[0020] In some embodiments, the control block includes an 8-bit cbPosition for identifying the position of the control block in a common control page, a chained control page, or a control page chain list.

[0021] The calculation formula for the relative position of the control block in the common control page, chain control page or control page chain list is as follows:

[0022]

[0023] cpResolution: controls the page size;

[0024] cpOffset: The quotient obtained indicates the position of the control page where the control block is located in the control page list;

[0025] cbOffset: The remainder obtained indicates the relative position of the control block in the control page.

[0026] Another aspect of the present invention further provides a system for constructing a control page linked list based on a general computing acceleration architecture, comprising:

[0027] A common control page component module, used to construct a common control page, including a 128-byte control page header area, a control block storage area of ​​several bytes, a 64-byte data cache pointer area, and a 64-byte original NVMe management and IO instruction backup area; and

[0028] The chain control page construction module is used to construct the chain control page, which includes a 64-byte control page header area and a control block storage area of ​​several bytes.

[0029] The control page header area of ​​the common control page includes an 8-byte address pointer pointing to the next chain control page.

[0030] The control page header area of ​​the chain control page includes three 8-byte chain pointers, which point to the first common control page, the previous control page, and the next chain control page respectively, and

[0031] The common control pages and the chained control pages constituting the control page chain list have the same size.

[0032] In some embodiments, the control page header area of ​​the ordinary control page also includes: 8 bytes of control page attributes, which are used to identify the type of control page, and identify whether the control page is located in the control page linked list, and its position in the linked list; 8 bytes of the current control page serial number, which is specified when the control page is created; 8 bytes of NVMe queue related information, which includes a 2-byte completion queue ID, a 2-byte submission queue ID, and a 4-byte training queue header information; a 4-byte timestamp, which is used to record the key time nodes in the execution process of the ordinary control page; and 64 bytes of firmware reserved space.

[0033] In some embodiments, the control page header area of ​​the linked control page also includes: an 8-byte control page attribute, which is used to identify the type of the control page, and whether the control page is located in the control page linked list, and its position in the linked list; and 4 8-byte timestamps, which are used to record key time nodes during the execution of the linked control page.

[0034] In some embodiments, the sizes of the common control page and the chain control page are 512 bytes, 1K bytes or 2K bytes respectively, the size of the control block storage area of ​​the common control page is correspondingly 256 bytes, 768 bytes or 1792 bytes, and the size of the control block storage area of ​​the chain control page is correspondingly 448 bytes, 960 bytes or 1984 bytes. The size of the control block is 16 bytes, 32 bytes, 64 bytes or 128 bytes.

[0035] In some embodiments, the control block includes an 8-bit cbPosition for identifying the position of the control block in a common control page, a chained control page, or a control page chain list.

[0036] The calculation formula for the relative position of the control block in the common control page, chain control page or control page chain list is as follows:

[0037]

[0038] cpResolution: controls the page size;

[0039] cpOffset: The quotient obtained indicates the position of the control page where the control block is located in the control page list;

[0040] cbOffset: The remainder obtained, indicating the relative position of the control block in the control page.

[0041] According to another aspect of the present invention, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions implement any one of the above methods when executed.

[0042] According to another aspect of the present invention, a computer device is provided, comprising a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, any one of the above methods is executed.

[0043] The present invention proposes a method and system for constructing a control page linked list based on a general computing acceleration architecture. By introducing the concept of a CP linked list, the scalability and resource utilization efficiency of the computing acceleration architecture are further improved, and it can cope with complex and multi-type task mixed application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A schematic diagram of a method for constructing a control page linked list based on a general computing acceleration architecture provided according to an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of a system for constructing a control page linked list based on a general computing acceleration architecture according to an embodiment of the present invention;

[0047] Figure 3 A schematic diagram of an example of a control page linked list based on a general computing acceleration architecture provided according to an embodiment of the present invention;

[0048] Figures 4(a) to 4(c) A flowchart of the engine searching the CP linked list is shown, wherein FIG4(a) shows the flowchart when searching for a common data cache pointer area, FIG4(b) shows the flowchart when preparing the address pointer of the next CB, and FIG4(c) shows the flowchart when updating the timestamp information.

[0049] Figure 5 A schematic diagram of a computer-readable storage medium for implementing a method for constructing a control page linked list based on a general computing acceleration architecture according to an embodiment of the present invention;

[0050] Figure 6A schematic diagram of the hardware structure of a computer device for executing a method for constructing a control page linked list based on a general computing acceleration architecture provided in accordance with an embodiment of the present invention;

[0051] Figure 7 The diagram is a schematic diagram of an example of a control page in the prior art. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0053] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product or device that includes a series of steps or units.

[0054] Based on the above objectives, a first aspect of an embodiment of the present invention provides an embodiment of a method for constructing a control page linked list based on a general computing acceleration architecture. Figure 1 FIG. 2 is a schematic diagram of an embodiment of a method for constructing a control page linked list based on a general computing acceleration architecture provided by the present invention. Figure 1 As shown, the embodiment of the present invention includes the following steps:

[0055] Step S10, construct a common control page, including a 128-byte control page header area, a control block storage area of ​​several bytes, a 64-byte data cache pointer area, and a 64-byte original NVMe management and IO instruction backup area;

[0056] Step S20: construct a chain control page, including a 64-byte control page header area and a control block storage area of ​​several bytes.

[0057] Among them, the control page header area of ​​the common control page includes an 8-byte address pointer pointing to the next chained control page, and the control page header area of ​​the chained control page includes three 8-byte chain pointers, which point to the first common control page, the previous control page, and the next chained control page respectively, and the common control pages and chained control pages that constitute the control page linked list are the same size.

[0058] The data cache pointer area is used to point to the public data cache area. The original NVMe management and IO instruction backup area facilitates firmware intervention for error recovery when an exception occurs.

[0059] The present invention uses 8-byte (64-bit wide) addresses, but 4-byte (32-bit wide) addresses may also be used.

[0060] As shown in Table 1, the control page header area of ​​the common control page also includes: 8 bytes of control page attributes, which are used to identify the type of control page, and whether the control page is located in the control page linked list, and its position in the linked list; 8 bytes of the current control page serial number, which is specified when the control page is created; 8 bytes of NVMe queue related information, including 2 bytes of completion queue ID, 2 bytes of submission queue ID and 4 bytes of training queue header information; 4 bytes of timestamp, which is used to record the key time nodes in the execution process of the common control page; and 64 bytes of firmware reserved space.

[0061] [Table 1]

[0062]

[0063]

[0064] As shown in Table 2, the control page header area of ​​the chain control page also includes: 8 bytes of control page attributes, which are used to identify the type of the control page, and whether the control page is located in the control page chain list, and its position in the chain list; and 4 8-byte timestamps, which are used to record key time nodes in the execution process of the chain control page.

[0065] [Table 2]

[0066]

[0067] In some preferred embodiments, the sizes of the common control page and the chain control page are 512 bytes, 1K bytes or 2K bytes respectively, the size of the control block storage area of ​​the common control page is 256 bytes, 768 bytes or 1792 bytes correspondingly, and the size of the control block storage area of ​​the chain control page is 448 bytes, 960 bytes or 1984 bytes correspondingly. The size of the control block is 16 bytes, 32 bytes, 64 bytes or 128 bytes. However, the length of a single control page may not be limited to the 512B, 1KB and 2KB mentioned in the present invention, and those skilled in the art may set it as needed.

[0068] For the engine, after obtaining its own CB, there are several situations where it needs to search the CP list:

[0069] 1. Find the common data cache pointer area;

[0070] 2. Prepare the address pointer of the next CB;

[0071] 3. Update timestamp information;

[0072] At this point, the engine first needs to locate the relative position of the corresponding CB in the CP / CP linked list. As shown in Table 3, this is a common CB header definition, which is a common definition for each CB. Among them, 8 bits of data are responsible for identifying the position of the CB in the entire CP / CP linked list, which is given by the AEM (host interface management engine) or the firmware when compiling the CB. The count value of 0 to 255 uses 16 bytes as the minimum granularity of the count, and can cover a maximum CP linked list length of 4KB. Therefore, in the case of different CP lengths of 512 bytes, 1K bytes or 2K bytes, the maximum length of the CP linked list is 8, 4 or 2.

[0073] [Table 3]

[0074]

[0075] The calculation formula for the relative position of CB in the entire CP / CP linked list is as follows:

[0076]

[0077] cpResolution: controls the page size;

[0078] cpOffset: The quotient obtained indicates the position of the control page where the control block is located in the control page list;

[0079] cbOffset: The remainder obtained indicates the relative position of the control block in the control page.

[0080] Since each control block identifies its position in the entire control page list, it is convenient for the engine to quickly locate the required information during processing.

[0081] Figures 4(a) to 4(c) A flowchart of the engine searching the CP linked list is shown, wherein FIG4(a) shows the flowchart when searching for a common data cache pointer area, FIG4(b) shows the flowchart when preparing the address pointer of the next CB, and FIG4(c) shows the flowchart when updating the timestamp information.

[0082] like Figure 1 As shown, the present invention proposes a method for constructing a control page linked list based on a general computing acceleration architecture. By introducing the concept of a CP linked list, the scalability and resource utilization efficiency of the computing acceleration architecture are further improved, and it can cope with complex and multi-type task mixed application scenarios.

[0083] A second aspect of an embodiment of the present invention further provides a system for constructing a control page linked list based on a general computing acceleration architecture. Figure 2FIG. 1 is a schematic diagram of an embodiment of a system for constructing a control page linked list based on a general computing acceleration architecture provided by the present invention. Figure 2 As shown, a system for constructing a control page linked list based on a general computing acceleration architecture includes: a common control page component module 10, which is used to construct a common control page, so that it includes a 128-byte control page header area, a control block storage area of ​​several bytes, a 64-byte data cache pointer area and a 64-byte original NVMe management and IO instruction backup area; and a chained control page construction module 20, which is used to construct a chained control page, so that it includes a 64-byte control page header area and a control block storage area of ​​several bytes. The control page header area of ​​the common control page includes an 8-byte address pointer pointing to the next chained control page, and the control page header area of ​​the chained control page includes three 8-byte chain pointers, which point to the first common control page, the previous control page, and the next chained control page, respectively, and the common control page and the chained control page constituting the control page linked list are the same size.

[0084] Figure 3 What is shown is a schematic diagram of an example of a control page linked list based on a general computing acceleration architecture provided according to an embodiment of the present invention.

[0085] In some preferred embodiments, the control page header area of ​​a common control page also includes: 8 bytes of control page attributes, which are used to identify the type of control page, and whether the control page is located in the control page linked list, and its position in the linked list; 8 bytes of the current control page serial number, which is specified when the control page is created; 8 bytes of NVMe queue related information, which includes a 2-byte completion queue ID, a 2-byte submission queue ID, and a 4-byte adjustment queue header information; 4 bytes of timestamps, which are used to record the key time nodes in the execution process of the common control page; and 64 bytes of firmware reserved space. The control page header area of ​​a chained control page also includes: 8 bytes of control page attributes, which are used to identify the type of control page, and whether the control page is located in the control page linked list, and its position in the linked list; and 4 8-byte timestamps, which are used to record the key time nodes in the execution process of the chained control page.

[0086] In some preferred embodiments, the sizes of the common control page and the chain control page are 512 bytes, 1K bytes or 2K bytes respectively, the size of the control block storage area of ​​the common control page is correspondingly 256 bytes, 768 bytes or 1792 bytes, and the size of the control block storage area of ​​the chain control page is correspondingly 448 bytes, 960 bytes or 1984 bytes. The size of the control block is 16 bytes, 32 bytes, 64 bytes or 128 bytes.

[0087] In some embodiments, the control block includes an 8-bit cbPosition for identifying the position of the control block in a normal control page, a chained control page, or a control page chain list.

[0088] The calculation formula for the relative position of a control block in a normal control page, a chained control page, or a control page chain list is as follows:

[0089]

[0090] cpResolution: controls the page size;

[0091] cpOffset: The quotient obtained indicates the position of the control page where the control block is located in the control page list;

[0092] cbOffset: The remainder obtained indicates the relative position of the control block in the control page.

[0093] The definition bit width of cbPosition can be increased to support longer CP linked lists.

[0094] like Figure 2 The control page linked list construction system based on the general computing acceleration architecture shown in the figure further improves the scalability and resource utilization efficiency of the computing acceleration architecture by introducing the concept of CP linked list, and can cope with complex and multi-type task mixed application scenarios.

[0095] A third aspect of the embodiments of the present invention further provides a computer-readable storage medium. Figure 5 A schematic diagram of a computer-readable storage medium for implementing a method for constructing a control page linked list based on a general computing acceleration architecture provided according to an embodiment of the present invention is shown. Figure 5 As shown, the computer-readable storage medium 3 stores computer program instructions 31, which can be executed by a processor. When the computer program instructions 31 are executed, the method of any of the above embodiments is implemented.

[0096] It should be understood that, to the extent that they do not conflict with each other, all the embodiments, features and advantages described above for the method for constructing a control page linked list based on a general computing acceleration architecture according to the present invention are also applicable to the system and storage medium for constructing a control page linked list based on a general computing acceleration architecture according to the present invention.

[0097] A fourth aspect of the embodiments of the present invention further provides a computer device, including a memory 402 and a processor 401, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method of any one of the above embodiments is implemented.

[0098] like Figure 6As shown in FIG. 1 , a hardware structure diagram of an embodiment of a computer device for executing a method for constructing a control page linked list based on a general computing acceleration architecture provided by the present invention is shown. Figure 6 As an example, the computer device shown in FIG. 4 includes a processor 401 and a memory 402, and may also include: an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403 and the output device 404 may be connected via a bus or other means, and FIG. 4 takes the bus connection as an example. The input device 403 may receive input digital or character information, and generate key signal input related to user settings and function control of the system constructed based on the control page linked list of the general computing acceleration architecture. The output device 404 may include a display device such as a display screen.

[0099] The memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the method for constructing a control page list based on a general computing acceleration architecture in the embodiment of the present application. The memory 402 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of the method for constructing a control page list based on a general computing acceleration architecture, etc. In addition, the memory 402 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 402 may optionally include a memory remotely arranged relative to the processor 401, and these remote memories may be connected to the local module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0100] The processor 401 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 402, that is, implements the method of constructing a control page linked list based on a general computing acceleration architecture of the above method embodiment.

[0101] Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein may be a volatile memory or a nonvolatile memory, or may include both a volatile memory and a nonvolatile memory. As an example and not by way of limitation, a nonvolatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. A volatile memory may include a random access memory (RAM), which may act as an external cache memory. As an example and not by way of limitation, RAM may be obtained in a variety of forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

[0102] It will also be appreciated by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given to the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0103] The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using the following components designed to perform the functions herein: a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and / or any other such configuration.

[0104] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0105] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

[0106] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for controlling the construction of a page linked list, characterized in that: The following steps are involved: Constructing a common control page to include a 128-byte control page header area, a control block storage area of ​​several bytes, a 64-byte data cache pointer area, and a 64-byte original NVMe management and IO instruction backup area; and Construct a chain control page that includes a 64-byte control page header area and several bytes of control block storage area. The control page header area of ​​the common control page includes an 8-byte address pointer pointing to the next chain control page. The control page header area of ​​the chain control page includes three 8-byte chain pointers, which point to the first common control page, the previous control page, and the next chain control page respectively, and The common control pages and the chained control pages constituting the control page chain list have the same size.

2. The method according to claim 1, characterized in that The control page header area of ​​the common control page also includes: The 8-byte control page attribute is used to identify the type of the control page and whether the control page is in the control page linked list and its position in the linked list; 8-byte serial number of the current control page, specified when the control page is created; 8 bytes of NVMe queue related information, including 2 bytes of completion queue ID, 2 bytes of submission queue ID and 4 bytes of training queue header information; A 4-byte timestamp, used to record key time nodes during the execution of the common control page; and 64 bytes of firmware reserved space.

3. The method according to claim 1, characterized in that The control page header area of ​​the chain control page also includes: 8-byte control page attribute, which is used to identify the type of the control page and whether the control page is in the control page linked list and its position in the linked list; and Four 8-byte timestamps are used to record key time nodes during the execution of the chain control page.

4. The method according to claim 1, characterized in that: The sizes of the common control page and the chain control page are 512 bytes, 1K bytes or 2K bytes respectively. The size of the control block storage area of ​​the common control page is 256 bytes, 768 bytes or 1792 bytes, and The size of the control block storage area of ​​the chain control page is 448 bytes, 960 bytes or 1984 bytes respectively.

5. The method according to claim 1, characterized in that The control block includes an 8-bit cbPosition, which is used to identify the position of the control block in a common control page, a chained control page or a control page chain list. The calculation formula for the relative position of the control block in the common control page, chain control page or control page chain list is as follows: cpResolution: controls the page size; cpOffset: The quotient obtained indicates the position of the control page where the control block is located in the control page list; cbOffset: The remainder obtained indicates the relative position of the control block in the control page.

6. A system for controlling the construction of a page linked list, characterized in that: include: A common control page construction module, used to construct a common control page, including a 128-byte control page header area, a control block storage area of ​​several bytes, a 64-byte data cache pointer area, and a 64-byte original NVMe management and IO instruction backup area; and The chain control page construction module is used to construct the chain control page, which includes a 64-byte control page header area and a control block storage area of ​​several bytes. The control page header area of ​​the common control page includes an 8-byte address pointer pointing to the next chain control page. The control page header area of ​​the chain control page includes three 8-byte chain pointers, which point to the first common control page, the previous control page, and the next chain control page respectively, and The common control pages and the chained control pages constituting the control page chain list have the same size.

7. The system according to claim 6, characterized in that The control page header area of ​​the common control page also includes: The 8-byte control page attribute is used to identify the type of the control page and whether the control page is in the control page linked list and its position in the linked list; 8-byte serial number of the current control page, specified when the control page is created; 8 bytes of NVMe queue related information, including 2 bytes of completion queue ID, 2 bytes of submission queue ID and 4 bytes of training queue header information; A 4-byte timestamp, used to record key time nodes during the execution of the common control page; and 64 bytes of firmware reserved space.

8. The system according to claim 6, characterized in that The control page header area of ​​the chain control page also includes: 8-byte control page attribute, which is used to identify the type of the control page and whether the control page is in the control page linked list and its position in the linked list; and Four 8-byte timestamps, used to record key time nodes in the execution of the chained control page; and, The sizes of the common control page and the chain control page are 512 bytes, 1K bytes or 2K bytes respectively. The size of the control block storage area of ​​the common control page is 256 bytes, 768 bytes or 1792 bytes, respectively. The size of the control block storage area of ​​the chain control page is 448 bytes, 960 bytes or 1984 bytes, and The size of the control block is 16 bytes, 32 bytes, 64 bytes or 128 bytes.

9. A computer-readable storage medium, characterized in that: Computer program instructions are stored, and when the computer program instructions are executed, the method according to any one of claims 1 to 5 is implemented.

10. A computer device comprising a memory and a processor, characterized in that: The memory stores a computer program, and when the computer program is executed by the processor, the method according to any one of claims 1 to 5 is performed.

Images