Host memory access method, apparatus and electronic device

Abstract

Embodiments of the present application provide a host memory access method and device and electronic equipment, wherein the method comprises: obtaining a control command, determining a host memory access mode adopted by the control command according to a preset condition; if the preset condition is met, realizing host memory access through an address mapping mode, the address mapping being a mapping relationship between an address of a host storage unit and a source address; if the preset condition is not met, realizing the host memory access through a DMA mode. In this way, the host memory access can be realized through the address mapping mode or the DMA mode, which can improve access efficiency and avoid access delay.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a host memory access method and device and electronic equipment. BACKGROUND

[0002] The solid state drive (SSD) in the prior art is a hard disk made of an array of solid-state electronic storage chips, and the main components are a controller and a storage chip, and the internal structure is simple. According to whether a dynamic random access memory (DRAM) is used, there are two designs of SSD, namely, a SSD with a DRAM and a DRAM-Less SSD. The DRAM can be used to store a mapping table of a host logical address space and a flash memory physical address space, and the cost of the DRAM is very high, which accounts for a large proportion of the total hardware cost of the SSD. The SSD with a DRAM has a high cost, which reduces the competitiveness of the product. Therefore, a cost-oriented DRAM-Less SSD is generated.

[0003] The Non Volatile Memory Express (NVMe) protocol defines a host memory buffer (HMB) function, so that a solid state disk supporting the NVMe protocol can use the host divided memory. Such a solid state disk can not need to be equipped with a DRAM itself, which greatly reduces the cost.

[0004] The NVMe protocol specifies that the HMB can be continuous or non-continuous, but the size must be one or more complete host memory pages. A host memory descriptor list is used to describe the address of one or more memory blocks provided by the host for the HMB. Each host memory descriptor in the host memory descriptor list describes a memory block provided by the host for the HMB, including the start address of the memory block and the memory block size. The host memory descriptor list is composed of a plurality of different host memory descriptors, so that a plurality of different memory blocks can be provided to jointly constitute the complete HMB provided by the host to the SSD. The SSD usually uses an internal address space to build a mapping relationship with the HMB to use the HMB, and the SSD needs to traverse all the host memory descriptor entries to calculate the host address when accessing the HMB. The access efficiency of locating the host address by traversing the host memory descriptor is relatively low, and there is an access delay. SUMMARY

[0005] In order to solve the above technical problems, the present application provides a host memory access method, device and electronic equipment.

[0006] In a first aspect, an embodiment of the present application provides a host memory access method, the method comprising:

[0007] obtaining a control command, and determining a host memory access mode adopted by the control command according to a preset condition;

[0008] if the preset condition is met, implementing the host memory access in a manner of address mapping, the address mapping being a mapping relationship between an address of a host storage unit and a source address;

[0009] if the preset condition is not met, implementing the host memory access in a manner of DMA.

[0010] In a second aspect, an embodiment of the present application provides a host memory access device, the device comprising:

[0011] a determining module, configured to obtain a control command, and determine a host memory access mode adopted by the control command according to a preset condition;

[0012] a first processing module, configured to, if the preset condition is met, implement the host memory access in a manner of address mapping, the address mapping being a mapping relationship between an address of a host storage unit and a source address;

[0013] a second processing module, configured to, if the preset condition is not met, implement the host memory access in a manner of DMA.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory and a processor, the memory being configured to store a computer program, the computer program being configured to execute the host memory access method provided in the first aspect when the processor runs.

[0015] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, the computer program being configured to execute the host memory access method provided in the first aspect when running on a processor.

[0016] The host memory access method provided in the present application comprises the following steps: obtaining a control command, and determining a host memory access mode adopted by the control command according to a preset condition; if the preset condition is met, implementing the host memory access in a manner of address mapping, the address mapping being a mapping relationship between an address of a host storage unit and a source address; and if the preset condition is not met, implementing the host memory access in a manner of DMA. In this way, the host memory access can be implemented in a manner of address mapping or in a manner of DMA, so that the access efficiency can be improved and the access delay can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the protection scope of the present application. In the various drawings, similar components are denoted by similar reference numerals.

[0018] Figure 1 A schematic diagram showing the relationship between the host memory descriptor list and the host storage unit in the prior art is shown.

[0019] Figure 2 A schematic diagram showing a flow of the host memory access method provided by the embodiments of the present application is shown.

[0020] Figure 3 A schematic diagram showing a process of generating a check code provided by the embodiments of the present application is shown.

[0021] Figure 4 A schematic diagram showing a structure of the host memory access device provided by the embodiments of the present application is shown. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments.

[0023] The components of the embodiments of the present application generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0024] In the following, the terms "include", "have", and their conjugates in various embodiments of the present application are only intended to indicate that specific features, numbers, steps, operations, elements, components, or combinations thereof are present, and should not be understood as excluding the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0025] In addition, the terms "first", "second", "third", etc. are only used for differentiation in description, and should not be understood as indicating or implying relative importance.

[0026] Unless specifically stated otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. The terminology used in the description herein (such as the terminology used in the specification and / or the claims) should not be interpreted in accordance with the broadest form of the terms used in general dictionaries, but should be interpreted in accordance with the contextual meaning in the relevant technical field and should not be interpreted in accordance with an idealized or overly formal meaning, unless clearly defined in various embodiments of the present application.

[0027] In the prior art, a host memory descriptor list is composed of a plurality of different host memory descriptors, so that a plurality of different storage blocks can be provided to jointly constitute the complete HMB provided by the host to the SSD. To use the HMB, the SSD usually constructs a mapping relationship with the HMB using an internal address space. Please refer to Figure 1 , the internal address 0-32KB address of the SSD constructs a mapping relationship with the host memory descriptor entry 0, the host memory descriptor entry 1, the host memory descriptor entry 2, and the host memory descriptor entry 3, and the host memory descriptor entry 0, the host memory descriptor entry 1, the host memory descriptor entry 2, and the host memory descriptor entry 3 correspond to the storage block 0, the storage block 1, the storage block 2, and the storage block 3 of the HMB respectively, the capacity of the storage block 0 is 4KB, the capacity of the storage block 1 is 8KB, the capacity of the storage block 2 is 4KB, and the capacity of the storage block 3 is 14KB. Assuming that the SSD wants to access a position with an internal address of 18KB of the host, the first step is to access the host memory descriptor entry 0, and it is found that 4KB is less than 18KB, which means that the HMB host address to be accessed is not in the storage block 0;

[0028] The second step is to access the host memory descriptor entry 1, and the sum of 4KB and 8KB is less than 18KB, which means that the HMB host address to be accessed is not in the storage block 1;

[0029] The third step is to access the host memory descriptor entry 2, and the sum of 4KB, 8KB, and 4KB is less than 18KB, which means that the HMB host address to be accessed is not in the storage block 2;

[0030] The fourth step is to access the host memory descriptor entry 3, and the sum of 4KB, 8KB, 4KB, and 16KB is greater than 18KB, which means that the HMB host address to be accessed is in the storage block 3, and the offset on the storage block 3 is 18KB-(4KB+8KB+4KB)=2KB.

[0031] As can be seen, the access efficiency of locating the host address by traversing the host memory descriptor is relatively low and has access delay.

[0032] Embodiment 1

[0033] The present disclosure provides a host memory access method.

[0034] Specifically, refer to Figure 2 The host memory access method provided by the embodiments of the present disclosure comprises:

[0035] In step S201, a control command is acquired, and a host memory access mode adopted by the control command is determined according to a preset condition.

[0036] In this embodiment, the control command can be a corresponding control command generated by a central processing unit (CPU) according to data access demand when there is a data access demand.

[0037] In this embodiment, the preset condition comprises a first preset sub-condition, and the first preset sub-condition is that a source address of the control command is a CPU directly accessible address.

[0038] In this way, the host memory mode adopted by the control command can be determined according to the preset condition.

[0039] In this embodiment, in order to further accurately determine the host memory access mode adopted by the control command, the preset condition further comprises a second preset sub-condition, and the second preset sub-condition is that a data capacity to be accessed by the control command is less than or equal to a first preset threshold value, and the first preset threshold value is determined according to an address of a host storage unit corresponding to the source address of the control command.

[0040] It should be noted that the mapping relationship between the address of the host storage unit and the source address can be acquired in advance, and based on the mapping relationship between the address of the host storage unit and the source address, the first preset threshold value can be determined. For example, the first preset threshold value can be the address capacity value of the host storage unit, or a value smaller than the address capacity of the host storage unit.

[0041] In this embodiment, the acquisition process of the mapping relationship between the address of the host storage unit and the source address comprises:

[0042] A host memory descriptor list is acquired, and the host memory descriptor list is parsed to obtain a plurality of starting addresses corresponding to a plurality of host storage units.

[0043] The starting address of each host storage unit is allocated with a CPU directly accessible address to obtain the mapping relationship between the address of the host storage unit and the source address.

[0044] In the embodiment, in the initialization process, the host (HOST) provides a host memory descriptor list to the SSD according to the requirements of the SSD to describe the host storage unit. After the SSD receives the host memory descriptor list, the SSD parses the start address and storage block capacity of the host storage unit corresponding to each host memory descriptor, writes the start address and storage capacity of the host storage unit to a register in the SSD, and then configures the direct access address of the CPU of the SSD as a source address corresponding to the address of the host storage unit in a one-to-one manner. The address of the host storage unit and the source address are mapped in a one-to-one manner. Such a mapping register group can be configured in multiple groups to realize the function of mapping the host storage unit described by multiple host memory descriptor entries to the direct access address of the CPU in the SSD, and can also be turned off when not in use.

[0045] In this way, by parsing the host memory descriptor list, the start addresses of multiple host storage units are obtained, and then the start addresses of the host storage units are allocated with corresponding direct access addresses of the CPU to obtain the mapping relationship between the address of the host storage unit and the source address, so that the mapping relationship is quickly obtained and the processing efficiency is improved.

[0046] In step S202, the host memory access is realized by address mapping, and the address mapping is the mapping relationship between the address of the host storage unit and the source address.

[0047] In step S202, the host memory access is realized by address mapping, and the address mapping is the mapping relationship between the address of the host storage unit and the source address.

[0048] The plurality of address mapping groups in the mapping relationship are parsed in parallel to obtain a to-be-accessed destination host address corresponding to the source address of the control command, a CPU access host storage unit command is arbitrated according to the to-be-accessed destination host address, and the to-be-accessed destination host address is accessed according to the CPU access host storage unit command.

[0049] In the embodiment, the plurality of address mapping groups are parsed in parallel and synchronously, the to-be-accessed destination host address corresponding to the source address in the control command is parsed, and then a group of CPU access host storage unit commands are arbitrated. The data access to the host storage unit is realized by the CPU access host storage unit command. Specifically, the CPU access host storage unit command can be directly parsed into an AXI4 standard interface signal to realize the access to the host storage unit.

[0050] In step S203, the host memory access is realized by the DMA.

[0051] In step S203, the host memory access is realized by the DMA.

[0052] determining the control command as a DMA command, reading a host address, a slave address, a data transfer length and a data transfer direction from the DMA command, the slave address being a memory address or a cache address of the solid state disk;

[0053] determining a source address and a destination address from the host address and the slave address according to the data transfer direction;

[0054] obtaining first data according to the source address and writing the first data into the destination address.

[0055] In the embodiment, the data transfer direction can be transferring data stored in the host address to the slave address, or transferring data stored in the slave address to the host address. If the data stored in the host address is transferred to the slave address, the host address is the source address and the slave address is the destination address. If the data stored in the slave address is transferred to the host address, the slave address is the source address and the host address is the destination address.

[0056] In the embodiment, the generation process of the DMA command specifically includes the following steps:

[0057] generating a corresponding DMA command when the data capacity exchanged between the solid state disk and the host storage unit is greater than a preset threshold or data access is performed between the buffer of the solid state disk and the host storage unit;

[0058] storing the generated DMA command into a DMA command first-in-first-out queue.

[0059] In the embodiment, the DMA command is stored in a DMA command first-in-first-out (FIFO) queue, so that the corresponding DMA command can be read from the DMA command FIFO queue, and a large amount of data can be moved between the SSD and the host.

[0060] It is to be supplemented that when the SSD internal cache space which cannot be directly accessed by the CPU needs to exchange data with the host memory unit, or a large amount of data needs to be exchanged between the host and the SSD, the CPU is configured to configure a host address (HOST_ADDR), a slave address (DEVICE_ADDR), a data transfer length, a data transfer direction, wherein the slave address is a hard disk address. Then, a corresponding DMA command is generated according to the host address, the slave address, the data transfer length and the data transfer direction, and the DMA command is stored in the DMA command FIFO queue through the configuration of a trigger register.

[0061] In this embodiment, the depth of the DMA command FIFO queue is 4, and four DMA commands can be stored. When the DMA command FIFO queue is not full and the CPU configures the trigger register (tx_req), the host address, slave address, data transfer length (tx_length), and data transfer direction (tx_dir) are spliced as a DMA command, which is stored in the DMA command FIFO queue. The DMA commands in the DMA command FIFO queue are taken out and executed in turn. When the DMA command FIFO queue is not empty, the DMA command is taken out and executed, and a response (tx_done) is received after execution, and the next DMA command is taken out and executed.

[0062] In this embodiment, the processing process of the DMA command is as follows: the CPU configures the register signal tx_req, and when the register signal tx_req is 1, the SRC_REQ state is entered to initiate the command of reading the source address. After the command is sent, the source responds (src_ack & buffer_last), and the SRC_WAIT state is entered to wait for the source to send data. After receiving the data sent by the source (src_data_valid & src_data_end & last_req), the data is written to the destination address. The command of writing the destination address is initiated in the DST_REQ state, and the destination responds (dst_ack & buffer_last) after receiving the command. The DST_WAIT state is entered to wait for the response returned by the destination. The data is sent to the destination in the DST_WAIT state, and after the destination sends the data reception completion (dst_done & last_req), the NEXT_LENGTH state is entered. In the NEXT_LENGTH state, it is judged whether the data transfer length reaches the length required in the DMA command. If the data transfer length (last_data) is reached, the entire DMA command is executed, and the IDLE state is returned; if not, the SRC_REQ state is returned to initiate the command of reading the source address space. According to the transfer direction (tx_dir) and the data length (cur_len) that has been transmitted, the source address and the destination address can be calculated.

[0063] When `tx_dir` is 0, it indicates that data is written to the host. The source address equals the starting read address of the slave address (DEVICE_ADDR) plus the length of data already transmitted (cur_len), and the destination address equals the starting write address of the host address (HOST_ADDR) plus the length of data already transmitted (cur_len). When `tx_dir` is 1, it indicates that data is read from the host. The source address equals the starting read address of the host address (HOST_ADDR) plus the length of data already transmitted (cur_len), and the destination address equals the starting write address of the slave address (DEVICE_ADDR) plus the length of data already transmitted (cur_len).

[0064] It should be noted that when there are multiple control commands, some of which access host memory through address mapping and others through DMA, arbitration is required for each control command. This embodiment uses round-robin arbitration.

[0065] In this embodiment, to improve the accuracy of data writing by the host, a data verification process is also provided, specifically including:

[0066] When writing the second data to the address of the host storage unit, it is determined whether the length of the second data is a preset fixed bit length;

[0067] If the length of the second data is a preset fixed bit length, then a corresponding first check code is generated based on the second data, and the first check code is stored in correspondence with the second data.

[0068] If the length of the second data is not a preset fixed length, then the second data is modified to a third data of a preset fixed length, a corresponding second check code is generated based on the third data, and the second check code is stored in correspondence with the third data.

[0069] Additionally, it can be noted that Error Correcting Code (ECC) functionality can be configured for host addresses. The process for configuring ECC functionality includes: configuring the host address space supporting ECC functionality (ECC_DATA_BASE_ADDR), configuring the host address space used to store ECC checksums (ECC_BASE_ADDR), enabling interrupt reporting, and finally configuring ECC_ENABLE to enable ECC functionality.

[0070] In this embodiment, the preset fixed bit length can be 256 bits, or other values; no limitation is imposed here. For example, an ECC module that generates 10 parity bits every 256 bits can be set up, so the data bus width receiving the AXI4 interface signal is required to be fixed at 256 bits. However, to support unaligned transmission, such as supporting minimum 32-bit data transmission, this embodiment requires a "read-modify-write" operation if the data written from the SSD to the host is not 256-bit aligned when ECC is enabled.

[0071] Please see Figure 3 The 256-bit wide data bus on the AXI interface is designated as data lines 0 to 255, and the transmitted data is designated as data 0 to data 255. These data are stored in host addresses 0 to 31. Suppose a 64-bit data needs to be written to addresses 8 to 15 via data lines 64 to 127. Since the ECC module generates 10 parity bits every 256 bits, the data 0 to 63 and data 128 to 255 from the previous 256-bit data are retrieved from the host memory address and concatenated with the current data 64 to 127 to form a new 256-bit wide data before ECC calculation. The actual data written to the host is the concatenated data.

[0072] In this embodiment, the host memory access method may further include the following steps:

[0073] When the destination address is the host address and the host address is configured with error correction function, if the second data is read from the destination address, a corresponding third check code is generated based on the second data. The third check code is compared with the first check code. If the two are the same, the second data is determined to be correct. If the two are different, the second data is determined to be incorrect.

[0074] In this embodiment, if the third checksum is different from the first checksum, a 1-bit error can be recovered based on the result of a bitwise XOR operation of the two checksums, and a 2-bit or 3-bit error can be detected. The error information, including the host address where the error occurred and whether the error is recoverable, is written to a register for storage. This allows for the verification of the second data, improving data reliability.

[0075] In this embodiment, data access to the host memory unit can be achieved by establishing a mapping relationship between the SSD's memory address space and the host memory unit, or by using DMA commands. When the data volume is small, using the mapping relationship between the SSD's memory address space and the host memory is more efficient, processing only 32 bits or 64 bits of data at a time. When the data volume is large, or when processing data interaction between the SSD's internal cache space and the host memory unit that the CPU cannot directly access, DMA commands are used. Thus, using address mapping or DMA to achieve host memory access saves the time required to traverse all host memory descriptor entries and ensures consistent host memory address access latency. When the data volume is large, DMA improves the efficiency of accessing host memory addresses. Enabling the ECC function through register operations increases the reliability of data transfer from the host to the SSD's internal cache.

[0076] The host memory access method provided in this application obtains a control command and determines the host memory access method to be used by the control command based on preset conditions. If the preset conditions are met, host memory access is achieved through address mapping, where address mapping is a mapping relationship between the address of a host storage unit and a source address. If the preset conditions are not met, host memory access is achieved through DMA. In this way, host memory access can be achieved through address mapping or DMA, which can improve access efficiency and avoid access latency.

[0077] Example 2

[0078] This disclosure provides a host memory access device.

[0079] For details, please see Figure 4 The host memory access device 400 provided in this embodiment includes:

[0080] The determination module 401 is used to acquire control commands and determine the host memory access method used by the control commands according to preset conditions.

[0081] The first processing module 402 is used to access the host memory through address mapping if the preset conditions are met. The address mapping is a mapping relationship between the address of the host storage unit and the address of the solid-state drive.

[0082] The second processing module 403 is used to access the host memory via DMA if the preset conditions are not met.

[0083] In this embodiment, the first processing module 402 is further configured to parse multiple address mapping groups in the mapping relationship in parallel to obtain the destination host address to be accessed corresponding to the source address of the control command, arbitrate the destination host address to be accessed to obtain the CPU access host memory unit command, and perform access operation on the destination host address to be accessed according to the CPU access host memory unit command.

[0084] The second processing module 403 is further configured to determine that the control command is a DMA command, and read the host address, slave address, data transfer length and data transfer direction from the DMA command, wherein the slave address is the memory address or cache address of the solid-state drive;

[0085] The source address and destination address are determined from the host address and the slave address based on the data transmission direction;

[0086] First data is obtained based on the source address, and the first data is written to the destination address.

[0087] In this embodiment, the host memory access device 400 further includes:

[0088] The third processing module is used to generate a corresponding DMA command when the amount of data accessed between the solid-state drive and the host storage unit exceeds a preset threshold or when data access is performed between the cache of the solid-state drive and the host storage unit.

[0089] The generated DMA commands are stored in the DMA command first-in-first-out queue.

[0090] In this embodiment, the host memory access device 400 further includes:

[0091] The fourth processing module is used to obtain a list of host memory descriptors and parse the list of host memory descriptors to obtain the starting addresses corresponding to multiple host storage units;

[0092] The CPU directly accesses the starting address of each host memory unit to obtain the mapping relationship between the address and the source address of the host memory unit.

[0093] In this embodiment, the host memory access device 400 further includes:

[0094] When writing the second data to the address of the host storage unit, it is determined whether the length of the second data is a preset fixed bit length;

[0095] The fifth processing module is used to generate a corresponding first check code based on the second data if the length of the second data is a preset fixed bit length, and store the first check code and the second data accordingly.

[0096] If the length of the second data is not a preset fixed length, then the second data is modified to a third data of a preset fixed length, a corresponding second check code is generated based on the third data, and the second check code is stored in correspondence with the third data.

[0097] The host memory access device provided in this application acquires a control command and determines the host memory access method to be used by the control command based on preset conditions. If the preset conditions are met, host memory access is implemented through address mapping, where address mapping is a mapping relationship between the address of a host storage unit and a source address. If the preset conditions are not met, host memory access is implemented through DMA. In this way, host memory access can be implemented through address mapping or DMA, which can improve access efficiency and avoid access latency.

[0098] Example 3

[0099] Furthermore, this disclosure provides an electronic device including a memory and a processor. The memory stores a computer program, which, when executed on the processor, performs the host memory access method provided in Embodiment 1 above.

[0100] It should be understood that the electronic device provided in this embodiment can implement the host memory access method provided in Embodiment 1. For relevant descriptions, please refer to the content of Embodiment 1. To avoid repetition, it will not be repeated here.

[0101] Example 4

[0102] Furthermore, this disclosure provides a computer-readable storage medium storing a computer program that, when executed on the processor, performs the host memory access method provided in Embodiment 1 above.

[0103] It should be understood that the computer-readable storage medium provided in this embodiment can implement the host memory access method provided in Embodiment 1. For relevant descriptions, please refer to the content of Embodiment 1. To avoid repetition, it will not be repeated here.

[0104] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0105] In addition, the functional modules or units in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0106] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A host memory access method, characterized in that, The method includes: Obtain control commands and determine the host memory access method used by the control commands based on preset conditions; If the preset conditions are met, host memory access is achieved through address mapping, where the address mapping is the mapping relationship between the address of the host storage unit and the source address. If the preset conditions are not met, the host memory access is achieved through DMA; the preset conditions include a first preset sub-condition, wherein the source address of the control command is an address that the CPU can directly access. The preset conditions also include a second preset sub-condition, wherein the data to be accessed by the control command is less than or equal to a first preset threshold, and the first preset threshold is determined based on the address of the host storage unit corresponding to the source address of the control command. The method further includes: When the amount of data accessed between the solid-state drive and the host storage unit exceeds a preset threshold, or when data access is performed between the cache of the solid-state drive and the host storage unit, a corresponding DMA command is generated. Store the generated DMA commands into the DMA command first-in-first-out queue; The method of accessing host memory via address mapping includes: Multiple address mapping groups in the mapping relationship are parsed in parallel to obtain the destination host address to be accessed corresponding to the source address of the control command. The CPU access host memory unit command is obtained by arbitration based on the destination host address to be accessed, and the access operation is performed on the destination host address to be accessed based on the CPU access host memory unit command. The method of accessing host memory via DMA includes: The control command is determined to be a DMA command. The host address, slave address, data transfer length, and data transfer direction are read from the DMA command. The slave address is the memory address or cache address of the solid-state drive. The source address and destination address are determined from the host address and the slave address based on the data transmission direction; First data is obtained based on the source address, and the first data is written to the destination address.

2. The method according to claim 1, characterized in that, The method further includes: Obtain the host memory descriptor list, parse the host memory descriptor list to obtain the starting addresses corresponding to multiple host storage units; The CPU directly accesses the starting address of each host memory unit to obtain the mapping relationship between the address and the source address of the host memory unit.

3. The method according to claim 1, characterized in that, The method further includes: When writing the second data to the address of the host storage unit, it is determined whether the length of the second data is a preset fixed bit length; If the length of the second data is a preset fixed bit length, then a corresponding first check code is generated based on the second data, and the first check code is stored in correspondence with the second data. If the length of the second data is not a preset fixed length, then the second data is modified to a third data of a preset fixed length, a corresponding second check code is generated based on the third data, and the second check code is stored in correspondence with the third data.

4. A host memory access device, characterized in that, The device includes: The determination module is used to acquire control commands and determine the host memory access method used by the control commands based on preset conditions. The first processing module is used to access the host memory through address mapping if the preset conditions are met. The address mapping is a mapping relationship between the address of the host storage unit and the address of the solid-state drive. The second processing module is used to access the host memory via DMA if the preset conditions are not met. The preset conditions include a first preset sub-condition, wherein the source address of the control command is an address that the CPU can directly access. The preset conditions also include a second preset sub-condition, wherein the data to be accessed by the control command is less than or equal to a first preset threshold, and the first preset threshold is determined based on the address of the host storage unit corresponding to the source address of the control command. The third processing module is used to generate a corresponding DMA command when the amount of data accessed between the solid-state drive and the host storage unit exceeds a preset threshold or when data access is performed between the cache of the solid-state drive and the host storage unit. Store the generated DMA commands into the DMA command first-in-first-out queue; The method of accessing host memory via address mapping includes: Multiple address mapping groups in the mapping relationship are parsed in parallel to obtain the destination host address to be accessed corresponding to the source address of the control command. The CPU access host memory unit command is obtained by arbitration based on the destination host address to be accessed, and the access operation is performed on the destination host address to be accessed based on the CPU access host memory unit command. The method of accessing host memory via DMA includes: The control command is determined to be a DMA command. The host address, slave address, data transfer length, and data transfer direction are read from the DMA command. The slave address is the memory address or cache address of the solid-state drive. The source address and destination address are determined from the host address and the slave address based on the data transmission direction; First data is obtained based on the source address, and the first data is written to the destination address.

5. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program that executes the host memory access method according to any one of claims 1 to 3 when the processor is running.

6. A computer-readable storage medium, characterized in that, It stores a computer program that, when run on a processor, executes the host memory access method according to any one of claims 1 to 3.

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