Semiconductor device with deep diffusion region

Abstract

The invention relates to a semiconductor device with a deep diffusion region. A method (2) for processing a semiconductor device (1) comprises: providing (20) a semiconductor body (10) having a dopant of a first conductivity type; forming (21) at least one trench (11a) extending into the semiconductor body in a vertical direction (Z), the trench being laterally bounded by two trench sidewalls (113a) and vertically bounded by a trench bottom (114a); applying (26) a substance (31) to at least a portion (111a) of a trench surface formed by one of the trench sidewalls and / or the trench bottom, wherein applying (26) the substance (31) comprises preventing the substance from being applied to another of the trench sidewalls; and causing the applied substance (31) to diffuse (28) from the portion (111a) into the semiconductor body, thereby forming a semiconductor region (12a) having a dopant of a second conductivity type in the semiconductor body, and the semiconductor region is arranged adjacent to the portion (111a).

Description

[0001] This application is a divisional application of the Chinese patent application filed on October 21, 2016, with application number 201610921726.8 and invention name “Semiconductor device with deep diffusion region”. Technical Field

[0002] The present description relates to embodiments of a method for processing a semiconductor device and to embodiments of a power semiconductor transistor. In particular, the present description relates to embodiments of a semiconductor device having a deeply doped semiconductor region formed by means of diffusion. Background Art

[0003] Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or electric machines, rely on semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used in a variety of applications including, but not limited to, switches in power supplies and power converters.

[0004] Such a power semiconductor device, for example a power semiconductor transistor, may exhibit a plurality of doped semiconductor regions, such as a doped body region, a doped source region, a doped drift region, a doped contact region, a doped field stop layer, to name a few.

[0005] For example, doped semiconductor regions may be formed by means of diffusion, implantation and / or epitaxy.Diffusion generally involves carrying out a temperature treatment for a certain amount of time. Summary of the invention

[0006] According to an embodiment, a method for processing a semiconductor device includes: providing a semiconductor body having a dopant of a first conductivity type; forming at least one trench extending into the semiconductor body in a vertical direction, wherein the trench is laterally defined by two trench sidewalls and vertically defined by a trench bottom; applying a substance to at least a portion of a trench surface formed by one of the trench sidewalls and / or the trench bottom of at least one trench, wherein applying the substance includes preventing the substance from being applied to another of the trench sidewalls; and causing the applied substance to diffuse from the above-mentioned portion into the semiconductor body, thereby forming a semiconductor region having a dopant of a second conductivity type in the semiconductor body, and the semiconductor region is arranged adjacent to the above-mentioned portion, wherein the semiconductor region is arranged adjacent to only one of the two trench sidewalls.

[0007] According to another embodiment, a power semiconductor transistor includes a semiconductor body and at least one transistor unit, wherein the at least one transistor unit has: a semiconductor drift region, which is included in the semiconductor body and has a dopant of a first conductivity type; a semiconductor body region, which is included in the semiconductor body and has a dopant of a second conductivity type; a source region, wherein the semiconductor body region isolates the source region from the semiconductor drift region; a trench, which extends into the semiconductor body in a vertical direction and includes a control electrode electrically insulated from each of the semiconductor drift region, the semiconductor body region and the source region; and a semiconductor region, which has a dopant of the second conductivity type and is arranged adjacent to the trench and separated from the semiconductor body region, wherein the transition between the trench and the semiconductor region extends along the trench sidewall of the trench, and wherein the dopant concentration of the semiconductor region adjacent to the trench sidewall is converted to a value in the range of 50% to 150% of the fixed dopant concentration value at any point along at least 60% of the total extension of the semiconductor region in the vertical direction.

[0008] According to another embodiment, a power semiconductor transistor includes a semiconductor body and at least one transistor unit, wherein the at least one transistor unit has: a semiconductor drift region, which is included in the semiconductor body and has a dopant of a first conductivity type; a semiconductor body region, which is included in the semiconductor body and has a dopant of a second conductivity type; a source region, wherein the semiconductor body region isolates the source region from the semiconductor drift region; a trench, which extends into the semiconductor body in a vertical direction and includes a control electrode electrically insulated from each of the semiconductor drift region, the semiconductor body region and the source region; and a semiconductor region, which has a dopant of the second conductivity type and is arranged adjacent to the trench and separated from the semiconductor body region, wherein the transition between the trench and the semiconductor region extends along a trench sidewall of the trench, and wherein, in a portion equivalent to at least 80% of the total extension of the semiconductor region in the vertical direction, the dopant concentration of the semiconductor region adjacent to the trench sidewall changes by at least 30% from the dopant concentration value present in the portion.

[0009] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The parts in the drawings are not necessarily to scale, instead emphasis is placed on illustrating the principles of the present invention. In addition, in the drawings, the same reference numerals represent corresponding parts. In the drawings:

[0011] Figure 1 schematically illustrates different stages of a method of processing a semiconductor device according to one or more embodiments;

[0012] Figure 2schematically illustrates steps of a method for processing a semiconductor device according to one or more embodiments;

[0013] Figure 3 Schematically illustrating steps of a method of processing a semiconductor device according to one or more embodiments;

[0014] Figure 4 schematically illustrates steps of a method for processing a semiconductor device according to one or more embodiments;

[0015] Figure 5 Schematically illustrating steps of a method of processing a semiconductor device according to one or more embodiments;

[0016] Figure 6 schematically illustrates steps of a method for processing a semiconductor device according to one or more embodiments;

[0017] Figure 7 Schematically illustrating steps of a method of processing a semiconductor device according to one or more embodiments;

[0018] Figure 8 schematically illustrates a portion of a vertical cross section of a power semiconductor transistor according to one or more embodiments; and

[0019] Fig. 9 (A) Fig. 9 (B) Fig. 9 (C) and Fig. 9 ) and (D) schematically illustrate a portion of a vertical cross section of a processed semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0020] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0021] In this regard, directional terms such as "top," "bottom," "below," "front," "after," "back," "front," "rear," "below," "above," etc. may be used with reference to the orientation of the figures being described. Since portions of the embodiments may be positioned in many different orientations, directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments may be used and that structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a restrictive sense, and the scope of the present invention is defined by the appended claims.

[0022] Reference will now be made in detail to various embodiments, one or more examples of which are shown in the accompanying drawings. Each example is provided in an illustrative manner, and each example is not intended to be a limitation of the present invention. For example, a feature shown or described as a part of one embodiment may be used in other embodiments or used in combination with other embodiments to produce yet another embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustration purposes only. For clarity, unless otherwise stated, the same elements or manufacturing steps are indicated by the same reference numerals in different drawings.

[0023] The term "horizontal" as used in this specification is intended to describe an orientation that is substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor region. This may be, for example, a surface of a semiconductor wafer or chip. For example, the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0024] The term "vertical" as used in this specification is intended to describe an orientation that is generally arranged perpendicular to a horizontal surface, i.e., parallel to a normal direction of the surface of the semiconductor wafer. For example, the extension direction Z mentioned below may be a vertical direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0025] In this specification, n-doping may be referred to as "first conductivity type", and p-doping may be collectively referred to as "second conductivity type". Alternatively, an opposite doping relationship may be utilized so that the first conductivity type may be p-doped and the second conductivity type may be n-doped. Also alternatively, the terms "first conductivity type" and "second conductivity type" may both refer to n-doping or p-doping. Thus, in one or more embodiments, the second conductivity type may be the same as the first conductivity type. In one or more other embodiments, the second conductivity type may be complementary to the first conductivity type.

[0026] Furthermore, in this specification, the term "dopant concentration" may refer to an average dopant concentration, or to an average dopant concentration or a sheet charge carrier concentration of a specified semiconductor region or semiconductor regions such as a semiconductor region within a trench, respectively. Thus, for example, a statement claiming that a specified semiconductor region exhibits a higher or lower dopant concentration than the dopant concentration of another semiconductor region may indicate that the respective average dopant concentrations of the semiconductor regions are different from each other.

[0027] In the context of this specification, the terms "ohmic contact", "electrical contact", "ohmic connection" and "electrical connection" are intended to describe the presence of a low ohmic electrical connection or a low ohmic current path between two regions, sections, areas, parts or portions of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a part or portion of a semiconductor device. In addition, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with each other may not include additional intermediate elements, etc.

[0028] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies, and to corresponding processing methods. For example, the power semiconductor device may include one or more power semiconductor units, such as an integrated diode unit, and / or an integrated transistor unit, and / or an integrated IGBT unit, and / or an integrated MOS gate-controlled diode (MGD) unit, and / or an integrated MOSFET unit and / or its derivatives. Such a diode unit and such a transistor unit can be integrated in a power semiconductor module.

[0029] The term "power semiconductor device" as used in this specification is intended to describe a semiconductor device with high voltage blocking and / or high current carrying capability on a single chip. In other words, such a power semiconductor device is prepared for high current (usually in the ampere range, for example up to tens or hundreds of amperes) and / or high voltage (usually above 50V, more typically 500V and above).

[0030] Figure 1 Different stages of a method 2 for processing a semiconductor device according to one or more embodiments are schematically illustrated.

[0031] In a first step 20, a semiconductor body 10 is provided. The semiconductor body 10 may present a dopant of a first conductivity type. For example, the semiconductor body 10 is n-doped. The semiconductor body 10 may be provided as part of a semiconductor wafer. For example, the semiconductor wafer may have a diameter of at least 200 mm, such as a diameter of 300 mm or even a diameter greater than 300 mm. For example, the semiconductor body 10 is a semiconductor wafer.

[0032] The semiconductor body 10 has a surface 10 - 1 which may extend along both a first lateral direction X and a second lateral direction Y, wherein each of these lateral directions X and Y may be a horizontal direction. Furthermore, the semiconductor body 10 may extend along a vertical direction Z perpendicular to the lateral directions X and Y, for example extending up to at least 10 μm, at least 40 μm, at least 60 μm, at least 110 μm or even more than 180 μm.

[0033] In a next step 21, at least one trench extending along the vertical direction Z into the semiconductor body 10 is formed. Figures 1 to 7 In FIG. 1 , two such grooves 11a and 11b are schematically shown. However, Figure 8 and Fig. 9 Only one such trench 11a is shown. It should be understood that, according to other embodiments, more than one trench or more than two trenches may be formed during step 21, respectively. For example, each trench formed during step 21 constitutes a transistor cell (in Figure 1 The step 21 of forming at least one trench 11a, 11b (step 21) may include an etching process step.

[0034] For example, the formed trenches 11a, 11b extend along the vertical direction Z by at least 1 μm, by at least 2 μm or by even more than 4 μm. The trenches 11a and 11b are laterally defined along the first lateral direction X by two trench sidewalls 113a, 113b, respectively. Furthermore, the trenches 11a and 11b are vertically defined along the vertical direction Z by trench bottoms 114a, 114b, respectively. For example, the trench sidewalls 113a and 113b extend substantially along a direction parallel to the vertical direction Z, and the trench bottoms 114a and 114b extend substantially along a direction parallel to the first lateral direction X and also along the vertical direction Z at the transition from the trench bottoms 114a, 114b to the trench sidewalls 113a, 113b; in other words, as Figure 1, the transition between the groove sidewalls 113a, 113b to the groove bottoms 114a and 114b can be curved. For example, in the context of the present specification, the groove sidewalls 113a, 113b can be portions of the groove surface that extend substantially only along the vertical direction Z. In addition, the widths of the grooves 11a, 11b along the first lateral direction X can each amount to less than 2 μm or even less than 1 μm. For example, the width of each groove 11a, 11b along the first lateral direction X is less than 40% or even less than 20% of the total extension of the corresponding groove 11a, 11b along the vertical direction Z. In addition, the grooves 11a and 11b can extend along the second lateral direction Y by at least 1 μm or at least 2 μm.

[0035] In a further step 26, the substance 31 is applied to at least a portion 111a, 111b of the groove surface formed by one of the groove side walls 113a, 113b and / or the groove bottom 114a, 114b of the respective groove 11a, 11b. At the same time, it can be prevented that the substance 31 is also applied to the other of the two groove side walls 113a, 113b. Thus, according to Figure 1 In the embodiment shown, the portion 111a of the groove surface of the groove 11a is constituted by only the right one of the groove side walls 113a and a portion of the groove bottom 114a, but not by the left one of the groove side walls 113a. In addition, according to this embodiment, the portion 111b of the groove surface of the groove 11b is constituted by only the left one of the two groove side walls 113b and portions of the groove bottom 114b, but not by the right one of the two groove side walls 113b. An exemplary manner of preventing the remaining portion of the groove surface from being subjected to the step of applying the substance 31 will be described in more detail below.

[0036] In an embodiment, only a portion of the groove bottoms 114a, 114b contributes to the portion 111a, 111b subjected to the application of the substance 31. For example, the portion amounts to no more than 80% of the total extension of the groove bottoms 114a, 114b along the first transverse direction X, no more than 65% or 60% of the total extension. Furthermore, the portion of the groove bottoms 114a, 114b may amount to more than 5%, 10% or even 20% of the total extension of the groove bottoms 114a, 114b along the first transverse direction X. For example, as in Figure 1 as well as Figures 5 to 7 as well as Fig. 9As schematically shown in each of the drawings, according to one or more embodiments, the portion of the groove bottom 114a, 114b that contributes to the portion 111a, 111b may be equivalent to about 40% to 60% of the total extension, wherein, according to one or more embodiments, the remaining portion of the groove bottom 114a, 114b is not subjected to the application of the substance 31. Figures 5 and 6 This aspect will be explained in more detail by way of example.

[0037] Applying the substance 31 during step 26 may include at least one of: plasma deposition (PLAD); angled implantation; and implantation substantially only along the vertical direction Z. For example, during angled implantation, it may be ensured that the angle between the ion implantation beam and the vertical direction Z is kept below 10°, below 8°, below 6° or even below 4°. Furthermore, the angles may even amount to substantially 0°, so that the implantation occurs substantially only along the vertical direction Z. Further variations of this implantation will be described in more detail below.

[0038] In a further step 28, diffusion is performed. Thus, the applied substance 31 can diffuse from the portions 111a, 111b of the trench surface into the semiconductor body 10. Thus, semiconductor regions 12a, 12b with dopants of the second conductivity type are formed. The second conductivity type can be the same as or complementary to the first conductivity type. For example, the semiconductor regions 12a, 12b formed can be p-doped regions. The semiconductor regions 12a, 12b can be arranged adjacent to the respective portions 111a, 111b. For example, as Figure 1 As indicated in FIG. 2 , the semiconductor region 12a is arranged adjacent to the portion 111a that has been subjected to the step of applying the substance 31 (step 26), and the semiconductor region 12b may be arranged adjacent to the portion 111b that has been subjected to the step of applying the substance 31 in the groove surface of the groove 11b. In addition, as Figure 1 As exemplarily shown in FIG. 1 , the portions 111 a and 111 b may include at least a portion of the respective groove bottoms 114 a , 114 b .

[0039] Thus, according to one or more embodiments, the formed semiconductor region 12a may be arranged adjacent to only one of the two trench sidewalls 113a. For example, the formed semiconductor region 12a may not be arranged adjacent to the remaining portion of the trench surface of the trench 11a that has not been subjected to the application of the substance 31. Similarly, the formed semiconductor region 12b may not be arranged adjacent to the remaining portion of the trench surface of the trench 11b that has not been subjected to the application of the substance 31, for example.

[0040] Furthermore, according to one or more embodiments, the formed semiconductor regions 12a, 12b may extend deeper into the semiconductor body 10 along the vertical direction Z than the corresponding trenches 11a, 11b. For example, the semiconductor region 12a extends into the semiconductor body 10 by more than 10%, more than 30%, more than 60% or even more than 100% of the total extension of the trench 11a, wherein the total extension of the trench 11a may be, for example, the distance between the trench surface 10-1 and the lowest point of the trench bottom 114a along the vertical direction Z. In other words, the lowest point of the semiconductor region 12a may be positioned deeper in the semiconductor body 10 than the lowest point of the trench bottom 114a. For example, the distance between the two lowest points along the vertical direction Z may be equivalent to at least 1 μm or at least 3 μm. The dopant concentration of the dopant of the second conductivity type at the lowest point of the formed semiconductor region 12a may be equivalent to at least 10 15 cm -3 , equivalent to at least 10 16 cm -3 Or even converted to more than 10 17 cm -3 The above description is also applicable to the semiconductor region 12b formed. In addition, it should be understood that Figure 1 , the formed semiconductor regions 12a, 12b do not necessarily extend from the surface 10-1 of the semiconductor body 10 along the vertical direction Z. More precisely, at least the upper parts of the parts 111a, 111b forming the trench sidewalls 113a, 113b may also be prevented from being subjected to the application of the substance 31. For example, only the trench bottoms 114a, 114b or respectively a part thereof may be subjected to the application of the substance 31.

[0041] Therefore, relative to the surface 10-1 of the semiconductor body 10, relatively deep semiconductor regions 12a, 12b can be formed by implementing a diffusion treatment, wherein, since the distance over which the applied substance 31 must diffuse into the semiconductor body 10 is relatively low, the diffusion treatment can be implemented using a relatively low temperature and / or within a relatively short period of time.

[0042] according to Figure 1In the embodiment schematically shown in FIG. 1 , the transition between the trenches 11a, 11b and the semiconductor regions 12a, 12b formed and arranged adjacent to the trenches 11a, 11b may extend continuously along only one of the trench sidewalls 113a, 113b to the trench bottom 114a, 114b. For example, the transition may start at the surface 10-1 of the semiconductor body 10 and may extend continuously along the vertical direction to the starting point of the trench bottom 114a, 114b and extend along a portion of the trench bottom 114a, 114b along the first lateral direction X (or in the opposite direction). Furthermore, depending on, for example, the duration of the diffusion and at least one of the percentage of the trench bottom 114a, 114b that may contribute to the portions 111a, 111b, the formed semiconductor regions 12a, 12b may further extend laterally along the trench bottom 114a, 114b, for example even such that the formed semiconductor regions 12a, 12b reach the transition from the trench bottom 114a, 114b to the other of the trench sidewalls 113a, 113b.

[0043] However, it should be understood that, according to another embodiment, the step of applying the substance 31 (step 26) can be implemented so as to ensure that the substance 31 is not applied to any of the trench sidewalls 113a, 113b. For example, the step 26 of applying the substance 31 can therefore be implemented by a substantially vertical ion beam implantation in a direction substantially parallel to the extension direction of the trenches 11a, 11b (for example substantially only in the vertical direction Z); wherein, in this specification, the latter expression is intended to express a beam direction in the vertical direction Z or within a deviation of, for example, less than 15° from the vertical direction Z. For this purpose, the sidewalls 113a, 113b of the trenches 11a, 11b can be protected so that they are not subjected to the implantation, which will be explained in more detail below. Moreover, as indicated above, in an embodiment, only a portion of the trench bottom 114a, 114b contributes to the portion 111a, 111b subjected to the application of the substance 31. For example, the portion is converted to no more than 80%, no more than 65% or 60% of the total extension of the groove bottoms 114a, 114b along the first transverse direction X. In addition, the portion of the groove bottoms 114a, 114b can be converted to more than 5%, 10% or even 20% of the total extension of the groove bottoms 114a, 114b along the first transverse direction X.

[0044] Now with regard to the step of applying the substance 31 in detail (step 26), it should be understood that the substance 31 can be gaseous and that applying the substance 31 can include a masked diffusion process, for example, instead of the implantation process mentioned above as an example. For this purpose, the surface 10-1 of the semiconductor body 10 can be masked with a mask (not shown), and then a masked diffusion can be performed so that, for example, only parts 111a, 111b of the surface of the trenches 11a, 11b are subjected to the application of the substance 31.

[0045] For example, the substance 31 may include at least one of boron, aluminum and gallium. For example, in the case of an n-doped semiconductor body 10, such a substance is used to form p-doped semiconductor regions 12a, 12b. In another embodiment, the substance may include at least one of phosphorus, antimony and arsenic. For example, in the case of a p-doped semiconductor body 10, such a substance is used to form n-doped semiconductor regions 12a, 12b.

[0046] Furthermore, according to an embodiment, a sputtering process may be performed before applying the substance 31 during step 26. Such a sputtering process may be performed to remove an oxide layer (not shown) present at the portions 111a, 111b, which is formed after the trenches 11a, 11b are formed or after the masking layer ( Figure 1 11a, 11b). For example, the thickness of such an oxide layer can be less than 3 nm. Therefore, according to an embodiment, such a sputtering process can ensure that the substance 31 is applied directly to the surface of the trenches 11a, 11b and can therefore support the subsequent diffusion step, because the applied substance 31 does not have to pass through the oxide layer. In addition, if the sputtering process is carried out after the masking layer has been formed, the sputtering process can be carried out so that the masking layer remains present on the semiconductor body 10 with sufficient thickness, for example in an area that should not be subjected to the application of the substance 31.

[0047] An exemplary manner of preventing the remainder of the groove surface from becoming subject to the application of substance 31 is described in more detail below:

[0048] For example, regarding Figure 2 In the method step 22 schematically shown in FIG. 2 , after the trenches 11a, 11b have been formed (step 21), a masking layer 13 may be formed at or on the trench surface formed by the sidewalls 113a, 113b and the trench bottoms 114a, 114b of the trenches 11a, 11b. Figure 2 As shown in , in addition, the surface 10 - 1 of the semiconductor body 10 may also be covered by a masking layer 13. Forming the masking layer 13 (step 22) may include performing an oxidation step. Thus, the masking layer 13 may be formed of an oxide such as silicon dioxide.

[0049] Now about Figure 3 In method step 23 schematically shown in FIG. 1 , after a masking layer 13 has been formed on the trench surface, the trenches 11a, 11b may be filled with a trench filling material 32. The trench filling material 32 may include at least one of carbon, oxide or other materials that can be easily etched.

[0050] In addition, regarding Figure 4 and Figure 5 , a mask 4 may be formed that only partially covers the openings 115a, 115b of the trenches 11a, 11b. The step 24 of forming the mask 4 may include performing a trench lithography process step, for example, such that the trenches 11a, 11b become only partially opened. For example, the mask 4 covers at least 30% of the trench opening 115a. In another embodiment, the mask 4 may cover at least 50%, at least 70%, or at least 90% of the trench opening 115a. For example, the portion of the mask 4 that partially covers the opening 115a of the trench 11a is supported by the trench filling material 32 that has been filled into the trench 11a before the step of forming the mask 4. Thus, according to the embodiment, at least 10%, at least 20%, at least 30%, or at least 50% of the trench opening 115a is covered by the mask 4. The above may also apply to the trench 11b.

[0051] In the next step 25, if Figure 5 As schematically shown in , both the portion of the trench filling material 32 not covered by the mask 4 and the portion of the masking layer 13 adjacent to the portion of the trench filling material 32 not covered by the mask 4 can be removed. Such removal can include the implementation of an etching process step, which can include, for example, an anisotropic etching process. As a result, the portions 111a, 111b are exposed so that they can later be subjected to the subsequent application of the substance 31 (step 26). As previously explained, before applying the substance 31, a sputtering process can be implemented to remove the masking layer or oxide layer that eventually remains. In addition, in an embodiment, within the removal step 25, only a portion of the trench bottom 114a, 114b is exposed, resulting in only the exposed portion contributing to the portions 111a, 111b that may be subjected to the application of the substance 31. For example, the exposed portion is equivalent to no more than 80% of the total extension of the groove bottom 114a, 114b along the first transverse direction X, is equivalent to no more than 65% of the total extension, or is equivalent to no more than 60% of the total extension. In addition, the portion of the groove bottom 114a, 114b can be equivalent to more than 5%, 10% or even 20% of the total extension of the groove bottom 114a, 114b along the first transverse direction X.

[0052] like Figure 6As schematically shown, during the application of the substance 31 (step 26), the remaining portion of the trench filling material 32 and / or the remaining portion of the masking layer 13 may cover the remaining portion of the trench surface, for example at least one of the two trench sidewalls 113a, 113b. Figure 6 The left groove side wall 113a of the groove 11a and the right groove side wall 113b of the groove 11b are not subjected to the application of the substance 31.

[0053] For example, after applying the substance 31 (step 26), the remaining portion of the trench filling material 32 within the trenches 11a, 11b and the remaining masking layer 13 may be removed (step 27). Next, a diffusion step 28 may be performed to form the semiconductor regions 12a, 12b. In an embodiment, the diffusion step 28 may be performed in an oxidizing atmosphere, for example to avoid outdiffusion of the substance 31 through the trench sidewalls 113a, 113b. Alternatively or additionally, an oxide may be deposited, for example at a relatively low temperature, along the trench sidewalls 113a, 113b.

[0054] After the diffusion process, for example after the formation of the semiconductor regions 12a, 12b, the semiconductor device 1 may be further processed, wherein such further processing may include forming control electrodes in the trenches 11a, 11b (see Figure 8 For example, such a control electrode may be formed by a trench isolation material (in Figures 1 to 7 (not shown) a gate electrode insulated from the semiconductor body 10. In addition, further processing may include forming a semiconductor source region and a semiconductor body region adjacent to the trenches 11a, 11b; for example, to form a MOS control head of a transistor cell. Figure 8 Let's explain these aspects in more detail.

[0055] With respect to all embodiments, as described above, the application of the substance 31 (step 26) may include a plasma deposition treatment step. For example, the plasma deposition treatment step is performed after a portion of the trench filling material 32 has been removed and portions 111a, 111b of the trenches 11a, 11b have been exposed. Instead of or in addition to the plasma deposition treatment step, an implantation may be performed, such as a vertical implantation and / or an angled implantation along the vertical direction Z, wherein, as already described above, the angle of the ion beam of the angled implantation may be less than 10°. By means of the vertical implantation, the dopant concentration in the deeper parts of the semiconductor regions 12a, 12b may be increased, wherein the angled implantation may increase the dopant concentration in the areas adjacent to the trench sidewalls, for example in the upper parts of the semiconductor regions 12a, 12b. The combination of angled implantation, vertical implantation and / or plasma deposition may allow different dopant concentration profiles to be achieved within the formed semiconductor regions 12a, 12b along the vertical direction Z. Reference will be made to FIG. 1 for details. Fig. 9 An example of such a dopant concentration profile is described in more detail.

[0056] like Figures 1 to 7 As has been shown, more than one trench may be produced in the semiconductor body 10, for example at least two trenches 11a, 11b may be produced, and of course many more than two trenches may be produced in the semiconductor body 10 during step 21. Figures 4 to 7 In the schematically illustrated embodiment, semiconductor regions 12a and 12b are formed in a mesa section 10-2 of a semiconductor body 10 that is laterally bounded by one of two side walls 113a and one of two side walls 113b. For example, the distance between two mutually opposite side walls of different trenches 11a and 11b along the first lateral direction X can be converted to less than 10 μm, less than 5 μm, less than 2 μm or even less than 1 μm. For this purpose, the mask 4 can be formed so that the portion of the surface 10-1 above the mesa section 10-2 of the semiconductor body 10 also remains exposed, that is, not covered by the mask 4. The step of removing the masking layer 13 can also include at least partially removing the masking layer 13 that has been formed on the surface 10-1 above the mesa section 10-2. Then, during the application of the substance 31 (step 26), at least the corresponding portion of the surface 10-1 above the mesa portion 10-2 may also be subjected to the application of the substance 31, for example, by plasma deposition, vertical implantation and / or angled implantation and / or masked diffusion. Accordingly, during the diffusion step (step 28), the substance 31 may also be diffused from the surface 10-1 above the mesa portion 10-2 into the semiconductor body 10 along the vertical direction Z, thereby forming Figure 7, wherein the further semiconductor region 19 and the formed semiconductor regions 12a and 12b can form a continuous semiconductor region having a dopant of the second conductivity type. After the diffusion treatment, the dopant concentration in the continuous semiconductor regions 19, 12a, 12b can also be adjusted by performing surface implantation. For example, after such continuous semiconductor regions 19, 12a, 12b have been formed, the semiconductor device 1 can be further processed, wherein such further processing can include forming a MOS control header, which is arranged to be adjacent to another side wall of the trench sidewalls 113a and 113b that is not adjacent to the continuous semiconductor regions 12a, 19, 12b. This aspect will now be described in more detail.

[0057] Figure 8 A portion of a vertical cross section of a power semiconductor transistor 5 (hereinafter also referred to as a "transistor") is schematically shown, the transistor 5 comprising a semiconductor body 10 and at least one transistor cell 50. For example, the transistor 5 presents an IGBT structure or a MOSFET structure. The transistor cell 50 comprises a semiconductor drift region 501 having a dopant of a first conductivity type. For example, the semiconductor drift region is an n-doped semiconductor region. In addition, the transistor cell 50 comprises a semiconductor body region 502, which is included in the semiconductor body 10 and has a dopant of a second conductivity type. For example, the semiconductor body region 502 is a p-region. In addition, the transistor 50 comprises a source region 503, which may be a semiconductor source region 503, wherein the semiconductor body region 502 isolates the source region 503 from the semiconductor drift region 501.

[0058] The transistor cell 50 further includes a trench 11a extending into the semiconductor body 10 along the vertical direction Z and including a control electrode 116a, the control electrode 116a being electrically insulated from each of the semiconductor drift region 501, the semiconductor body region 502 and the source region 503. For this purpose, an insulator 117a ensuring the insulation may be included in the trench 11a. The control electrode 116a may be a gate electrode. Thus, the transistor cell 50 may include a MOS control head having a gate trench structure.

[0059] The power semiconductor transistor 5 may further include a first load terminal 51 and a second load terminal 52 coupled to the semiconductor body 10. For example, the transistor is configured to conduct a load current between the first load terminal 51 and the second load terminal 52, wherein the transistor 5 may be controlled by a control signal provided to the control electrode 116a. For this purpose, the control electrode 116a may be electrically connected to a control terminal 53. The control terminal 53 may be a gate terminal, the first load terminal 51 may be a source terminal, and the second load terminal 52 may be a drain terminal. Each of the source region 503 and the semiconductor body region 502 may be electrically connected to the first load terminal 51 by means of a first metallization 511. The second load terminal 52 may be electrically connected to the semiconductor body 10 by means of a second metallization 521. For example, the first metallization 511 is a front side metallization of the transistor 5, and the second metallization 521 is a back side metallization of the transistor 5. The transistor 5 may include a plurality of transistor cells 50.

[0060] like Figure 8 As schematically shown in FIG. 1 , both the source region 503 and the semiconductor body region 502 may be in contact with one of the two sidewalls 113 a of the trench 11 a , that is, in contact with the insulator 117 a .

[0061] Adjacent to the other of the two trench sidewalls 113a, a semiconductor region 12a having a dopant of the second conductivity type may be included. For example, the semiconductor region 12a is a p-doped semiconductor region.

[0062] For example, according to the above reference Figures 1 to 7 One or more embodiments of the method 2 described have formed the semiconductor region 12 a of the power semiconductor transistor 5 .

[0063] For example, the semiconductor region 12a is arranged adjacent to the trench 11a, i.e. in contact with one of the trench sidewalls 113a and the trench bottom 114a. In addition, the semiconductor region 12a may be arranged to be separated from the semiconductor body region 502. For example, the semiconductor body region 502 and the semiconductor region 12a are spatially isolated from each other by means of the trench 11a and the drift region 501. In addition, as already explained above, the further semiconductor region 19 (not shown) Figure 8 As shown in Figure 7 ) may be arranged laterally adjacent to the semiconductor region 12a. What has been stated above with respect to the further semiconductor region 19 may also apply to the power semiconductor transistor 5.

[0064] Furthermore, the semiconductor region 12 a may be an electrically floating region. For example, the semiconductor region 12 a is not connected to any of the first load terminal 51 , the second load terminal 52 , and the control terminal 53 , nor to any other defined potential.

[0065] According to an embodiment, the dopant concentration of the semiconductor region 12a adjacent to the trench sidewall 113a is converted to a fixed dopant concentration value in the range of 50% to 150%, in the range of 70% to 130%, or even in the range of 90% to 110%, wherein the fixed dopant concentration value is a fixed dopant concentration value at any point along at least 60% of the total extension of the semiconductor region 12a in the vertical direction Z. Such a substantially uniform dopant concentration distribution may exist for up to or even greater than 60% of the total extension in the vertical direction Z, for example, even greater than 70%, 80%, 90%, or even greater than 95%, for example, greater than 98% of the total extension of the semiconductor region 12a in the vertical direction Z. Fig. 9 Such a uniform dopant concentration along the vertical direction Z is schematically illustrated in , with the variable (A) indicating the dopant concentration CC along the vertical direction Z. Therefore, according to the variable (A), the dopant concentration CC does not substantially deviate from the fixed dopant concentration value CC1. On the contrary, the dopant concentration CC may be in the range of 90% to 110% of the fixed dopant concentration value CC1, wherein the range may be even smaller, such as 95% to 105% of the fixed dopant concentration value CC1, or even smaller, such as between 98% and 102% of the fixed dopant concentration value CC1. According to an embodiment, such a substantially uniform dopant concentration along the vertical direction Z may be achieved by means of an angled implantation or by means of a plasma deposition step, as has been exemplarily described above with reference to method step 26.

[0066] According to another embodiment, the dopant concentration CC of the semiconductor region 12a adjacent to the trench sidewall 113a varies by at least 30% from the dopant concentration value present in a portion equivalent to at least 80% of the total extension of the semiconductor region 12a in the vertical direction Z. For example, by applying (step 26) the substance 31 in combination with plasma deposition, angled implantation and / or vertical implantation in the vertical direction Z and / or masked diffusion, a dopant profile exhibiting a significant variation in magnitude in the vertical direction Z can be formed in the semiconductor region 12a.

[0067] For example, Fig. 9 As schematically shown in FIG. 1 , the portion equivalent to at least 80% of the total extension of the semiconductor region 12a along the vertical direction Z can be divided into a first portion 12a-1 and a second portion 12a-2. It should be understood that the portion can also be equivalent to more than 85% of the total extension of the semiconductor region 12a along the vertical direction Z, more than 90% of the total extension of the semiconductor region 12a along the vertical direction Z, more than 95% or even more than 99%.

[0068] according to Fig. 9The variation of the dopant concentration in the above-mentioned part is constituted by an increase along the vertical direction Z. Thus, in the first part 12a-1 and the second part 12a-2, the dopant concentration of the semiconductor region 12a can increase along the vertical direction Z, wherein the increase can be converted to at least 30% of the fixed dopant concentration CC1. In other words, in the upper part of the semiconductor region 12a, the dopant concentration CC can be converted to the value CC1, while in the lower part of the semiconductor region 12a, the dopant concentration CC can be converted to at least 1.3*CC1.

[0069] According to Fig. 9 In another embodiment schematically shown in (C), the variation of the dopant concentration in the above-mentioned portion may consist of a decrease along the vertical direction Z. Therefore, in the upper portion of the semiconductor region 12a, the dopant concentration may be converted to a value CC1, while in the lower portion, the dopant concentration CC of the semiconductor region 12a may be converted to at most 0.7*CC1.

[0070] According to yet another embodiment, the dopant concentration in the first portion 12a - 1 decreases along the vertical direction Z, while the dopant concentration in the second portion 12a - 2 increases along the vertical direction Z. Fig. 9 This embodiment is schematically shown in (D) of FIG. 1 . For example, such a dopant profile can be achieved by not only performing a vertical implantation so that the substance 31 is applied substantially only to at least a portion of the trench bottom 114 a, but also subjecting the surface 10 - 1 of the semiconductor body 10 to a surface implantation. Thereafter, diffusion can be performed, which can produce a dopant profile such as Fig. 9 The dopant concentration distribution is schematically shown in (D).

[0071] As shown, the first portion 12a-1 may be an upper portion of the semiconductor region 12a, and the second portion 12a-2 may be a lower portion of the semiconductor region 12a. The decrease in the vertical direction Z in the first portion 12a-1 may be equivalent to at least 30% of the initial dopant concentration value present adjacent to the surface 10-1 of the semiconductor body 10. In addition, the increase in the vertical direction Z within the second portion 12a-2 may also be equivalent to at least 30% of the dopant concentration value present at the transition between the first portion 12a-1 and the second portion 12a-2.

[0072] According to all embodiments, the total extension of the semiconductor regions 12a, 12b along the vertical direction Z may be in the range of 2 to 50 μm, in the range of 3 to 15 μm or in the range of 4 to 10 μm. Instead of constituting electrically floating regions, the semiconductor regions 12a, 12b may also be connected to a fixed potential, such as the potential of the first load terminal 51, the potential of the gate terminal 53, to name a few. Thus, a low voltage between the semiconductor region 12a and the control electrode 116a may be achieved, thereby reducing the electric field within the trench insulator 117a.

[0073] Features of further embodiments are defined in the dependent claims. Features of further embodiments and features of the embodiments described above may be combined with one another to form additional embodiments, as long as the features are not explicitly described as alternatives to one another.

[0074] In the above, embodiments related to semiconductor wafers and methods and systems for processing semiconductor wafers are described. For example, these semiconductor wafers are based on silicon (Si). Therefore, single crystal semiconductor regions or layers, such as semiconductor regions 10 and 12a to 12b, 503, 502 in the exemplary embodiment, can be single crystal silicon regions or silicon layers. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0075] However, it should be understood that the semiconductor regions 10 and 12a to 12b, 503, 502 can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to: basic semiconductor materials such as silicon (Si) or germanium (Ge); Group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), gallium indium aluminum nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) (to name a few). The semiconductor materials mentioned above are also called "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-gallium indium aluminum nitride (AlGaInN), indium gallium nitride (InGaN)-gallium indium aluminum nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs and GaN materials are currently used.

[0076] For ease of description, spatially relative terms such as "under", "below", "lower", "above", "higher", etc. are used to illustrate the positioning of one element relative to a second element. These terms are intended to include different orientations of various devices other than those shown in the drawings. In addition, terms such as "first", "second", etc. are also used to describe various elements, regions, parts, etc., and terms such as "first", "second", etc. are also not intended to be limiting. Throughout this specification, the same terms refer to the same elements.

[0077] As used herein, the terms "having", "comprising", "including", "containing", "presenting", etc. are open terms that indicate the presence of described elements or features, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include plural as well as singular forms.

[0078] In view of the above series of variations and applications, it should be understood that the present invention is not limited to the foregoing description, nor is it limited to the accompanying drawings. Instead, the present invention is limited only by the appended claims and their legal equivalents.

Claims

1. A method (2) for processing a semiconductor device (1), comprising: Providing (20) a semiconductor body (10) having a dopant of a first conductivity type; forming (21) a left trench (11a) and a right trench (11b) extending into the semiconductor body (10) in a vertical direction, wherein each of the trenches (11a, 11b) is laterally defined by two trench sidewalls (113a, 113b) and vertically defined by a trench bottom (114a); applying (26) a substance (31) to at least a portion (111a, 111b) of a respective groove surface of the grooves (11a, 11b), each portion (111a, 111b) being formed by one of the groove sidewalls (113a, 113b) and / or the groove bottom (114a, 114b) of the respective groove (11a, 11b), wherein applying (26) the substance (31) comprises preventing the substance from being applied to the other of the groove sidewalls (113a); wherein the portion (111a) of the groove surface of the left groove (11a) is constituted only by the right groove sidewall of the groove sidewall (113a) and a portion of the groove bottom (114a), but not by the left groove sidewall of the groove sidewall (113a); and wherein the portion (111b) of the groove surface of the right groove (11b) is constituted only by the left groove sidewall of the two groove sidewalls (113b) and a portion of the groove bottom (114b), but not by the right groove sidewall of the two groove sidewalls (113b); and causing the applied substance (31) to diffuse (28) from the portion (111a) into the semiconductor body (10), thereby forming a semiconductor region (12a) having a dopant of the second conductivity type in the semiconductor body (10), wherein the semiconductor region (12a) is arranged adjacent to the portion (111a), The steps of applying the substance (31) and diffusing the applied substance (31) are performed so that the dopant concentration of the semiconductor region (12a) formed adjacent to the side wall of the one trench is converted to a value in the range of 50% to 150% of a fixed dopant concentration value, wherein the fixed dopant concentration value is a fixed dopant concentration value at any point along at least 60% of the total extension of the semiconductor region (12a) in the vertical direction.

2. The method (2) according to claim 1, wherein: Applying (26) the substance (31) comprises at least one of: plasma deposition; angled implantation; and implantation substantially only along the vertical direction.

3. The method (2) according to claim 1 or 2, wherein: The substance (31) is gaseous, and applying (26) the substance (31) comprises masked diffusion.

4. The method (2) according to claim 1 or 2, further comprising: Before applying (26) the substance (31), a sputtering process is performed to remove an oxide layer existing at the portion (111a) generated after forming (21) the trench (11a).

5. The method (2) according to claim 1 or 2, wherein: The substance (31) includes at least one of boron, aluminum and gallium.

6. The method (2) according to claim 1 or 2, wherein: The substance (31) includes at least one of phosphorus, antimony and arsenic.

7. The method (2) according to claim 1 or 2, wherein: The portion (111a) includes only the groove bottom (114a) or a portion thereof, and wherein applying (26) the substance (31) includes ensuring that the substance (31) is not applied to any of the groove sidewalls (113a).

8. The method (2) according to claim 1 or 2, wherein: The transition between the trench (11a) and the formed semiconductor region (12a) extends continuously along only one of the trench sidewalls (113a) to the trench bottom (114a).

9. The method (2) according to claim 1 or 2, wherein: The semiconductor body (10) is provided as part of a semiconductor wafer having a diameter of at least 200 mm.

10. The method (2) according to claim 1 or 2, further comprising: Dopants of the second conductivity type are implanted into the semiconductor body (10) by performing a surface implantation.

11. The method (2) according to claim 1 or 2, further comprising: Prior to applying (26) the substance (31), forming (22) a masking layer (13) on the surface (113a, 114a) of the groove; filling (23) the trench (11a) with a trench filling material (32); forming (24) a mask (4) that only partially covers the opening (115a) of the trench (11a); as well as Portions of the trench filling material (32) not covered by the mask (4) and portions of the masking layer (13) adjacent to the portions of the trench filling material (32) not covered by the mask (4) are removed (25) to expose only a portion (111a) of the trench surface (113a, 114a) that is subsequently subjected to application (26) of the substance (31).

12. The method (2) according to claim 11, further comprising: After applying (26) the substance (31), Remaining portions of the trench filling material (32) and remaining masking layer (13) within the trench (11a) are removed (27), wherein a diffusion step (28) is performed after the removing step (27).

13. The method (2) according to claim 1 or 2, further comprising: A control electrode (116a) is formed in the trench (11a).

14. The method (2) according to claim 1 or 2, wherein: The steps of applying (26) the substance (31) and diffusing (28) the applied substance (31) are performed so that the dopant concentration of the semiconductor region (12a) adjacent to the trench sidewall (113a) in a portion (12a-1, 12a-2) equivalent to at least 80% of the total extension of the semiconductor region (12a) along the vertical direction changes by at least 30% from the dopant concentration value existing in the portion (12a-1, 12a-2).

15. A method (2) for processing a semiconductor device (1), comprising: Providing (20) a semiconductor body (10) having a dopant of a first conductivity type; forming (21) at least one trench (11a) extending into the semiconductor body (10) in a vertical direction; applying (26) a substance (31) to at least a portion (111a) of a groove surface formed by at least one of the groove sidewalls (113a) and the groove bottom (114a) of the at least one groove (11a); as well as causing the applied substance (31) to diffuse from the portion (111a) into the semiconductor body (10), thereby forming a semiconductor region (12a) having a dopant of the second conductivity type in the semiconductor body (10), and the semiconductor region (12a) is arranged adjacent to the portion (111a), wherein the formed semiconductor region (12a) extends deeper than the at least one trench (11a) in the vertical direction, The steps of applying the substance (31) and diffusing the applied substance (31) are performed so that the dopant concentration of the formed semiconductor region (12a) adjacent to the side wall of the at least one trench is converted to a value in the range of 50% to 150% of a fixed dopant concentration value, wherein the fixed dopant concentration value is a fixed dopant concentration value at any point along at least 60% of the total extension of the semiconductor region (12a) in the vertical direction.

16. The method (2) according to claim 15, wherein: Applying (26) the substance (31) comprises at least one of: plasma deposition; angled implantation; and implantation substantially only along the vertical direction.

17. The method (2) according to claim 15 or 16, wherein: The substance (31) is gaseous, and applying (26) the substance (31) comprises masked diffusion.

18. The method (2) according to claim 15 or 16, further comprising: Before applying (26) the substance (31), a sputtering process is performed to remove an oxide layer existing at the portion (111a) produced after forming (21) the at least one trench (11a).

19. The method (2) according to claim 15 or 16, wherein: The substance (31) includes at least one of boron, aluminum and gallium.

20. The method (2) according to claim 15 or 16, wherein: The substance (31) includes at least one of phosphorus, antimony and arsenic.

21. The method (2) according to claim 15 or 16, wherein: Applying (26) the substance (31) includes ensuring that the substance (31) is not applied to any of the trench sidewalls (113a).

22. The method (2) according to claim 15 or 16, wherein: The transition between the at least one trench (11a) and the formed semiconductor region (12a) extends continuously along only one of the trench sidewalls (113a) to the trench bottom (114a).

23. The method (2) according to claim 15 or 16, wherein: The semiconductor body (10) is provided as part of a semiconductor wafer having a diameter of at least 200 mm.

24. The method (2) according to claim 15 or 16, further comprising: Dopants of the second conductivity type are implanted into the semiconductor body (10) by performing a surface implantation.

25. The method (2) according to claim 15 or 16, further comprising: Prior to applying (26) the substance (31), forming (22) a masking layer (13) on the surface (113a, 114a) of the groove; filling (23) the at least one trench (11a) with a trench filling material (32); forming (24) a mask (4) that only partially covers the opening (115a) of the at least one trench (11a); as well as Portions of the trench filling material (32) not covered by the mask (4) and portions of the masking layer (13) adjacent to the portions of the trench filling material (32) not covered by the mask (4) are removed (25) to expose only a portion (111a) of the trench surface (113a, 114a) that is subsequently subjected to application (26) of the substance (31).

26. The method (2) according to claim 25, further comprising: After applying (26) the substance (31), Remaining portions of the trench filling material (32) and remaining masking layer (13) within the at least one trench (11a) are removed (27), wherein a diffusion step (28) is performed after the removing step (27).

27. The method (2) according to claim 15 or 16, further comprising: A control electrode (116a) is formed in the at least one trench (11a).

28. The method (2) according to claim 15 or 16, wherein: The steps of applying (26) the substance (31) and diffusing (28) the applied substance (31) are performed so that the dopant concentration of the semiconductor region (12a) adjacent to the trench sidewall (113a) in a portion (12a-1, 12a-2) equivalent to at least 80% of the total extension of the semiconductor region (12a) along the vertical direction changes by at least 30% from the dopant concentration value existing in the portion (12a-1, 12a-2).

29. A power semiconductor transistor (5), comprising a semiconductor body (10) and at least one transistor unit (50), wherein the at least one transistor unit (50) has: a semiconductor drift region (501) included in the semiconductor body (10) and having a dopant of a first conductivity type; a semiconductor body region (502) included in the semiconductor body (10) and having a dopant of a second conductivity type; A source region (503), wherein the semiconductor body region (502) isolates the source region (503) from the semiconductor drift region (501); a trench (11a) extending into the semiconductor body (10) in a vertical direction and comprising a control electrode (116a) electrically insulated from each of the semiconductor drift region (501), the semiconductor body region (502) and the source region (503); and a semiconductor region (12a) having a dopant of a second conductivity type and arranged adjacent to the trench (11a) and separated from the semiconductor body region (502), wherein the transition between the trench (11a) and the semiconductor region (12a) extends along a trench sidewall (113a) of the trench (11a), And wherein, the dopant concentration of the semiconductor region (12a) adjacent to the trench sidewall (113a) is converted to a value in the range of 50% to 150% of a fixed dopant concentration value, wherein the fixed dopant concentration value is a fixed dopant concentration value at any point along at least 60% of the total extension of the semiconductor region (12a) in the vertical direction.

30. A power semiconductor transistor (5), comprising a semiconductor body (10) and at least one transistor unit (50), wherein the at least one transistor unit (50) has: a semiconductor drift region (501) included in the semiconductor body (10) and having a dopant of a first conductivity type; a semiconductor body region (502) included in the semiconductor body (10) and having a dopant of a second conductivity type; A source region (503), wherein The semiconductor body region (502) isolates the source region (503) from the semiconductor drift region (501); a trench (11a) extending into the semiconductor body (10) in a vertical direction and comprising a control electrode (116a) electrically insulated from each of the semiconductor drift region (501), the semiconductor body region (502) and the source region (503); and a semiconductor region (12a) having a dopant of a second conductivity type and arranged adjacent to the trench (11a) and separated from the semiconductor body region (502), wherein the transition between the trench (11a) and the semiconductor region (12a) extends along a trench sidewall (113a) of the trench (11a), wherein, in a portion (12a-1, 12a-2) equivalent to at least 80% of the total extension of the semiconductor region (12a) along the vertical direction, the dopant concentration of the semiconductor region (12a) adjacent to the trench sidewall (113a) changes by at least 30% from the dopant concentration value present in the portion (12a-1, 12a-2), And wherein, the dopant concentration of the semiconductor region (12a) adjacent to the trench sidewall (113a) is converted to a value in the range of 50% to 150% of a fixed dopant concentration value, wherein the fixed dopant concentration value is a fixed dopant concentration value at any point along at least 60% of the total extension of the semiconductor region (12a) in the vertical direction.

31. The transistor (5) according to claim 30, wherein The variation of the dopant concentration in the portions (12a-1, 12a-2) consists of an increase along the vertical direction.

32. The transistor (5) according to claim 30, wherein The variation of the dopant concentration in the portions (12a-1, 12a-2) consists of a decrease along the vertical direction.

33. The transistor (5) according to claim 30, wherein The portion is divided into a first portion (12a-1) and a second portion (12a-2), and wherein, in the first portion (12a-1), the dopant concentration decreases along the vertical direction; and in the second portion (12a-2), the dopant concentration increases along the vertical direction.

34. A method (2) of processing a semiconductor device (1), comprising: Providing (20) a semiconductor body (10) having a dopant of a first conductivity type; forming (21) at least one trench (11a) extending into the semiconductor body (10) in a vertical direction, the trench (11a) being laterally delimited by two trench sidewalls (113a) and vertically delimited by a trench bottom (114a); applying (26) a substance (31) to at least a portion (111a) of a groove surface formed by one of the groove sidewalls (113a) and / or the groove bottom (114a) of the at least one groove (11a), wherein applying (26) the substance (31) includes preventing the substance from being applied to another of the groove sidewalls (113a); and causing the applied substance (31) to diffuse (28) from the portion (111a) into the semiconductor body (10), thereby forming a semiconductor region (12a) having a dopant of the second conductivity type in the semiconductor body (10), wherein the semiconductor region (12a) is arranged adjacent to the portion (111a), The steps of applying the substance (31) and diffusing the applied substance (31) are performed so that the dopant concentration of the semiconductor region (12a) formed adjacent to the side wall of the one trench is converted to a value in the range of 50% to 150% of a fixed dopant concentration value, wherein the fixed dopant concentration value is a fixed dopant concentration value at any point along at least 60% of the total extension of the semiconductor region (12a) in the vertical direction.

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