String operation method, string operation device and storage medium

Abstract

A string operation method, string operation device, and storage medium are disclosed. The method comprises: obtaining a unit operation width corresponding to the type of string operation; obtaining a processing data width for the target data to be operated; obtaining a number of repeated operations of the string operation on the target data; determining mask information based on the unit operation width, the processing data width, and the number of repeated operations; and writing the operation portion to a target address based on the mask information. This method effectively improves the execution speed of string operation instructions, reduces the number of micro-operations during the execution of string operation instructions, and increases the utilization of processor hardware resources.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a string operation method, a string operation device, and a storage medium. Background Art

[0002] With the advancement of information technology, more and more data requires efficient and rapid computation. This data processing places increasingly stringent demands on processor performance, making the design and generation of high-performance processors a pressing challenge. Optimizing processor performance requires significant improvements to the processor's architecture, such as improving the execution order of instructions, minimizing power consumption, and enhancing parallel computing capabilities. Summary of the Invention

[0003] Some embodiments of the present disclosure provide a string operation method, which includes: obtaining a unit operation width corresponding to the type of the string operation, wherein the unit operation width is the data width in a single operation of the string operation; obtaining a processing data width for object data to be operated; obtaining the number of repeated operations of the string operation for the object data, wherein the number of repeated operations is the total number of times the single operation needs to be repeated to operate the object data; determining masking information based on the unit operation width, the processing data width, and the number of repeated operations, wherein the object data includes an operation part and a non-operation part, and the masking information is used to indicate the non-operation part; and writing the operation part to a target address based on the masking information.

[0004] For example, in a string operation method provided in some embodiments of the present disclosure, the string operation includes a string storage operation or a string load operation.

[0005] For example, some embodiments of the present disclosure provide a string operation method further comprising: reading the object data of the processing data width from a source address.

[0006] For example, in a string operation method provided in some embodiments of the present disclosure, the string operation includes a string transfer operation.

[0007] For example, in a string operation method provided in some embodiments of the present disclosure, the type of the string operation includes byte type, word type, double word type or quad word type.

[0008] For example, in a string operation method provided in some embodiments of the present disclosure, the processing data width is the system pipeline width.

[0009] For example, in a string operation method provided by some embodiments of the present disclosure, the mask information includes a binary mask sequence stored in a register of a processor.

[0010] For example, in a string operation method provided in some embodiments of the present disclosure, the binary masking sequence includes valid bits and invalid bits: the valid bits have a first value and the total number of the valid bits is equal to the number of repeated operations; the invalid bits have a second value and the total number of invalid bits is the remainder of the length of the binary masking sequence minus the total number of valid bits, wherein the length of the binary masking sequence is obtained according to the quotient of the processing data width and the unit operation width.

[0011] For example, in a string operation method provided by some embodiments of the present disclosure, the valid bits are consecutive low bits in the binary mask sequence, and the invalid bits are consecutive high bits in the binary mask sequence.

[0012] For example, some embodiments of the present disclosure provide a string operation method further comprising: after writing the operation portion to the target address, clearing the number of repeated operations of the string operation to zero.

[0013] For example, in a string operation method provided in some embodiments of the present disclosure, the object data is the end part of the target data to be operated. In addition to operating the object data, the string operation processing method also includes: performing one or more operations on other parts of the target data except the end part in units of the processing data width.

[0014] For example, in the string operation method described in any of the above embodiments of the present disclosure, writing the operation part to the target address includes: writing the entire operation part to the target address.

[0015] Some embodiments of the present disclosure also provide a string operation device, which includes: an acquisition module, configured to acquire a unit operation width corresponding to the type of the string operation, a processing data width of the object data to be operated, and the number of repeated operations of the string operation for the object data, wherein the unit operation width is the data width in a single operation of the string operation, and the number of repeated operations is the total number of times the single operation needs to be repeated to operate the object data; a masking information determination module, configured to determine masking information based on the unit operation width, the processing data width and the number of repeated operations, wherein the object data includes an operation part and a non-operation part, and the masking information is used to indicate the non-operation part; an operation processing module, configured to write the operation part to the target address based on the masking information.

[0016] For example, in a string operation device provided by some embodiments of the present disclosure, the operation processing module is further configured to read the object data of the processing data width from a source address.

[0017] For example, in a string operation device provided by some embodiments of the present disclosure, the operation processing module is further configured to clear the number of repeated operations to zero after writing the operation part to the target address.

[0018] For example, in a string operation device provided in some embodiments of the present disclosure, the object data is the end portion of the target data, and the operation processing module is further configured to perform one or more operations on other portions of the target data except the end portion in units of the processing data width.

[0019] For example, in a string operation device provided in some embodiments of the present disclosure, the operation processing module is further configured to write the entire operation part to the target address.

[0020] Some embodiments of the present disclosure further provide a string operation device, comprising: a memory for non-temporarily storing computer-executable instructions; and a processor for executing the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, execute the string operation method described in any of the above embodiments.

[0021] Some embodiments of the present disclosure further provide a non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein when the computer-executable instructions are executed by a computer, the string operation method according to any of the above embodiments is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0023] Figure 1 It is a schematic diagram of the execution process of a string transfer instruction;

[0024] Figure 2 It is a flow chart of the execution process of a string transfer instruction;

[0025] Figure 3 It is a flow chart of the execution process of a string storage instruction;

[0026] Figure 4 It is a schematic diagram of the data transmission process of a string transmission instruction;

[0027] Figure 5 is a flow chart of a string operation method proposed in at least one embodiment of the present disclosure;

[0028] Figure 6 is a flowchart of an exemplary string operation method proposed in at least one embodiment of the present disclosure;

[0029] Figure 7 A flowchart of an exemplary string operation method proposed in at least one embodiment of the present disclosure;

[0030] Figure 8 A schematic diagram of a data transmission process of an exemplary string operation method proposed in at least one embodiment of the present disclosure;

[0031] Figure 9 is a schematic diagram of an exemplary string operation device proposed in at least one embodiment of the present disclosure; and

[0032] Figure 10 A schematic structural diagram of a string operation processing device proposed in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0035] The present disclosure is described below using several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0036] A string of characters or data at consecutive memory locations is called a string or data stream. String manipulation instructions are instructions used to operate on each character or data in a string, with the string serving as the target data. For example, string manipulation instructions can operate on both byte and word strings, automatically modifying the pointer after each byte (or word) operation to allow the next byte (or word) operation to be performed. String manipulation instructions can include transfers between two memory locations (e.g., string transfer instructions) or comparisons (e.g., string compare instructions).

[0037] For example, the program segment structure using string instructions is as follows:

[0038] Set the source string pointer (optional);

[0039] Set the destination string pointer (optional);

[0040] Set the number of times the operation is repeated (can be omitted if only one operation is performed);

[0041] Set the operation direction (Direction Flag, DF);

[0042] The repeat prefix (REP (repeat) / REPZ (repeat on zero) / REPNZ (repeat on non-zero)) can be omitted when executing only once.

[0043] For example, string operation instructions may include the move string instruction (MOVS), compare string instruction (CMPS), scan string instruction (SCAS), load string instruction (LODS), and store string instruction (STOS). Each string operation instruction can be further divided into byte-type, word-type, double-word-type, or quartered-word-type string operation instructions based on the size of the indivisible data in each operation (the smallest data unit operated by the string operation instruction). For example, string operation instructions may include string operation instructions of different data types, such as the byte string operation instruction (MOVSB), word string operation instruction (MOVSW), double-word string operation instruction (MOVSD), and quad-word string operation instruction (MOVSQ).

[0044] For example, the MOVS instruction can transfer a word or byte from the data segment (DS) pointed to by the source index (SI) register to a word or byte in the extra segment (ES) pointed to by the destination index (DI) register, while modifying the values of the SI and DI registers based on the value of the direction flag (DF) register and the data format (word or byte). When this MOVS instruction is used with the REP prefix, multiple executions of the instruction can transfer the entire string of data from the data segment to the extra segment. For example, if the source string is in the data segment and the destination string is in the extra segment, the source string can be modified using a segment-spanning prefix. When used with the REP prefix, the length of the data string is first sent to the counter (CX) register to control the execution of the MOVS instruction. Depending on the processor bit width, the counter register can be an extended counter register. For example, if the processor bit width is 64 bits, the counter register can be an extended counter register (RCX).

[0045] Figure 1 This is a schematic diagram of the execution process of a string transfer instruction. Figure 1 As shown, the execution of the string transfer instruction can first prepare the following: put the source string head address stored in the data segment (for example, the last address when the value corresponding to DF indicates reverse transfer) into the SI register; put the destination string head address in the additional segment where the data string is to be stored (for example, the last address when the value corresponding to DF indicates reverse transfer) into the DI register; put the length of the data string into the CX register so that the length of the data string is the value of the counter register and establish a direction flag to indicate the transfer direction of the data string. After the execution preparation of the string transfer instruction is completed, the string transfer instruction will be executed. During the execution process, the string transfer instruction can calculate the address of the corresponding data in the data string in the memory based on the segment address of the data segment and the value of the source index register, as well as the reference base address. Similarly, the address of the corresponding data in the data string to be transferred in the memory can also be calculated based on the segment address of the additional segment and the value of the destination index register, as well as the reference base address. Each string move instruction transfers data of a specified width from the address pointed to by SI to the address pointed to by DI. The specified width can be the pipeline width of the system (e.g., CPU or CPU core) (or the pipeline width of the Load Store Unit (LSU)), such as 16 bytes, 32 bytes, or 64 bytes. The total number of times a string move instruction is executed is the data string length, that is, the value of the CX register.

[0046] Figure 2 It is a flow chart of the execution process of a string transfer instruction. Figure 1 The execution process of the string transfer instruction can be Figure 2 The flowchart shown is used for explanation. Figure 2 As shown, when the string transfer instruction enters the string transfer operation loop during execution, the data in the memory address pointed to by the source index register is loaded according to the value of the source index register, and the data is temporarily stored in the register; then the data temporarily stored in the register is stored in the memory address pointed to by the destination index register; the source index register and the destination index register are moved in the direction specified by the direction flag register, for example, when the value of DF indicates forward transfer, the values of the source index register and the destination index register are each increased by one unit, and when the value of DF indicates reverse transfer, the values of the source index register and the destination index register are each decreased by one unit; the value of the extension counter register is reduced until the value of the extension counter register is zero, that is, the data string transfer is completed, thereby ending the entire string transfer operation loop.

[0047] For example, the Store String (STOS) instruction stores a data string into the memory address pointed to by the DI register. The specific operation process of the Store String instruction is similar to that of the Move String instruction. Since the Store String instruction operation does not involve the source data string, the address of the source data string does not need to be stored in the SI register.

[0048] Figure 3 It is a flow chart of the execution process of a string storage instruction. Figure 3 As shown, the execution flow of the string storage instruction is the same as Figure 2 The execution flow of the string transfer instruction shown is similar, with the main difference being that the source data string does not need to be loaded from the source index register. When the string store instruction enters the string store operation loop during execution, the data is loaded and stored at the memory address pointed to by the destination index register. The destination index register is moved in the direction specified by the direction flag register. For example, if the value of DF indicates a forward transfer, the value of the destination index register is increased by one unit, while if the value of DF indicates a reverse transfer, the value of the destination index register is decreased by one unit. The value of the extension counter register is decremented until the value of the extension counter register reaches zero, indicating that the data string is stored, thus ending the entire string store operation loop.

[0049] As described above, the pipeline width of the memory access unit can be 16 bytes, 32 bytes, or 64 bytes, etc. The data width loaded or stored by each instruction can be at most the pipeline width. Therefore, to maximize pipeline utilization, for string operation instructions, when the value of a counter register (e.g., an extended counter register) is greater than or equal to a predetermined threshold, the execution of the string operation instruction can be entered into a fast loop.

[0050] Figure 4 This is a diagram of the data transfer process of a string transfer instruction, used to illustrate Figure 2 The fast loop operation of the string operation instruction is to merge several string operation instructions with shorter width into a string operation instruction with the width of the pipeline to maximize the use of the pipeline width. Figure 4 As shown, during the fast loop, four 8-byte four-word string transfer instructions can be combined into a single 32-byte pipeline width string operation instruction, allowing each string transfer operation to transfer 4*8=32 bytes of data. The fast loop reduces the total number of instructions required for the string operation, thereby speeding up execution. However, if the end of the data string in the fast loop is insufficient to be combined into a single pipeline width, the string operation enters the normal operation mode, also known as the slow loop, where each string operation instruction is executed sequentially according to the data width specified (e.g., 8 bytes for a byte string transfer instruction) until completion.

[0051] For example, in Figure 4 In the example, for a four-word string transfer instruction (MOVSQ), that is, a string transfer instruction that moves 8 bytes of data width each time, if the end data width of the data string is 24 bytes, it needs to be moved 3 times. Figure 4 The end data of the data string in the current loop is 24 bytes and needs to be moved three times. In the fast loop, however, three transfer operations can move 3*32 bytes, or 96 bytes of data. Therefore, the transfer efficiency of the end data of the current data string is only 1 / 4 of that of the fast loop; for the byte string transfer instructions of the string transfer instructions, the efficiency is only 1 / 32. In the most extreme case (for example, when the end data of the data string is 31 bytes), the byte string transfer instruction will move the end data of the data string 31 times. For some loops with shorter data lengths, this processing of the end data of the data string significantly reduces processor performance.

[0052] For example, in string operation instructions with a repeat prefix (such as REP MOVS or REP STOS), if the data width at the end of the data string cannot be combined into the pipeline width, that is, if it is misaligned, the string operation instruction will be executed several times according to the data width specified by the instruction. This increases the total number of instructions required to run during the string operation, resulting in a loss in processor performance. This performance loss is particularly significant for shorter string transfer instructions. For example, for the byte string transfer instruction (MOVSB), which moves data width by 1 byte at a time, if the data width at the end of the data string is 31 bytes, the byte string transfer instruction will be executed 31 times, which will have a very negative impact on the performance of the string operation.

[0053] At least one embodiment of the present disclosure provides a string operation method for a processor. The string operation method includes: obtaining a unit operation width corresponding to the type of the string operation, wherein the unit operation width is the data width in a single operation of the string operation; obtaining a processing data width for the object data to be operated; obtaining a number of repeated operations of the string operation for the object data, wherein the number of repeated operations is the total number of times the single operation needs to be repeated to operate the object data; determining mask information based on the unit operation width, the processing data width, and the number of repeated operations, wherein the object data includes an operation portion and a non-operation portion, and the mask information is used to indicate the non-operation portion; and writing the operation portion to a target address based on the mask information.

[0054] The string operation method of the above-mentioned embodiments of the present disclosure can effectively improve the execution speed of string operation instructions by reducing the number of cycles and micro-operations during the execution process of string operation instructions. This at least alleviates the problem of slow string data processing speed caused by the misalignment of the string operation instruction data width with the pipeline width. Moreover, in some embodiments of the present disclosure, the execution speed improvement is even more significant for string operation instructions with shorter data widths, thereby increasing hardware resource utilization.

[0055] Figure 5 This is a flow chart of a string operation method proposed in at least one embodiment of the present disclosure. Figure 5 As shown, the string operation method includes at least the following five steps S101 to S105:

[0056] Step S101, obtaining the unit operation width corresponding to the type of string operation;

[0057] Step S102, obtaining the processing data width for the object data to be operated;

[0058] Step S103, obtaining the number of repeated operations of the string operation on the object data;

[0059] Step S104, determining shielding information according to the unit operation width, the processing data width, and the number of repeated operations;

[0060] Step S105: writing the operation part to the target address according to the mask information.

[0061] In addition to the above five steps S101 to S105, in some embodiments, the following steps are also required:

[0062] Step S106: Read object data of the processing data width from the source address.

[0063] For example, the unit operation width of step S101 is the data width in a single operation of the string operation. The data width in a single operation of the string operation can be the size of indivisible data in each operation of the corresponding string operation (string operation instruction), and the indivisible data is part of the object data. For example, the string operation instruction can be a string store operation (string store instruction), a string transfer operation (string transfer instruction), or a string load operation (string load instruction). When the string transfer instruction is executed, the step of reading the object data of the processing data width from the source address in S106 needs to be performed.

[0064] For example, as described above, string store instructions, string transfer instructions, or string load instructions can also be further divided into byte type, word type, double word type, or quartered word type according to the size of the indivisible data in each operation. For example, string transfer instructions can include string operation instructions of different data types such as byte string transfer instruction (MOVSB), word string transfer instruction (MOVSW), double word string transfer instruction (MOVSD), and quad word string transfer instruction (MOVSQ). The data sizes corresponding to each operation of these four string operation instructions can be 1 byte, 2 bytes, 4 bytes, and 8 bytes, respectively. For example, based on the data size of 1 byte corresponding to each operation of the byte string transfer instruction, the unit operation width can be determined to be 1 byte.

[0065] For example, the processing data width in step S102 may be the pipeline width of the processor system where the string operation instruction resides. This processing data width is used to provide the maximum width of the operation pipeline when the string operation instruction operates on the target data. For example, it may be 16 bytes, 32 bytes, or 64 bytes, etc., which is not limited in this disclosure. The target data is the end data of the data string operated by the string operation instruction.

[0066] For example, the number of repeated operations in step S103 can be the total number of single operations that need to be performed when the string operation instruction operates the object data. The total number of operations can be based on the object data to be operated (for example, including Figure 4 The result is the size of the end data (shown as the end data) divided by the unit operation width. For example, if the end data portion is 24 bytes, the unit operation width of the string operation instruction is 8 bytes, and the processing data width of the target data is 32 bytes, the number of repetitions is 3 (24 / 8). The resulting number of repetitions can generally be stored in a counter (CX) register (e.g., the extended counter register RCX) as the counter register value, so that the execution of the string operation instruction can be controlled by the counter register value.

[0067] For example, in step S104, the object data includes an operation part and a non-operation part. For example, the operation part corresponds to Figure 4The end data shown is the actual end data to be operated on; the mask information is used to indicate the non-operational portion, such as the remaining placeholder portion of the object data other than the actual end data to be operated on, that is, the portion that does not actually need to be operated on or the empty position with no data. The mask information can be a binary sequence used for masking, namely a binary mask sequence.

[0068] For example, the mask register corresponding to the Advanced Vector Extensions (AVX) instruction set of the x86 architecture microprocessor, the Advanced Vector Extensions instruction set can correspond to different bit widths, such as the 128-bit Advanced Vector Extensions instruction set (AVX-128), the 256-bit Advanced Vector Extensions instruction set (AVX-256), the 512-bit Advanced Vector Extensions instruction set (AVX-512), etc., and the present disclosure does not limit this. Among them, the instructions in the Advanced Vector Extensions instruction set can use a mask register (also known as a K register) to perform a mask operation (OPMask), such as a mask store / load operation (MaskStore / Load). The binary mask sequence can be stored in a register, which can be a mask information register, and the mask information register can be implemented by the above-mentioned mask register (such as the K register). For example, the length, valid bits and invalid bits of the binary mask sequence can be determined to determine the entire binary mask sequence. For example, the length of the binary mask sequence can be determined based on the unit operation width and the processing data width group; the valid bits and invalid bits of the binary mask sequence can be determined based on the number of repeated operations and the length of the binary mask sequence. For example, the valid value of the valid bit can be represented by 1, and the valid value of the valid bit is equivalent to the first value of the valid bit disclosed herein; the invalid value of the invalid bit can be represented by 0, and the invalid value of the invalid bit is equivalent to the second value of the invalid bit disclosed herein. For example, the total number of valid bits is equal to the number of repeated operations in step S103, so as to correspond to the operation portion of the data string (e.g., the end data of the data string); the total number of invalid bits is obtained by subtracting the total number of valid bits from the length of the binary mask sequence, so as to correspond to the portion exceeding the operation portion. For example, the length of the binary mask sequence can be obtained based on the quotient of the processing data width and the unit operation width. The valid bits can be the consecutive low bits in the binary mask sequence, and the invalid bits can be the consecutive high bits in the binary mask sequence. For example, when the number of repeated operations is 3, the processing data width is 32, and the unit operation width is 4, the length of the binary mask sequence is 8 (32 / 4), the total number of valid bits is 3, and the total number of invalid bits is 5 (8-3), so that the binary mask sequence can be determined to be 00000111 (0x07).

[0069] For example, in step S105, the operation portion is written to the target address in its entirety, using mask information. The valid data corresponding to the valid bits of the mask information is then selected and written to the target address based on the mask information. For example, when the binary mask sequence is 00000111, the object data corresponding to the lower three bits 111, i.e., data for the three-bit operation width, is retained, while the data corresponding to the upper five bits 00000 is discarded. The target address may be a memory address pointed to by a value determined jointly by the additional segment and the value of the destination index register.

[0070] For example, the object data may be the end portion of the target data to be operated on by the string operation instruction. In addition to operating the object data, the string operation processing method may also use the processing data width as an operation unit to perform one or more operations on the remaining portion of the target data excluding the end portion (e.g., the "fast loop" described above). For example, for the remaining portion of the target data excluding the end portion, multiple string operation instructions executed according to the unit operation width may be combined to form an operation of the processing data width, and a smaller number of string operations may be performed according to the combined data width, thereby reducing the total number of operations during the execution of the string operation instruction and improving the operation efficiency of the string operation instruction.

[0071] For example, a string operation method proposed in at least one embodiment of the present disclosure may further include:

[0072] Step S107: clear the number of repeated operations of the string operation to zero.

[0073] For example, after all operations on the target data are completed (e.g., all the target data are stored at the target address), since the operation is completed in one go, the value of the counter register is not changed during the operation, e.g., it retains the value at the start of the operation. Therefore, after all operations on the target data are completed, the number of repetitions of the string operation needs to be reset to zero, for example, by resetting the value of the counter register to zero.

[0074] A string operation method and a string operation device for executing the string operation method proposed in at least one embodiment of the present disclosure will be described below with reference to a specific but non-limiting example.

[0075] For example, at least one embodiment of the present disclosure proposes a string operation method that optimizes data operations at the end of a data string. Instead of sequentially moving data according to the inherent data width of the string operation, the method loads the pipeline-width data at once. A mask information register is then used to generate mask information based on the value of a counter register. This allows only unmasked data to be stored in the LSU. The mask information register can be a K register, which is not a limitation of the present disclosure. The mask information can be a binary sequence, where each bit value in the binary sequence can have two states: valid and invalid. A valid value indicates that the corresponding data is not masked, while an invalid value indicates that the corresponding data is masked, and vice versa. This is not a limitation of the present disclosure.

[0076] For example, the generation of mask information is determined by two variables: the item size, which indicates how many bytes of data each bit in the mask information can mask. The item size can be equal to the data size of each operation performed by the string operation instruction (for example, for the MOVSB instruction, the item size is 1 byte); and the data size, which indicates the width of the system pipeline. For example, when the item size is 8 bytes and the data size is 32 bytes, the mask information can be a 4-bit binary sequence, so the lower 4 bits of the mask information register are valid to generate this 4-bit binary sequence. Each of the lower 4 bits in the mask information register can mask 8 bytes of data.

[0077] Figure 6 This is a flowchart of an exemplary string operation method proposed in at least one embodiment of the present disclosure.

[0078] like Figure 6 As shown, taking the string transfer instruction as an example, when the string transfer instruction enters the end data processing during the operation, the source data string pointed to by the source index register is loaded and temporarily stored in the register; the mask information (such as the binary sequence used for masking) is calculated according to the value of the counter register (such as the extended counter register), and is stored in the mask information register (such as the K register, that is, the K register corresponding to the AVX512 instruction set); the data is selectively stored in the address pointed to by the destination index register according to the value of the mask information; after the end data processing of the string transfer instruction is completed, the value of the counter register is cleared.

[0079] Figure 8 The present invention is a schematic diagram of a data transmission process of an exemplary string operation method proposed in at least one embodiment of the present disclosure.

[0080] Figure 8 The fast cycle process of the string operation instruction shown is the same as Figure 4 The fast loop process of the string operation instructions shown is the same and will not be repeated here. Figure 8The end data processing process in the data transmission process shown is equivalent to Figure 6 The end data processing process flow is shown. When the string operation instruction is a four-word string transfer instruction (MOVSQ) and the end data width of the data string is 24 bytes, the value of the counter register is 3 when the end data of the data string is processed (the end data width of the data string / the data size of each operation of the four-word string transfer instruction, that is, 24 / 8). The data size of each operation of the four-word string transfer instruction is 8 bytes, that is, the item size is 8 bytes, and the pipeline width is 32 bytes, that is, the data size is 32 bytes. From this, the mask information can be calculated to be 0111, so the value of the mask information register is 0x7 (0111). Therefore, during the operation, the four-word string transfer instruction will load 32 bytes of data containing the end 24 bytes of data of the source data string from the memory address pointed to by the SI register, but according to the value of the mask information in the mask register, only the lower 24 bytes (that is, the end 24 bytes of the source data string) will be stored in the memory address pointed to by the DI register. Compared to Figure 4 The end data processing of the data string shown needs to transmit data three times. Figure 8 The end data processing of the data string shown controls the number of data transfers to 1, thereby reducing the number of load data or store data that the memory access unit needs to process, and simplifying the data processing flow when the processor executes the string operation instruction.

[0081] Figure 7 A flowchart of an exemplary string operation method proposed in at least one embodiment of the present disclosure is provided. Figure 7 The string operation method shown is the same as Figure 6 Compared with the string operation method shown, the step of reading data from the memory address pointed to by the source index register can be omitted.

[0082] like Figure 7As shown, taking the string store instruction as an example, when the string store instruction enters the end data processing during operation, its process is similar to that of the string transfer instruction. During the end data processing, the string store instruction calculates the mask information (e.g., the binary sequence used for masking) based on the value of the counter register (e.g., the extended counter register) and stores the mask information in the mask information register (e.g., the K register, i.e., the K register in AVX512); based on the value of the mask information, the data is selectively loaded and stored at the address pointed to by the destination index register; after the end data processing of the string store instruction is completed, the value of the counter register is cleared. Compared with the end data processing of the string transfer instruction, the end data processing of the string store instruction does not require the process of loading the source data string pointed to by the SI register, and can directly store the data at the address pointed to by the DI register. The optimization of the end data processing of the string store instruction is similar to that of the end data processing of the string transfer instruction. It also uses the value of the counter register (e.g., the extended counter register) to generate a mask information, and then performs a single data storage operation to complete the process.

[0083] For example, to evaluate the theoretical upper limit of the performance improvement of string operation instructions disclosed herein, a worst-case scenario can be assumed, namely, the maximum number of iterations required for each string operation instruction to process the end data of the data string (e.g., the theoretical worst-case scenario). For example, for the four string transfer instructions of byte string transfer instruction (MOVSB), word string transfer instruction (MOVSW), double word string transfer instruction (MOVSD), and quad word string transfer instruction (MOVSQ), the data width of each move is 1 byte, 2 bytes, 4 bytes, and 8 bytes, respectively. When the pipeline width is 32 bytes, the maximum number of iterations of each of the above string transfer instructions before the improvement corresponds to 31, 15, 7, and 3, respectively. The performance improvement is shown in Table 1:

[0084] Number of times before improvement Number of times after improvement Theoretical performance improvement MOVSB 31 1 3000％ MOVSW 15 1 1400％ MOVSD 7 1 600％ MOVSQ 3 1 200％

[0085] Table 1

[0086] As can be seen from Table 1, the improved maximum number of iterations for each of the above string transfer instructions is 1. Considering only the microinstructions (UOPs) executed during the end data processing period of the string operation instruction, the embodiments of the present disclosure can improve theoretical performance by 3000%. Considering that string transfer instructions are not limited to microinstructions executed during the end data processing period, the overall performance improvement of the entire string transfer instruction execution process will be lower than the theoretical performance improvement value in Table 1.

[0087] The present disclosure takes the string transfer instruction as an example above. The method and process of the string storage instruction are similar to those of the string transfer instruction, and the theoretical performance improvement is also similar, so it will not be repeated here.

[0088] At least one embodiment of the present disclosure provides a string operation device, including: an acquisition module, a shielding information determination module, and an operation processing module.

[0089] The acquisition module is used to obtain the unit operation width corresponding to the type of string operation, the processed data width of the object data to be operated on, and the number of repeated operations of the string operation on the object data. The unit operation width is the data width of a single string operation, and the number of repeated operations is the total number of times the single operation needs to be repeated to operate on the object data. The mask information determination module is used to determine mask information based on the unit operation width, the processed data width, and the number of repeated operations. The object data includes an operation portion and a non-operation portion, and the mask information is used to indicate the non-operation portion. The operation processing module is used to write the operation portion to the target address based on the mask information.

[0090] Figure 9 is a schematic diagram of an exemplary string operation device proposed in at least one embodiment of the present disclosure, which can be used to perform Figure 5 The string operation method shown.

[0091] like Figure 9 As shown, the string operation device 10 includes an acquisition module 110 , a mask information determination module 120 and an operation processing module 130 .

[0092] For example, the unit operation width obtained by the acquisition module 110 can correspond to a byte type, a word type, a double word type, a quad word type, etc.; the obtained processing data width can be the width of the system pipeline; the total number of times a single operation is repeated can be obtained by dividing the size of the end data by the unit operation width.

[0093] For example, the masking information obtained by the masking information determination module 120 may be a binary masking sequence, wherein the total number of valid bits in the binary masking sequence is equal to the number of repeated operations, and the total number of invalid bits is obtained by subtracting the total number of valid bits from the length of the binary masking sequence. For example, the length of the binary masking sequence may be obtained by dividing the processing data width by the unit operation width, the valid bits may be consecutive low bits in the binary masking sequence, and the invalid bits may be consecutive high bits in the binary masking sequence.

[0094] For example, in some examples, the operation processing module 130 may select valid data corresponding to valid bits of the mask information according to the mask information and write the data into the target address.

[0095] For example, in some examples, the operation processing module 130 may be configured to read object data of a processing data width from a source address to be compatible with a string operation instruction that requires reading data from a source address.

[0096] For example, in some examples, the operation processing module 130 may be configured to clear the number of repeated operations after writing the operation portion to the target address, for example, clearing the value of the counter register after all operations on the object data are completed.

[0097] For example, in some examples, the operation processing module 130 can perform one or more operations on the other parts of the target data except the end part in units of processing data width. For example, for the remaining part of the target data except the end part, multiple string operation instructions executed according to the unit operation width can be merged into operations of the processing data width, and a smaller number of multiple string operations or one operation can be performed according to the merged data width.

[0098] For example, in some examples, the operation processing module 130 may write the operation part as a whole to the target address. For example, due to the use of mask information, the operation part may be written to the target address as a whole at one time.

[0099] The technical effect of the string operation device is Figure 5 The technical effects of the string operation method shown are the same and will not be repeated here.

[0100] At least one embodiment of the present disclosure further proposes a string operation processing device, comprising: a memory for non-temporarily storing computer-executable instructions; and a processor for executing the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, execute the string operation method proposed in at least one embodiment of the present disclosure.

[0101] Figure 10 This is a structural diagram of a string operation processing device proposed in at least one embodiment of the present disclosure. The string operation processing device can be used to perform Figure 5 The string operation method shown.

[0102] like Figure 10As shown, the string operation processing device 20 includes a memory 210 for non-temporarily storing computer executable instructions and a processor 220 for running computer executable instructions. For example, the processor 220 can be implemented as hardware or firmware such as a CPU, SoC, FPGA, ASIC, or any combination of hardware or firmware and software, and the embodiments of the present disclosure are not limited to this. When the processor 220 runs the above-mentioned computer executable instructions, it executes the following string operation method: obtaining the unit operation width corresponding to the type of string operation, wherein the unit operation width is the data width in a single operation of the string operation; obtaining the processing data width for the object data to be operated; obtaining the number of repeated operations of the string operation for the object data, wherein the number of repeated operations is the total number of times a single operation needs to be repeated to operate the object data; determining the mask information based on the unit operation width, the processing data width and the number of repeated operations, wherein the object data includes an operation part and a non-operation part, and the mask information is used to indicate the non-operation part; writing the operation part to the target address based on the mask information.

[0103] Figure 10 The technical effect of the string operation processing device shown is the same as the technical effect of the above-mentioned string operation method, which will not be repeated here.

[0104] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitory stores computer-executable instructions. For example, the non-transitory storage medium may be, but is not limited to, a magnetic tape, an optical disk, a magnetic disk, a flash memory, or other non-transitory storage medium. When the computer-executable instructions are executed by a computer, the string operation method provided in at least one embodiment of the present disclosure is executed. The technical effects of the non-transitory storage medium are the same as those of the aforementioned string operation method.

[0105] The string operation method, string operation device, and storage medium of the above-mentioned embodiments of the present disclosure are not only used for end data operations of a data string of a string operation instruction, but can also be used in general string operations, such as operations of a string transfer instruction.

[0106] At the same time, the string operation method, string operation device and storage medium of the above-mentioned embodiments of the present disclosure are not limited to string transfer instructions (MOVS), but can also be used for string operation instructions such as string load instructions (LODS) and string store instructions (STOS). The present disclosure does not limit this and will not repeat it.

[0107] Regarding this disclosure, the following points need to be explained:

[0108] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0109] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0110] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A string operation method, comprising: Obtaining a unit operation width corresponding to the type of the string operation, wherein the unit operation width is a data width in a single operation of the string operation; Get the processing data width for the object data to be operated; Obtaining a number of repeated operations of the string operation for the object data, wherein the number of repeated operations is a total number of times the single operation needs to be repeated to operate the object data; determining shielding information according to the unit operation width, the processing data width, and the number of repeated operations, wherein the object data includes an operation portion and a non-operation portion, and the shielding information is used to indicate the non-operation portion; The operation part is written as a whole to the target address according to the mask information.

2. The method according to claim 1, wherein The string operation includes a string store operation or a string load operation.

3. The method of claim 1 , further comprising: The object data of the processing data width is read from a source address.

4. The method according to claim 3, wherein: The string operation includes a string transfer operation.

5. The method according to claim 1, wherein The types of the string operation include byte type, word type, double word type or quad word type.

6. The method of claim 1, wherein: The processing data width is the system pipeline width.

7. The method of claim 1, wherein: The mask information comprises a binary mask sequence stored in a register of the processor.

8. The method of claim 7, wherein: The binary mask sequence includes valid bits and invalid bits: The valid bits have a first value and the total number of the valid bits is equal to the number of repeated operations; The invalid bits have a second value and the total number of the invalid bits is a remainder obtained by subtracting the total number of valid bits from the length of the binary mask sequence, wherein the length of the binary mask sequence is obtained according to a quotient of the processing data width and the unit operation width.

9. The method of claim 8, wherein: The valid bits are consecutive low bits in the binary mask sequence, and the invalid bits are consecutive high bits in the binary mask sequence.

10. The method of claim 1, further comprising: After writing the operation portion to the target address, the number of repeated operations of the string operation is cleared to zero.

11. The method of claim 1, wherein: The object data is an end portion of target data to be operated. In addition to operating the object data, the string operation processing method further includes: One or more operations are performed on the portion of the target data other than the end portion using the processing data width as a unit.

12. A string operation device comprising: an acquisition module configured to acquire a unit operation width corresponding to the type of the string operation, a processed data width of the object data to be operated, and a number of repeated operations of the string operation for the object data, wherein the unit operation width is the data width in a single operation of the string operation, and the number of repeated operations is the total number of times the single operation needs to be repeated to operate the object data; a shielding information determining module configured to determine shielding information according to the unit operation width, the processed data width, and the number of repeated operations, wherein the object data includes an operation portion and a non-operation portion, and the shielding information is used to indicate the non-operation portion; The operation processing module is configured to write the entire operation part to the target address according to the masking information.

13. The string operation device according to claim 12, wherein: The operation processing module is further configured to read the object data of the processing data width from a source address.

14. The string operation device according to claim 12, wherein: The operation processing module is further configured to clear the number of repeated operations to zero after writing the operation portion to the target address.

15. The string operation device according to any one of claims 12 to 14, wherein: The object data is the end portion of the target data, The operation processing module is further configured to perform one or more operations on the other parts of the target data except the end part in units of the processing data width.

16. A string operation processing device, comprising: a memory for non-transitory storage of computer-executable instructions; as well as a processor for executing the computer-executable instructions, Wherein, when the computer executable instructions are executed by the processor, the method for string operation according to any one of claims 1 to 11 is executed.

17. A non-transitory storage medium that non-transitory stores computer-executable instructions, wherein: When the computer-executable instructions are executed by a computer, the string operation method according to any one of claims 1 to 11 is performed.

Images