A disassembled micro-operating module, processor, and electronic device

Abstract

This invention proposes a micro-operation decomposition module, processor, and electronic device. A numbering update unit provides the current micro-operation number to an element quantity counting unit and an execution module. The element quantity counting unit determines the current micro-operation element quantity based on the current micro-operation number and the reference information corresponding to the target vector instruction. The execution module executes the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and decoding information. Performing micro-operations before instruction execution avoids excessive pipeline delays caused by micro-operations, enabling rapid response to instruction changes, accurate completion of micro-operations, and improved instruction processing efficiency, thus meeting the demands of high-performance computing.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a microcontroller module, processor, and electronic device. Background Technology

[0002] The RISC-V instruction set architecture is an open and free instruction set architecture (ISA) developed by the University of California, Berkeley starting in 2010. It boasts advantages such as high scalability and flexibility, attracting attention and participation from numerous companies and academic institutions.

[0003] The RISC-V instruction set architecture is simple and clear, including a basic integer instruction set (RV32I, RV64I) and various optional standard extensions, such as floating-point instruction sets (RV32F, RV64F) and vector instruction sets (RV32V, RV64V), to meet the needs of different fields and applications.

[0004] In the RISC-V instruction set architecture, Vector Extension introduces vector processing capabilities, aiming to efficiently support data-parallel tasks such as high-performance computing and machine learning. Split Macro-Operations (MOPs) is a key optimization strategy in Vector Extension design, with the core objective of improving the execution efficiency of vector instructions and the utilization of hardware resources. In the RISC-V instruction set architecture, the vector registers (e.g., v0~v31) of Vector Extension can be configured according to the vector control registers, allowing the amount of data that a single instruction can process to be unlimited by the register bit width, effectively treating multiple registers as a single register. For example, when the register set is configured to 4, a vector instruction might require 4 vector registers, but due to read and write port limitations, block operations are necessary.

[0005] How to efficiently and accurately perform the decomposition of vector instructions has become one of the challenges that continues to concern those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a solution that separates the micro-operation module from the processor and the electronic device, thereby improving the aforementioned problems.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0008] In a first aspect, embodiments of the present invention provide a micro-operation module, the micro-operation module comprising: a numbering update unit and an element quantity counting unit;

[0009] The output terminal of the numbering update unit is connected to the first input terminal of the element quantity counting unit. The second input terminal of the element quantity counting unit is used to connect to the decoding module. The first output terminal of the element quantity counting unit is used to connect to the execution module. The second output terminal of the element quantity counting unit is connected to the control terminal of the numbering update unit. The output terminal of the numbering update unit is also used to connect to the execution module.

[0010] The number update unit is used to provide the current micro-operation number to the element quantity counting unit and the execution module, wherein the current micro-operation number is the micro-operation number corresponding to the current clock cycle;

[0011] The element quantity counting unit is used to determine the current micro-operation element quantity based on the current micro-operation number and the reference information corresponding to the target vector instruction;

[0012] Wherein, the target vector instruction is the vector instruction currently being executed, the reference information includes the decoding information and configuration information corresponding to the target vector instruction, and the current number of micro-operation elements is the number of micro-operation elements corresponding to the current clock cycle;

[0013] The execution module is used to execute the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and the decoding information.

[0014] Secondly, embodiments of the present invention provide a processor including the aforementioned micro-operation module.

[0015] Thirdly, embodiments of the present invention provide an electronic device including the processor described above.

[0016] Compared to existing technologies, the micro-operation module, processor, and electronic device provided in this embodiment of the invention include a numbering update unit that provides the current micro-operation number to an element quantity counting unit and an execution module. The current micro-operation number corresponds to the current clock cycle. The element quantity counting unit determines the current micro-operation element quantity based on the current micro-operation number and reference information corresponding to the target vector instruction. The target vector instruction is the currently executing vector instruction, and the reference information includes the decoding information and configuration information corresponding to the target vector instruction. The current micro-operation element quantity is the number of micro-operation elements corresponding to the current clock cycle. The execution module executes the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and the decoding information. Performing micro-operations before instruction execution avoids excessive pipeline delays caused by micro-operations, enabling rapid response to instruction changes, accurate completion of micro-operations, and improved instruction processing efficiency, thus meeting the demands of high-performance computing.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the micro-operation module provided in an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the numbering update unit provided in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram illustrating the relationship between the total number of vector operation elements and the vector register, provided for an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0027] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0029] This invention provides a microdisassembly module deployed on a processor. Please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of the micro-operation module provided in an embodiment of the present invention.

[0030] The micro-operation module includes a numbering update unit and an element quantity counting unit.

[0031] The output of the numbering update unit is connected to the first input of the element quantity counting unit. The second input of the element quantity counting unit is used to connect to the decoding module. The first output of the element quantity counting unit is used to connect to the execution module. The decoding module is also connected to the execution module. The second output of the element quantity counting unit is connected to the control terminal of the numbering update unit. The output of the numbering update unit is also used to connect to the execution module.

[0032] Optionally, the first output of the element quantity counting unit includes two sub-ports, one of which is used to output the current micro-operation element quantity, and the other is used to output the valid mask signal. The second input of the element quantity counting unit includes two sub-ports, one of which is used to receive the decoding information corresponding to the target vector instruction transmitted by the decoding module, and the other is used to receive the configuration information corresponding to the target vector instruction transmitted by the decoding module.

[0033] The second output of the element quantity counting unit, along with the output of the maximum micro-disassembly operation counting unit and the instruction processing unit (described below), can be directly connected to the control terminal of the number update unit. Alternatively, as... Figure 1 As shown, the second output terminal of the element quantity counting unit, the output terminal of the maximum micro-operation counting unit, and the output terminal of the instruction processing unit are respectively connected to different input terminals of the changeover switch. The output terminal of the changeover switch is connected to the control terminal of the number update unit. The output terminal of the changeover switch and each input terminal of the changeover switch are kept in a conducting state.

[0034] The numbering update unit is used to provide the current micro-operation number to the element quantity counting unit and the execution module, wherein the current micro-operation number is the micro-operation number corresponding to the current clock cycle.

[0035] The element quantity counting unit is used to determine the current micro-operation element quantity based on the current micro-operation number and the reference information corresponding to the target vector instruction.

[0036] The target vector instruction is the vector instruction currently being executed. The reference information includes the decoding information and configuration information corresponding to the target vector instruction. The current number of micro-operation elements is the number of micro-operation elements corresponding to the current clock cycle.

[0037] The execution module is used to execute the corresponding micro-operation based on the current micro-operation number, the current number of micro-operation elements, and the decoding information.

[0038] This invention provides a micro-disassemble module deployed on a processor, which performs micro-disassemble operations before instruction execution. This avoids excessive pipeline delay caused by micro-disassemble operations, enables rapid response to instruction changes, accurately completes micro-disassemble operations, improves instruction processing efficiency, and meets the needs of high-performance computing.

[0039] exist Figure 1Based on this, regarding the specific structure of the numbering update unit, this embodiment of the invention also provides an optional implementation method, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the numbering update unit provided in an embodiment of the present invention.

[0040] The number update unit includes an adder, a selector, and a register.

[0041] The output of the register is connected to the input of the adder, the output of the adder is connected to the first input of the selector, the second input of the selector is used to input the initial micro-operation number (e.g., 0 or 1), the control terminal of the selector serves as the control terminal of the number update unit and can be connected to the second output of the element quantity counting unit, and the output of the selector is connected to the input of the register.

[0042] The output of the register serves as the output of the number update unit.

[0043] The register is used to provide the current micro-operation number to the element quantity counting unit and the execution module. The current micro-operation number is the micro-operation number written to the register in the previous clock cycle.

[0044] The adder is used to perform an addition operation on the current micro-operation number to generate a new micro-operation number.

[0045] The selector is used to write the newly generated micro-operation number of the adder into the register when no trigger control signal (end signal) is received in the current clock cycle, so that it can be used as the current micro-operation number for the next clock cycle.

[0046] The selector is used to write the initial micro-operation number into the register when a trigger control signal (end signal) is received in the current clock cycle, so that it can be used as the current micro-operation number for the next clock cycle.

[0047] Based on the preceding text, regarding the specific process by which the element quantity counting unit determines the current micro-operation element quantity according to the current micro-operation number and the reference information corresponding to the target vector instruction, this embodiment of the invention also provides an optional implementation method, please refer to the following text.

[0048] The element count unit is used to obtain the actual element width of the target vector instruction.

[0049] The element count unit is used to determine the maximum number of elements that can be processed in a single run based on the vector register width (in the processor in which it is deployed) and the actual element width.

[0050] The maximum number of elements that can be processed is the quotient of the vector register width and the actual element width.

[0051] If the processor vector register width is 256 bits (vlen=256) and the actual element width is 8, then the maximum number of elements that can be processed in a single run is 256 / 8=32. If the actual element width is 16, then the maximum number of elements that can be processed in a single run is 256 / 16=16.

[0052] The element quantity counting unit is used to determine the number of elements that have been completed based on the maximum processable element quantity and the current micro-operation number.

[0053] Optionally, the number of times the micro-operation has been completed is determined based on the current micro-operation number, and the product of the maximum number of elements that can be processed and the number of times it has been completed is taken as the number of elements completed.

[0054] When the initial micro-operation number is 0, the number of completed operations = the current micro-operation number + 1, and the number of completed elements is the product of the maximum number of elements that can be processed and (the current micro-operation number + 1); when the initial micro-operation number is 1, the number of completed operations = the current micro-operation number, and the number of completed elements is the product of the maximum number of elements that can be processed and the current micro-operation number.

[0055] The element count unit is used to determine the remaining element quantity based on the total number of vector operation elements (vl) and the number of elements completed in the configuration information of the target vector instruction.

[0056] The element quantity counting unit is used to take the maximum processable element quantity as the current micro-operation element quantity when the remaining element quantity is greater than the maximum processable element quantity.

[0057] The element quantity counting unit is used to take the remaining element quantity as the current micro-operation element quantity when the remaining element quantity is less than the maximum processable element quantity, output a valid mask signal (i.e., the mask signal is pulled high) to the execution module, and output a trigger control signal (end signal) to the number update unit.

[0058] Please refer to Figure 3 , Figure 3 This diagram illustrates the relationship between the total number of vector operation elements and the vector registers provided in this embodiment of the invention. Taking an example where the total number of vector operation elements is 18 and the maximum number of processable elements is 8, the vector register corresponding to the first micro-operation number is allocated 8 micro-operation elements, the vector register corresponding to the second micro-operation number is allocated 8 micro-operation elements, leaving only 2 micro-operation elements. Since the remaining number of elements is less than the maximum number of processable elements, the vector register corresponding to the third micro-operation number is allocated 2 micro-operation elements. At this point, a valid mask signal is output to the execution module.

[0059] The element quantity counting unit is used to take the maximum processable element quantity as the current micro-operation element quantity when the remaining element quantity is equal to the maximum processable element quantity, and output a trigger control signal (end signal) to the number update unit.

[0060] Optionally, the specific process by which the element count unit obtains the actual element width of the target vector instruction is as follows.

[0061] When the decoding information of the target vector instruction includes the instruction element width (also known as the eew field), the instruction element width is used as the actual element width.

[0062] For example, when the target vector instruction is a vector load / store instruction (vle / vse instruction), the decoding information includes the instruction element width, which can be directly used as the actual element width.

[0063] When the decoding information of the target vector instruction does not include the instruction element width, but the decoding information of the target vector instruction includes a valid widening instruction signal, the configuration element width (also known as the sew field) in the configuration information of the target vector instruction is widened (e.g., multiplied by 2) according to a preset rule to obtain the actual element width.

[0064] Optionally, the specific method for widening the width of the configuration element in the configuration information of the target vector instruction according to the preset rules may, but is not limited to, multiplying the width of the configuration element by 2 and using the product as the actual element width.

[0065] When the decoding information of the target vector instruction does not include the instruction element width, and there is no valid widening instruction signal in the decoding information of the target vector instruction, the configuration element width is used as the actual element width.

[0066] Please continue to refer to this. Figure 1 In one optional embodiment, the micro-operation module further includes a maximum micro-operation counting unit. The output of the maximum micro-operation counting unit is connected to the control terminal of the number update unit. The first input of the maximum micro-operation counting unit is connected to the output of the number update unit. The second input of the maximum micro-operation counting unit is used to connect to the decoding module to obtain the decoding information and configuration information of the target vector instruction transmitted by the decoding module.

[0067] The maximum micro-operation counting unit is used to obtain the target number of micro-operations (maximum number of micro-operations).

[0068] The maximum micro-operation counting unit is used to determine whether the micro-operation of the target vector instruction has ended based on the current micro-operation number and the number of micro-operation targets. If so, it outputs a trigger control signal (end signal) to the number update unit.

[0069] Optionally, the specific implementation process for the maximum micro-operation counting unit to obtain the target number of micro-operations is as follows.

[0070] When the decoding information of the target vector instruction includes segment operation information (nf), the number of registers in the target register set (vlmul) and the segment operation information determine the target number of micro-operations (nf × vlmul). The target register set is the register set in the configuration information of the target vector instruction.

[0071] For example, when the target vector instruction is a load store instruction, the decoded information includes segment operation information.

[0072] When the decoding information of the target vector instruction does not include segment operation information, and the decoding information of the target vector instruction includes a valid widening instruction signal, the number of registers in the target register group is widened according to a preset rule (e.g., multiplied by 2) to obtain the target number of micro-operations (2×vlmul).

[0073] When the decoding information of the target vector instruction does not include segment operation information, and there is no valid widening instruction signal in the decoding information of the target vector instruction, the number of registers in the target register set is used as the target number of micro-operations.

[0074] Because widened instructions occupy more register space, the number of micro-operations required for them must be doubled. For example, if the register count `vlmul` supports 1, 2, and 4, a regular instruction requires 1, 2, and 4 micro-operations, while a widened instruction requires 2, 4, and 8 micro-operations. It should be noted that when the register count `vlmul` is 8, widened instructions are invalid; the RISC-V architecture still stipulates that the maximum result of `nf × vlmul` cannot exceed 8.

[0075] When the initial micro-operation number is 0, determine whether the current micro-operation number is less than the target number of micro-operations minus 1. If yes, it is determined that the micro-operation of the target vector instruction has not yet ended; otherwise, it is determined that the micro-operation of the target vector instruction has ended.

[0076] When the initial micro-operation number is 1, determine whether the current micro-operation number is less than the target number of micro-operations. If yes, determine that the micro-operation of the target vector instruction has not yet ended. If no, determine that the micro-operation of the target vector instruction has ended.

[0077] Please continue referring to the figure. In one optional embodiment, the micro-operation module further includes an instruction processing unit. The output of the instruction processing unit is connected to the control terminal of the number update unit, and the input of the instruction processing unit is connected to the decoding module for transmitting the acquisition decoding information and configuration information.

[0078] The instruction processing unit outputs a trigger control signal (end signal) to the number update unit when it recognizes that the instruction type in the decoding information of the target vector instruction is the target type.

[0079] Some special instructions do not require micro-operations. For example, the vector register move instruction (vmv instruction) does not care about vlmul, only operates on a single register, does not require micro-operations, and directly outputs the trigger control signal (end signal) to the number update unit.

[0080] The following examples illustrate the instructions for target types. The vmv series of instructions are used to move data between vector registers and scalar registers. They do not depend on VL and vlmul because they only involve one register and operate on only one register. Some instructions interact with vector registers through scalars, but usually do not depend on VL or vlmul settings, such as vadd.vx, vsub.vx, etc. There are also a few special instructions, such as: vfmv.fs fa0,v1, which moves v1[0] to the floating-point scalar register (operating only the first element).

[0081] In the micro-operation module provided in this embodiment of the invention, the actual number of elements in each micro-operation is dynamically calculated based on the vector register capacity and element width. A masking mechanism is introduced to handle non-integer register data, maximizing the utilization of the vector register and reducing the number of data transfers. The masking is only enabled in the last MOP or when data is insufficient to avoid invalid filling of the entire register. This reduces storage and computational redundancy, improves energy efficiency, and ensures data alignment and operational integrity.

[0082] By performing MOP splitting logic during the decoding stage, both hardware resource utilization and instruction-level parallelism are optimized. This allows the operation result of each MOP to be adapted to the single-write port limit of the vector register file. This method requires no modification to the original register file and execution unit interface of the architecture, is fully compatible with the RISC-V vector extension specification, and significantly reduces the complexity of the execution unit—the splitting logic is entirely carried out by the decoder hardware, and the execution unit only needs to process the stateless MOP operation flow sequentially.

[0083] The instruction decoding module directly parses the fields (such as vm, vtype, vl) of RISC-V vector instructions, calculates the MOP (Multiple-Operation Pattern) splitting strategy in real time, and dynamically generates multiple basic operation instructions (such as addition / multiplication combinations). This pre-processing in the decoding stage eliminates pipeline bubbles caused by MOP splitting in traditional solutions, significantly improving processor IPC (instructions per cycle). Deep integration with RISC-V vector instruction encoding rules is required to design hardware-friendly dynamic splitting logic (such as an element-level splitting algorithm based on vl).

[0084] This invention also provides a processor including the aforementioned micro-operation module.

[0085] This invention also provides an electronic device including the processor described above.

[0086] In summary, the micro-operation module, processor, and electronic device provided by this embodiment of the invention include a numbering update unit that provides the current micro-operation number to the element quantity counting unit and the execution module. The current micro-operation number is the micro-operation number corresponding to the current clock cycle. The element quantity counting unit determines the current micro-operation element quantity based on the current micro-operation number and reference information corresponding to the target vector instruction. The target vector instruction is the currently executing vector instruction, and the reference information includes the decoding information and configuration information corresponding to the target vector instruction. The current micro-operation element quantity is the number of micro-operation elements corresponding to the current clock cycle. The execution module executes the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and the decoding information. Performing micro-operation before instruction execution avoids excessive pipeline delays caused by micro-operation, enabling rapid response to instruction changes, accurate completion of micro-operation, and improved instruction processing efficiency, thus meeting the demands of high-performance computing.

[0087] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0088] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A tear micro-operation module characterized by, The micro-operation disassembling module comprises a number updating unit and an element quantity counting unit; an output end of the number updating unit is connected with a first input end of the element quantity counting unit, a second input end of the element quantity counting unit is used for connecting a decoding module, a first output end of the element quantity counting unit is used for connecting an execution module, a second output end of the element quantity counting unit is connected with a control end of the number updating unit, and an output end of the number updating unit is also used for connecting the execution module; the number updating unit is used for providing a current micro-operation number to the element quantity counting unit and the execution module, wherein the current micro-operation number is a micro-operation number corresponding to a current clock cycle; the element quantity counting unit is used for determining a current micro-operation element quantity according to the current micro-operation number and reference information corresponding to a target vector instruction; the target vector instruction is a vector instruction currently being executed, the reference information comprises decoding information and configuration information corresponding to the target vector instruction, and the current micro-operation element quantity is a number of micro-operation elements corresponding to a current clock cycle; the execution module is used for executing a corresponding micro-operation according to the current micro-operation number, the current micro-operation element quantity and the decoding information; the element quantity counting unit is used for obtaining an actual element width of the target vector instruction; the element quantity counting unit is used for determining a maximum processable element quantity in a single time according to a vector register width and the actual element width; the element quantity counting unit is used for determining a completed element quantity according to the maximum processable element quantity and the current micro-operation number; the element quantity counting unit is used for determining a remaining element quantity according to a total amount of vector operation elements in the configuration information of the target vector instruction and the completed element quantity; the element quantity counting unit is used for taking the maximum processable element quantity as the current micro-operation element quantity when the remaining element quantity is greater than the maximum processable element quantity; the element quantity counting unit is used for taking the remaining element quantity as the current micro-operation element quantity, outputting a valid mask signal to the execution module and outputting a trigger control signal to the number updating unit when the remaining element quantity is less than the maximum processable element quantity; the element quantity counting unit is used for taking the maximum processable element quantity as the current micro-operation element quantity and outputting a trigger control signal to the number updating unit when the remaining element quantity is equal to the maximum processable element quantity.

2. The micro-operation module of claim 1, wherein, The number updating unit comprises an adder, a selector and a register; an output end of the register is connected with an input end of the adder, an output end of the adder is connected with a first input end of the selector, a second input end of the selector is used for accessing an initial micro-operation number, a control end of the selector is used as a control end of the number updating unit, and an output end of the selector is connected with an input end of the register; an output end of the register is used as an output end of the number updating unit.

3. The micro-operation module of claim 2, wherein, The register is configured to provide a current micro-operation number to the element quantity counting unit and the execution module, wherein the current micro-operation number is a micro-operation number written into the register in a previous clock cycle; The adder is configured to perform an addition operation based on the current micro-operation number to generate a new micro-operation number; The selector is configured to write the new micro-operation number generated by the adder into the register in a case that a trigger control signal is not received in a current clock cycle; The selector is configured to write the initial micro-operation number into the register in a case that the trigger control signal is received in the current clock cycle.

4. The micro-operation module of claim 1, wherein, The element quantity counting unit acquires an actual element width of the target vector instruction, including: When the decoding information of the target vector instruction includes an instruction element width, the instruction element width is taken as the actual element width; When the decoding information of the target vector instruction does not include the instruction element width and the decoding information of the target vector instruction includes a valid widening instruction signal, a configuration element width in configuration information of the target vector instruction is widened according to a preset rule to obtain the actual element width; When the decoding information of the target vector instruction does not include the instruction element width and the decoding information of the target vector instruction does not include the valid widening instruction signal, the configuration element width is taken as the actual element width.

5. The micro-operation module of claim 1, wherein, The micro-operation splitting module further includes a maximum micro-operation splitting counting unit, an output end of the maximum micro-operation splitting counting unit is connected to a control end of the number updating unit, a first input end of the maximum micro-operation splitting counting unit is connected to an output end of the number updating unit, and a second input end of the maximum micro-operation splitting counting unit is configured to be connected to the decoding module; The maximum micro-operation splitting counting unit is configured to acquire a target number of micro-operation splitting; The maximum micro-operation splitting counting unit is configured to determine whether micro-operation splitting of the target vector instruction is completed according to the current micro-operation number and the target number of micro-operation splitting, and output a trigger control signal to the number updating unit if the micro-operation splitting is completed.

6. The micro-operation module of claim 5, wherein, The maximum micro-operation splitting counting unit acquires a target number of micro-operation splitting, including: When the decoding information of the target vector instruction includes segment operation information, the target number of micro-operation splitting is determined according to a number of registers in a target register group and the segment operation information; The target register group is a register group in configuration information of the target vector instruction; When the decoding information of the target vector instruction does not include the segment operation information and the decoding information of the target vector instruction includes a valid widening instruction signal, the number of registers in the target register group is widened according to a preset rule to obtain the target number of micro-operation splitting; When the decoding information of the target vector instruction does not include the segment operation information and the decoding information of the target vector instruction does not include the valid widening instruction signal, the number of registers in the target register group is taken as the target number of micro-operation splitting.

7. The micro-operation module of claim 1, wherein, The microinstruction disassembling module further comprises an instruction processing unit, an output end of the instruction processing unit being connected to a control end of the numbering updating unit, and an input end of the instruction processing unit being connected to the decoding module; The instruction processing unit is configured to output a trigger control signal to the numbering updating unit when identifying that the instruction type in the decoding information of the target vector instruction is a target type.

8. A processor, comprising: The microinstruction disassembling module of any one of claims 1-7.

9. An electronic device, comprising: The processor of claim 8.

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