Task execution method, device, equipment and storage medium

Abstract

The embodiments of the present application provide a task execution method, apparatus, device and storage medium, which are applied to an operating system with a dual-state separation architecture, wherein the operating system is divided into a user space and a kernel space, and the method comprises: when executing a task in the operating system, receiving an interrupt request; based on the interrupt request, entering the kernel space to perform interrupt processing; if the currently executed task is a user-state task executed in the user space, and the operation currently executing the task is an atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation, so as to re-execute the atomic operation of the task after the task is restored. When an atomic operation exists in a task, the embodiments of the present application do not need to ensure that the atomic operation is not affected by other tasks by a system call method of turning off the interrupt operation and turning on the interrupt mode, thereby improving the system performance of the operating system.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a task execution method and apparatus, an electronic device, and a storage medium. Background Art

[0002] Atomic operations are a fundamental type of operation. They are uninterruptible operations, or a series of operations, that cannot be interrupted by any other task or event before the atomic operation is completed. Atomic operations are the basis for implementing other operations, such as locks and reference counters.

[0003] Some CPU (Central Processing Unit) architectures offer only simple atomic operations, typically implemented by disabling interrupts. However, in a dual-state architecture (an operating system architecture where application code runs in user space and system code runs in kernel space), user-state code must invoke a system request to disable interrupts. Each atomic operation requires one interrupt-disabling operation and one interrupt-enabling operation, meaning two system calls, significantly impacting system performance. Summary of the Invention

[0004] An embodiment of the present application provides a task execution method to solve the problem of affecting the system performance of an operating system when there are atomic operations in a task.

[0005] Correspondingly, an embodiment of the present application also provides a task execution device, an electronic device and a storage medium to ensure the implementation and application of the above method.

[0006] To solve the above problems, an embodiment of the present application discloses a task execution method, which is applied to an operating system with a dual-state separation architecture, wherein the operating system is divided into a user space and a kernel space. The method includes:

[0007] receiving an interrupt request while executing a task in the operating system;

[0008] Based on the interrupt request, entering the kernel space to perform interrupt processing;

[0009] If the currently executed task is a user-mode task executed in the user space, and the operation currently executing the task is an atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation to re-execute the atomic operation of the task after the task is restored.

[0010] Optionally, after entering the kernel space to perform interrupt processing based on the interrupt request, the method further includes:

[0011] If the currently executed task is a kernel-mode task executed in the kernel space, or if the currently executed task is a user-mode task but no atomic operation of the task is currently being executed, interrupt processing is performed in the kernel space.

[0012] Optionally, entering the kernel space to perform interrupt processing based on the interrupt request includes:

[0013] executing tasks in the user space;

[0014] receiving an interrupt processing request, and switching the task from the user space to the kernel space for interrupt processing;

[0015] Recording the context information of the task; the context information is used to restore the task to a state before switching from the user space to the kernel space when switching from the kernel space to the user space.

[0016] Optionally, the currently executing task is a user-mode task in the following way:

[0017] Read the task control block of the process corresponding to the task;

[0018] If the process structure in the task control block is not empty, it is determined that the task is the user mode task.

[0019] Optionally, determining whether the operation currently executing the task is an atomic operation is performed in the following manner:

[0020] Read the atomic operation function entry address and check length in the process structure of the process corresponding to the task;

[0021] By comparing the atomic operation function entry address and the check length with the context information, it is determined whether the atomic operation of the task is currently being executed.

[0022] Optionally, the method further includes:

[0023] When the currently executed task is a kernel-state task and the kernel-state task includes an atomic operation, performing an interrupt disabling operation;

[0024] After the atomic operation of the task is completed, an interruption operation is performed.

[0025] Optionally, the invention is applied to an operating system of a dual-state separation architecture of a single-core processor.

[0026] The present application also discloses a task execution device, which is applied to an operating system with a dual-state separation architecture, wherein the operating system is divided into a user space and a kernel space, and the device includes:

[0027] An interrupt request receiving module, configured to receive an interrupt request when executing a task in the operating system;

[0028] An interrupt processing module, configured to enter the kernel space and perform interrupt processing based on the interrupt request;

[0029] The user-state atomic operation processing module is used to roll back the execution flow of the task to the atomic operation entry of the atomic operation if the currently executed task is a user-state task executed in the user space and the operation currently executing the task is an atomic operation, so as to re-execute the atomic operation of the task after the task is restored.

[0030] Optionally, the device also includes: a kernel-mode task execution module, which is used to perform interrupt processing in the kernel mode if the currently executed task is a kernel-mode task executed in the kernel space, or if the currently executed task is a user-mode task but no atomic operation of the task is currently being executed.

[0031] Optionally, the interrupt processing module is used to execute tasks in the user space; receive an interrupt processing request, switch the task from the user space to the kernel space for interrupt processing; record the context information of the task; the context information is used to restore the task to the state before switching from the user state to the kernel state when switching the task from the kernel state to the user state.

[0032] Optionally, the device further comprises: a user-mode task determination module, configured to read a task control block of a process corresponding to the task; and determine that the task is the user-mode task if the process structure in the task control block is not empty.

[0033] Optionally, the device also includes: an atomic operation determination module, which is used to read the atomic operation function entry address and check length in the process structure of the process corresponding to the task; and determine whether the atomic operation of the task is currently being executed by comparing the atomic operation function entry address and the check length with the context information.

[0034] Optionally, the device also includes: a kernel-state atomic operation processing module, which is used to disable interrupt operations when the currently executed task is a kernel-state task and the kernel-state task includes atomic operations; and to enable interrupt operations after the atomic operations of the task are completed.

[0035] Optionally, the invention is applied to an operating system of a dual-state separation architecture of a single-core processor.

[0036] An embodiment of the present application also discloses an electronic device, including: a processor; and a memory, on which executable code is stored. When the executable code is executed, the processor executes one or more task execution methods described in the embodiments of the present application.

[0037] The embodiments of the present application also disclose one or more machine-readable media on which executable codes are stored. When the executable codes are executed, the processor executes the task execution method as described in one or more of the embodiments of the present application.

[0038] Compared with the prior art, the embodiments of the present application have the following advantages:

[0039] In an embodiment of the present application, when executing a task in an operating system, if an interrupt request is received, the kernel space is entered to perform interrupt processing. If the currently executed task is a user-mode task and the operation of the currently executed task is an atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation, so that the atomic operation of the task can be re-executed after the user-mode task is restored. In an embodiment of the present application, when an atomic operation exists in a task, there is no need to use a system call method of turning off and on the interrupt operation to ensure that the atomic operation is not affected by other tasks, thereby improving the system performance of the operating system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for the description of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 This is a flowchart of the steps of an embodiment of a task execution method of the present application;

[0042] Figure 2 It is a schematic diagram of task execution in an operating system of the present application;

[0043] Figure 3 is a flowchart of another embodiment of a task execution method of the present application;

[0044] Figure 4 is a schematic diagram of a memory layout of context information of this application;

[0045] Figure 5 This is a schematic diagram of atomic operations on an IoT operating system with a dual-state separation architecture of the present application;

[0046] Figure 6 This is a structural block diagram of an embodiment of a task execution device of the present application;

[0047] Figure 7 It is a structural diagram of a device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0049] Some technical terms involved in the embodiments of this application are explained below:

[0050] Kernel state: Privileged operating state, can access all system resources.

[0051] User mode: a non-privileged operating state with controlled access rights.

[0052] Dual-state separation architecture: an operating system architecture in which application code runs in user state and system code runs in kernel state.

[0053] Atomic operation: an operation or a series of operations that cannot be interrupted.

[0054] CAS (Compare And Swap): A compare and swap operation. If the value at the specified address is equal to the expected value, the new value is written to the address, otherwise nothing is done.

[0055] Reference Figure 1 , is a step flow chart of an embodiment of a task execution method of the present application, which is applied to an operating system with a dual-state separation architecture, wherein the operating system is divided into user space and kernel space.

[0056] In a specific implementation, the operating system may be an IoT operating system, which can be applied to IoT devices such as shared cars, smart homes, mobile phones, and tablets. IoT operating systems may include, but are not limited to, FreeRTOS, RT-Thread, ThreadX, ARMmbed, Zephyr, LiteOS, and TinyOS. In a specific implementation, because the resources of an IoT operating system, such as an IoT operating system, are limited, excessive resource access operations will inevitably consume excessive resources. Failure to distinguish between these operations may result in resource access conflicts. Therefore, to reduce conflicts in access and use of limited resources, different operations are assigned different execution levels.

[0057] Taking the IoT operating system as an example, it is divided into two operating levels: user mode and kernel mode, which are used to distinguish the execution levels of different tasks. Specifically, kernel mode has more resources, or access to more resources, and is therefore also called a privileged state. In contrast, user mode is a non-privileged state, and its access to resources is restricted. If a task (process) runs in kernel mode, it can access any computer resource, meaning its resource access rights are unrestricted. However, if a task runs in user mode, its resource requirements are subject to various restrictions. For example, access operations such as reading data from the hard drive or receiving input from the keyboard require entering kernel mode. User mode has a corresponding user space, and kernel mode has a corresponding kernel space. When a task runs in kernel space, it is in kernel mode, and when it runs in user space, it is in user mode.

[0058] Specifically, the task execution method may include the following steps:

[0059] Step 102: Receive an interrupt request while executing a task in the operating system.

[0060] Step 104: Based on the interrupt request, enter the kernel space to perform interrupt processing.

[0061] In a specific implementation, a task can be executed in user space or in kernel space. A task executed in user space is a user-state task, and a task that needs to be executed in kernel space is a kernel-state task.

[0062] In the embodiment of the present application, when an asynchronous event occurs, for example, a peripheral device sends an interrupt request to the CPU of the operating system, such as a serial port receiving data or a network card receiving data, interrupt processing is performed based on the interrupt request when entering kernel mode. If the task is a user-mode task executed in user space, it is necessary to switch the task from user space to kernel space to enter kernel space for interrupt processing.

[0063] An example of interrupt processing is given below: When the CPU is executing a task, if the peripheral device sends an interrupt request to the CPU of the operating system, the CPU will send an interrupt response signal if the response is met, and at the same time turn off the interrupt operation, indicating that the CPU will no longer accept the interrupt request of another device. At this time, the CPU will find out which device is the source of the interrupt request, and save the contents of the CPU's own program counter (PC), and then transfer to the interrupt service routine that handles the interrupt source. The CPU saves the field information, and the field information will be restored after the device service (such as exchanging data). Finally, the interrupt operation can be enabled and the task that was originally interrupted can be returned to continue execution.

[0064] Step 106: If the currently executed task is a user-mode task executed in the user space, and the operation currently executing the task is an atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation to re-execute the atomic operation of the task after the task is restored.

[0065] Among them, a task is usually composed of one or more operations, and the operations in the task may include atomic operations. Specifically, the atomic operation is indivisible and will not be interrupted by any other task or event after execution. If any step in the atomic operation is not completed, then all the completed operation steps must be rolled back to ensure that either all the operation steps are not completed or all the operation steps are completed. In the related art, in order to ensure the atomicity of the atomic operation (i.e., it will not be interrupted by other tasks), the atomic operation is implemented in the user state by turning off the interrupt system call. Specifically, a system call is first initiated to disable the interrupt, then the atomic operation is executed, and finally a system call is initiated again to enable the interrupt (turn off the interrupt). It can be understood that the atomicity of the atomic operation is guaranteed by turning off the interrupt system call. Not only is the efficiency low, but the switch interrupt service is not suitable for being open to the user state as a system service.

[0066] In an embodiment of the present application, when interrupt processing is triggered, the intervention of the operating system is required to carry out management work. Since the management work of the operating system (such as process switching, allocation of IO devices, etc.) requires the use of privileged instructions, if it is in user space, it is necessary to switch from user space to kernel space. Among them, if a user-state task is executed in user space before switching from user space to kernel space, and the atomic operation in the user-state task is currently being executed, in order to ensure the atomicity of the atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation, so that the atomic operation of the task can be re-executed after the user-state task is restored.

[0067] In order to better illustrate the embodiments of the present application, specific examples are used below for illustration. Figure 2 , which is a schematic diagram of task execution in an operating system of the present application. The operating system includes user space and kernel space. Tasks can be executed in user space or kernel space. When an interrupt request is received, it enters the kernel space. Among them, if the task is a user-mode task executed in user space and the operation of the currently executing task is an atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation, so as to continue to execute the atomic operation.

[0068] In the above-mentioned task execution method, when executing a task in the operating system, if an interrupt request is received, the kernel space is entered to perform interrupt processing. If the currently executed task is a user-mode task and the operation of the currently executed task is an atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation, so that the atomic operation of the task can be re-executed after the user-mode task is restored. In the embodiment of the present application, when there is an atomic operation in the task, there is no need to use a system call method of turning off the interrupt operation and turning on the interrupt mode to ensure that the atomic operation is not affected by other tasks, thereby improving the system performance of the operating system.

[0069] Reference Figure 3 , is a flowchart of a task execution method embodiment of the present application, which is applied to an operating system with a dual-state separation architecture, wherein the operating system is divided into a user space and a kernel space, and the method comprises the following steps:

[0070] Step 302: Receive an interrupt request while executing a task in the operating system.

[0071] Step 304: Based on the interrupt request, enter the kernel space to perform interrupt processing.

[0072] In a specific implementation, when an interrupt is triggered, interrupt processing is performed in the kernel state of the operating system. If the system is in the user state when the interrupt is triggered, it is necessary to switch from the user space to the kernel space.

[0073] In an exemplary embodiment, the step 304 of entering the kernel space to perform interrupt processing based on the interrupt request may include the following steps:

[0074] executing tasks in the user space;

[0075] receiving an interrupt processing request, and switching the task from the user space to the kernel space for interrupt processing;

[0076] Recording the context information of the task; the context information is used to restore the task to a state before switching from the user space to the kernel space when switching from the kernel space to the user space.

[0077] Context information refers to the state of a task executing on the CPU. It consists of information in general registers, control registers, stack addresses, program counters, and other registers. Context information includes the PC (Program Counter, the program execution location).

[0078] Specifically, when executing a task in user space, if an interrupt processing request is received, interrupt processing will be entered, and the task needs to be switched from user space to kernel space. Before switching to kernel space, the scene needs to be saved first. Specifically, before switching to kernel space, the context information of the task needs to be recorded, and then switched to kernel space. By saving the scene, when switching from kernel space to user space again, the state before switching from user space to kernel space can be restored.

[0079] Step 306: If the currently executed task is a user-mode task and the operation currently executing the task is an atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation to re-execute the atomic operation of the task after the task is restored.

[0080] In an exemplary embodiment, the currently executing task is a user mode task in the following manner:

[0081] Read the task control block of the process corresponding to the task;

[0082] If the process structure in the task control block is not empty, it is determined that the task is the user mode task.

[0083] In a specific implementation, for a user-state task, it belongs to a certain process, so the task_group field of the task control block of the user-state task is not NULL (empty), while the task_group field of the kernel-state task is NULL. Therefore, in an embodiment of the present application, by reading the task_group field of the task control block of the process corresponding to the task, if the task_group field is not empty, it can be determined that the task is a user-state task.

[0084] In an exemplary embodiment, the operation of currently executing the task is determined to be an atomic operation in the following manner:

[0085] Read the atomic operation function entry address and check length in the process structure of the process corresponding to the task;

[0086] By comparing the atomic operation function entry address and the check length with the context information, it is determined whether the atomic operation of the task is currently being executed.

[0087] In the specific implementation, the process structure task_group_t where the current user-mode task is located can be obtained. The process structure records the atomic operation function entry address (cmpxchg_start) and check length (cmpxchg_check_scope) of the atomic operation.

[0088] As a specific example, when a user-mode task enters kernel space, the context information of the user-mode task is saved. The schematic diagram of the memory layout of the context information can be referred to Figure 4 , assuming that the pointer ctx points to the memory area that stores the context information, the PC can be obtained through the statement ctx->pc.

[0089] After obtaining the PC from the context information, compare cmpxchg_start, cmpxchg_check_scope, and PC to determine whether the following conditions are met:

[0090] cmpxchg_start <pc<cmpxchg_start+cmpxchg_check_scope

[0091] If cmpxchg_start, cmpxchg_check_scope and PC meet the above conditions, it can be determined that the current user-state task is performing an atomic operation, and the PC value in the context information of the user-state task can be set to return to the atomic operation function entry address of the u_cmpxchg function: ctx->pc = cmpxchg_start, then the atomic operation in the user-state task can be executed again from the atomic operation function entry address of the u_cmpxchg function, ensuring that other tasks accessing memory will not affect the atomic operation in the user-state task, thereby ensuring the atomicity of the atomic operation of the user-state task.

[0092] Step 308: If the currently executed task is a kernel-mode task executed in the kernel space, or if the currently executed task is a user-mode task but no atomic operation of the task is currently being executed, interrupt processing is performed in the kernel mode.

[0093] In an embodiment of the present application, when an interrupt occurs, if the system is executing a user-mode task in user mode, and the currently executing task is an atomic operation in the user-mode task, in order to ensure the atomicity of the atomic operation, the execution flow of the task is rolled back to the atomic operation entry point so that the atomic operation of the task can be re-executed after the user-mode task is restored. If the currently executing task is a kernel-mode task, or if the currently executing task is a user-mode task but is not currently executing an atomic operation of the task, there is no need to perform a rollback operation.

[0094] In an exemplary embodiment, the method may further include the following steps:

[0095] When the currently executed task is a kernel-state task and the kernel-state task includes an atomic operation, performing an interrupt disabling operation;

[0096] After the atomic operation of the task is completed, an interruption operation is performed.

[0097] In a specific implementation, for atomic operations in kernel-mode tasks, the interrupt disabling operation is performed first, followed by the atomic operations in the kernel-mode task, and finally the interrupt enabling operation is performed, thereby ensuring the atomicity of atomic operations in the kernel-mode task. It can be seen that the embodiments of the present application can ensure the atomicity of atomic operations in both user-mode tasks and kernel-mode tasks.

[0098] In order to enable those skilled in the art to better understand the embodiments of the present application, the following specific examples are used for illustration. Figure 5 , is a schematic diagram of atomic operations on an IoT operating system with a dual-state separation architecture of the present application, which divides the operating system into user space and kernel space. First, the atomic operations (CAS atomic operations) of user-mode tasks are implemented based on ordinary instructions. For example, the interface for implementing CAS atomic operations can be:

[0099] int32_t u_cmpxchg(int32_t oldval,int32_t newval,volatile int32_t*ptr);

[0100] Where oldval represents the expected old value, newval represents the new value to be written, and ptr is the memory address where the atomic operation is performed. The above interface is specifically defined as follows: if the memory value at address ptr is equal to old, then write new to ptr and return 0; otherwise, return a non-zero value.

[0101] In the embodiment of the present application, the entire atomic operation interface set is implemented based on the above-mentioned CAS atomic operation, such as the atomic operation of addition, the atomic operation of subtraction, the atomic operation of and, etc. Through the atomic operation interface set, the atomic operations in the task can be executed based on the interface sequence.

[0102] However, since the above interfaces are implemented using ordinary instructions, the atomicity of atomic operations cannot be guaranteed. On a single-core processor, the execution of atomic operations can only be interrupted by interrupts, including the trigger source of task scheduling.

[0103] To address the above issues, in an embodiment of the present application, an atomic operation check operation may be triggered in the interrupt processing flow:

[0104] If the interrupt processing is triggered and the current task is a user-mode task and the u_cmpxchg function (CAS atomic operation) in the user-mode task is being executed, the context information is modified to return the PC to the atomic operation function entry address of the u_cmpxchg function. In this case, after the user-mode task interrupted by the interrupt is restored, it will be executed again from the atomic operation function entry address of the u_cmpxchg function, ensuring that other tasks accessing memory will not affect the execution of the u_cmpxchg function; if the task currently being executed is a non-user-mode task (kernel-mode task) when the interrupt is triggered, or although the task currently being executed is a user-mode task, there is no u_cmpxchg function in the user-mode task being executed, the check ends directly.

[0105] By adding an atomic operation check to the interrupt flow, the present embodiment ensures the atomicity of the u_cmpxchg function in the task. By using the present embodiment, high-performance atomic operations can be implemented through software on a single-core processor that does not support complete atomic operations, thereby improving the system performance of the operating system.

[0106] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0107] On the basis of the above embodiments, this embodiment further provides a task execution device, which is applied to electronic devices such as terminal devices and servers.

[0108] Reference Figure 6 , shows a structural block diagram of an embodiment of a task execution device of the present application, which is applied to an operating system with a dual-state separation architecture, wherein the operating system is divided into a user space and a kernel space. The device may specifically include the following modules:

[0109] An interrupt request receiving module 602, configured to receive an interrupt request when executing a task in the operating system;

[0110] The interrupt processing module 604 is used to enter the kernel space to perform interrupt processing based on the interrupt request; the user-state atomic operation processing module 606 is used to roll back the execution flow of the task to the atomic operation entry of the atomic operation if the currently executed task is a user-state task executed in the user space and the operation currently executing the task is an atomic operation, so as to re-execute the atomic operation of the task after the task is restored.

[0111] In an exemplary embodiment, the apparatus may further include:

[0112] A kernel-mode task execution module is used to perform interrupt processing in the kernel mode if the currently executed task is a kernel-mode task executed in the kernel space, or if the currently executed task is a user-mode task but no atomic operation of the task is currently being executed.

[0113] In an exemplary embodiment, the interrupt processing module 604 is used to execute a task in the user space; receive an interrupt processing request, and switch the task from the user space to the kernel space for interrupt processing; record the context information of the task; and the context information is used to restore the task to the state before switching from the user space to the kernel space when switching the task from the kernel space to the user space.

[0114] In an exemplary embodiment, the apparatus may further include: a user-mode task determination module configured to read a task control block of a process corresponding to the task; and determine that the task is the user-mode task if the process structure in the task control block is not empty.

[0115] In an exemplary embodiment, the device may also include: an atomic operation determination module, used to read the atomic operation function entry address and check length in the process structure of the process corresponding to the task; by comparing the atomic operation function entry address and the check length with the context information to determine whether the atomic operation of the task is currently being executed.

[0116] In an exemplary embodiment, the device may also include: a kernel-state atomic operation processing module, used to disable interrupt operations when the currently executed task is a kernel-state task and the kernel-state task includes atomic operations; and to enable interrupt operations after the atomic operation of the task is completed.

[0117] In an exemplary embodiment, the operating system is applied to a dual-state split architecture of a single-core processor.

[0118] In summary, in an embodiment of the present application, when executing a task in the operating system, if an interrupt request is received, the kernel space is entered to perform interrupt processing. If the currently executing task is a user-mode task and the operation of the currently executing task is an atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation, so that the atomic operation of the task can be re-executed after the user-mode task is restored. When an atomic operation exists in a task, in an embodiment of the present application, there is no need to use a system call method of disabling interrupt operations and enabling interrupt modes to ensure that the atomic operation is not affected by other tasks, thereby improving the system performance of the operating system.

[0119] An embodiment of the present application further provides a non-volatile readable storage medium, which stores one or more modules (programs). When the one or more modules are applied to a device, the device can execute instructions (instructions) of each method step in the embodiment of the present application.

[0120] The present application provides one or more machine-readable media having instructions stored thereon, which, when executed by one or more processors, cause an electronic device to perform one or more of the methods described in the above embodiments. In the present application, the electronic device includes various types of devices such as terminal devices and servers (clusters).

[0121] The embodiments of the present disclosure may be implemented as a device configured as desired using any appropriate hardware, firmware, software, or any combination thereof, and the device may include electronic devices such as terminal devices and servers (clusters). Figure 7 An exemplary apparatus 700 that can be used to implement various embodiments described in this application is schematically illustrated.

[0122] For one embodiment, Figure 7 An exemplary apparatus 700 is shown having one or more processors 702, a control module (chip set) 704 coupled to at least one of the processor(s) 702, a memory 706 coupled to the control module 704, a non-volatile memory (NVM) / storage device 708 coupled to the control module 704, one or more input / output devices 710 coupled to the control module 704, and a network interface 712 coupled to the control module 704.

[0123] The processor 702 may include one or more single-core or multi-core processors, and the processor 702 may include any combination of general-purpose processors or dedicated processors (e.g., graphics processors, application processors, baseband processors, etc.). In some embodiments, the apparatus 700 can serve as a terminal device, server (cluster), or other device described in the embodiments of the present application.

[0124] In some embodiments, the apparatus 700 may include one or more computer-readable media (e.g., memory 706 or NVM / storage 708) having instructions 714 and one or more processors 702 configured in conjunction with the one or more computer-readable media to execute the instructions 714 to implement a module to perform the actions described in the present disclosure.

[0125] For one embodiment, the control module 704 may include any suitable interface controller to provide any suitable interface to at least one of the processor(s) 702 and / or any suitable device or component in communication with the control module 704 .

[0126] The control module 704 may include a memory controller module to provide an interface to the memory 706. The memory controller module may be a hardware module, a software module, and / or a firmware module.

[0127] The memory 706 can be used, for example, to load and store data and / or instructions 714 for the device 700. For one embodiment, the memory 706 can include any suitable volatile memory, such as a suitable DRAM. In some embodiments, the memory 706 can include double data rate type four synchronous dynamic random access memory (DDR4 SDRAM).

[0128] For one embodiment, the control module 704 may include one or more input / output controllers to provide interfaces to the NVM / storage device 708 and the input / output device(s) 710 .

[0129] For example, NVM / storage 708 may be used to store data and / or instructions 714. NVM / storage 708 may include any suitable non-volatile memory (e.g., flash memory) and / or may include any suitable non-volatile storage device(s) (e.g., one or more hard disk drives (HDDs), one or more compact disk (CD) drives, and / or one or more digital versatile disk (DVD) drives).

[0130] NVM / storage device 708 may include storage resources that are physically part of the device on which apparatus 700 is installed, or it may be accessible to the device without being part of the device. For example, NVM / storage device 708 may be accessible over a network via input / output device(s) 710.

[0131] (One or more) input / output devices 710 may provide an interface for apparatus 700 to communicate with any other appropriate devices. Input / output devices 710 may include communication components, audio components, sensor components, etc. Network interface 712 may provide an interface for apparatus 700 to communicate via one or more networks. Apparatus 700 may wirelessly communicate with one or more components of a wireless network according to any of one or more wireless network standards and / or protocols, for example, accessing a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G, 5G, etc., or a combination thereof for wireless communication.

[0132] For one embodiment, at least one of the processor(s) 702 may be packaged together with the logic of one or more controllers (e.g., a memory controller module) of the control module 704. For one embodiment, at least one of the processor(s) 702 may be packaged together with the logic of one or more controllers of the control module 704 to form a system-in-package (SiP). For one embodiment, at least one of the processor(s) 702 may be integrated on the same die with the logic of one or more controllers of the control module 704. For one embodiment, at least one of the processor(s) 702 may be integrated on the same die with the logic of one or more controllers of the control module 704 to form a system-on-chip (SoC).

[0133] In various embodiments, the apparatus 700 may be, but is not limited to, a terminal device such as a server, a desktop computing device, or a mobile computing device (e.g., a laptop computing device, a handheld computing device, a tablet computer, a netbook, etc.). In various embodiments, the apparatus 700 may have more or fewer components and / or a different architecture. For example, in some embodiments, the apparatus 700 includes one or more cameras, a keyboard, a liquid crystal display (LCD) screen (including a touchscreen display), a non-volatile memory port, multiple antennas, a graphics chip, an application-specific integrated circuit (ASIC), and a speaker.

[0134] Among them, the main control chip can be used as a processor or control module in the detection device, sensor data, location information, etc. are stored in the memory or NVM / storage device, the sensor group can be used as an input / output device, and the communication interface may include a network interface.

[0135] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0136] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0137] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable task execution terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable task execution terminal device generate instructions for implementing the process in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0138] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable task execution terminal device to work in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0139] These computer program instructions can also be loaded onto a computer or other programmable task execution terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0140] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0141] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0142] The above is a detailed introduction to a task execution method and device, an electronic device and a storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A task execution method, characterized in that: An Internet of Things operating system applied to a dual-state separation architecture, wherein the operating system is divided into a user space and a kernel space, and the method includes: receiving an interrupt request while executing a task in the operating system; Entering the kernel space to perform interrupt processing based on the interrupt request includes: executing a task in the user space; receiving an interrupt processing request, switching the task from the user space to the kernel space for interrupt processing; recording context information of the task; the context information is a state set of task execution, including a program execution location, and is used to restore the task to a state before switching from the user space to the kernel space when switching from the kernel space to the user space; If the currently executed task is a user-mode task executed in the user space, and the operation currently executing the task is an atomic operation, the execution flow of the task is rolled back to the atomic operation entry of the atomic operation to re-execute the atomic operation of the task after the task is restored.

2. The method according to claim 1, characterized in that After entering the kernel space to perform interrupt processing based on the interrupt request, the method further includes: If the currently executed task is a kernel-mode task executed in the kernel space, or if the currently executed task is a user-mode task but no atomic operation of the task is currently being executed, interrupt processing is performed in the kernel space.

3. The method according to claim 1, characterized in that The task currently being executed is a user-mode task: Read the task control block of the process corresponding to the task; If the process structure in the task control block is not empty, it is determined that the task is the user mode task.

4. The method according to claim 1, wherein Determine whether the operation currently executing the task is an atomic operation by: Read the atomic operation function entry address and check length in the process structure of the process corresponding to the task; By comparing the atomic operation function entry address and the check length with the context information, it is determined whether the atomic operation of the task is currently being executed.

5. The method according to claim 3, characterized in that The method further comprises: When the currently executed task is a kernel-state task and the kernel-state task includes an atomic operation, performing an interrupt disabling operation; After the atomic operation of the task is completed, an interruption operation is performed.

6. The method according to claim 1, characterized in that An operating system for a dual-state split architecture of a single-core processor.

7. A task execution device, characterized in that: An operating system applied to a dual-state separation architecture, wherein the operating system is divided into a user space and a kernel space, and the device comprises: An interrupt request receiving module, configured to receive an interrupt request when executing a task in the operating system; an interrupt processing module, configured to enter the kernel space to perform interrupt processing based on the interrupt request, including: executing a task in the user space; receiving an interrupt processing request, switching the task from the user space to the kernel space for interrupt processing; and recording context information of the task; wherein the context information is a set of task execution states, including a program execution location, and is configured to restore the task to a state before the task was switched from the kernel space to the user space when the task was switched from the kernel space to the user space; The user-state atomic operation processing module is used to roll back the execution flow of the task to the atomic operation entry if the currently executed task is a user-state task executed in the user space and the operation currently executing the task is an atomic operation, so as to re-execute the atomic operation of the task after the task is restored.

8. An electronic device, characterized in that: include: processor; and A memory having executable codes stored thereon, which, when executed, causes the processor to execute the task execution method according to one or more of claims 1-6.

9. One or more machine-readable media having executable codes stored thereon, which, when executed, cause a processor to execute the task execution method according to one or more of claims 1-6.

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