Display device

Abstract

A display device is provided. The display device includes a display panel, a gate driving block outputting a scan signal to the display panel, a source driving block outputting a data signal to the display panel, and a controller. In a low frequency mode, the controller divides the display panel into a first area operating at a first frequency lower than a reference frequency and a second area operating at a second frequency lower than the first frequency according to image data, the source driving block outputs the data signal to the first area at the first frequency and outputs the data signal to the second area at the second frequency, and the gate driving block outputs a first scan signal to the first area at the first frequency and outputs a second scan signal to the second area at the second frequency.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0097623 filed on August 4, 2020, as well as all derivative applications thereof, the contents of which are incorporated herein in their entirety by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to a display apparatus. More particularly, embodiments of the present application relate to a display apparatus capable of reducing power consumption. BACKGROUND

[0003] Various types of display apparatuses are being developed that are applied to multimedia apparatuses such as televisions, mobile phones, tablet computers, navigators, etc.

[0004] As the use fields of these display apparatuses are diversified, the types of images displayed through the display apparatuses are also diversified. Also, different images can be displayed through one display apparatus. SUMMARY

[0005] Displaying an image through a display apparatus consumes a large amount of power, and as the driving frequency of the display apparatus becomes higher, the power consumption of the display apparatus becomes higher. Accordingly, a technology for reducing the power consumption of the display apparatus is desired.

[0006] Embodiments of the present application provide a display apparatus having reduced power consumption.

[0007] Embodiments of the present application provide a display apparatus including a display panel, a gate driving block, a source driving block, and a controller, the display panel displays an image, the gate driving block outputs a scan signal to the display panel, the source driving block has a normal mode operating at a reference frequency and a low frequency mode operating at a frequency lower than the reference frequency and outputs a data signal to the display panel, and the controller receives an image signal and an external control signal and generates a gate driving signal, a source driving signal, and image data in response to the image signal and the external control signal. The controller divides the display panel into a first area operating at a first frequency lower than the reference frequency and a second area operating at a second frequency lower than the first frequency according to the image data in the low frequency mode. The source driving block outputs the data signal to the first area at the first frequency and outputs the data signal to the second area at the second frequency in the low frequency mode. The gate driving block outputs a first scan signal to the first area at the first frequency and outputs a second scan signal to the second area at the second frequency in the low frequency mode.

[0008] In an embodiment, the controller can include a driving controller that outputs a low frequency control signal according to the normal mode operating at the reference frequency and the low frequency mode operating at at least one of the first frequency and the second frequency lower than the reference frequency in response to the image data.

[0009] In an embodiment, the controller can further include a region setting unit that divides the display panel into the first region and the second region in response to the low frequency control signal and the image data, and outputs a first control signal for driving the first region at the first frequency and a second control signal for driving the second region at the second frequency.

[0010] In an embodiment, the controller can further include a generator that generates a masking signal in response to the first control signal and the second control signal, and the controller can apply the gate driving signal and the masking signal to the gate driving block.

[0011] In an embodiment, the gate driving block can include a gate driver that generates a gate output signal in response to the gate driving signal, and a masking unit that masks the gate output signal in response to the masking signal to output a scan signal.

[0012] In an embodiment, the gate driver can output the gate output signal at a reference frequency. The masking unit can mask the gate output signal corresponding to the first region to output a first scan signal at the first frequency, and mask the gate output signal corresponding to the second region to output a second scan signal at the second frequency. The masking signal can include a first masking interval in which the gate output signal corresponding to the first region is masked, and a second masking interval in which the gate output signal corresponding to the second region is masked.

[0013] In an embodiment, the gate driver can output the gate output signal at the first frequency in the low frequency mode. The masking unit can not mask the gate output signal corresponding to the first region to output a first scan signal at the first frequency, and mask the gate output signal corresponding to the second region to output a second scan signal at the second frequency. The masking signal can include a second masking interval in which the gate output signal corresponding to the second region is masked.

[0014] In an embodiment, the controller can apply the image data, the source driving signal, and the first control signal and the second control signal to a source driving block. The source driving block can include a power controller that generates a power control signal in response to the first control signal and the second control signal, and a source driver that converts the image data into a data signal in response to the power control signal and the source driving signal.

[0015] In an embodiment, the first frequency can be equal to or lower than about 1 hertz (Hz).

[0016] In an embodiment, the second region can include at least two regions.

[0017] Embodiments of the present application provide a display apparatus including a display panel, a gate driver block, a source driver block, and a controller, the display panel displays an image, the gate driver block outputs a scan signal to the display panel, the source driver block outputs a data signal to the display panel, and the controller receives an image signal and an external control signal and generates a gate driving signal, a source driving signal, and image data in response to the image signal and the external control signal. The controller divides the display panel into a reference area operated at a reference frequency and a low frequency area operated at a frequency lower than the reference frequency according to the image data, and divides the low frequency area into a first area operated at a first frequency lower than the reference frequency and a second area operated at a second frequency lower than the first frequency according to the image data. The source driver block outputs the data signal to the reference area at the reference frequency, outputs the data signal to the first area at the first frequency, and outputs the data signal to the second area at the second frequency. The gate driver block outputs a reference scan signal to the reference area at the reference frequency, outputs a first scan signal to the first area at the first frequency, and outputs a second scan signal to the second area at the second frequency.

[0018] In embodiments, the controller can include a region setting unit that divides the display panel into the reference area and the low frequency area according to the image data, divides the low frequency area into the first area and the second area, and outputs a reference control signal for driving the reference area at the reference frequency, a first control signal for driving the first area at the first frequency, and a second control signal for driving the second area at the second frequency.

[0019] In embodiments, the controller can further include a generator that generates a masking signal in response to the reference control signal and the first and second control signals, and the controller can apply the gate driving signal and the masking signal to the gate driver block.

[0020] In embodiments, the gate driver block can include a gate driver that generates a gate output signal in response to the gate driving signal, and a masking unit that masks the gate output signal in response to the masking signal to output the scan signal.

[0021] In embodiments, the gate driver can output the gate output signal at the reference frequency in the reference area and the first and second areas, the masking unit can not mask the gate output signal corresponding to the reference area to output the reference scan signal at the reference frequency, mask the gate output signal corresponding to the first area to output the first scan signal at the first frequency, and mask the gate output signal corresponding to the second area to output the second scan signal at the second frequency. The masking signal can include a first masking interval in which the gate output signal corresponding to the first area is masked, and a second masking interval in which the gate output signal corresponding to the second area is masked.

[0022] In an embodiment, the first masking interval can have a frequency different from a frequency of the second masking interval.

[0023] In an embodiment, the controller can apply the image data, the source driving signal, the reference control signal, and the first and second control signals to the source driving block.

[0024] In an embodiment, the source driving block can include a power controller that generates a power control signal in response to the reference control signal and the first and second control signals, and a source driver that converts the image data into a data signal in response to the power control signal and the source driving signal.

[0025] In an embodiment, the reference frequency can be equal to or less than about 1 Hz.

[0026] In an embodiment, the second area can include at least two areas.

[0027] According to the above, the display panel is divided into a plurality of areas according to an image displayed therein, and the plurality of areas are operated at frequencies different from each other. Accordingly, power consumption of the display apparatus is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other advantages of the present application will become readily apparent by reference to the following detailed description when considered in connection with the accompanying drawings wherein:

[0029] Figure 1 is a plan view illustrating an embodiment of a display apparatus according to the present application;

[0030] Figure 2 is a block diagram illustrating an embodiment of a display apparatus according to the present application;

[0031] Figure 3 is a block diagram illustrating an embodiment of a controller, a gate driving block, and a source driving block according to the present application;

[0032] Figure 4A is a plan view illustrating an embodiment of a display panel according to the present application;

[0033] Figure 4B is a plan view illustrating an embodiment of a display panel according to the present application;

[0034] Figure 4C is a plan view illustrating an embodiment of a display panel according to the present application;

[0035] Figure 5 is a block diagram illustrating an embodiment of a gate driving block according to the present application;

[0036] Figure 6is a circuit diagram showing an embodiment of the k-th gate driving circuit and the k-th masking circuit according to the present application;

[0037] Figure 7A is a timing chart showing an embodiment of the operation of the gate driving block according to the present application;

[0038] Figure 7B is a timing chart showing an embodiment of the operation of the gate driving block according to Figure 7A the present application;

[0039] Figure 8 is a timing chart showing an embodiment of the operation of the source driving block according to the present application;

[0040] Figure 9 is a block diagram showing an embodiment of the controller, the gate driving block, and the source driving block according to the present application;

[0041] Figure 10A is a plan view showing an embodiment of the display panel according to the present application;

[0042] Figure 10B is a plan view showing an embodiment of the display panel according to the present application;

[0043] Figure 11 is a block diagram showing an embodiment of the gate driving block according to the present application;

[0044] Figure 12A is a timing chart showing an embodiment of the operation of the gate driving block according to the present application;

[0045] Figure 12B is a timing chart showing an embodiment of the output of the scan signal of the operation of the gate driving block according to Figure 12A the present application; and

[0046] Figure 13 is a timing chart showing an embodiment of the operation of the source driving block according to the present application. DETAILED DESCRIPTION

[0047] In the present disclosure, it is to be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers can be present.

[0048] Like reference numerals refer to like elements throughout the specification. In the drawings, the thickness, proportions and dimensions of components can be exaggerated for effective description of technical content.

[0049] As used herein, the term "and / or," includes any and all combinations of one or more of the associated listed items.

[0050] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0051] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.

[0052] "About" or "approximately", as used herein when used in connection with a quantity, includes the stated value and means within a reasonable range of error for the quantity as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For example, terms such as "unit" or "block" can refer to a circuit or processor.

[0054] It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0055] In the following, the present application will be explained in detail with reference to the accompanying drawings.

[0056] Figure 1 is a plan view showing an embodiment of a display device DD according to the present application.

[0057] Referring to Figure 1 , a mobile terminal is shown as a representative embodiment of a display device DD. The mobile terminal can include a tablet personal computer ("PC"), a smart phone, a personal digital assistant, a portable multimedia player, a game unit, a watch-type electronic device, etc., however, the present application should not be limited thereto or thereby. The display device according to the present application can be applied to large electronic products such as a television, an outdoor billboard, etc., as well as to medium and small electronic products such as a personal computer, a notebook computer, an information kiosk, a car navigation unit, a camera, etc. However, this is merely exemplary, and the display device can be applied to other electronic devices so long as they do not depart from the inventive concept of the present disclosure.

[0058] Referring to Figure 1 , a display surface through which a reference image IMR and a low-frequency image IML are displayed is substantially parallel to a plane defined by a first direction DR1 and a second direction DR2. The display device DD includes a plurality of regions distinguished from each other on the display surface. The display surface includes a display region DA through which an image is displayed and a non-display region NDA adjacent to the display region DA. The non-display region NDA can also be referred to as a "bezel region". In an embodiment, the display region DA can have a quadrangular shape. The non-display region NDA can surround the display region DA. In addition, although not shown in the drawings, the display device DD can have a shape partially bent. As a result, a portion of the display region DA can have a bent shape.

[0059] The display region DA of the display device DD includes a reference region DAR and a low-frequency region LAR. In a predetermined application program, the reference image IMR is displayed through the reference region DAR, and the low-frequency image IML is displayed through the low-frequency region LAR. In an embodiment, the reference image IMR can be a video, however, it should not be particularly limited. The low-frequency image IML can be a still image such as a keypad, or an image containing text information having a long change period, however, it should not be particularly limited.

[0060] The display device DD in an embodiment can drive the reference region DAR at a reference frequency RF (refer to Figure 7A ), and can drive the low-frequency region LAR at a frequency lower than the reference frequency RF. The display device DD can reduce the driving frequency of the low-frequency region LAR, and thus can reduce power consumption.

[0061] Each of the reference region DAR and the low frequency region LAR can have a predetermined size, and the size can be changed by an application program. In an embodiment, the display region DA can include only the reference region DAR through which the reference image IMR is displayed, or can include only the low frequency region LAR through which the low frequency image IML is displayed. In addition, the low frequency region LAR can be divided into two or more regions, and a driving frequency of each of the regions can be determined depending on a type or a gray scale of an image displayed through each region.

[0062] Figure 2 is a block diagram illustrating an embodiment of a display apparatus according to the present application. Figure 3 is a block diagram illustrating an embodiment of a controller CP, a gate driving block GDB, and a source driving block SDB according to the present application. Figure 4A to Figure 4C is a plan view illustrating an embodiment of a display panel according to the present application.

[0063] Referring to Figure 2 and Figure 3 , the display apparatus DD includes a display panel DP, a controller CP, a source driving block SDB, a gate driving block GDB, an emission control block EDB, and a voltage generator VGT.

[0064] The controller CP receives an image signal RGB and an external control signal CTRL from an external source. The controller CP converts a data format of the image signal RGB to a data format suitable for an interface between the controller CP and the source driving block SDB to generate image data IMD. The controller CP generates a source driving signal SDS, a gate driving signal GDS, a control signal CS, a masking signal MS, and an emission control signal ECS based on the external control signal CTRL. The controller CP provides the image data IMD, the source driving signal SDS, and the control signal CS to the source driving block SDB. The controller CP provides the gate driving signal GDS and the masking signal MS to the gate driving block GDB, and provides the emission control signal ECS to the emission control block EDB.

[0065] The source driving block SDB converts the image data IMD to a data signal DS in response to the source driving signal SDS and the control signal CS, and outputs the data signal DS to a plurality of data lines DL1 to DLm (m is a natural number) described later. The data signal DS is an analog voltage corresponding to a gray scale value of the image data IMD.

[0066] The gate drive block GDB receives a gate drive signal GDS and a masking signal MS from the controller CP. The gate drive block GDB generates a gate output signal GOS based on the gate drive signal GDS. In addition, the gate drive block GDB masks the gate output signal GOS in response to the masking signal MS to generate and output scan signals SS1 to SSn (n is a natural number) to the plurality of scan lines SL1 to SLn.

[0067] The emission control block EDB receives an emission control signal ECS from the controller CP. The emission control block EDB outputs an emission signal to the emission lines EML1 to EMLn in response to the emission control signal ECS.

[0068] The voltage generator VGT generates a voltage required for operation of the display panel DP. In an embodiment of the present application, the voltage generator VGT generates a first drive voltage ELVDD, a second drive voltage ELVSS, and an initialization voltage VINT. In an embodiment of the present application, the voltage generator VGT can operate in response to control by the controller CP.

[0069] The display panel DP includes the scan lines SL1 to SLn, the data lines DL1 to DLm, the emission lines EML1 to EMLn, and the pixels PX. The scan lines SL1 to SLn extend from the gate drive block GDB in a first direction DR1 and are arranged in the second direction DR2 at intervals from each other. The data lines DL1 to DLm extend from the source drive block SDB in a direction opposite to the second direction DR2 and are arranged in the first direction DR1 at intervals from each other.

[0070] Each of the pixels PX is electrically connected to corresponding three of the scan lines SL1 to SLn. In addition, each of the pixels PX is electrically connected to corresponding one of the emission lines EML1 to EMLn and corresponding one of the data lines DL1 to DLm. In an embodiment, for example, as shown in FIG. 1, a first pixel among the pixels PX is connected to a first scan line SL1, a second scan line SL2, and a third scan line SL3, a first emission line EML1, and a first data line DL1. Figure 2

[0071] Each of the pixels PX includes an organic light emitting diode and a pixel circuit that controls emission of the organic light emitting diode. The pixel circuit includes a plurality of transistors and a capacitor. Each of the pixels PX receives the first drive voltage ELVDD, the second drive voltage ELVSS, and the initialization voltage VINT.

[0072] Referring to Figure 3 to Figure 4C , the controller CP includes a drive controller DCP, a region setting unit DAS, and a generator GP.

[0073] ​The driving controller DCP receives an image signal RGB and an external control signal CTRL from an external source. The driving controller DCP generates a gate driving signal GDS and a source driving signal SDS from the external control signal CTRL to control the gate driving block GDB and the source driving block SDB, respectively. The gate driving signal GDS for controlling the gate driving block GDB includes a vertical start signal and a scan clock signal. The source driving signal SDS for controlling the source driving block SDB includes a horizontal start signal and a data clock signal.

[0074] The driving controller DCP converts a data format of the image signal RGB into a data format suitable for an interface between the driving controller DCP and the source driving block SDB and generates image data IMD.

[0075] The driving controller DCP generates a low frequency control signal ICS based on the image data IMD to allow the display device DD (refer to FIG. 1) to operate in a normal mode NM in which the display device DD operates at a reference frequency RF (refer to FIG. 1) and in a low frequency mode LFM in which the display device DD operates at frequencies RF1 and RF2 (refer to FIG. 1) equal to or lower than the reference frequency RF. Figure 2 Figure 7A Figure 7B

[0076] The area setting unit DAS receives the image data IMD and the low frequency control signal ICS from the driving controller DCP. The area setting unit DAS can be turned on or off in response to the low frequency control signal ICS. In detail, the low frequency control signal ICS is deactivated in the normal mode NM and activated in the low frequency mode LFM. That is, the area setting unit DAS can be turned off in response to the low frequency control signal ICS being deactivated in the normal mode NM and turned on in response to the low frequency control signal ICS being activated in the low frequency mode LFM. In the low frequency mode LFM, the area setting unit DAS can divide the low frequency area LAR into a first area DA1 in which a first image IM1 is displayed at a first frequency RF1 lower than the reference frequency RF and a second area DA2 in which a second image IM2 is displayed at a second frequency RF2 lower than the first frequency RF1. In this case, the first frequency RF1 can be set to one of a plurality of frequencies in a frequency range in which deterioration of display quality due to flicker does not occur when the first image IM1 is displayed in the first area DA1. Also, the second frequency RF2 can be set to one of a plurality of frequencies in a frequency range in which deterioration of display quality due to flicker does not occur when the second image IM2 is displayed in the second area DA2. In this case, the first image IM1 and the second image IM2 can be displayed in the first area DA1 and the second area DA2, respectively, according to a display mode of the display device DD (refer to FIG. 1). Figure 2 ​​​) to change the frequencies (e.g., the reference frequency RF, the first frequency RF1, and the second frequency RF2) set in each region. In an embodiment of the present disclosure, when the transistors included in the pixels PX are provided through a low temperature poly-silicon ("LTPS") process, it is desirable to cause the image including the pattern having a high gray scale to operate at a relatively high frequency than the image including the pattern having a low gray scale, however, they should not be limited thereto or thereby. In another embodiment, as needed, it can be desirable to cause the image including the pattern having a low gray scale to operate at a relatively high frequency than the image including the pattern having a high gray scale.

[0077] The region setting unit DAS generates a control signal CS (refer to Figure 2 ) based on information about the first region DA1 and the second region DA2. In an embodiment of the present disclosure, the control signal CS includes a first control signal CS1 and a second control signal CS2. The first control signal CS1 is a signal to drive the first region DA1 at a first frequency RF1 lower than the reference frequency RF, and the second control signal CS2 is a signal to drive the second region DA2 at a second frequency RF2 lower than the first frequency RF1.

[0078] Figure 3 and Figure 4B The region setting unit DAS divides the display panel DP into the first region DA1 and the second region DA2 is shown, however, the present disclosure should not be limited thereto or thereby. In the low frequency mode LFM, the region setting unit DAS can divide the display panel DP into the first region DA1, the second region DA2, and a third region (not shown). In this case, the region setting unit DAS generates a third control signal to drive the third region at a third frequency lower than the second frequency RF2. When the display panel DP is divided into the first region, the second region, and the third region, two or more regions can be driven at the same frequency. In an embodiment, for example, the second region DA2 driven at the second frequency RF2 in the display panel DP can include two or more regions, and the two or more regions are spaced apart from each other in the first direction DR1 (see Figure 2 ) on the display panel DP. In an embodiment, for example, the first frequency RF1 can be about 1 hertz (Hz), and the second frequency RF2 can be an ultra-low frequency lower than about 1 Hz.

[0079] In Figure 3In the embodiment, the drive controller DCP and the region setting unit DAS are provided separately from each other, but they should not be limited thereto or thereby. In an embodiment, the region setting unit DAS can be included in the drive controller DCP. In this case, the drive controller DCP generates the low frequency control signal ICS, the first control signal CS1, and the second control signal CS2. The generator GP receives the first control signal CS1 and the second control signal CS2. The generator GP generates and outputs the masking signal MS based on the first control signal CS1 and the second control signal CS2. The masking signal MS is a signal that controls the frequency of the scan signals SS1 to SSn generated by the gate driving block GDB. The masking signal MS is applied to the masking unit MP in the gate driving block GDB. The masking signal MS is commonly applied to the masking circuits MC1 to MCn of the masking unit MP (refer to Figure 5 ).

[0080] The gate driving block GDB includes the gate driver GDP and the masking unit MP.

[0081] The gate driver GDP receives the gate driving signal GDS from the controller CP. The gate driver GDP generates and outputs the gate output signal GOS in response to the gate driving signal GDS.

[0082] The masking unit MP receives the masking signal MS from the controller CP, and receives the gate output signal GOS from the gate driver GDP. The masking unit MP masks the gate output signal GOS in response to the masking signal MS to generate and output the scan signals SS1 to SSn.

[0083] The source driving block SDB includes the power controller PCP and the source driver SDP.

[0084] The power controller PCP receives the first control signal CS1 and the second control signal CS2 from the region setting unit DAS. The power controller PCP generates and outputs the power control signal PCS in response to the first control signal CS1 and the second control signal CS2.

[0085] The source driver SDP receives the source driving signal SDS and the image data IMD from the driving controller DCP, and receives the power control signal PCS from the power controller PCP. The source driver SDP converts the image data IMD into the data signal DS in response to the power control signal PCS and the source driving signal SDS. The source driver SDP determines whether to apply the data signal DS to the display panel DP in response to the power control signal PCS. In detail, when the power control signal PCS is activated, the source driver SDP can not apply the data signal DS to the display panel DP for several frames. In addition, the power consumption of the display apparatus DD can be reduced by reducing the driving voltage or driving current to drive the source driver SDP while the data signal DS is not applied to the display panel DP.

[0086] Referring to Figure 1 , Figure 3 and Figure 4A , when the reference image IMR is displayed by the display panel DP, the reference region DAR through which the reference image IMR is displayed can be driven at a reference frequency RF (see Figure 7A ). When the entire display region DA is driven at the reference frequency RF, the display apparatus DD operates in a normal mode NM. In the normal mode NM, the driving controller DCP outputs the low frequency control signal ICS which is not activated.

[0087] Referring to Figure 1 , Figure 3 and Figure 4B , when the low frequency image IML is displayed by the display panel DP, the low frequency region LAR through which the low frequency image IML is displayed can be driven at a frequency lower than the reference frequency RF. The low frequency image IML can include a first image IM1 having a predetermined gray pattern and a second image IM2 not having the predetermined gray pattern. In an embodiment of the present application, the first image IM1 including the predetermined gray pattern can be an image desired to be driven at a high frequency so that the first image IM1 is displayed without flicker. The display apparatus DD can drive a first region DA1 through which the first image IM1 is displayed at a first frequency RF1 (see Figure 7B ), and can drive a second region DA2 through which the second image IM2 is displayed at a second frequency RF2 (see Figure 7B) the second region DA2 through which the second image IM2 is displayed. The second frequency RF2 can have a frequency lower than the first frequency RF1. The first image IM1 can be displayed without interruption or flicker even if the first region DA1 is driven at the first frequency RF1 lower than the reference frequency RF. The second image IM2 can be displayed without interruption or flicker even if the second region DA2 is driven at the second frequency RF2 lower than the first frequency RF1. The display device DD can operate in the low frequency mode LFM when at least one of the first region DA1 and the second region DA2 driven at the first frequency RF1 and the second frequency RF2 lower than the reference frequency RF is located in the display panel DP. In the low frequency mode LFM, the drive controller DCP outputs the activated low frequency control signal ICS.

[0088] Referring to Figure 1 , Figure 3 and Figure 4C , the display panel DP can include the first region DA1 and a plurality of second regions DA2. In an embodiment of the present application, the plurality of second regions DA2 can include two or more second regions DA2 spaced apart from each other in the second direction DR2 with the first region DA1 interposed therebetween in the display panel DP. However, the present application should not be limited to or by this. The first region DA1 can be provided as a plurality in the display panel DP. In an embodiment, the display panel DP can further include a third region through which a third image is displayed. The third region can be driven at a third frequency different from the first frequency RF1 and the second frequency RF2. In an embodiment of the present application, the third image can be displayed without interruption or flicker even if the third region is driven at a frequency lower than the second frequency RF2.

[0089] Figure 5 is a block diagram illustrating an embodiment of the gate driving block GDB in an embodiment of the present application, and Figure 6 is a circuit diagram illustrating an embodiment of the kth gate driving circuit and the kth masking circuit according to the present application. Figure 7A is a timing diagram illustrating an embodiment of the operation of the gate driving block GDB according to the present application, and Figure 7B is a timing diagram illustrating the output of a scan signal for the operation of the gate driving block GDB according to Figure 7A .

[0090] Referring to Figure 3 and Figure 5, the gate drive block GDB includes a gate driver GDP and a masking unit MP. The gate driver GDP includes shift registers in which stages GDC1 to GDCn are connected one after another. The gate driver GDP receives a gate drive signal GDS from the drive controller DCP. In an embodiment of the present application, the gate drive signal GDS includes a first clock signal CLK1, a second clock signal CLK2, and a vertical start signal FLM. The number of clock signals included in the gate drive signal GDS should not be limited to this or restricted thereby. Each of the stages GDC1 to GDCn also receives a first voltage VGL (refer to Figure 6 ) and a second voltage VGH (refer to Figure 6 ).

[0091] The stages GDC1 to GDCn in the present embodiment respectively output gate output signals GOS1 to GOSn. The masking unit MP includes masking circuits MC1 to MCn connected to the stages GDC1 to GDCn, respectively. The gate output signals GOS1 to GOSn respectively output from the stages GDC1 to GDCn are respectively supplied to the masking circuits MC1 to MCn. Hereinafter, for the convenience of description, the stages GDC1 to GDCn are also referred to as gate drive circuits GDC1 to GDCn.

[0092] The gate drive circuits GDC1 to GDCn are connected one after another, and each of the gate drive circuits GDC1 to GDCn receives a gate output signal output from a preceding gate drive circuit as a carry signal. Among the gate drive circuits GDC1 to GDCn, the first gate drive circuit GDC1 receives the vertical start signal FLM as the carry signal. A k-th gate output signal GOSk (k is a natural number smaller than n) output from a k-th gate drive circuit GDCk among the gate drive circuits GDC1 to GDCn is supplied as a carry signal of a (k+1)-th gate drive circuit GDCk+1.

[0093] Referring to Figure 5 , Figure 7A and Figure 7B , the masking circuits MC1 to MCn receive a masking signal MS from a generator GP (refer to Figure 3 ). The masking signal MS is commonly applied to the masking circuits MC1 to MCn. The masking circuits MC1 to MCn respectively receive the gate output signals GOS1 to GOSn from the gate driver GDP.

[0094] Among the masking circuits MC1 to MCn, a k-th masking circuit MCk receives a k-th gate output signal GOSk output from a k-th gate drive circuit GDCk and the masking signal MS from the controller CP. The k-th masking circuit MCk masks the k-th gate output signal GOSk in response to the masking signal MS and outputs a k-th scan signal SSk.

[0095] The masking signal MS controls the frequency of the scan signals SS1 to SSn generated by the gate driving block GDB. In detail, the masking unit MP masks the gate output signals GOS1 to GOSn output from the gate driver GDP in response to the masking signal MS to control the frequency of the scan signals SS1 to SSn. When the gate driver GDP outputs the gate output signals GOS1 to GOSn having the reference frequency RF, the masking unit MP masks the gate output signals GOS1 to GOSk corresponding to the first area DA1 of the display panel DP and outputs a first group of scan signals SSF1 including the scan signals SS1 to SSk having a first frequency RF1. In addition, the masking unit MP masks the gate output signals GOSk+1 to GOSn corresponding to the second area DA2 of the display panel DP and outputs a second group of scan signals SSF2 including the scan signals SSk+1 to SSn having a second frequency RF2. The masking signal MS includes a first masking interval MSW1 masking the gate output signals GOS1 to GOSk corresponding to the first area DA1 and a second masking interval MSW2 masking the gate output signals GOSk+1 to GOSn corresponding to the second area DA2.

[0096] Referring to Figure 6 , Figure 7A and Figure 7B , the kth gate driving circuit GDCk includes a first clock line CK1, a second clock line CK2, a kth carry line CRk, a first voltage line VL1, a second voltage line VL2, and a kth gate output line GOLk. The first clock line CK1 receives a first clock signal CLK1, and the second clock line CK2 receives a second clock signal CLK2. The kth carry line CRk receives a (k-1)th gate output signal GOSk-1. The first voltage line VL1 receives a first voltage VGL, and the second voltage line VL2 receives a second voltage VGH. The first clock signal CLK1 and the second clock signal CLK2 have the reference frequency RF and have phases opposite to each other.

[0097] For convenience of explanation, in the description with reference to Figure 6 , the kth carry line CRk is also referred to as a "carry line CRk", and the kth gate output line GOLk is also referred to as a "gate output line GOLk".

[0098] In the illustrated embodiment, the k-th gate drive circuit GDCk includes a first transistor Tl, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, and a first capacitor Cl and a second capacitor C2. In addition, the k-th masking circuit MCk includes a ninth transistor T9 and a tenth transistor TlO. In the illustrated embodiment, each of the first transistor Tl to the tenth transistor TlO will be described as a p-type transistor. However, the present application should not be limited to this or thereby restricted, and each of the first transistor Tl to the tenth transistor TlO can be realized as a p-type transistor or an n-type transistor. In another embodiment, some of the first transistor Tl to the tenth transistor TlO can be realized as a p-type transistor, while the others can be realized as an n-type transistor. In addition, the number of transistors included in the k-th gate drive circuit GDCk and the k-th masking circuit MCk should not be limited to this or thereby restricted. That is, at least one of the first transistor Tl to the tenth transistor TlO can be omitted, and in another embodiment, one or more transistors can be added.

[0099] The first transistor Tl includes a first electrode connected to the carry line CRk, a second electrode electrically connected to the first node Nl, and a gate electrode connected to the second clock line CK2. The first transistor Tl applies the (k-l)-th gate output signal GOSk-l provided through the carry line CRk to the first node Nl in response to the second clock signal CLK2.

[0100] The second transistor T2 includes a first electrode connected to the second voltage line VL2, a second electrode electrically connected to the first node Nl via the third transistor T3, and a gate electrode connected to the second node N2. The second transistor T2 applies the second voltage VGH to the first electrode of the third transistor T3 in accordance with the potential of the second node N2.

[0101] The third transistor T3 is connected between the second transistor T2 and the first node Nl. In particular, the third transistor T3 includes a first electrode connected to the second transistor T2, a second electrode electrically connected to the first node Nl, and a gate electrode connected to the first clock line CKl. The third transistor T3 applies the second voltage VGH provided through the second transistor T2 to the first node Nl in response to the first clock signal CLKl.

[0102] The fourth transistor T4 includes a first electrode connected to the second clock line CK2, a second electrode electrically connected to the second node N2, and a gate electrode electrically connected to the first node Nl. The fourth transistor T4 applies the second clock signal CLK2 to the second node N2 in accordance with the potential of the first node Nl.

[0103] The fifth transistor T5 includes a first electrode connected to the first voltage line VL1, a second electrode electrically connected to the second node N2, and a gate electrode connected to the second clock line CK2. The fifth transistor T5 discharges the electric potential of the second node N2 to the first voltage VGL in response to the second clock signal CLK2.

[0104] The sixth transistor T6 includes a first electrode connected to the second voltage line VL2, a second electrode connected to the gate output line GOLk, and a gate electrode electrically connected to the second node N2. The sixth transistor T6 applies the second voltage VGH to the gate output line GOLk in accordance with the electric potential of the second node N2.

[0105] The seventh transistor T7 includes a first electrode connected to the first clock line CK1, a second electrode connected to the gate output line GOLk, and a gate electrode electrically connected to the first node N1 via the eighth transistor T8. The seventh transistor T7 applies the first clock signal CLK1 to the gate output line GOLk in accordance with the output of the eighth transistor T8.

[0106] The eighth transistor T8 includes a first electrode electrically connected to the first node N1, a second electrode connected to the gate electrode of the seventh transistor T7, and a gate electrode connected to the first voltage line VL1. The eighth transistor T8 applies the signal of the first node N1 to the gate electrode of the seventh transistor T7 in response to the first voltage VGL.

[0107] One end of the first capacitor C1 is connected to the gate electrode of the seventh transistor T7, and the other end of the first capacitor C1 is connected to the gate output line GOLk. One end of the second capacitor C2 is connected to the second voltage line VL2, and the other end of the second capacitor C2 is electrically connected to the second node N2.

[0108] During the low period of the second clock signal CLK2, the first transistor T1 applies the (k-1)th gate output signal GOSk-1 provided thereto through the carry line CRk to the first node N1. The fourth transistor T4 connected to the first node N1 turns on in response to the (k-1)th gate output signal GOSk-1, and the second clock signal CLK2 is applied to the second node N2 through the turned-on fourth transistor T4. In addition, the (k-1)th gate output signal GOSk-1 applied to the first node N1 is applied to the gate electrode of the seventh transistor T7 through the eighth transistor T8 which turns on in response to the first voltage VGL. Accordingly, the seventh transistor T7 applies the first clock signal CLK1 in a low state to the gate output line GOLk in response to the (k-1)th gate output signal GOSk-1. Accordingly, the kth gate output signal GOSk is controlled to have an activation level. The first capacitor C1 is connected to the gate electrode of the seventh transistor T7 and the second electrode of the seventh transistor T7 to maintain the activation level of the kth gate output signal GOSk.

[0109] When the second clock signal CLK2 in a high state is applied to the second node N2 through the turned-on fourth transistor T4, the sixth transistor T6 remains in an off state. Then, when the second clock signal CLK2 transitions to a low state, the sixth transistor T6 turns on in response to the second clock signal CLK2 in a low state, and the second voltage VGH is applied to the gate output line GOLk through the turned-on sixth transistor T6. Accordingly, the kth gate output signal GOSk is controlled to have a deactivation level. The second capacitor C2 is connected to the gate electrode of the sixth transistor T6 and the first electrode of the sixth transistor T6 to maintain the deactivation level of the kth gate output signal GOSk.

[0110] Accordingly, the gate output signals GOS1 to GOSn have the same reference frequency RF as that of the first clock signal CLK1 and the second clock signal CLK2.

[0111] The second voltage VGH is applied to the gate output line GOLk connected to the second electrode of the sixth transistor T6 through the sixth transistor T6 which turns on in response to the potential of the second node N2. Accordingly, the kth gate output signal GOSk is controlled to have a deactivation level. The second capacitor C2 is connected to the gate electrode of the sixth transistor T6 and the first electrode of the sixth transistor T6 to maintain the deactivation level of the kth gate output signal GOSk.

[0112] The second transistor T2 connected to the second node N2 turns on in response to the second clock signal CLK2 being in the low state, and the second voltage VGH is applied to the third transistor T3 connected to the second electrode of the second transistor T2 through the turned-on second transistor T2. Then, the second voltage VGH is applied to the first node N1 through the third transistor T3 in response to the first clock signal CLK1 being in the low state. Thus, the kth gate output signal GOSk in the activation state becomes stable. The fifth transistor T5 applies the first voltage VGL to the second node N2 in response to the second clock signal CLK2. As a result, the kth gate output signal GOSk in the deactivation state becomes stable.

[0113] Referring to Figure 6 , Figure 7A and Figure 7B , the kth masking circuit MCk receives the second voltage VGH from the second voltage line VL2 and receives the kth gate output signal GOSk from the gate output line GOLk. The kth masking circuit MCk includes a masking line ML. The masking line ML receives a masking signal MS. The kth masking circuit MCk outputs the kth scan signal SSk to the kth scan line SLk. For the convenience of explanation, the kth scan line SLk will also be referred to as a "scan line SLk" in the description with reference to Figure 6 .

[0114] In the illustrated embodiment, the ninth transistor T9 includes a first electrode connected to the second voltage line VL2, a second electrode connected to the scan line SLk, and a gate electrode electrically connected to the second node N2. The ninth transistor T9 applies the second voltage VGH to the scan line SLk according to the potential of the second node N2.

[0115] The tenth transistor T10 includes a first electrode connected to the masking line ML, a second electrode connected to the scan line SLk, and a gate electrode connected to the gate output line GOLk. The tenth transistor T10 turns on in response to the gate output signal GOSk and applies the masking signal MS to the scan line SLk.

[0116] When the ninth transistor T9 is turned on according to the electric potential of the second node N2, the second voltage VGH is applied to the scan line SLk through the turned-on ninth transistor T9. Accordingly, the kth scan signal SSk is controlled to have the deactivation level. That is, the ninth transistor T9 and the sixth transistor T6 are substantially simultaneously turned on, and thus, the kth gate output signal GOSk and the kth scan signal SSk are substantially simultaneously deactivated. The tenth transistor T10 is turned on in response to the activated kth gate output signal GOSk. In this case, the masking signal MS is applied to the scan line SLk connected to the second electrode of the tenth transistor T10. The masking signal MS includes a masking interval in which the masking signals GOS1 to GOSn are masked and a non-masking interval in which the masking signals GOS1 to GOSn are not masked. In the masking interval of the masking signal MS applied to the scan line SLk, the kth scan signal SSk is controlled to have the deactivation level. In the non-masking interval of the masking signal MS applied to the scan line SLk, the kth scan signal SSk is controlled to have the activation level. The kth scan signal SSk has substantially the same frequency as that of the non-masking interval of the masking signal MS.

[0117] Although the kth scan signal SSk is controlled to have the deactivation level by the masking signal MS, the kth gate output signal GOSk output from the kth gate driver circuit GDCk is provided as a carry signal of the (k+1)th gate driver circuit GDCk+1. In the low frequency mode LFM (refer to Figure 4B ), the gate output signals GOS1 to GOSn have the reference frequency RF substantially the same as that of the first clock signal CLK1 and the second clock signal CLK2. Even though the gate output signals GOS1 to GOSn have the reference frequency RF in the low frequency mode LFM, the scan signals SS1 to SSn can have the first frequency RF1 or the second frequency RF2 lower than the reference frequency RF.

[0118] Referring to Figure 5 , Figure 7A and Figure 7B , the gate output signals GOS1 to GOSn are signals having the reference frequency RF and output from the gate driver GDP.

[0119] The masking unit MP masks the gate output signals GOS1 to GOSn using the masking signal MS, and outputs the scan signals SS1 to SSn having a frequency lower than the reference frequency RF. The interval in which the masking signal MS has a low level corresponds to the non-masking interval in which the gate output signals GOS1 to GOSn are not masked. The interval in which the masking signal MS has a high level corresponds to the masking interval in which the gate output signals GOS1 to GOSn are masked. As Figure 7AAs shown in FIG. 6, the masking signal MS includes a first non-masking interval NMW1 in which the gate output signals GOS1 to GOSk corresponding to the first area DA1 of the display panel DP are not masked, a first masking interval MSW1 in which the gate output signals GOS1 to GOSk corresponding to the first area DA1 of the display panel DP are masked, a second non-masking interval NMW2 in which the gate output signals GOSk+1 to GOSn corresponding to the second area DA2 of the display panel DP are not masked, and a second masking interval MSW2 in which the gate output signals GOSk+1 to GOSn corresponding to the second area DA2 of the display panel DP are masked. In this case, the masking unit MP masks the gate output signals GOS1 to GOSk corresponding to the first area DA1 during the first masking interval MSW1, and outputs a first group of scan signals SSF1 including the scan signals SS1 to SSk having the first frequency RF1. In addition, the masking unit MP masks the gate output signals GOSk+1 to GOSn corresponding to the second area DA2 during the second masking interval MSW2, and outputs a second group of scan signals SSF2 including the scan signals SSk+1 to SSn having the second frequency RF2.

[0120] However, the present application should not be limited thereto or thereby, and the masking signal MS can further include a third non-masking interval in which the gate output signals corresponding to the third area are not masked, and a third masking interval in which the gate output signals corresponding to the third area are masked. In addition, when the display device DD (refer to Figure 1 ) operates in the low frequency mode LFM, the gate driver GDP outputs the gate output signals GOS1 to GOSn having the first frequency RF1. In this case, the gate output signals GOS1 to GOSk corresponding to the first area DA1 of the display panel DP need not be masked by the masking signal MS. Accordingly, the masking signal MS can include only the first and second non-masking intervals NMW1 and NMW2, and the second masking interval MSW2 in which the gate output signals GOSk+1 to GOSn corresponding to the second area DA2 of the display panel DP are masked.

[0121] Figure 8 is a timing diagram illustrating an embodiment of the operation of the source driving block according to the present application.

[0122] Referring to Figure 3 , Figure 4A , Figure 4B and Figure 8, the source driver SDP converts the image data IMD into a data signal DS in response to the power control signal PCS and the source driving signal SDS. The source driver SDP can not apply the data signal DS to the display panel DP in response to the power control signal PCS. In detail, the source driver SDP can not apply the data signal DS to the display panel DP in a high level period of the power control signal PCS, and can apply the data signal DS to the display panel DP in a low level period of the power control signal PCS.

[0123] In the normal mode NM, the power control signal PCS is maintained at a low level. In the low frequency mode LFM, the power control signal PCS includes a low level period and a high level period generated at a predetermined frequency. In the low frequency mode LFM, the power control signal PCS includes a first low level period LP1 generated at a first frequency RF1 and a second low level period LP2 generated at a second frequency RF2. The source driver SDP outputs a first data signal DS1 corresponding to a first area DA1 of the display panel DP during the first low level period LP1 of the power control signal PCS, and outputs a second data signal DS2 corresponding to a second area DA2 of the display panel DP during the second low level period LP2 of the power control signal PCS. Accordingly, the first data signal DS1 is output at the first frequency RF1 through the first low level period LP1 generated at the first frequency RF1, and the second data signal DS2 is output at the second frequency RF2 through the second low level period LP2 generated at the second frequency RF2.

[0124] As shown in Figure 8 , the source driver SDP outputs the first data signal DS1 to the first area DA1 at the first frequency RF1 in response to the power control signal PCS. The source driver SDP outputs the second data signal DS2 to the second area DA2 at the second frequency RF2 in response to the power control signal PCS. The source driver SDP applies the data signal DS to the first area DA1 of the display panel DP at the first frequency RF1 lower than the reference frequency RF, and applies the data signal DS to the second area DA2 of the display panel DP at the second frequency RF2 lower than the reference frequency RF. When the display device DD operates in the low frequency mode LFM, the low frequency area LAR includes the first area DA1 and the second area DA2. In this case, when the first data signal DS1 is applied to the first area DA1 of the display panel DP at the first frequency RF1, and the second data signal DS2 is applied to the second area DA2 of the display panel DP at the second frequency RF2, the power consumption of the display device DD can be reduced when compared to a case in which only the first data signal DS1 is applied to the low frequency area LAR of the display panel DP at the first frequency RF1.

[0125] In detail, referring to Figure 4A、 Figure 4B 、 Figure 5 、 Figure 7A 、 Figure 7B and Figure 8 In the low frequency mode LFM, the display apparatus DD outputs the first set of scan signals SSF1 and the second set of scan signals SSF2 to the first area DA1 and the second area DA2 displaying the first image IM1 and the second image IM2, respectively, through the gate driving block GDB. Accordingly, the first image IM1 and the second image IM2 displayed in the display panel DP are displayed without interruption or flickering. In this case, the display apparatus DD applies the first data signal DS1 and the second data signal DS2 to the first area DA1 and the second area DA2 of the display panel DP, respectively, using the source driving block SDB at the first frequency RF1 and the second frequency RF2 of the first set of scan signals SSF1 and the second set of scan signals SSF2. Accordingly, the source driving block SDB can apply the first data signal DS1 and the second data signal DS2 to the display panel DP at the first frequency RF1 lower than the reference frequency RF and at the second frequency RF2 lower than the first frequency RF1, respectively. Accordingly, in the low frequency mode LFM, power consumed for converting and outputting the data signal DS can be reduced compared to when the display apparatus DD applies the reference data signal DSR (refer to Figure 13 ) to the display panel DP at the reference frequency RF or applies only the first data signal DS1 to the display panel DP at the first frequency RF1.

[0126] The source driving block SDB should not be limited to or by this. Although the second area DA2 of the display panel DP includes two or more areas spaced apart from each other in the second direction DR2 in the display panel DP, the second data signal DS2 can be applied to each area at the second frequency RF2. In addition, when the display panel DP further includes a third area driven at a third frequency lower than the second frequency RF2, a third data signal can be output to the third area at the third frequency.

[0127] Figure 9 FIG. 1 is a block diagram illustrating an embodiment of a display apparatus according to the present application. Figure 10A and Figure 10B are plan views illustrating embodiments of a display panel according to the present application.

[0128] Referring to Figure 9 、 Figure 10A and Figure 10B , the controller CP includes a driving controller DCP, an area setting unit DAS, and a generator GP.

[0129] The drive controller DCP receives the image signal RGB and the external control signal CTRL. The drive controller DCP generates the gate drive signal GDS and the source drive signal SDS from the external control signal CTRL to control the gate drive block GDB and the source drive block SDB, respectively. The display device in the illustrated embodiment of the present application can operate in a normal mode NM (refer to Figure 4A ) in which the entire area of the display panel is operated at one frequency and in a multi-frequency drive mode MFD in which the display panel includes a plurality of areas operated at different frequencies from each other. The drive controller DCP generates a multi-frequency drive signal MFS in the multi-frequency drive mode MFD. That is, the multi-frequency drive signal MFS is deactivated in the normal mode NM and activated in the multi-frequency drive mode MFD.

[0130] The area setting unit DAS receives the image data IMD and the multi-frequency drive signal MFS from the drive controller DCP. The area setting unit DAS is turned off in the normal mode NM in response to the deactivated multi-frequency drive signal MFS and turned on in the multi-frequency drive mode MFD in response to the activated multi-frequency drive signal MFS. In the multi-frequency drive mode MFD, the area setting unit DAS can divide the display panel DP into a reference area DAR and a low-frequency area LAR based on the image data IMD. The reference area DAR is an area in which a reference image IMR is displayed at a reference frequency RF (refer to Figure 12B ) and the low-frequency area LAR is an area in which a low-frequency image IML is displayed at a frequency lower than the reference frequency RF. In the embodiment of the present application, the low-frequency area LAR includes a first area DA1 and a second area DA2. The first area DA1 is an area in which a first image IM1 is driven at a first frequency RF1 (see Figure 12B ) lower than the reference frequency RF and the second area DA2 is an area in which a second image IM2 is driven at a second frequency RF2 (refer to Figure 12B ) lower than the first frequency RF1. In this case, the reference frequency RF is about 1 Hz, the first frequency RF1 is a super low frequency lower than about 1 Hz, and the second frequency RF2 is a super low frequency lower than the first frequency RF1.

[0131] The area setting unit DAS generates and outputs a control signal CS (refer to Figure 2 ) in response to the multi-frequency drive signal MFS. The control signal CS includes a reference control signal CSR, a first control signal CS1, and a second control signal CS2. The reference control signal CSR is a signal to drive the reference area DAR at the reference frequency RF, the first control signal CS1 is a signal to drive the first area DA1 at the first frequency RF1, and the second control signal CS2 is a signal to drive the second area DA2 at the second frequency RF2.

[0132] InFigure 9 In the middle, the drive controller DCP and the region setting unit DAS are shown as separate components, however, they should not be limited thereto or thereby. The region setting unit DAS can be included in the drive controller DCP. In this case, the control signal CS can be output from the drive controller DCP.

[0133] The generator GP receives the reference control signal CSR, the first control signal CS1, and the second control signal CS2. The generator GP generates the mask signal MS based on the reference control signal CSR, the first control signal CS1, and the second control signal CS2. The mask signal MS is a signal that controls the frequency of the scan signals SS1 to SSn generated by the gate driving block GDB. The mask signal MS is applied to the mask unit MP of the gate driving block GDB. The mask signal MS is commonly applied to the mask circuits MC1 to MCn of the mask unit MP (refer to Figure 11 ).

[0134] Referring to Figure 9 , the source driving block SDB includes the power controller PCP and the source driver SDP.

[0135] The power controller PCP receives the reference control signal CSR, the first control signal CS1, and the second control signal CS2 from the controller CP. The power controller PCP generates the power control signal PCS based on the reference control signal CSR, the first control signal CS1, and the second control signal CS2.

[0136] Referring to Figure 10A and Figure 10BWhen the reference image IMR and the low-frequency image IML are displayed through the display panel DP, a low-frequency region LAR displaying the low-frequency image IML can be driven at a frequency lower than the reference frequency RF. The low-frequency image IML can include a first image IM1 including a predetermined gray pattern and a second image IM2 not including the predetermined gray pattern. The display apparatus DD can drive the reference region DAR displaying the reference image IMR at the reference frequency RF, can drive the first region DA1 displaying the first image IM1 at a first frequency RF1, and can drive the second region DA2 displaying the second image IM2 at a second frequency RF2. The first frequency RF1 can have a frequency lower than the reference frequency RF, and the second frequency RF2 can have a frequency lower than the first frequency RF1. The reference image IMR can be an image that is displayed without interruption or flicker even if the reference region DAR is driven at the reference frequency RF. The first image IM1 can be an image that is displayed without interruption or flicker even if the first region DA1 is driven at the first frequency RF1 lower than the reference frequency RF. The second image IM2 can be an image that is displayed without interruption or flicker even if the second region DA2 is driven at the second frequency RF2 lower than the first frequency RF1. The display apparatus DD can operate in a multi-frequency driving mode MFD when the reference region DAR driven at the reference frequency RF and at least one of the first region DA1 and the second region DA2 driven at the first frequency RF1 and the second frequency RF2 lower than the reference frequency RF are located in the display panel DP. In the multi-frequency driving mode MFD, the driving controller DCP can generate a multi-frequency driving signal MFS that is activated.

[0137] Referring to Figure 10B , the display panel DP can include the reference region DAR, the first region DA1, and a plurality of second regions DA2. In an embodiment of the present application, the second regions DA2 include two or more regions spaced apart from each other in the second direction DR2 with the first region DA1 interposed therebetween in the display panel DP. However, the present application should not be limited thereto or thereby, and the display panel DP can include a plurality of reference regions DAR or a plurality of first regions DA1. In an embodiment, the display panel DP can further include a third region displaying a third image. The third region can be driven at a third frequency different from the reference frequency RF, the first frequency RF1, and the second frequency RF2. In an embodiment of the present application, the third image can be an image that is displayed without interruption or flicker even if the third region is driven at a frequency lower than the second frequency RF2.

[0138] Figure 11 is a block diagram illustrating an embodiment of a gate driving block GDB in an embodiment of the present application, and Figure 12A is a timing chart illustrating an embodiment of an operation of a gate driving block GDB according to the present application. Figure 12B is a timing chart illustrating an embodiment of an operation of a gate driving block GDB according to the present application.Figure 12A a timing chart of an embodiment of an output of a scan signal of an operation of a gate driving block.

[0139] Referring to Figure 11 , Figure 12A and Figure 12B , the gate driving block GDB includes the gate driver GDP and the masking unit MP. Since the plurality of stages GDC1 to GDCn of the gate driver GDP and the masking circuits MC1 to MCn of the masking unit MP shown in Figure 11 have substantially the same configuration as the stages GDC1 to GDCn of the gate driver GDP and the masking circuits MC1 to MCn of the masking unit MP shown in Figure 5 , the same reference numerals are used to indicate the same components, and details regarding the same components are omitted. Hereinafter, for the convenience of description, the stages GDC1 to GDCn are also referred to as gate driving circuits GDC1 to GDCn.

[0140] The masking signal MS is a signal that controls the frequencies of the scan signals SS1 to SSn generated by the gate driving block GDB. When the gate driver GDP outputs the gate output signals GOS1 to GOSn having the reference frequency RF, the masking unit MP does not mask the gate output signals GOS1 to GOSi corresponding to the reference region DAR of the display panel DP, and outputs the reference group scan signals SSFR including the scan signals SS1 to SSi having the reference frequency RF. In addition, the masking unit MP masks the gate output signals GOSi+1 to GOSk corresponding to the first region DA1 of the display panel DP, and outputs the first group scan signals SSF1 including the scan signals SSi+1 to SSk having the first frequency RF1. The masking unit MP masks the gate output signals GOSk+1 to GOSn corresponding to the second region DA2 of the display panel DP, and outputs the second group scan signals SSF2 including the scan signals SSk+1 to SSn having the second frequency RF2. The masking signal MS includes a first masking interval MSW1 that masks the gate output signals GOSi+1 to GOSk corresponding to the first region DA1 and a second masking interval MSW2 that masks the gate output signals GOSk+1 to GOSn corresponding to the second region DA2.

[0141] Referring to Figure 12A and Figure 12B , the gate output signals GOS1 to GOSn are signals having the reference frequency RF and output from the gate driver GDP.

[0142] The masking signal MS includes the masked intervals that mask the gate output signals GOS1 to GOSn, and the unmasked intervals that do not mask the gate output signals GOS1 to GOSn. The intervals where the masking signal MS is low are also referred to as the unmasked intervals where the gate output signals GOS1 to GOSn are not masked. The intervals where the masking signal MS is high are also referred to as the masked intervals where the gate output signals GOS1 to GOSn are masked. Figure 12A As shown, the masking signal MS includes a first unmasked interval NMW1 where the gate output signals GOS1 to GOSi corresponding to the reference region DAR of the display panel DP are not masked; a second unmasked interval NMW2 where the gate output signals GOSi+1 to GOSk corresponding to the first region DA1 of the display panel DP are not masked; a first masked interval MSW1 where the gate output signals GOSi+1 to GOSk corresponding to the first region DA1 of the display panel DP are masked; and a third unmasked interval NMW3 where the gate output signals GOSk+1 to GOSn corresponding to the second region DA2 of the display panel DP are not masked; and a second masked interval MSW2 where the gate output signals GOSk+1 to GOSn corresponding to the second region DA2 of the display panel DP are masked. In this case, the masking unit MP does not mask the gate output signals GOS1 to GOSi (i is a natural number less than k) corresponding to the reference region DAR in the first unmasked interval NMW1, and therefore, the masking unit MP outputs a reference group scan signal SSFR including scan signals SS1 to SSi with a reference frequency RF. The masking unit MP masks the gate output signals GOSi+1 to GOSk corresponding to the first region DA1 in the first masking interval MSW1. Therefore, the masking unit MP outputs a first set of scan signals SSF1, which includes scan signals SSi+1 to SSk with a first frequency RF1. Additionally, the masking unit MP masks the gate output signals GOSk+1 to GOSn corresponding to the second region DA2 in the second masking interval MSW2. Therefore, the masking unit MP outputs a second set of scan signals SSF2, which includes scan signals SSk+1 to SSn with a second frequency RF2.

[0143] However, the present invention should not be limited thereto or thereby restricted. The masking signal MS may further include a fourth unmasked region in which the gate output signal corresponding to the third region is not masked, and a third masked region in which the gate output signal corresponding to the third region is masked.

[0144] Figure 13 This is a timing diagram illustrating an embodiment of the operation of the source drive block according to the present invention.

[0145] Reference Figure 9 , Figure 10A , Figure 10B and Figure 13The source driver SDP can convert the image data IMD into the data signal DS in response to the power control signal PCS and the source driving signal SDS. The source driver SDP can not apply the data signal DS to the display panel DP according to the power control signal PCS. In detail, the source driver SDP can not apply the data signal DS to the display panel DP in a high level period of the power control signal PCS, and can apply the data signal DS to the display panel DP in a low level period of the power control signal PCS.

[0146] In the normal mode NM, the power control signal PCS is maintained at a low level. In the multi-frequency driving mode MFD, the power control signal PCS includes low level periods and high level periods generated at a predetermined frequency. In the multi-frequency driving mode MFD, the power control signal PCS includes a first low level period LP1 generated at a reference frequency RF, a second low level period LP2 generated at a first frequency RF1, and a third low level period LP3 generated at a second frequency RF2. The source driver SDP outputs a reference data signal DSR corresponding to a reference area DAR of the display panel DP during the first low level period LP1 of the power control signal PCS, outputs a first data signal DS1 corresponding to a first area DA1 of the display panel DP during the second low level period LP2 of the power control signal PCS, and outputs a second data signal DS2 corresponding to a second area DA2 of the display panel DP during the third low level period LP3 of the power control signal PCS. Accordingly, the reference data signal DSR is output at the reference frequency RF through the first low level period LP1 generated at the reference frequency RF, the first data signal DS1 is output at the first frequency RF1 through the second low level period LP2 generated at the first frequency RF1, and the second data signal DS2 is output at the second frequency RF2 through the third low level period LP3 generated at the second frequency RF2.

[0147] The source driver SDP outputs a reference data signal DSR to the reference area DAR at a reference frequency RF in response to the power control signal PCS, and outputs a first data signal DS1 to the first area DA1 at a first frequency RF1. In addition, the source driver SDP outputs a second data signal DS2 to the second area DA2 at a second frequency RF2 in response to the power control signal PCS. The source driver SDP applies the first data signal DS1 to the first area DA1 of the display panel DP at the first frequency RF1 which is lower than the reference frequency RF, and applies the second data signal DS2 to the second area DA2 of the display panel DP at the second frequency RF2 which is lower than the first frequency RF1. When the display device DD operates in the multi-frequency driving mode MFD, the display area DA includes the reference area DAR and the low frequency area LAR. The low frequency area LAR includes the first area DA1 and the second area DA2. In this case, when compared to a case where only the first data signal DS1 is applied to the low frequency area LAR of the display panel DP at the first frequency RF1, the power consumption of the display device DD can be reduced when the first data signal DS1 is applied to the first area DA1 at the first frequency RF1 and the second data signal DS2 is applied to the second area DA2 at the second frequency RF2.

[0148] While embodiments of the present application have been described, it is to be understood that the application is not to be limited to those embodiments. Various modifications can be made by those skilled in the art without departing from the spirit and scope of the application as claimed hereinafter.

[0149] Accordingly, the disclosed subject matter is not to be limited to any single embodiment described herein and one skilled in the art will recognize that many modifications and variations are possible without departing from the spirit and scope of the present application as set forth in the following claims.

Claims

1. A display apparatus comprising: a display panel displaying an image; a gate driver block outputting a scan signal to the display panel; a source driver block having a normal mode operating at a reference frequency and a low frequency mode operating at a frequency lower than the reference frequency, and outputting a data signal to the display panel; and a controller receiving an image signal and an external control signal, and generating a gate driving signal, a source driving signal, and image data in response to the image signal and the external control signal, wherein the controller divides the display panel into a reference area operating at the reference frequency and a low frequency area operating at a frequency lower than the reference frequency according to the image data in the low frequency mode, and divides the display panel into a first area operating at a first frequency lower than the reference frequency and a second area operating at a second frequency lower than the first frequency when an image displayed in the low frequency area includes a predetermined pattern, wherein the first area is an area having the predetermined pattern in the low frequency area, and the second area is an area not having the predetermined pattern in the low frequency area, each of the first area and the second area operates at the reference frequency in the normal mode, the source driver block outputs the data signal to the first area at the first frequency and outputs the data signal to the second area at the second frequency in the low frequency mode, the gate driver block outputs a first scan signal to the first area at the first frequency and outputs a second scan signal to the second area at the second frequency in the low frequency mode, wherein the controller comprises: a driving controller outputting a low frequency control signal in response to the image data according to the normal mode operating at the reference frequency and the low frequency mode operating at at least one of the first frequency and the second frequency lower than the reference frequency; an area setting unit dividing the display panel into the first area and the second area in response to the low frequency control signal and the image data, and outputting a first control signal for driving the first area at the first frequency and a second control signal for driving the second area at the second frequency; and a generator generating a masking signal in response to the first control signal and the second control signal, and the controller applies the gate driving signal and the masking signal to the gate driver block. the gate driver block comprises:

2. The display device of claim 1, wherein, a gate driver generating a gate output signal in response to the gate driving signal; and a masking unit masking the gate output signal in response to the masking signal to output the scan signal. ​ 3. The display device of claim 2, wherein, The gate driver outputs the gate output signal at the reference frequency, the masking unit masks the gate output signal corresponding to the first area to output the first scan signal at the first frequency, and masks the gate output signal corresponding to the second area to output the second scan signal at the second frequency, and the masking signal includes: a first masking interval in which the gate output signal corresponding to the first area is masked; and a second masking interval in which the gate output signal corresponding to the second area is masked.

4. The display device of claim 2, wherein, The gate driver outputs the gate output signal at the first frequency in the low frequency mode, the masking unit does not mask the gate output signal corresponding to the first area to output the first scan signal at the first frequency, and masks the gate output signal corresponding to the second area to output the second scan signal at the second frequency, and the masking signal includes a second masking interval in which the gate output signal corresponding to the second area is masked.

5. The display device of claim 1, wherein, The controller applies the image data, the source driving signal, and the first and second control signals to the source driving block, and the source driving block includes: a power controller that generates a power control signal in response to the first and second control signals; and a source driver that converts the image data into the data signal in response to the power control signal and the source driving signal.

6. The display device of claim 1, wherein, The first frequency is equal to or lower than 1 Hz.

7. The display device of claim 1, wherein, The second area includes at least two areas.

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