Memory device and method of operating the same

Abstract

The present technology includes a memory device and an operation method thereof. The memory device includes: a memory block including a plurality of pages; a voltage generator configured to generate a programming voltage or a verification voltage applied to a selected page among the plurality of pages; a page buffer connected to the selected page through a bit line and configured to perform a pre-charge operation, an evaluation operation, and a sensing operation on the bit line during a verification operation; and a control circuit configured to store a page address of a slow page and adjust an evaluation time of the evaluation operation according to the page address, a programming operation speed of each slow page being slower than an average programming speed of the plurality of pages.

Description

Technical Field

[0001] The present disclosure relates to a memory device and an operation method thereof, and more particularly, to a memory device capable of performing a programming operation and an operation method thereof. Background Art

[0002] A memory device may include a volatile memory device in which data stored is lost when power is cut off, and a non-volatile memory device in which stored data is retained even when power is cut off.

[0003] The volatile memory device may include a dynamic random access memory (DRAM) and a static random access memory (SRAM). The non-volatile memory device may include a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electric EPROM (EEPROM), a NAND flash memory, and the like.

[0004] A memory device may include a memory cell array, a group of circuits collectively referred to as a peripheral circuit, and a logic circuit.

[0005] The memory cell array may include a plurality of memory cells storing data. In terms of storage capacity, the memory cell array may be configured by any one of various types of memory cells. A single-level cell (SLC) is capable of storing one bit of data, a multi-level cell (MLC) is capable of storing two bits of data, a triple-level cell (TLC) is capable of storing three bits of data, and a quad-level cell (QLC) is capable of storing four bits of data. Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory device and a method of operating the memory device that can improve the reliability of the memory device by adjusting a programming operation in consideration of characteristics of slow cells and fast cells.

[0007] A memory device according to an embodiment of the present disclosure includes: a memory block including a plurality of pages; a voltage generator configured to generate a programming voltage or a verification voltage applied to a selected page among the plurality of pages; a page buffer connected to the selected page through a bit line and configured to perform a precharge operation, an evaluation operation, and a sensing operation on the bit line during a verification operation; and a control circuit configured to store a page address of a slow page and adjust an evaluation time of the evaluation operation according to the page address, wherein a programming operation speed of each slow page is slower than an average programming speed of the plurality of pages.

[0008] A method of operating a memory device according to an embodiment of the present disclosure includes the steps of: classifying each of a plurality of pages as a fast page or a slow page according to a programming operation speed; and when a selected page is a fast page, performing a verification operation of the programming operation so that an evaluation operation is performed during a first evaluation time, and when the selected page is a slow page, performing the verification operation so that the evaluation operation is performed during a second evaluation time shorter than the first evaluation time, wherein when the verification operation has passed, the programming operation ends, and when the verification operation fails, the classification and execution are repeated until the verification operation passes.

[0009] A method of operating a memory device according to an embodiment of the present disclosure includes the steps of: classifying each of a plurality of pages as a fast page or a slow page according to a programming operation speed; and when a selected page is a fast page, performing a verification operation of the programming operation so that an evaluation operation is performed during a first evaluation time; and when the selected page is a slow page, performing the verification operation so that the evaluation operation is performed based on the first evaluation time, and when a reference time point is reached during the programming operation of the slow page, performing the verification operation so that the evaluation operation is performed during a second evaluation time shorter than the first evaluation time, wherein when the verification operation has passed, the programming operation ends, and when the verification operation fails, the classification and execution are repeated until the verification operation passes.

[0010] A memory device according to an embodiment of the present disclosure includes: a memory cell array including a plurality of pages; and a control circuit configured to perform a programming operation on a target page among the plurality of pages, determine whether the target page is a slow page or a fast page based on a result of the programming operation, and perform a verification operation of the programming operation based on the determination result, wherein the verification operation includes: an evaluation operation performed according to a first evaluation time when the target page is a slow page; and an evaluation operation performed according to a second evaluation time shorter than the first evaluation time when the target page is a fast page.

[0011] By controlling the programming operation by considering the characteristics of slow cells and fast cells, the present technology can improve the reliability of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram illustrating a memory cell array and a page buffer group.

[0015] Figure 4 is a diagram illustrating a memory block.

[0016] Figure 5 is a diagram illustrating the change in the threshold voltage of a memory cell according to a programming voltage.

[0017] Figure 6 is a diagram illustrating the change in the threshold voltage of slow cells and fast cells according to the same programming voltage.

[0018] Figure 7 is a diagram illustrating a method of classifying each page of a memory block as a slow page or a fast page.

[0019] Figure 8 is a diagram illustrating a control circuit according to an embodiment of the present disclosure.

[0020] Figure 9 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0021] Figure 10 is a flowchart illustrating a programming operation according to an embodiment of the present disclosure.

[0022] Figure 11 is an illustration of, for example Figure 10 a flowchart of another embodiment of a slow page programming operation such as

[0023] Figure 12 is a diagram illustrating an operation sequence of a page buffer during a verification operation.

[0024] Figure 13 is a diagram illustrating an evaluation operation during a verification operation.

[0025] Figure 14 is a diagram illustrating a programming operation of slow cells and fast cells according to an embodiment of the present disclosure.

[0026] Figure 15 is a diagram illustrating a method of classifying pages of a memory block as part of a slow group or part of a fast group.

[0027] Figure 16 is a diagram illustrating a control circuit according to an embodiment of the present disclosure.

[0028] Figure 17 is a diagram illustrating an embodiment of adjusting the time for performing an evaluation operation according to the number of programming pulses.

[0029] Figure 18 is a diagram illustrating an embodiment of controlling the time for performing an evaluation operation according to the threshold voltage of a memory cell.

[0030] Figure 19 is a diagram illustrating a memory system according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Throughout the specification, references to "an embodiment", "another embodiment", etc. are not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment.

[0032] Figure 1 FIG. is an illustration of a memory system 1000 according to an embodiment of the present disclosure.

[0033] Referring Figure 1 , the memory system 1000 may include a storage for storing data and a controller 1200 for controlling the storage.

[0034] The storage may include a plurality of memory devices 1100 that communicate with the controller 1200 through a plurality of channels, respectively.

[0035] The controller 1200 may send a command CMD and data DATA to one or more memory devices 1100 through the (multiple) channels, and may also send an address. For example, the controller 1200 may send a command CMD to one or more memory devices 1100 according to a request RQ from the host 2000. In addition, the controller 1200 may even perform a background operation for improving the performance of the memory system 1000 without a request from the host 2000. The host 2000 may generate requests for various operations and may output the generated requests to the memory system 1000. For example, the host 2000 may send a request instructing the memory system 1000 to perform a programming operation, a read operation, an erase operation, etc. When the host 2000 outputs the data DATA to be programmed together with a request RQ for a programming operation, the controller 1200 may send the data DATA to be used in the programming operation together with the command CMD to the memory device 1100.

[0036] The host 2000 may communicate with the memory system 1000 through any one of various interfaces such as: Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0037] Figure 2 FIG. is an illustration of a memory device 1100 according to an embodiment of the present disclosure.

[0038] Referring Figure 2, the memory device 1100 may include: a memory cell array 110 for storing data; a peripheral circuit including components 120, 130, 140, 150, and 160 for performing programming operations, read operations, or erase operations; and a control circuit 170 for controlling the peripheral circuit.

[0039] The memory cell array 110 may include a plurality of memory blocks for storing data.

[0040] The peripheral circuit may include a voltage generator 120, a row decoder 130, a page buffer bank 140, a column decoder 150, and an input and output (I / O) circuit 160.

[0041] The voltage generator 120 may generate and output an operation voltage Vop for various operations in response to an operation code OPc. For example, the voltage generator 120 may generate and output a programming voltage, a verification voltage, a read voltage, a pass voltage, and an erase voltage, change the level of the operation voltage Vop according to the operation code OPc, and change the time of outputting the operation voltage Vop. For example, during a programming operation, the voltage generator 120 may output an operation voltage Vop including a programming voltage and a verification voltage.

[0042] The row decoder 130 may select one of the memory blocks in the memory cell array 110 according to a row address ADDR, and may send the operation voltage Vop to the selected memory block.

[0043] The page buffer bank 140 may be connected to the memory cell array 110 through bit lines. For example, the page buffer bank 140 may include a plurality of page buffers respectively connected to a plurality of bit lines. The plurality of page buffers may operate simultaneously in response to a page buffer control signal PBSIG, and may temporarily store data during a programming operation or a read operation. During a verification operation, the page buffer bank 140 may perform a precharge operation of precharging the bit lines to a positive voltage, an evaluation operation of changing or maintaining the potential of the bit lines according to the threshold voltage of the memory cells of the selected page, and a sensing operation of storing data in a latch according to the voltage of the bit lines.

[0044] The column decoder 150 may sequentially send data DATA between the input / output circuit 160 and the page buffer bank 140 according to a column address ADDC.

[0045] The input / output circuit 160 may be connected to the controller 1200 through an input / output line IO ( Figure 1) The input / output circuit 160 may input or output a command CMD, an address ADD, and data DATA through the input / output lines IO. For example, the input / output circuit 160 may send the command CMD and the address ADD received through the input / output lines IO to the control circuit 170, and may send the data received through the input / output lines IO to the page buffer group 140. The input / output circuit 160 may output the data received from the page buffer group 140 to the controller 1200 through the input / output lines IO.

[0046] The control circuit 170 may output an operation code OPc, a row address ADDR, a page buffer control signal PBSIG, and a column address ADDC in response to the command CMD and the address ADD. For example, the control circuit 170 may include software such as an algorithm executed according to the command CMD, and may include hardware for outputting various codes or signals according to the algorithm.

[0047] During a programming operation, the control circuit 170 may adjust the time period or interval for performing a verification operation according to the programming speed of the memory cells. To this end, the control circuit 170 may include an operation controller 170A, an address decoder 170B, an address register 170C, a page buffer controller 170D, and a voltage generator controller 170E.

[0048] The operation controller 170A may include algorithms for various operations, and may execute the algorithm selected according to the input command CMD. For example, the operation controller 170A may include an algorithm capable of performing a programming operation in response to a programming command. When a programming command is input, the operation controller 170A may execute an algorithm capable of controlling the address decoder 170B, the address register 170C, the page buffer controller 170D, and the voltage generator controller 170E according to the input command CMD.

[0049] The address decoder 170B may decode the input address ADD, and output the row address ADDR and the column address ADDC.

[0050] The address register 170C may store the address of a page or a page group with a relatively slow programming speed. For example, during a test operation of the memory device 1100, when a page or a page group with a relatively slow programming speed is detected, the address of the detected page or page group may be stored in the address register 170C.

[0051] The page buffer controller 170D may output a page buffer control signal PBSIG for controlling the page buffer group 140 under the control of the operation controller 170A.

[0052] The voltage generator controller 170E can output an operation code OPc for controlling the operation of the voltage generator 120 under the control of the operation controller 170A.

[0053] During a programming operation, the operation controller 170A can adjust the time period of an evaluation operation for performing a verification operation according to the address of a page or a page group stored in the address register 170C.

[0054] Figure 3 is a diagram illustrating the memory cell array 110 and the page buffer group 140.

[0055] Referring to Figure 3 , the memory cell array 110 may include a first memory block BLK1 to an i-th memory block BLKi (where i is a positive integer of 2 or greater). The first memory block BLK1 to the i-th memory block BLKi may be configured identically to each other and may be commonly connected to a first bit line BL1 to an m-th bit line BLm.

[0056] The page buffer group 140 may include a first page buffer PB1 to an m-th page buffer PBm respectively connected to the first bit line BL1 to the m-th bit line BLm.

[0057] A programming operation may be performed on a memory block selected from the first memory block BLK1 to the i-th memory block BLKi, and the first page buffer PB1 to the m-th page buffer PBm may be respectively connected to the selected memory block through the first bit line BL1 to the m-th bit line BLm.

[0058] The first memory block BLK1 to the i-th memory block BLKi may be configured as a two-dimensional structure or a three-dimensional structure. A memory block configured in a two-dimensional manner may include a plurality of memory cells arranged in a direction parallel to the substrate. A memory block configured in a three-dimensional manner may include a plurality of memory cells stacked in a direction perpendicular to the substrate.

[0059] Embodiments may be applied to both a memory block configured in a two-dimensional manner and a memory block configured in a three-dimensional manner. Hereinafter, a memory block having a three-dimensional structure will be described as an example. Since the first memory block BLK1 to the i-th memory block BLKi are configured identically to each other, the i-th memory block BLKi will be described as an example.

[0060] Figure 4 is a diagram illustrating a representative memory block BLKi.

[0061] Referring to Figure 4 , the memory block BLKi may include a plurality of strings ST. Each string ST may include a source selection transistor SST, a plurality of memory cells C1 to Cn, and a drain selection transistor DST. In Figure 4In [the figure], a source selection transistor SST and a drain selection transistor DST are shown in each string ST, but more source selection transistors SST and more drain selection transistors DST may be included in each string ST. Additionally, dummy cells may be included between multiple memory cells C1 to Cn and between multiple memory cells C1 to Cn and the source selection transistor SST or the drain selection transistor DST.

[0062] Each string ST is configured as described below.

[0063] The source selection transistor SST may be electrically connected or disconnected from the source line SL and the first memory cell C1 according to the voltage applied to the source selection line SSL. The gates of the first memory cell C1 to the nth memory cell Cn may be connected to the first word line WL1 to the nth word line WLn, respectively. The drain selection transistor DST may be electrically connected or disconnected from the first bit line BL1 to the mth bit line BLm and the string ST according to the voltage applied to the drain selection line DSL. The source selection transistor SST may be electrically connected or disconnected from the string ST and the source line SL according to the voltage applied to the source selection line SSL.

[0064] A group of memory cells connected to the same word line forms a page PG, and programming operations and read operations may be performed in units of the page PG. For example, when the page PG corresponding to the fifth word line WL5 is selected during a programming operation, the programming operation may be performed on the memory cells in the selected page PG. The memory cells in the selected page PG are distinguished from the memory cells in the unselected pages by the voltage applied to the first bit line BL1 to the mth bit line BLm.

[0065] Figure 5 is a diagram illustrating the change in the threshold voltage of a memory cell according to a programming voltage.

[0066] Referring to Figure 5 , the threshold voltage of a memory cell is shown. The horizontal axis of the graph represents the voltage V, and the vertical axis represents the number N# of memory cells. The programming operation includes increasing the threshold voltage 51 of a memory cell in an erased state. For example, when a first programming voltage Vpgm1 is applied to the selected word line, the threshold voltage 51 of the memory cell in the erased state may increase (52). Subsequently, when a second programming voltage Vpgm2 higher than the first programming voltage Vpgm1 is applied to the selected word line, the threshold voltage 52 may increase by a set level (53). In this method, when a third programming voltage Vpgm3 and a fourth programming voltage Vpgm4 are sequentially applied to the selected word line, the threshold voltage of the memory cell may gradually increase.

[0067] Since multiple memory cells are connected to the selected page and the electrical characteristics of these memory cells can be different from each other, the threshold voltages of the memory cells to which the programming voltage is applied can form a distribution. The reason why the threshold voltages of the memory cells in the selected page form such a distribution is that those memory cells have different programming speeds. That is, in response to the same programming voltage, a memory cell with a relatively small change in threshold voltage is called a slow cell, while a memory cell with a relatively large change in threshold voltage is called a fast cell. Refer to Figure 6 Specifically describe slow cells and fast cells.

[0068] Figure 6 is a diagram illustrating the threshold voltage changes of slow cell Cs and fast cell Cf according to the same programming voltage.

[0069] Refer to Figure 6 , the slow cell Cs and the fast cell Cf in the selected page have the same initial threshold voltage Vint. In this case, when the same programming voltage is applied to the slow cell Cs and the fast cell Cf, the threshold voltage of the fast cell Cf can be higher than the target voltage Vt, but the threshold voltage of the slow cell Cs can increase to a level lower than the target voltage Vt. In this case, the slow cell Cs is not programmed in the selected page, so further programming is required. Therefore, the slow cell Cs increases the overall programming operation time.

[0070] Figure 7 is a diagram illustrating a method of classifying each page of a memory block as a slow page or a fast page.

[0071] Refer to Figure 7 , when the first page PG1 to the nth page PGn are included in the i-th memory block BLKi, the programming operation speeds of the first page PG1 to the nth page PGn can be different. For example, a page programmed at a speed slower than the programming reference speed is considered a slow page, while a page programmed at a speed faster than the programming reference speed is considered a fast page. Here, the programming reference speed can be the average speed at which multiple pages are programmed. Since the slow pages reduce the overall programming operation speed, in an embodiment, the page address ADDpg of each slow page is stored in an address register, and the programming operation can be adjusted according to the stored page address ADDpg. Each of the slow pages and the fast pages can be formed by mixing multiple slow cells and multiple fast cells, where each slow page has cells slower than the fast cells, and each fast page has cells faster than the slow cells.

[0072] Figure 8 is a diagram illustrating the control circuit 170 according to an embodiment of the present disclosure.

[0073] Refer to Figure 8 , the control circuit 170 can be as Figure 2It includes, as shown, an operation controller 170A, an address decoder 170B, an address register 170C, a page buffer controller 170D, and a voltage generator controller 170E.

[0074] When an input command CMD is received, the operation controller 170A can execute an algorithm corresponding to the input command CMD. When an input address ADD is received, the address decoder 170B can divide the input address ADD into a row address ADDR and a column address ADDC, and output the row address ADDR and the column address ADDC.

[0075] The operation controller 170A can receive the row address ADDR output from the address decoder 170B, and compare the page address in the received row address ADDR with the page address stored in the address register 170C.

[0076] Assume that a fifth page address PA5, a sixth page address PA6, and a ninth page address PA9 corresponding to slow pages are stored in the address register 170C, as Figure 8 shown.

[0077] When the first page is the current programming target page, the operation controller 170A can compare the page address stored in the address register 170C with the first page address PA1. When the comparison result indicates that PA1 does not exist in the address register 170C, the operation controller 170A can generate a page buffer control code PBCD and a voltage generator control code VGCD so as to perform a verification operation in which a first evaluation time is set. The page buffer controller 170D can output a page buffer control signal PBSIG in response to the page buffer control code PBCD. The voltage generator controller 170E can output an operation code OPc in response to the voltage generator control code VGCD.

[0078] When the fifth page is the current programming target page, the operation controller 170A can check the address register 170C to determine whether the fifth page address PA5 exists therein. When it is determined that PA5 exists in the address register 170C, the operation controller 170A can generate a page buffer control code PBCD and a voltage generator control code VGCD so as to perform a verification operation in which a second evaluation time shorter than the first evaluation time is set. The page buffer controller 170D can output a page buffer control signal PBSIG in response to the page buffer control code PBCD. The voltage generator controller 170E can output an operation code OPc in response to the voltage generator control code VGCD.

[0079] Figure 9 is a flowchart illustrating a method of operating a memory device (e.g., Figure 1 and Figure 2 the memory device 1100) according to an embodiment of the present disclosure.

[0080] Refer to Figure 9 , a test operation (operation S91) for classifying each page as a fast page or a slow page can be performed. Here, the test operation can be a test programming operation. The test operation can be performed by measuring the time taken to program the same test data in each page of the selected memory block. The test operation can be performed on all memory blocks in the memory device, or can be performed only on some memory blocks.

[0081] The programming speed of each page on which the test operation is performed can be checked, and based on this check, each page slower than the programming reference speed can be classified as a slow page, and each page faster than the programming reference speed can be classified as a fast page (operation S92).

[0082] Store the page address ADDpg of the slow page in Figure 8 the address register 170C (operation S93). When the page address ADDpg of the slow page is stored in the address register 170C, the test operation can end.

[0083] After the test operation, a normal programming operation can be performed (operation S94). The normal programming operation can be an operation performed at the request of a host (e.g., Figure 1 host 2000). The normal programming operation can be sequentially performed on the pages in the selected memory block. When each page is selected, the memory device can check the page address of the page. When the selected page is a fast page, the memory device can perform a verification operation applying a first evaluation time 1tEV. When the selected page is a slow page, the memory device can perform a verification operation applying a second evaluation time 2tEV shorter than the first evaluation time 1tEV.

[0084] The programming operation (operation S94) applying the first evaluation time 1tEV or the second evaluation time 2tEV is specifically described as follows.

[0085] Figure 10 is a flowchart illustrating a programming operation S94 according to an embodiment of the present disclosure.

[0086] Refer to Figure 10 , when starting the programming operation S94 after operation S93, an operation of determining whether the selected page is a slow page or a fast page can be performed (operation S100). For example, Figure 8 the operation controller 170A of Figure 8 can compare the address of the selected page with the page address stored in the address register 170C of Figure 8 to determine whether the address of the selected page is stored in the address register 170C. When the address of the selected page is not included in the address register 170C, the operation controller 170A can determine that the selected page is a fast page and perform a fast page programming operation P94f.

[0087] When starting the fast page programming operation P94f, a programming voltage application operation (operation S101) of applying a positive programming voltage Vpgm to the selected word line can be performed. When the programming voltage Vpgm is applied to the selected word line during a set time period, a verification operation of the selected page can be performed (operation S102). The verification operation can include determining whether the threshold voltage of the memory cells in the selected page has increased to a target voltage, and the verification operation can be performed by applying a verification voltage to the selected word line. The verification operation can include a precharge operation of precharging the bit line, an evaluation operation of maintaining or changing the voltage or current of the bit line according to the threshold voltage of the selected memory cell, and a sensing operation of sensing the data in the latch of the page buffer according to the voltage or current of the bit line. In the fast page programming operation P94f, the evaluation operation can be set to be performed during a first evaluation time 1tEV.

[0088] After performing the verification operation (S102), the operation controller 170A can determine whether the verification operation of the selected page passes (operation S103). When it is determined that the verification operation of the selected page passes (PASS), the programming operation of the selected page can end. In operation S103, when it is determined that the verification operation of the selected page fails (FAIL), the programming voltage Vpgm is increased by a step voltage (operation S104), and operation 101 is performed again. Operations S101 to S104 can be repeated until the verification operation passes in operation S103.

[0089] When, in operation S100, the address of the selected page is included in the address register 170C, the operation controller 170A can determine that the selected page is a slow page and perform the slow page programming operation P94s.

[0090] When starting the slow page programming operation P94s, a programming voltage application operation (operation S105) of applying a positive programming voltage Vpgm to the selected word line can be performed. When the programming voltage Vpgm is applied to the selected word line during a set time period, a verification operation of the selected page can be performed (operation S106). The verification operation has been described in conjunction with operation S102 above, so it will not be repeated here. In the slow page programming operation P94s, the evaluation operation performed in the verification operation can be set to be performed during a second evaluation time 2tEV shorter than the first evaluation time 1tEV. When the evaluation time is shortened in the verification operation, the total time of the verification operation is shortened, so the next programming voltage can be applied to the selected page faster than in other ways.

[0091] After performing the verification operation (S106), the operation controller 170A may determine whether the verification operation of the selected page has passed (operation S107). When it is determined that the verification operation of the selected page has passed (PASS), the programming operation of the selected page may be ended. In operation S107, when it is determined that the verification operation of the selected page has failed (FAIL), the programming voltage Vpgm is increased by the step voltage (operation S108), and operation 105 is performed again. Operations S105 to S108 may be repeated until the verification operation passes in operation S107.

[0092] Since the memory cells in the slow page are programmed at a slower speed than the memory cells in the fast page, the number of programming cycles applied in the slow page programming operation is greater than the number of programming cycles applied to the fast page in the fast page programming operation. Therefore, the number of programming pulses applied to the selected word line in the slow page programming operation is greater than the number of programming pulses applied to the selected word line in the fast page in the fast page programming operation. In an embodiment, during the verification operation of a programming operation in which the number of programming pulses increases (such as in the slow page programming operation P94s), the programming operation time may be shortened by reducing the evaluation operation time. That is, in the slow page, even if sufficient evaluation time is given, the possibility of the verification operation of the memory cells failing may increase. Therefore, the total programming operation time may be shortened by reducing the operation time so that the verification operation ends quickly and the next programming pulse can be applied.

[0093] Figure 10 It is shown that in the programming operation of the slow page, the second evaluation time 2tEV is used in each cycle, but in another embodiment, the first evaluation time 1tEV may be applied in one or more cycles of the slow page programming operation. The programming operation of the slow page that selectively applies the first evaluation time 1tEV and the second evaluation time 2tEV is described below.

[0094] Figure 11 is an illustration of Figure 10 Another embodiment of the slow page programming operation of

[0095] Referring to Figure 11 , when starting the slow page programming operation P94s, a programming voltage application operation of applying a positive programming voltage Vpgm to the selected word line may be performed (operation S111). When the programming voltage Vpgm is applied to the selected word line during the set time period, a verification operation of the selected page may be performed (operation S112). The evaluation operation performed in the verification operation may be set to be performed during the first evaluation time 1tEV. That is, the verification operation may be performed during the first evaluation time 1tEV, which occurs at the start of the programming operation of the memory cells in the selected page.

[0096] After performing the verification operation (S112), the operation controller 170A may detect whether any memory cells pass (operation S113). Subsequently, the operation controller 170A may determine whether the verification operation of the selected page passes (operation S114). When it is determined that the verification operation of the selected page passes (PASS), the programming operation of the selected page may be ended. In operation S114, when it is determined that the verification operation of the selected page fails (FAIL), an operation S115 or S116 of increasing the programming voltage Vpgm by the step voltage may be performed.

[0097] When there are no memory cells whose threshold voltage increases to the target voltage, resulting in the verification operation failing (FAIL; there are no passing memory cells), operation S115 may be performed. When some, but not all, memory cells whose threshold voltage increases to the target voltage are detected, resulting in the verification operation failing (FAIL; there are passing memory cells), operation S116 may be performed.

[0098] When operation S115 is performed, operations S111 to S115 may be repeated until the verification operation passes (PASS) in operation S114 or some passing memory cells are detected.

[0099] Since performing operation S116 means that the selected page includes memory cells whose threshold voltage increases to the target voltage, the time taken to perform the evaluation operation may be changed from the first evaluation time 1tEV to the second evaluation time 2tEV.

[0100] When the programming voltage Vpgm is set high in operation S116, a programming voltage application operation of applying a positive programming voltage Vpgm to the selected word line may be performed (operation S117). When the programming voltage Vpgm is applied to the selected word line during a set time period, a verification operation of the selected page may be performed (operation S118). The evaluation operation performed in the verification operation S118 may be set to be performed during a second evaluation time 2tEV shorter than the first evaluation time 1tEV. When the evaluation time is shortened in the verification operation, the total time of the verification operation is shortened, so the time to apply the next programming voltage to the selected page may be advanced.

[0101] After the verification operation (S118) is performed, the operation controller 170A may determine whether the verification operation of the selected page has passed (operation S119). When it is determined that the verification operation of the selected page has passed (PASS), the programming operation of the selected page may be ended. In operation S119, when it is determined that the verification operation of the selected page has failed (FAIL), the programming voltage Vpgm is increased by the step voltage (operation S120), and operation S117 is performed again. Operations S117 to S120 may be repeated until the verification operation passes (PASS) in operation S119.

[0102] The verification operation, which is one of the above operations, is performed as described below.

[0103] Figure 12 is a diagram illustrating the operation sequence of the page buffer during the verification operation. Figure 13 is a diagram illustrating the evaluation operation during the verification operation.

[0104] Refer to Figure 12 and Figure 13 The verification operation may include a precharge operation 51 for precharging the bit line, an evaluation operation 52 for changing or maintaining the potential of the bit line according to the threshold voltage of the memory cells of the selected page, and a sensing operation 53 for storing data in the latch according to the voltage of the bit line. Since the above precharge operation 51, evaluation operation 52, and sensing operation 53 are performed in each page buffer, the following description will be given taking the m-th page buffer PBm as an example.

[0105] The m-th page buffer PBm may include a precharge circuit PRE, a bit line transfer circuit BL_TRAN, a discharge circuit DIS, and a latch LAT. In addition to Figure 12 the circuits shown, the m-th page buffer PBm generally also includes various other circuits, but only the circuits related to the operations described in conjunction with Figure 12 are shown therein.

[0106] The precharge circuit PRE may precharge the m-th bit line BLm to a positive voltage (i.e., Figure 13 the period from T1 to T2 in

[0107] by transmitting the power supply voltage VCC to the m-th bit line BLm in response to the bit line precharge signal BL_PRE. At this time, a ground voltage GND may be applied to the selected word line Sel_WL. Figure 13At time T2, a verification voltage Vvf can be applied to the selected word line Sel_WL, and an evaluation operation 52 can be performed. The evaluation time tEV during which the evaluation operation 52 is performed therebetween can be set to occur during a period when the threshold voltage of the memory cell can be reflected on the m-th bit line BLm. For example, since the memory cell M13 having a threshold voltage lower than the verification voltage is turned on by the verification voltage, the voltage of the precharged m-th bit line BLm can be reduced.

[0108] The bit line transfer circuit BL_TRAN can connect the m-th bit line BLm and the sense node SO to each other in response to the page sense signal PBSENSE. For example, when the evaluation operation 52 is performed during the evaluation time tEV (i.e., Figure 13 At time T3), the bit line transfer circuit BL_TRAN can be activated, and thus a sensing operation 53 can be performed, in which the voltage or current of the m-th bit line BLm is transferred to the latch LAT through the sense node SO. That is, the evaluation time tEV can be adjusted to occur when the bit line transfer circuit BL_TRAN is activated.

[0109] The discharge circuit DIS can discharge the sense node SO in response to the discharge signal SIG_D, and can be used when the sense node SO is initialized or data is transferred between multiple latches.

[0110] Figure 14 is a diagram illustrating a programming operation of a slow cell Cs and a fast cell Cf according to an embodiment of the present disclosure.

[0111] Referring to Figure 14 , when the slow cell Cs and the fast cell Cf are programmed such that the threshold voltages of the slow cell Cs and the fast cell Cf increase to the same target voltage, the evaluation operation of the fast cell Cf can be set to be performed during the first evaluation time 1tEV, and the evaluation operation of the slow cell Cs can be set to be performed during a second evaluation time 2tEV shorter than the first evaluation time 1tEV.

[0112] The total time taken to perform the verification operation can include the time tPRE for performing the precharge operation 51, the time 1tEV or 2tEV for performing the evaluation operation 52, and the time tSEN for performing the sensing operation 53. For example, after applying the first programming voltage 1Vpgm to the selected word line, the precharge operation 51 can be performed. The precharge operation 51 can be performed in the fast cell Cf and the slow cell Cs during the same time period tPRE.

[0113] The time for performing the evaluation operation 52 of the slow cell Cs can be set to a time 2tEV shorter than the time 1tEV for performing the evaluation operation 52 of the fast cell Cf. Since the slow cell Cs is programmed at a slower speed than the fast cell Cf, more programming pulses can be used than for the fast cell Cf. Therefore, by shortening the time for performing the evaluation operation of the slow cell Cs to the second evaluation time 2tEV, the verification time can be shortened by tRED compared to the fast cell Cf. Accordingly, the time for applying the next programming voltage 2Vpgm can be advanced, and thus the total programming operation time of the slow cell Cs can be shortened.

[0114] Figure 15 FIG. is a diagram illustrating a method of classifying some of the pages PG1 to PGn of the memory block BLKi into one or more slow groups and classifying the other pages into one or more fast groups.

[0115] Refer to Figure 15 , the pages PG1 to PGn of the i-th memory block BLKi can be classified into a plurality of page groups, and a group address ADDgr can be set in each page group. For example, the first page PG1 to the third page PG3 can be set as the first page group GR1, and the first group address GA1 can be assigned to the first page group GR1. The fourth page PG4 to the sixth page PG6 can be set as the second page group GR2, and the second group address GA2 can be assigned to the second page group GR2. The seventh page PG7 to the ninth page PG9 can be set as the third page group GR3, and the third group address GA3 can be assigned to the third page group GR3. In this method, the (n - 2)-th page PG(n - 2) to the n-th page PGn can be classified into the j-th page group GRj, and the j-th group address GAj can be set for the j-th page group GRj.

[0116] When, as a result of a test operation (i.e., Figure 9 operation S91), the first page PG1 to the third page PG3 are detected as slow pages, the first page group GR1 including the first page PG1 to the third page PG3 can be set as a slow group. When one or more of the multiple pages in a page group are detected as slow pages, the corresponding page group can also be set as a slow group. For example, when the fourth page PG4 and the sixth page PG6 are detected as slow pages and the fifth page PG5 is detected as a fast page, the second page group GR2 including the fourth page PG4 and the sixth page PG6 can be set as a slow group. Various criteria can be used to set a page group as a slow group consistent with the teachings herein. Which criterion to use in a particular case depends on the characteristics of the memory device.

[0117] Figure 16 FIG. is a diagram illustrating a control circuit 170 according to an embodiment of the present disclosure.

[0118] Refer to Figure 16, the control circuit 170 may include an operation controller 170A, an address decoder 170B, an address register 170C, a page buffer controller 170D, and a voltage generator controller 170E.

[0119] When an input command CMD is received, the operation controller 170A may execute an algorithm corresponding to the input command CMD. When an input address ADD is received, the address decoder 170B divides the input address ADD into a row address ADDR and a column address ADDC, and outputs the row address ADDR and the column address ADDC.

[0120] The operation controller 170A may receive the row address ADDR output from the address decoder 170B, and compare the page address in the received row address ADDR with the index IN of the address register 170C.

[0121] The address register 170C may include a table that includes group GR# and index IN fields, in which the index of the page in the group is identified in association with the corresponding group GR#. GR# may identify a slow page group, and the index of the page in the slow group may be identified in the IN field. For example, when the first page group GR1 and the second page group GR2 are slow page groups, the index IN may include all page addresses PA1 to PA6 in the first page group GR1 and the second page group GR2. That is, all pages of the slow group including fast pages are identified in the IN field. For example, as Figure 15 shown, the fifth page PG5 is a fast page, but the second page group GR2 including the fifth page PG5 is a slow page group; therefore, the fifth page address PA5 corresponding to the fifth page PG5 may be included in the index IN of the address register 170C.

[0122] When the seventh page PG7 is the current programming target page, the operation controller 170A may compare the page address stored in the address register 170C with the seventh page address PA7. When the comparison result indicates that PG7 does not exist in the address register 170C, the operation controller 170A may generate a page buffer control code PBCD and a voltage generator control code VGCD such that a verification operation in which a first evaluation time is set is performed. The page buffer controller 170D may output a page buffer control signal PBSIG in response to the page buffer control code PBCD, and the voltage generator controller 170E may output an operation code OPc in response to the voltage generator control code VGCD.

[0123] When the second page PG2 is the current programming target page, the operation controller 170A can compare the page address stored in the address register 170C with the second page address PA2. When the comparison result indicates that PG2 exists in the address register 170C, the operation controller 170A can generate a page buffer control code PBCD and a voltage generator control code VGCD, so as to perform a verification operation in which a second evaluation time shorter than the first evaluation time is set. The page buffer controller 170D can output a page buffer control signal PBSIG in response to the page buffer control code PBCD, and the voltage generator controller 170E can output an operation code OPc in response to the voltage generator control code VGCD.

[0124] Figure 17 FIG. is an example of an embodiment in which the evaluation operation time is adjusted according to the number of programming pulses.

[0125] Referring to Figure 17 , when a slow cell in the erased state ER is programmed to the target state PV, an incremental step pulse programming (ISPP) method of gradually increasing the programming voltage can be used to perform the programming operation. In the programming operation performed according to the ISPP method, the operation of applying the programming voltage and the verification operation can form a cycle. Therefore, as the number of cycles increases, the number of programming pulses applied to the selected word line increases.

[0126] In Figure 17 the illustrated embodiment, the evaluation time can be adjusted according to the number of programming pulses PC#. For example, a verification operation applying the first evaluation time 1tEV can be performed at the start of programming a memory cell in the erased state ER, and a verification operation applying a second evaluation time 2tEV shorter than the first evaluation time 1tEV can be performed during a period when the threshold voltage is close to the target voltage Vt.

[0127] For example, when the number of programming pulses PC# is 1 to 3, a verification operation applying the first evaluation time 1tEV can be performed, and when the number of programming pulses PC# is 4 or more, a verification operation applying the second evaluation time 2tEV can be performed.

[0128] Figure 18 FIG. is an example of an embodiment in which the evaluation operation time is controlled according to the threshold voltage of the memory cell.

[0129] Referring to Figure 18, the evaluation time of the verification operation can be adjusted according to the threshold voltage of the slow memory cell. For example, at the start of programming a memory cell in the erased state ER, a verification operation applying a first evaluation time 1tEV can be performed. When a cell whose threshold voltage has increased to the target voltage Vt is detected among the memory cells, two verification operations can be performed in one cycle in the programming operation of the cells whose threshold voltage has not increased to the target voltage Vt. For example, a sub-target voltage Vts lower than the target voltage Vt can be set. That is, after performing the verification operation for the sub-target voltage Vts, the verification operation for the target voltage Vt can be successively performed. Starting from the cycle using the sub-target voltage Vts, a verification operation applying a second evaluation time 2tEV can be performed.

[0130] Figure 19 FIG. is an illustration of a memory system 70000 according to another embodiment of the present disclosure.

[0131] Referring to Figure 19 , the memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a semiconductor memory device 1100, a controller 1200, and a card interface 7100.

[0132] The controller 1200 can control data exchange between the memory device 1100 and the card interface 7100. According to an embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but the present invention is not limited thereto.

[0133] The memory device 1100 can perform the programming operation according to the above embodiment, and can output the data programmed in the memory device 1100 through the card interface 7100 under the control of the controller 1200.

[0134] The card interface 7100 can interface data exchange between the host 60000 and the controller 1200 according to the protocol of the host 60000. According to an embodiment, the card interface 7100 may support the Universal Serial Bus (USB) protocol and the Inter-Chip (IC)-USB protocol. Herein, the card interface 7100 may refer to hardware capable of supporting the protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0135] When the memory system 70000 is connected to a host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box, the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of a microprocessor (μP) 6100.

[0136] Although the present invention has been illustrated and described in conjunction with various embodiments, those skilled in the art will recognize that various modifications can be made to any of the disclosed embodiments within the spirit and scope of the present invention. The present invention encompasses all such modifications that fall within the scope of the claims.

[0137] Cross - reference to related applications

[0138] This application claims the priority of Korean Patent Application No. 10 - 2020 - 0098765, filed on August 6, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A memory block, the memory block including a plurality of pages; A voltage generator configured to generate a programming voltage or a verification voltage applied to a selected page among the plurality of pages; A page buffer connected to the selected page through a bit line and configured to perform a pre-charging operation, an evaluation operation, and a sensing operation on the bit line during a verification operation; And A control circuit configured to store a page address of a slow page and adjust an evaluation time of the evaluation operation according to the page address of the slow page such that the evaluation time is reduced without skipping the evaluation operation, wherein a programming operation speed of each slow page is slower than an average programming speed of the plurality of pages.

2. The memory device according to claim 1, wherein The control circuit includes: An address decoder configured to decode an address and output a row address and a column address; An address register configured to store the page address; A page buffer controller configured to output a page buffer control signal for controlling the page buffer in response to a page buffer control code; A voltage generator controller configured to output an operation code for controlling the voltage generator in response to a voltage generator control code; and An operation controller configured to execute an algorithm for a programming operation in response to a command, compare a page address in the row address with the page address stored in the address register, and output the page buffer control code and the voltage generator control code such that the evaluation time is adjusted according to a comparison result.

3. The memory device according to claim 2, wherein, The voltage generator sets a level of the verification voltage according to the operation code and adjusts a time for outputting the verification voltage.

4. The memory device according to claim 2, wherein, The page buffer controls the pre-charging operation, the evaluation operation, and the sensing operation according to the page buffer control signal.

5. The memory device according to claim 4, wherein, The page buffer pre-charges the bit line to a positive voltage during the pre-charging operation, performs the evaluation operation during a first evaluation time or a second evaluation time shorter than the first evaluation time such that a threshold voltage of a memory cell in the selected page is reflected on the bit line, and performs a sensing operation that senses a voltage or a current of the bit line for which the evaluation operation is performed and stores data corresponding to a sensing result in a latch.

6. The memory device according to claim 5, wherein, When there is no address identical to the page address in the row address among the page addresses stored in the address register, the operation controller outputs the page buffer control code and the voltage generator control code such that the evaluation operation is performed during the first evaluation time.

7. The memory device according to claim 5, wherein, When there is an address identical to the page address in the row address among the page addresses stored in the address register, the operation controller outputs the page buffer control code and the voltage generator control code such that the evaluation operation is performed during the second evaluation time.

8. The memory device according to claim 5, wherein, The operation controller outputs the page buffer control code and the voltage generator control code so that the evaluation operation is performed during the second evaluation time and the evaluation operation is performed until the programming operation of the slow page is completed.

9. The memory device according to claim 5, wherein, The operation controller outputs the page buffer control code and the voltage generator control code so that the evaluation operation is performed during the first evaluation time from the start of the programming operation of the slow page to the reference time point, and outputs the page buffer control code and the voltage generator control code so that the evaluation operation is performed during the second evaluation time from the reference time point to the end of the programming operation.

10. A method of operating a memory device, the method comprising the steps of: Classifying each of a plurality of pages as a fast page or a slow page according to a programming operation speed; Storing the page address of the slow page and adjusting the evaluation time of the evaluation operation according to the page address of the slow page so as to reduce the evaluation time without skipping the evaluation operation; And When the selected page is a fast page, performing a verification operation of the programming operation so that the evaluation operation is performed during a first evaluation time, and when the selected page is a slow page, performing the verification operation so that the evaluation operation is performed during a second evaluation time shorter than the first evaluation time, wherein when the verification operation passes, the programming operation ends, and when the verification operation fails, the classification and execution are repeated until the verification operation passes.

11. The method according to claim 10, wherein, The step of classifying each of the plurality of pages as a fast page or a slow page and storing the page address of the slow page comprises the steps of: Performing a test programming operation on the plurality of pages; As a result of the test programming operation, classifying a page with a programming speed slower than a reference speed as a slow page, and classifying a page with a programming speed faster than the reference speed as a fast page; and Storing the page address of each slow page in an address register.

12. The method according to claim 11, wherein, The step of performing the verification operation comprises the steps of: Precharging the bit line connected to the selected page among the plurality of pages to a positive voltage; Applying a verification voltage to the word line connected to the selected page and performing the evaluation operation during the first evaluation time or the second evaluation time; and Performing a sensing operation of sensing data according to the voltage or current of the bit line and storing the sensed data in a latch.

13. The method according to claim 12, wherein, When the verification operation of all memory cells in the selected page has passed, the programming operation ends, and when there is a cell in the memory cells of the selected page for which the verification operation has not passed, it is determined that the verification operation has failed.

14. A method of operating a memory device, the method comprising the steps of: Classifying each of a plurality of pages as a fast page or a slow page according to a programming operation speed; And When the selected page is a fast page, perform a verification operation for the programming operation so that the evaluation operation is performed during a first evaluation time. When the selected page is a slow page, perform the verification operation so that the evaluation operation is performed based on the first evaluation time. And when a reference time point is reached during the programming operation of the slow page, perform the verification operation so that the evaluation operation is performed during a second evaluation time shorter than the first evaluation time. Wherein, when the verification operation has passed, end the programming operation, and when the verification operation fails, repeat the classification and execution until the verification operation passes.

15. The method according to claim 14, wherein, The step of classifying each of the plurality of pages as a fast page or a slow page includes the following steps: Perform a test programming operation on the plurality of pages; As a result of the test programming operation, classify a page with a programming speed slower than a reference speed as a slow page, and classify a page with a programming speed faster than the reference speed as a fast page; and Store the page address of each of the slow pages in an address register.

16. The method according to claim 15, wherein, The step of performing the verification operation for the slow page includes the following steps: Precharge the bit line connected to the selected page among the plurality of pages to a positive voltage; Apply a verification voltage to the word line connected to the selected page, perform the evaluation operation during the first evaluation time from the start of the programming operation to the reference time point, and perform the evaluation operation during the second evaluation time after the reference time point; and Perform a sensing operation of sensing data according to the voltage or current of the bit line and storing the sensed data in a latch.

17. The method according to claim 14, wherein, The reference time point is set according to the number of programming pulses applied to the slow page.

18. The method according to claim 14, wherein The reference time point is set to the time point when a cell in which the threshold voltage among the memory cells in the slow page increases to a target voltage is detected.

19. The method according to claim 18, the method further includes the following steps: When a cell in which the threshold voltage increases to the target voltage is detected, before performing the verification operation using the target voltage of the next cycle, perform the verification operation using a sub-target voltage lower than the target voltage.

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