Semiconductor package

Abstract

A semiconductor package includes: a first sub-semiconductor device stacked on top of each other, an intermediate layer and a second sub-semiconductor device, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The intermediate layer includes a dielectric layer, a thermally conductive layer in contact with a bottom surface of the dielectric layer, a first thermally conductive pad in contact with a top surface of the dielectric layer, and a thermally conductive through-hole extending through the dielectric layer to connect the thermally conductive layer to the first thermally conductive pad. The bottom surface of the thermally conductive layer is adjacent to and connected to the top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermally conductive pad. The heat sink also covers the first thermally conductive pad for connection to the first thermally conductive pad.

Description

[0001] Cross-references to related applications

[0002] This U.S. non-provisional application claims priority to Korean Patent Application No. 10-2020-0098717, filed on August 6, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor package. Background Technology

[0004] Semiconductor packages are provided to implement integrated circuit chips, thus qualifying them for use in electronic products. Semiconductor packages are typically configured to mount semiconductor chips onto printed circuit boards (PCBs), and the semiconductor chips are electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, much research has been conducted to improve the reliability and durability of semiconductor packages. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide a semiconductor package with improved performance.

[0006] Some exemplary embodiments of the present invention provide a wiring structure capable of providing enhanced thermal radiation.

[0007] The purpose of this invention is not limited to those mentioned above, and those skilled in the art will clearly understand from the following description other purposes not mentioned above.

[0008] According to an embodiment of the present invention, a semiconductor package includes: a first sub-semiconductor device, an intermediate layer, and a second sub-semiconductor device, stacked on top of each other such that the intermediate layer is configured to connect the first and second sub-semiconductor devices to each other; and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip stacked on the first substrate. The intermediate layer includes: a dielectric layer; a thermally conductive layer in contact with a bottom surface of the dielectric layer; a first thermally conductive pad in contact with a top surface of the dielectric layer; and a plurality of thermally conductive through-holes passing through the dielectric layer and connecting the thermally conductive layer to the first thermally conductive pad. The bottom surface of the thermally conductive layer is adjacent to and connected to the top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer of the intermediate layer without overlapping the first thermally conductive pad of the intermediate layer. The heat sink also covers the first thermally conductive pad of the intermediate layer for connection to the first thermally conductive pad of the intermediate layer.

[0009] According to an exemplary embodiment of the present invention, a semiconductor package includes: a first sub-semiconductor device; an intermediate layer on the first sub-semiconductor device; a first thermal interface material layer between the first sub-semiconductor device and the intermediate layer; a second sub-semiconductor device located on the intermediate layer, the second sub-semiconductor device exposing a portion of the intermediate layer; a heat sink covering a top surface of the second sub-semiconductor device, a sidewall of the second sub-semiconductor device, and the portion of the intermediate layer; and a second thermal interface material layer between the heat sink and the portion of the intermediate layer. The first sub-semiconductor device includes a first substrate and a first semiconductor chip stacked on the first substrate. The intermediate layer includes: a dielectric layer; a thermally conductive layer in contact with a bottom surface of the dielectric layer; thermally conductive pads in contact with a top surface of the dielectric layer; and a plurality of thermally conductive through-holes passing through the dielectric layer and connecting the thermally conductive layer to the thermally conductive pads. The second sub-semiconductor device exposes the thermally conductive pads of the intermediate layer. The first thermal interface material layer is in contact with the bottom surface of the thermally conductive layer and the top surface of the first semiconductor chip. The second thermal interface material layer is in contact with the top surface of the thermally conductive pads and the bottommost surface of the heat sink. The width of the thermal pads ranges from approximately 500 μm to approximately 7,000 μm.

[0010] According to an embodiment of the present invention, a semiconductor package includes: a first sub-semiconductor device, an intermediate layer, and a second sub-semiconductor device, stacked on top of each other such that the intermediate layer is configured to connect the first and second sub-semiconductor devices to each other. The intermediate layer includes: a dielectric layer, a thermally conductive layer, and a plurality of lower conductive patterns that are in contact with and spaced apart from each other on a bottom surface of the dielectric layer; the bottom surface of the thermally conductive layer is adjacent to and connected to the top surface of the first sub-semiconductor device; thermally conductive pads and a plurality of upper conductive patterns that are in contact with and spaced apart from each other on the top surface of the dielectric layer; a plurality of thermally conductive through-holes that pass through the dielectric layer and connect the thermally conductive layer to the thermally conductive pads; and a plurality of circuit through-holes that pass through the dielectric layer. Each of the plurality of circuit through-holes connects a corresponding one of the plurality of upper conductive patterns to a corresponding one of the plurality of lower conductive patterns. The second sub-semiconductor device is disposed on the dielectric layer of the intermediate layer without overlapping the thermally conductive pads of the intermediate layer. A first width of each of the plurality of thermally conductive through-holes in a first direction parallel to the bottom surface of the dielectric layer is greater than a second width of each of the plurality of circuit through-holes in the first direction.

[0011] According to an embodiment of the present invention, an intermediate layer includes: a dielectric layer, a thermally conductive layer, and a plurality of lower conductive patterns that are in contact with and spaced apart from each other on the bottom surface of the dielectric layer; thermally conductive pads and a plurality of upper conductive patterns that are in contact with and spaced apart from each other on the top surface of the dielectric layer; a plurality of thermally conductive through-holes that pass through the dielectric layer and connect the thermally conductive layer to the thermally conductive pads; and a plurality of circuit through-holes that pass through the dielectric layer. Each of the plurality of circuit through-holes connects a corresponding one of the plurality of upper conductive patterns to a corresponding one of the plurality of lower conductive patterns. A first width of each of the plurality of thermally conductive through-holes in a first direction parallel to the bottom surface of the dielectric layer is greater than a second width of each of the plurality of circuit through-holes in the first direction. Attached Figure Description

[0012] Figure 1 A plan view of a semiconductor package showing some example embodiments of the concept according to the present invention is shown.

[0013] Figure 2 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0014] Figure 3A A plan view showing a wiring structure illustrating some example embodiments of the concept according to the present invention is shown.

[0015] Figure 3B It shows along Figure 3A A cross-sectional view taken by line IA-IA'.

[0016] Figure 4A and Figure 4B The display shows Figure 2 A magnified view of part P1.

[0017] Figure 4C The display shows Figure 2 A magnified view of part P2.

[0018] Figures 5A to 5E Display manufacturing is shown Figure 2 A cross-sectional view of a method for developing semiconductor packages.

[0019] Figure 6 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0020] Figure 7A A plan view showing a wiring structure illustrating some example embodiments of the concept according to the present invention is shown.

[0021] Figure 7B It shows along Figure 7A A cross-sectional view taken by line IA-IA'.

[0022] Figure 8A and Figure 8B The display shows Figure 6 A magnified view of part P3.

[0023] Figure 9 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0024] Figure 10 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0025] Figure 11 The display shows Figure 10 A magnified view of part P4.

[0026] Figure 12 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0027] Figure 13 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0028] Figure 14 A plan view of a semiconductor package showing some example embodiments of the concept according to the present invention is shown.

[0029] Figure 15 It shows along Figure 14 A cross-sectional view taken by line IA-IA'.

[0030] Figures 16A to 16E A plan view of a semiconductor package showing some example embodiments of the concept according to the present invention is shown.

[0031] Figure 17A and Figure 17B A plan view showing a wiring structure illustrating some example embodiments of the concept according to the present invention is shown. Detailed Implementation

[0032] Now, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings to help to clearly explain the inventive concept.

[0033] Figure 1 A plan view of a semiconductor package showing some example embodiments of the concept according to the present invention is shown. Figure 2 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0034] Reference Figure 1 and Figure 2According to some example embodiments, a semiconductor package 1000 may include a first sub-semiconductor package 500 (i.e., a first sub-semiconductor device), a wiring structure 600 (i.e., an intermediate layer), a second sub-semiconductor package 700 (i.e., a second sub-semiconductor device), and a heat-radiating member HS (i.e., a heat sink) stacked sequentially on top of each other. The first sub-semiconductor package 500 and the wiring structure 600 may have the same width in a first direction X. The sidewalls of the first sub-semiconductor package 500 and the wiring structure 600 may be aligned with each other. In the first direction X, the width of the second sub-semiconductor package 700 may be less than the width of the wiring structure 600. The first sidewall SW1 of the second sub-semiconductor package 700 may be aligned with the first sidewall SW2 of the wiring structure 600. The second sidewall SW3 of the second sub-semiconductor package 700 may be spaced apart from the second sidewall SW4 of the wiring structure 600. The second sub-semiconductor package 700 may expose a portion of the wiring structure 600. The first sidewall SW1 and the second sidewall SW3 of the second sub-semiconductor package 700 may be opposite each other in the first direction X. The first sidewall SW2 and its second sidewall SW4 of the wiring structure 600 may be opposite each other in the first direction X. Terms such as “identical,” “flat,” or “coplanar” as used herein, when referring to orientation, layout, location, shape, size, quantity, or other measure, do not necessarily mean exactly identical orientation, layout, location, shape, size, quantity, or other measure, but are intended to cover approximately identical orientation, layout, location, shape, size, quantity, or other measure within an acceptable range of variation, for example, due to manufacturing processes. Unless the context or other statement otherwise indicates, the term “substantially” may be used herein to emphasize this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially flat” may be exactly identical, equal, or flat, or may be identical, equal, or flat within an acceptable range of variation, for example, due to manufacturing processes.

[0035] The heat-radiating component HS may comprise or be formed of a material such as a metal (such as aluminum and copper) or graphene, having a high thermal conductivity, such that the heat-radiating component HS can be used as a heat sink for the semiconductor package 1000. The heat-radiating component HS may include a first heat-radiating portion HS1 (i.e., a first heat sink portion) overlapping with the second sub-semiconductor package 700 and a second heat-radiating portion HS2 (i.e., a second heat sink portion) extending from the sidewall of the first heat-radiating portion HS1 toward the wiring structure 600. The first heat-radiating portion HS1 and the second heat-radiating portion HS2 may be integrally joined to each other, and there may be no boundary between them. The second heat-radiating portion HS2 may be thicker than the first heat-radiating portion HS1. In this embodiment, when viewed in plan view of the semiconductor package 1000, the second heat-radiating portion HS2 may have an "L" shape, such as... Figure 1As shown. The second thermal radiating portion HS2 may have a first width W1 in the first direction X. For example, the first width W1 may have a value from about 500 μm to about 7,000 μm. Terms such as “about” or “approximately” may reflect an amount, size, orientation, or arrangement that varies only in a relatively small manner and / or in a manner that does not significantly alter the operation, function, or structure of a particular element. For example, a range of “about 0.1 to about 1” may cover deviations such as 0%-5% for about 0.1 and 0%-5% for about 1, especially if such deviations maintain the same effect as the listed ranges.

[0036] The first sub-semiconductor package 500 may include a first substrate S1, a first semiconductor device CH1 (i.e., a first semiconductor chip) mounted on the first substrate S1, and a first molding layer MD1 covering the sidewalls of the first semiconductor device CH1. The first substrate S1 may have a first thickness TH1. The wiring structure 600 may have a second thickness TH2. The second thickness TH2 may be less than the first thickness TH1. For example, the first substrate S1 may be a multilayer printed circuit board. The first substrate S1 may include a first body layer C1, a second body layer C2, and a third body layer C3. Each of the first body layer C1, the second body layer C2, and the third body layer C3 may include or be formed of a dielectric material. For example, each of the first body layer C1, the second body layer C2, and the third body layer C3 may be formed of a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated (or mixed with) a thermosetting or thermoplastic resin containing reinforcements formed of, for example, glass fiber and / or inorganic fillers. In the embodiments, the resin mixed with the reinforcing member may include prepreg, flame retardant-4 (FR4) or photosensitive resin, but the inventive concept is not limited thereto.

[0037] The second main layer C2 can be located above the first main layer C1, and the third main layer C3 can be located below the first main layer C1. The first main layer C1 may include a first internal line 14 on its top surface and a second internal line 12 on its bottom surface. A first upper conductive pattern 16 can be disposed on the second main layer C2, and a first lower conductive pattern 18 can be disposed on the bottom surface of the third main layer C3. A first upper passivation layer PS1 can be disposed on the second main layer C2, and the first upper conductive pattern 16 can be exposed on the second main layer C2. A first lower passivation layer PS2 can be disposed below the third main layer C3, and the first lower conductive pattern 18 can be exposed below the third main layer C3. A first circuit through-hole 10 can be disposed in the first main layer C1, the second main layer C2, and the third main layer C3, and the first internal line 14, the second internal line 12, the first upper conductive pattern 16, and the lower conductive pattern 18 can be electrically connected to each other through the first circuit through-hole 10. The first upper passivation layer PS1 and the first lower passivation layer PS2 can be photosensitive solder resist (PSR) layers. External connection terminals 300 can be bonded to the first lower conductive pattern 18. External connection terminals 300 may include one or more of solder balls, conductive bumps, and conductive pillars, or may be formed from one or more of solder balls, conductive bumps, and conductive pillars. External connection terminals 300 may include one or more of tin, lead, aluminum, gold, and nickel, or may be formed from one or more of tin, lead, aluminum, gold, and nickel.

[0038] The first semiconductor device CH1 (i.e., the semiconductor chip) may be a single semiconductor wafer, a semiconductor package comprising a single semiconductor wafer, or multiple semiconductor wafers of the same or different types. As used herein, for example, a semiconductor device may refer to a device such as a semiconductor chip (e.g., a memory chip and / or logic chip formed on a wafer), a stack of semiconductor chips, a semiconductor package comprising one or more semiconductor chips stacked on a package substrate, or a stacked package assembly comprising multiple packages. These devices may be formed using ball grid arrays, wire bonding, through-substrate pass-throughs, or other electrical connection elements, and may include memory devices such as volatile or non-volatile memory devices. A semiconductor package may include at least one semiconductor chip, a redistribution layer allowing input / output pads of an integrated circuit to be redistributed in other locations on the semiconductor chip, a package substrate, or an encapsulation formed on the package substrate and covering the semiconductor chip. The semiconductor device may be selected from image sensor chips such as CMOS image sensors (CIS), microelectromechanical systems (MEMS) device chips, application-specific integrated circuit (ASIC) chips, and memory device chips such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, ReRAM, HBM (high bandwidth memory), and HMC (hybrid memory block). The first semiconductor device CH1 may be flip-chip bonded to a first upper conductive pattern 16 of the first substrate S1 via a first internal interconnect member 310. The first internal interconnect member 310 may include one or more of solder balls, conductive bumps, and conductive pillars, or may be formed from one or more of solder balls, conductive bumps, and conductive pillars. A first underfill layer UF1 may be located between the first semiconductor device CH1 and the first substrate S1. The first underfill layer UF1 may include a thermosetting resin or a photocurable resin, or may be formed from a thermosetting resin or a photocurable resin. The first underfill layer UF1 may also include organic fillers or inorganic fillers.

[0039] The first molding layer MD1 may cover the sidewalls of the first semiconductor device CH1 and the top surface of the first substrate S1. The first molding layer MD1 may comprise, for example, an epoxy molding compound (EMC) dielectric resin or may be formed from, for example, an epoxy molding compound (EMC) dielectric resin. The first molding layer MD1 may also include a filler, and the filler may be dispersed in the dielectric resin.

[0040] Figure 3A A plan view showing a wiring structure illustrating some example embodiments of the concept according to the present invention is shown. Figure 3B It shows along Figure 3A A cross-sectional view taken by line IA-IA'.

[0041] Reference Figure 1 , Figure 2 , Figure 3A and Figure 3B The wiring structure 600 may be a double-sided printed circuit board. For example, the wiring structure 600 may include a fourth body layer C4, a second upper conductive pattern 34 on the top surface of the fourth body layer C4, and a second lower conductive pattern 32 on the bottom surface of the fourth body layer C4. A second circuit pass-through 30 may pass through the fourth body layer C4 and may electrically connect the second upper conductive pattern 34 to the second lower conductive pattern 32. For example, the fourth body layer C4 may include or be formed of the same or similar material as the first body layer C1. Alternatively, the fourth body layer C4 may include or be formed of silicon. In this embodiment, the wiring structure 600 may be an intermediate layer for extending connections to a wider pitch or for rerouting connections to electrical interfaces of different connections. In an embodiment, the wiring structure 600 may be a printed circuit board (PCB) intermediate layer, and the body layer of the wiring structure 600 may be formed of a dielectric layer. The invention is not limited thereto. For example, the wiring structure 600 may be a silicon intermediate layer with a body layer formed of silicon.

[0042] The wiring structure 600 may further include a thermally conductive layer TL disposed on the bottom surface of the fourth body layer C4, a thermally conductive pad TP disposed on the top surface of the fourth body layer C4, and a thermally conductive pass-through VT passing through the fourth body layer C4 and connecting the thermally conductive layer TL to the thermally conductive pad TP. A second upper passivation layer PS3 may be disposed on the fourth body layer C4, thereby exposing the thermally conductive pad TP and the second upper conductive pattern 34 disposed on the top surface of the fourth body layer C4. A second lower passivation layer PS4 may be disposed on the bottom surface of the fourth body layer C4, thereby exposing the thermally conductive layer TL and the second lower conductive pattern 32 disposed on the bottom surface of the fourth body layer C4. The second upper passivation layer PS3 and the second lower passivation layer PS4 may comprise the same material as the first upper passivation layer PS1 and the first lower passivation layer PS2, or may be formed from said same material. The thermally conductive pad TP, the thermally conductive pass-through VT, and the thermally conductive layer TL may constitute a thermally conductive structure through which heat generated from the first semiconductor device CH1 may be transferred to the heat-radiating component HS (i.e., a heat sink). By utilizing the heat-conducting structure and the heat-radiating component HS, the heat generated from the first semiconductor device CH1 can be dissipated to a fluid medium such as air or a liquid coolant, thereby allowing the temperature of the first semiconductor device CH1 to be regulated.

[0043] The thermally conductive layer TL can vertically overlap with the thermally conductive pad TP. The thermally conductive pad TP and the second thermal radiating portion HS2 can have the same planar shape and vertically overlap each other. When viewed in plan view of the wiring structure 600, the thermally conductive pad TP can have an "L" shape. The thermally conductive pad TP can have a second width W2 in the first direction X. For example, the second width W2 can have a value from about 500 μm to about 7,000 μm. When viewed in plan view of the wiring structure 600, the thermally conductive layer TL can have a flat rectangle.

[0044] The thermally conductive layer TL and the second lower conductive pattern 32 may be identical in thickness and material (e.g., a metal such as copper). The thermally conductive pad TP and the second upper conductive pattern 34 may be identical in thickness and material (e.g., a metal such as copper). The thermally conductive pass-through VT and the second circuit pass-through 30 may be identical in thickness and material (e.g., a metal such as copper). Alternatively, the thermally conductive layer TL, the thermally conductive pad TP, and the thermally conductive pass-through VT may each have a different material and thickness (e.g., a greater thickness) than the second lower conductive pattern 32, the second upper conductive pattern 34, and the second circuit pass-through 30. The thermally conductive layer TL, the thermally conductive pad TP, and the thermally conductive pass-through VT may each comprise a material (e.g., a metal or graphene) with a thermal conductivity greater than that of the second lower conductive pattern 32, the second upper conductive pattern 34, and the second circuit pass-through 30, or may each be formed of said material. In an embodiment, when viewed in plan view of the semiconductor package 1000, the area of ​​the thermally conductive layer TL may be greater than or equal to the area of ​​the first semiconductor device CH1. For example, the width of the thermally conductive layer TL in the first direction X may be greater than or equal to the width of the first semiconductor device CH1, and the width of the thermally conductive layer TL in the second direction Y may be greater than or equal to the width of the first semiconductor device CH1. Because the overlap area between the thermally conductive layer TL and the first semiconductor device CH1 is increased, the heat generated from the first semiconductor device CH1 can be transferred to the heat-radiating component HS more effectively.

[0045] Figure 4A and Figure 4B The display shows Figure 2 A magnified view of part P1. Figure 4C The display shows Figure 2 A magnified view of part P2.

[0046] Reference Figure 4A and Figure 4CThe thermally conductive through-hole VT may have a third width W3 in the first direction X. The second circuit through-hole 30 may have a fourth width W4 in the first direction X. The third width W3 may be greater than the fourth width W4. The third width W3 may have a value from about 100 μm to about 250 μm, for example, the fourth width W4 may have a value from about 1 μm to about 70 μm. The relatively large width of the thermally conductive through-hole VT can facilitate heat transfer from the thermally conductive layer TL to the thermally conductive pad TP. The inventive concept is not limited thereto. For example, the third width W3 of the thermally conductive through-hole VT may be the same as the fourth width W4 of the second circuit through-hole 30. When ensuring heat transfer from the thermally conductive layer TL to the thermally conductive pad TP, the thermally conductive through-hole VT and the second circuit through-hole 30 may have the same width. This heat transfer can also be ensured by increasing the number of thermally conductive through-holes VT.

[0047] Reference Figure 2 , Figure 4A and Figure 4B A first thermal interface material layer 550 may be located between the wiring structure 600 and the first sub-semiconductor package 500. The thickness of the first thermal interface material layer 550 may have a value from about 5 μm to about 40 μm. The first thermal interface material layer 550 may contact the bottom surface of the thermally conductive layer TL and the top surface of the first semiconductor device CH1. The first thermal interface material layer 550 may include a grease layer or a thermosetting resin layer, or may be formed from a grease layer or a thermosetting resin layer. The first thermal interface material layer 550 may also include filler particles dispersed in the thermosetting resin layer. The filler particles may include graphene powder or metal powder with high thermal conductivity, or may be formed from graphene powder or metal powder with high thermal conductivity. Alternatively, the filler particles may include one or more of silicon dioxide, aluminum oxide, zinc oxide, and boron nitride, or may be formed from one or more of them. The bottom surface of the first thermal interface material layer 550 may be lower than the top surface of the first molding layer MD1. The first molding layer MD1 may cover the sidewalls of the first thermal interface material layer 550. The first thermal interface material layer 550 can penetrate the second lower passivation layer PS4 and contact the thermally conductive layer TL. For example... Figure 4AAs shown, the sidewalls of the first thermal interface material layer 550 may be aligned with the sidewalls of the first semiconductor device CH1. Alternatively, a portion of the first thermal interface material layer 550 may protrude toward the first molding layer MD1. Therefore, the first molding layer MD1 may have a partially recessed region RC1 on its upper sidewall. It should be understood that when an element is referred to as being "connected" or "bonded" to another element or "located" "on" another element, the element may be directly connected to or directly bonded to said other element or directly located on said other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly connected to" or "directly bonded" to another element or referred to as "contacting" or "in contact with another element," there are no intermediate elements at the contact point.

[0048] The second internal connection member 20 can pass through the first molding layer MD1 and can electrically connect the wiring structure 600 to the first substrate S1 of the first sub-semiconductor package 500. The second internal connection member 20 can connect the first upper conductive pattern 16 to the second lower conductive pattern 32. The second internal connection member 20 can be one or more of solder balls, conductive bumps, and conductive pillars.

[0049] Reference Figure 2 The second thermal interface material layer 650 may be located between the second thermal radiation portion HS2 and the wiring structure 600. The second thermal interface material layer 650 may include or be formed of the same or similar material as the first thermal interface material layer 550. The second thermal interface material layer 650 may penetrate the second upper passivation layer PS3 and may contact the thermally conductive pad TP.

[0050] Refer to Figure 2The second sub-semiconductor package 700 may include a second substrate S2, a plurality of second semiconductor chips CH2 stacked on the second substrate S2, and a second molding layer MD2 covering the second semiconductor chips CH2. The second substrate S2 may be a double-sided printed circuit board or a multilayer printed circuit board. The second substrate S2 may include a fifth body layer C5, a third upper conductive pattern 54 disposed on the top surface of the fifth body layer C5, and a third lower conductive pattern 52 disposed on the bottom surface of the fifth body layer C5. A third circuit through-hole 50 may pass through the fifth body layer C5 and may electrically connect the third upper conductive pattern 54 to the third lower conductive pattern 52. The fifth body layer C5 may include or be formed of the same or similar material as the first body layer C1. A third upper passivation layer PS5 may be disposed on the top surface of the fifth body layer C5 and may partially expose the third upper conductive pattern 54. A third lower passivation layer PS6 may be disposed on the bottom surface of the fifth body layer C5 and may partially expose the third lower conductive pattern 52. The third upper passivation layer PS5 and the third lower passivation layer PS6 may comprise or be formed of the same or similar materials as the first upper passivation layer PS1 and the first lower passivation layer PS2. The second semiconductor chip CH2 may be a memory chip of the same type. The second semiconductor chips CH2 may be offset from each other in the first direction X or in both the first direction X and the second direction Y, and may be stacked to form a stepped structure. The second semiconductor chip CH2 may be connected to the third upper conductive pattern 54 via wire 60.

[0051] The second sub-semiconductor package 700 can be electrically connected to the wiring structure 600 via a third internal connection member 320. The third internal connection member 320 can connect a third lower conductive pattern 52 to a second upper conductive pattern 34. The third internal connection member 320 can be one or more of solder balls, conductive bumps, and conductive pillars.

[0052] The third thermal interface material layer 750 may be located between the second sub-semiconductor package 700 and the first thermal radiation portion HS1. The third thermal interface material layer 750 may comprise or be formed of the same or similar material as the first thermal interface material layer 550. The third thermal interface material layer 750 may contact the top surface of the second molding layer MD2.

[0053] Semiconductor package 1000 according to some exemplary embodiments of the present invention can be configured such that wiring structure 600 includes a thermally conductive layer TL, a thermally conductive pass-through VT, and a thermally conductive pad TP arranged to transfer heat from a first semiconductor device CH1 to a heat-radiating member HS. Therefore, heat generated from the first semiconductor device CH1 can be immediately dissipated. Thus, it may be possible to minimize, reduce, or prevent temperature rise in the first semiconductor device CH1. A decrease in the speed of the first semiconductor device CH1 can be prevented to avoid operational failures of the semiconductor package 1000, which can lead to an improvement in the overall performance of the semiconductor package 1000. The first circuit pass-through 10, the second circuit pass-through 30, and the third circuit pass-through 50 can transmit electrical signals. Although not shown, the third width W3 of the thermally conductive pass-through VT may be greater than the width of the first circuit pass-through 10. The third width W3 of the thermally conductive pass-through VT may be greater than the width of the third circuit pass-through 50. The width of the thermally conductive through-hole VT can be relatively larger than the widths of the first circuit through-hole 10, the second circuit through-hole 30, and the third circuit through-hole 50, in order to facilitate the transfer of heat from the first semiconductor device CH1 to the thermally radiating component HS.

[0054] Figures 5A to 5E Display manufacturing is shown Figure 2 A cross-sectional view of a method for developing semiconductor packages.

[0055] Reference Figure 5A A first substrate S1 can be fabricated. The first substrate S1 may include a chip region R1 and a separation region SR between the chip regions R1. The first substrate S1 may have a reference on each of the chip regions R1. Figure 2 The structures discussed are identical or similar. A first internal connection member 310 can be used to bond a flip chip of the first semiconductor device CH1 to a corresponding chip region R1 of the first substrate S1. A first lower fill layer UF1 can be located between each of the first semiconductor devices CH1 and the first substrate S1. A first initial connection member 20a can be bonded to a first upper conductive pattern 16 located next to the first semiconductor device CH1 on the first substrate S1. The first initial connection member 20a can be a solder ball, a conductive bump, or a conductive pillar.

[0056] Reference Figure 5B A first thermal interface material layer 550 can be formed on the first semiconductor device CH1. A wiring structure 600 can be located on the first substrate S1. The wiring structure 600 can have the same characteristics as the reference... Figure 3A and Figure 3B The same or similar structures are discussed. Wiring structure 600 may be aligned with chip region R1. A second initial connection member 20b may be bonded to the second lower conductive pattern 32 of wiring structure 600. For example, the second initial connection member 20b may be a solder ball, conductive bump, or conductive pillar.

[0057] Reference Figure 5C and Figure 5D A reflow process can be performed after the thermally conductive layer TL of the wiring structure 600 contacts the first thermal interface material layer 550 and the second initial connection member 20b contacts the first initial connection member 20a. In the reflow process, the first initial connection member 20a and the second initial connection member 20b can be melted and connected to each other to form a second internal connection member 20. A molding process can be performed to form a first molding layer MD1 that fills the space between the wiring structure 600 and the first substrate S1. External connection terminals 300 can be bonded to a first lower conductive pattern 18 of the first substrate S1.

[0058] Reference Figure 5D and Figure 5E A sawing or individualization process can be performed to separate the wiring structure 600, the first molding layer MD1, and the first substrate S1 from the separation region SR into individual initial semiconductor packages (PPKGs). In each initial semiconductor package (PPKG), the wiring structure 600 is stacked on a first sub-semiconductor package 500. The initial semiconductor packages (PPKGs) can be tested to select defect-free ones.

[0059] Return to reference Figure 2 and Figure 5E A second sub-semiconductor package 700 can be fabricated. The second sub-semiconductor package 700 can also be tested to select defect-free versions. The second sub-semiconductor package 700 can be flip-chip bonded to the initial semiconductor package PPKG. In this step, the second sub-semiconductor package 700 can be configured to expose the thermal pad TP. For example, in a second sub-semiconductor package 700 having an initial semiconductor package PPKG with which it is flip-chip bonded, the second sub-semiconductor package 700 does not cover the thermal pad TP. A second thermal interface material layer 650 and a third thermal interface material layer 750 can be formed on the second sub-semiconductor package 700 having an initial semiconductor package PPKG with which it is flip-chip bonded. For example, the second thermal interface material layer 650 can be formed on the thermal pad TP, and the third thermal interface material layer 750 can be formed on the second sub-semiconductor package 700. A thermal radiating member HS can be bonded to the second sub-semiconductor package 700 using the third thermal interface material layer 750. Therefore, as... Figure 2 As shown, semiconductor package 1000 can be manufactured.

[0060] Figure 6 It shows along Figure 1 A cross-sectional view taken by line IA-IA'. Figure 7A A plan view showing a wiring structure illustrating some example embodiments of the concept according to the present invention is shown. Figure 7B It shows along Figure 7A A cross-sectional view taken by line IA-IA'.

[0061] Reference Figure 6 , Figure 7A and Figure 7B According to this embodiment, the semiconductor package 1001 may include a first sub-semiconductor package 500, a wiring structure 601, a second sub-semiconductor package 700, and a heat-radiating component HS stacked sequentially on top of each other. The first sub-semiconductor package 500, the second sub-semiconductor package 700, and the heat-radiating component HS may be referenced. Figure 2 Those discussed are the same or similar. The structure of wiring structure 601 can be similar to... Figure 3A and Figure 3B The wiring structure shown is different from that of 600.

[0062] The wiring structure 601 may further include a dielectric support pattern SP bonded to the bottom surface of the second lower passivation layer PS4. The dielectric support pattern SP may include one or more of epoxy resin, wafer adhesive film (DAF), non-conductive film (NCF), and photoresist (PSR) layers, or may be formed from one or more of them. The dielectric support pattern SP may be formed having a plurality of islands spaced apart from each other in the first direction X and the second direction Y. Figure 5C During the manufacturing process, the dielectric support pattern SP can maintain a specific distance between the wiring structure 601 and the first semiconductor device CH1. The dielectric support pattern SP can support the wiring structure 601 and prevent the wiring structure 601 from warping. The semiconductor package 1001 with the dielectric support pattern SP can enhance reliability.

[0063] The thermally conductive layer TL of the wiring structure 601 can have a grid shape. When viewed in a plan view, the thermally conductive layer TL can have multiple island-like openings H1 spaced apart from each other. The openings H1 can be filled with a second lower passivation layer PS4. The dielectric support pattern SP can overlap with portions of the second lower passivation layer PS4 filling the openings H1. Other configurations may be referenced. Figure 3A and Figure 3B Those that are the same or similar in the discussion.

[0064] Figure 8A and Figure 8B The display shows Figure 6 A magnified view of part P3.

[0065] Reference Figure 8AThe dielectric support pattern SP can contact the top surface of the first semiconductor device CH1. The first thermal interface material layer 550, adjacent to the edge of the first semiconductor device CH1, can protrude laterally beyond the first semiconductor device CH1, thereby contacting the upper sidewall of the first semiconductor device CH1. The first thermal interface material layer 550 can contact the bottom surface of the second lower passivation layer PS4. The first molding layer MD1 can have a recessed area RC1 on its upper sidewall that contacts the first thermal interface material layer 550.

[0066] Alternatively, such as Figure 8B As shown, the dielectric support pattern SP may be spaced apart from the top surface of the first semiconductor device CH1. A portion of the first thermal interface material layer 550 may be located between the dielectric support pattern SP and the first semiconductor device CH1. Other structural features may be referenced. Figure 8A Those that are the same or similar in the discussion.

[0067] Figure 9 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0068] Reference Figure 9 The semiconductor package 1002 according to this embodiment may include a first sub-semiconductor package 500, a wiring structure 600, a second sub-semiconductor package 700, and a heat-radiating member HS stacked sequentially on top of each other. The first sub-semiconductor package 500, the wiring structure 600, and the second sub-semiconductor package 700 may be referenced to... Figure 2 Those discussed are the same or similar. The heat-radiating component HS can have the same... Figure 2 The structures differ. In this embodiment, the heat-radiating component HS can have a uniform thickness. The second heat-radiating portion HS2 of the heat-radiating component HS can have an L-shaped cross-section. The second thermal interface material layer 650 can extend from the gap between the second heat-radiating portion HS2 and the wiring structure 600 to the gap between the second heat-radiating portion HS2 and the sidewall of the second sub-semiconductor package 700. The second thermal interface material layer 650 can also extend to the gap between the first heat-radiating portion HS1 and the top surface of the second sub-semiconductor package 700. The second underfill layer UF2 can fill the space between the second sub-semiconductor package 700 and the wiring structure 600. The second underfill layer UF2 can include or be formed of the same or similar material as the first underfill layer UF1. Other configurations may be referenced. Figures 1 to 4C Those that are the same or similar in the discussion.

[0069] Figure 10 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0070] Reference Figure 10 According to this embodiment, the semiconductor package 1003 may include a first sub-semiconductor package 501, a wiring structure 602, a second sub-semiconductor package 700, and a thermal radiating member HS stacked sequentially on top of each other. The first sub-semiconductor package 501 may be shaped to resemble a chip last-type fan-out wafer-level package (FOWLP). The first sub-semiconductor package 501 may include a first redistribution substrate RD1, a first semiconductor device CH1 mounted on the first redistribution substrate RD1, and a first molding layer MD1 covering the first semiconductor device CH1. The first semiconductor device CH1 may be flip-chip bonded to the first redistribution substrate RD1 via a first internal interconnect member 310.

[0071] The first redistribution substrate RD1 may include a first redistribution dielectric layer IL1, a second redistribution dielectric layer IL2, a third redistribution dielectric layer IL3, and a fourth redistribution dielectric layer IL4 stacked sequentially on top of each other. The first redistribution dielectric layer IL1, the second redistribution dielectric layer IL2, the third redistribution dielectric layer IL3, and the fourth redistribution dielectric layer IL4 may be photoimageable dielectric (PID) layers. A first redistribution pattern 342, a second redistribution pattern 344, and a third redistribution pattern 346 may be disposed between the first redistribution dielectric layer IL1, the second redistribution dielectric layer IL2, the third redistribution dielectric layer IL3, and the fourth redistribution dielectric layer IL4. The first redistribution pattern 342, the second redistribution pattern 344, and the third redistribution pattern 346 may include a through-hole portion VP and a line portion LP integrally bonded to each other. The through-hole portion VP can be positioned below the line portion LP. The barrier / seed pattern SL can be located between the first redistribution pattern 342 and the first redistribution dielectric layer IL1, between the second redistribution pattern 344 and the second redistribution dielectric layer IL2, and between the third redistribution pattern 346 and the third redistribution dielectric layer IL3. The barrier / seed pattern SL can include barrier layers and seed layers stacked sequentially on top of each other. The barrier layer can include a metal nitride layer or can be formed from a metal nitride layer. The seed layer can include the same metal as the first redistribution pattern 342, the second redistribution pattern 344, and the third redistribution pattern 346, or can be formed from said same metal.

[0072] A first redistribution bump 340 may be disposed in a first redistribution dielectric layer IL1. A first redistribution pad 348 may be disposed in a fourth redistribution dielectric layer IL4. An external connection terminal 300 may be bonded to the first redistribution bump 340. A first molding layer MD1 may cover the sidewalls of the first semiconductor device CH1 and the top surface of the first redistribution substrate RD1. A first molding pass-through MV1 may pass through the first molding layer MD1 and may contact the first redistribution pad 348 of the first redistribution substrate RD1. The first molding pass-through MV1 may comprise or be formed of a metal such as copper. The first molding pass-through MV1 may electrically connect the wiring structure 602 to the first redistribution substrate RD1.

[0073] Figure 11 It is shown Figure 10 A magnified view of part P4.

[0074] Reference Figure 10 and Figure 11 The wiring structure 602 may have a structure similar to that of the first redistribution substrate RD1. In this embodiment, the wiring structure 602 may be referred to as the second redistribution substrate. The wiring structure 602 may include a fifth redistribution dielectric layer IL5, a sixth redistribution dielectric layer IL6, and a seventh redistribution dielectric layer IL7, and may also include a fourth redistribution pattern 352 and a fifth redistribution pattern 354 between the fifth redistribution dielectric layer IL5, the sixth redistribution dielectric layer IL6, and the seventh redistribution dielectric layer IL7. The sixth redistribution pattern 356 may be disposed on the seventh redistribution dielectric layer IL7. Like the first redistribution pattern 342, the second redistribution pattern 344, and the third redistribution pattern 346, each of the fourth redistribution pattern 352, the fifth redistribution pattern 354, and the sixth redistribution pattern 356 may also include a through-hole portion VP and a line portion LP. The through-piece portion VP of the first redistribution pattern 342, the second redistribution pattern 344, the third redistribution pattern 346, the fourth redistribution pattern 352, the fifth redistribution pattern 354 and the sixth redistribution pattern 356 may have inclined sidewalls.

[0075] The barrier / seed pattern SL may be located between the fourth redistribution pattern 352 and the fifth redistribution dielectric layer IL5, between the fifth redistribution pattern 354 and the sixth redistribution dielectric layer IL6, and between the sixth redistribution pattern 356 and the seventh redistribution dielectric layer IL7. The second redistribution bump 350 may be disposed in the fifth redistribution dielectric layer IL5.

[0076] The first molded through-hole MV1 can connect the second redistribution bump 350 to the first redistribution pad 348. The wiring structure 602 may include a thermally conductive layer TL, a thermally conductive pad TP, and a thermally conductive through-hole structure VST connecting the thermally conductive layer TL to the thermally conductive pad TP. The thermally conductive through-hole structure VST may include a first thermally conductive through-hole portion VT1, a second thermally conductive through-hole portion VT2, and a third thermally conductive through-hole portion VT3 stacked on top of each other. The term "thermally conductive through-hole portion" may be referred to as a "sub-through-hole".

[0077] The first thermally conductive punch-through portion VT1, the second thermally conductive punch-through portion VT2, and the third thermally conductive punch-through portion VT3 may have inclined sidewalls. The thermally conductive punch-through structure VST may also include a barrier / seed pattern SL, which is located between the first thermally conductive punch-through portion VT1 and the fifth redistribution dielectric layer IL5, between the second thermally conductive punch-through portion VT2 and the sixth redistribution dielectric layer IL6, and between the third thermally conductive punch-through portion VT3 and the seventh redistribution dielectric layer IL7. The barrier / seed pattern SL may also be located between the thermally conductive pad TP and the seventh redistribution dielectric layer IL7.

[0078] The first thermally conductive through-hole portion VT1, the second thermally conductive through-hole portion VT2, and the third thermally conductive through-hole portion VT3 may each have a fifth width W5, which is greater than the sixth width W6 of each of the through-hole portions VP of the fourth redistribution pattern 352, the fifth redistribution pattern 354, and the sixth redistribution pattern 356. In an embodiment, the fifth width W5 may be the minimum width of each of the first thermally conductive through-hole portion VT1, the second thermally conductive through-hole portion VT2, and the third thermally conductive through-hole portion VT3, and the sixth width W6 may be the minimum width of each of the through-hole portions VP. The first thermally conductive through-hole portion VT1 may have a width that increases from the fifth width W5 in the third direction Z. In an embodiment, the width of the first thermally conductive through-hole portion VT1 may gradually increase from the fifth width W5 in the third direction Z. This increase in the width of the first thermally conductive through-hole portion VT1 may be applied to the remaining thermally conductive through-hole portions VT2 and VT3. The width of each through-hole portion VP may increase from the sixth width W6 in the third direction Z. For example, the fifth width W5 can have a value from about 100 μm to about 250 μm. For example, the sixth width W6 can have a value from about 1 μm to about 70 μm.

[0079] The thermally conductive layer TL can have the same material and thickness as the second redistribution bump 350. The thermally conductive pad TP can be connected to the third thermally conductive through-hole portion VT3 and can have the same thickness and material as the line portion LP of the sixth redistribution pattern 356. The first thermally conductive through-hole portions VT1, VT2, and VT3 can have the same thickness and material as the through-hole portions VP of the fourth redistribution pattern 352, fifth redistribution pattern 354, and sixth redistribution pattern 356. Alternatively, the thermally conductive layer TL, the thermally conductive pad TP, and the first thermally conductive through-hole portions VT1, VT2, and VT3 can have different materials (e.g., a material with higher thermal conductivity) and thicknesses (e.g., a greater thickness) than the fourth redistribution pattern 352, fifth redistribution pattern 354, and sixth redistribution pattern 356.

[0080] exist Figure 10 and Figure 11 In the illustrated embodiment, it is possible to exclude Figure 2 The semiconductor package 1003 is implemented with a first thermal interface material layer 550. In this embodiment, the second thermal interface material layer 650 may cover the top surface and sidewalls of the thermal pad TP and the sidewalls of the barrier / seed pattern SL below the thermal pad TP. The bottom surface of the fifth redistribution dielectric layer IL5 may be lower than the bottom surface of the second redistribution bump 350 and the bottom surface of the thermal conductive layer TL. The first molding layer MD1 may surround the sidewalls of the first molding through-hole MV1 and the sidewalls of the first semiconductor device CH1. In this embodiment, the upper surface of the first molding layer MD1 may be uneven, and the first molding layer MD1 may be located between the upper portion of the first molding through-hole MV1 adjacent to each other in the first direction X and the lower portion of the fifth redistribution dielectric layer IL5, and between the upper portion of the first semiconductor device CH1 adjacent to each other in the first direction X and the lower portion of the first redistribution dielectric layer IL5. The topmost upper surface of the first molding layer MD1 may contact the bottom surface of the second redistribution bump 350 and the bottom surface of the thermal conductive layer TL. Other configurations can be found in the reference. Figures 1 to 4C Those that are the same or similar in the discussion.

[0081] Figure 12 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0082] Reference Figure 12According to this embodiment, the semiconductor package 1004 may include a first sub-semiconductor package 502, a wiring structure 602, a second sub-semiconductor package 700, and a thermal radiating member HS stacked sequentially on top of each other. The first sub-semiconductor package 502 may be shaped similarly to a chip-first-type fan-out wafer-level package (FOWLP). The first sub-semiconductor package 502 may include a first redistribution substrate RD1, a first semiconductor device CH1 mounted on the first redistribution substrate RD1, and a first molding layer MD1 covering the first semiconductor device CH1. The first semiconductor device CH1 may contact the first redistribution substrate RD1. The first sub-semiconductor package 502 does not contain... Figure 10 The first lower filler layer UF1 and the first internal connecting member 310.

[0083] Each of the first redistribution pattern 342, the second redistribution pattern 344, and the third redistribution pattern 346 included in the first redistribution substrate RD1 may include a through-hole portion VP and a line portion LP integrally bonded to each other. The through-hole portion VP may be located on the line portion LP. A barrier / seed pattern SL may be located between the first redistribution pattern 342 and the second redistribution dielectric layer IL2, between the second redistribution pattern 344 and the third redistribution dielectric layer IL3, and between the third redistribution pattern 346 and the fourth redistribution dielectric layer IL4. The first redistribution dielectric layer IL1 may have a first redistribution bump 340 therein that contacts the line portion LP of the first redistribution pattern 342. A first redistribution pad 348 may be located on the fourth redistribution dielectric layer IL4. Other configurations may be referenced. Figure 10 and Figure 11 Those that are the same or similar in the discussion.

[0084] Figure 13 It shows along Figure 1 A cross-sectional view taken by line IA-IA'.

[0085] Reference Figure 13 According to this embodiment, the semiconductor package 1005 may include a first sub-semiconductor package 503, a wiring structure 602, a second sub-semiconductor package 700, and a thermal radiating member HS stacked sequentially on top of each other. The first sub-semiconductor package 503 may be shaped similarly to a back-chip fan-out panel-level package (FOPLP). The first sub-semiconductor package 503 may include a first redistribution substrate RD1, a connection substrate 900 disposed on the first redistribution substrate RD1, and a first semiconductor device CH1 mounted on the first redistribution substrate RD1.

[0086] The connection substrate 900 may include a cavity region CV located at its center. A first semiconductor device CH1 may be disposed in the cavity region CV. The connection substrate 900 may include a plurality of base layers 910 and conductive structures 920. The base layers 910 may include or be formed of a dielectric material. For example, the base layer 910 may include or be formed of a carbon-based material, ceramic, or polymer. The conductive structure 920 may include a connection pad 921, a first connection pass-through 922, a connection line 923, and a second connection pass-through 924. The connection substrate 900 may be connected to a first redistribution substrate RD1 via a fourth internal connection member 305. A second underfill layer UF2 may be located between the connection substrate 900 and the first redistribution substrate RD1. A first molding layer MD1 may fill the space between the first semiconductor device CH1 and the inner wall of the cavity region CV of the connection substrate 900. The second connection pass-through 924 of the first sub-semiconductor package 503 may contact the second redistribution bump 350 of the wiring structure 602. Other configurations may be referenced. Figure 10 and Figure 11 Those that are the same or similar in the discussion.

[0087] Figure 14 A plan view of a semiconductor package showing some example embodiments of the concept according to the present invention is shown. Figure 15 It shows along Figure 14 A cross-sectional view taken by line IA-IA'.

[0088] Reference Figure 14 and Figure 15 According to this embodiment, the semiconductor package 1006 may include a first sub-semiconductor package 500 and a wiring structure 603 stacked sequentially on top of each other. A second sub-semiconductor package 100 and a third sub-semiconductor package 200 may be disposed on the wiring structure 603 and may be spaced apart from each other in a first direction X. A thermal radiating member HS may cover the second sub-semiconductor package 100 and the third sub-semiconductor package 200. The thermal radiating member HS may include a first thermal radiating portion HS1 overlapping the second sub-semiconductor package 100 and the third sub-semiconductor package 200, and may also include a second thermal radiating portion HS2 extending from the sidewall of the first thermal radiating portion HS1 toward the wiring structure 603. When the semiconductor package 1006 is viewed in plan view, the second thermal radiating portion HS2 may have a figure-eight shape. The second thermal radiating portion HS2 may also be located between the second sub-semiconductor package 100 and the third sub-semiconductor package 200. In this embodiment, each of the second sub-semiconductor package 100 and the third sub-semiconductor package 200 may be surrounded by the second thermal radiating portion HS2.

[0089] Wiring structure 603 may include a thermally conductive pad TP that overlaps with the second thermally radiating portion HS2. When viewed in plan view of semiconductor package 1006, the thermally conductive pad TP may have a figure-eight shape. Multiple thermally conductive through-holes VT may vertically overlap with the second thermally radiating portion HS2 between the second sub-semiconductor package 100 and the third sub-semiconductor package 200.

[0090] The second sub-semiconductor package 100 may include a second substrate 101, a second semiconductor chip 102 mounted on the second substrate 101 via wires 103, and a second molding layer 104 covering the second semiconductor chip 102. The third sub-semiconductor package 200 may include a plurality of second semiconductor chips 202 stacked on the first semiconductor chip 201. Each of the first semiconductor chip 201 and the second semiconductor chip 202 may include a through-hole 203. The sidewalls of the second semiconductor chips 202 may be covered by the third molding layer 204. The third sub-semiconductor package 200 may be a high-bandwidth memory (HBM) chip, wherein the first semiconductor chip 201 may be a logic device and the second semiconductor chip 202 may be a memory device. A third thermal interface material layer 750 may be located between the first thermally radiating portion HS1 and the second sub-semiconductor package 100, and between the first thermally radiating portion HS1 and the third sub-semiconductor package 200. Other configurations may be referenced. Figures 1 to 4C Those that are the same or similar in the discussion.

[0091] Figures 16A to 16E A plan view of a semiconductor package showing some example embodiments of the concept according to the present invention is shown.

[0092] Reference Figure 16A According to this embodiment, the semiconductor package 1007 can be configured such that when the semiconductor package 1007 is viewed in a plan view, the second thermally radiating portion HS2 and the thermally conductive pad TP have a "C" shape.

[0093] Reference Figure 16B According to this embodiment, the semiconductor package 1008 can be configured such that when the semiconductor package 1008 is viewed in a plan view, the second thermally radiating portion HS2 and the thermally conductive pad TP have an "I" shape.

[0094] Reference Figure 16C According to this embodiment, the semiconductor package 1009 can be configured such that when viewed in a plan view, the second thermally radiating portion HS2 and the thermally conductive pad TP have an "O" shape. The second thermally radiating portion HS2 can surround the second sub-semiconductor package 700.

[0095] Reference Figure 16DAccording to this embodiment, the semiconductor package 1010 can be configured such that, when viewed in a plan view, the second thermally radiating portion HS2 and the thermally conductive pad TP have a grid shape. Second sub-semiconductor packages 700a, 700b, 700c, and 700d can be arranged two-dimensionally along a first direction X and a second direction Y. The second thermally radiating portion HS2 can be located between the second sub-semiconductor packages 700a to 700d, while surrounding the second sub-semiconductor packages 700a to 700d.

[0096] Reference Figure 16E According to this embodiment, the semiconductor package 1011 can be configured such that, when viewed in a plan view, the second thermally radiating portion HS2 and the thermally conductive pad TP have a grid shape or an "E" shape. Second sub-semiconductor packages 700a and 700b can be linearly arranged in a second direction Y, different from the first direction X. The second sub-semiconductor packages 700a and 700b can be spaced apart from each other in the second direction Y. The second thermally radiating portion HS2 can be located between the second sub-semiconductor packages 700a and 700b.

[0097] exist Figures 16A to 16E In the embodiments shown, other configurations besides those discussed above may be used in conjunction with the referenced embodiments. Figures 1 to 15 Those that are the same or similar in the discussion.

[0098] Figure 17A and Figure 17B A plan view showing a wiring structure illustrating some example embodiments of the concept according to the present invention is shown.

[0099] Reference Figure 17A According to this embodiment, the wiring structure 604 may include a thermally conductive layer TL having island-shaped sections spaced apart from each other along a first direction X and a second direction Y. Thermally conductive through-holes VT may be arranged in the same or similar manner as the thermally conductive layer TL. Thermally conductive pads TP may include protrusions TPP connecting multiple thermally conductive through-holes VT. Other configurations may be referenced. Figure 3A and Figure 3B Those that are the same or similar in the discussion.

[0100] Reference Figure 17B The wiring structure 605 according to this embodiment may include a heat-conducting layer TL, which has a mesh shape when viewed in a plan view. Although not shown, the planar shape of the heat-conducting layer TL is not limited to... Figure 3A , Figure 17A and Figure 17B Instead of those shown, they can have a cross shape, a circle, a closed loop, or any other shape.

[0101] The semiconductor package according to the present invention can be configured such that the wiring structure includes a thermally conductive layer, thermally conductive through-holes, and thermally conductive pads, so that heat is discharged from a first semiconductor device of a first sub-semiconductor package to a heat sink of the semiconductor package. Therefore, a decrease in the speed of the first semiconductor device can be prevented to avoid operational failures of the semiconductor package, thereby increasing the operating speed of the semiconductor package, which can lead to an improvement in the overall performance of the semiconductor package.

[0102] The wiring structure conceived according to the present invention may include a thermally conductive through-hole with a width greater than that of the circuit through-hole, and this configuration can realize the advantage of thermal radiation.

[0103] Although the inventive concept has been described with reference to some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the scope and spirit of the inventive concept. Figures 1 to 17B The embodiments can be combined with each other.

Claims

1. A semiconductor package, comprising: A first sub-semiconductor device, an intermediate layer, and a second sub-semiconductor device are stacked on top of each other such that the intermediate layer is configured to connect the first sub-semiconductor device and the second sub-semiconductor device to each other. as well as A heat sink that covers the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip stacked on the first substrate. The intermediate layer includes: Dielectric layer, A thermally conductive layer that is in contact with the bottom surface of the dielectric layer. The first thermally conductive pad is in contact with the top surface of the dielectric layer, and Multiple thermally conductive through-holes pass through the dielectric layer and connect the thermally conductive layer to the first thermally conductive pad. The bottom surface of the thermally conductive layer is adjacent to and connected to the top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer of the intermediate layer, without overlapping with the first thermal pad of the intermediate layer, and The heat sink also covers the first thermally conductive pad of the intermediate layer for connection with the first thermally conductive pad of the intermediate layer.

2. The semiconductor package according to claim 1, further comprising: A first thermal interface material layer is located between the first sub-semiconductor device and the intermediate layer. The first thermal interface material layer is in contact with the thermally conductive layer and the first semiconductor chip.

3. The semiconductor package according to claim 2, in, The thickness of the first thermal interface material layer has a value ranging from 5 μm to 40 μm.

4. The semiconductor package according to claim 3, in, The first sub-semiconductor device further includes: A first molding layer covers the sidewalls of the first semiconductor chip and the top surface of the first substrate, and The first molding layer covers the sidewall of the first thermal interface material layer.

5. The semiconductor package according to claim 4, in, A portion of the first thermal interface material layer protrudes outward beyond the sidewall of the first semiconductor chip, and The upper sidewall of the first molding layer has a recessed area that contacts the first thermal interface material layer.

6. The semiconductor package according to claim 2, in, The intermediate layer also includes: A first lower passivation layer covers the bottom surface of the dielectric layer and exposes the thermally conductive layer. The first thermal interface material layer passes through the first lower passivation layer and contacts the thermally conductive layer.

7. The semiconductor package according to claim 1, in, The intermediate layer also includes: Multiple first conductive patterns are in contact with the top surface of the dielectric layer; Multiple first conductive patterns are in contact with the bottom surface of the dielectric layer; and Multiple first circuit through-holes pass through the dielectric layer. Each of the plurality of first circuit through-pieces connects a corresponding one of the plurality of first upper conductive patterns to a corresponding one of the plurality of first lower conductive patterns, and Wherein, the first width of each of the plurality of thermally conductive through-holes in a first direction parallel to the bottom surface of the dielectric layer of the intermediate layer is greater than the second width of each of the plurality of first circuit through-holes in the first direction.

8. The semiconductor package according to claim 7, in, The first width has a value from 100 μm to 250 μm, and The second width has a value ranging from 1 μm to 70 μm.

9. The semiconductor package according to claim 1, in, The heat sink includes: The first heat sink portion overlaps with the second sub-semiconductor device; and The second heat sink section extends from the sidewall of the first heat sink section toward the intermediate layer, and The width of the second heat sink portion ranges from 500 μm to 7,000 μm.

10. The semiconductor package according to claim 1, in, The heat sink includes: The first heat sink portion overlaps with the second sub-semiconductor device; and The second heat sink portion extends from the sidewall of the first heat sink portion toward the intermediate layer. When viewed in a plan view, the second heat sink portion has an "I" shape, an "L" shape, a "C" shape, an "E" shape, an "O" shape, an "8" shape, or a grid shape.

11. The semiconductor package according to claim 1, in, The heat sink includes: The first heat sink portion overlaps with the second sub-semiconductor device; and The second heat sink section extends from the sidewall of the first heat sink section toward the intermediate layer, and The second heat sink portion is thicker than the first heat sink portion.

12. The semiconductor package according to claim 1, in, The width of the first thermally conductive pad has a value ranging from 500 μm to 7,000 μm.

13. The semiconductor package according to claim 1, in, When the semiconductor package is viewed in a plan view, the first thermal pad has an "I" shape, an "L" shape, a "C" shape, an "E" shape, an "O" shape, an "8" shape, or a grid shape.

14. The semiconductor package according to claim 1, in, The intermediate layer also includes: A first lower passivation layer covers the bottom surface of the dielectric layer and exposes the thermally conductive layer; and A dielectric support pattern that contacts the first lower passivation layer and the first semiconductor chip.

15. The semiconductor package of claim 14, further comprising: A first thermal interface material layer is disposed between the intermediate layer and the first sub-semiconductor device. The first thermal interface material layer is located between the dielectric support pattern and the first semiconductor chip of the first sub-semiconductor device.

16. The semiconductor package according to claim 1, further comprising: The third sub-semiconductor device is located on the intermediate layer and adjacent to the second sub-semiconductor device. The intermediate layer further includes: A second thermally conductive pad contacts a portion of the dielectric layer, the portion of which is disposed between the second sub-semiconductor device and the third sub-semiconductor device. A portion of the heat sink covers the second thermally conductive pad for connection to the second thermally conductive pad.

17. The semiconductor package according to claim 1, in, Each of the plurality of thermally conductive through-holes includes a plurality of sub-through-holes stacked on top of each other.

18. The semiconductor package according to claim 1, in, The first substrate has a first thickness. The intermediate layer has a second thickness, and Wherein, the second thickness is less than the first thickness.

19. A semiconductor package, comprising: First semiconductor device; An intermediate layer, which is located on the first sub-semiconductor device; A first thermal interface material layer is located between the first sub-semiconductor device and the intermediate layer; A second sub-semiconductor device is located on the intermediate layer, and the second sub-semiconductor device exposes a portion of the intermediate layer; A heat sink that covers the top surface of the second sub-semiconductor device, the sidewalls of the second sub-semiconductor device, and the portion thereof of the intermediate layer; as well as A second thermal interface material layer is disposed between the portion of the heat sink and the intermediate layer. The first sub-semiconductor device includes a first substrate and a first semiconductor chip stacked on the first substrate. The intermediate layer includes: Dielectric layer; A thermally conductive layer that is in contact with the bottom surface of the dielectric layer; Thermally conductive pads that are in contact with the top surface of the dielectric layer; and Multiple thermally conductive through-holes pass through the dielectric layer and connect the thermally conductive layer to the thermally conductive pads. The second sub-semiconductor device exposes the thermally conductive pads of the intermediate layer. The first thermal interface material layer is in contact with the bottom surface of the thermally conductive layer and the top surface of the first semiconductor chip. The second thermal interface material layer is in contact with the top surface of the thermally conductive pad and the bottommost surface of the heat sink, and The width of the thermally conductive pad ranges from 500 μm to 7,000 μm.

20. A semiconductor package comprising a first sub-semiconductor device, an intermediate layer, and a second sub-semiconductor device, stacked on top of each other such that the intermediate layer is configured to connect the first sub-semiconductor device and the second sub-semiconductor device to each other. in, The intermediate layer includes: Dielectric layer, A thermally conductive layer and a plurality of lower conductive patterns are contacted with and spaced apart from the bottom surface of the dielectric layer, wherein the bottom surface of the thermally conductive layer is adjacent to and connected to the top surface of the first sub-semiconductor device. Thermally conductive pads and multiple upper conductive patterns are in contact with the top surface of the dielectric layer and are spaced apart from each other. Multiple thermally conductive through-holes pass through the dielectric layer and connect the thermally conductive layer to the thermally conductive pads, and Multiple circuit through-holes pass through the dielectric layer. Each of the plurality of circuit through-holes connects a corresponding one of the plurality of upper conductive patterns to a corresponding one of the plurality of lower conductive patterns. The second sub-semiconductor device is disposed on the dielectric layer of the intermediate layer, without overlapping with the thermal pads of the intermediate layer, and Wherein, the first width of each of the plurality of thermally conductive through-holes in a first direction parallel to the bottom surface of the dielectric layer is greater than the second width of each of the plurality of circuit through-holes in the first direction.

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