Source / drain integration in three-node access devices for vertical three-dimensional (3D) memory

Abstract

This application relates to source / drain integration in three-node access devices of vertical three-dimensional (3D) memory. An example method includes a method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeated iterations to form a vertical stack. A first vertical opening is formed using an etching process to expose vertical sidewalls of a first region of the sacrificial material in the vertical stack. The first region is selectively etched to form a first horizontal opening that removes the sacrificial material and is separated from the first vertical opening by a first horizontal distance. A multi-layer first source / drain material, a channel material, and a second source / drain material are deposited in the first horizontal opening to form a three-node access device of a memory cell among the array of memory cells of the vertical stack.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to source / drain integration in a three-node access device for a vertical three-dimensional (3D) memory. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, cellular phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, non-volatile read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), and so on.

[0003] As design rules shrink, less semiconductor space is available to fabricate memories including DRAM arrays. A corresponding memory cell for DRAM may include access means, such as transistors, having first and second source / drain regions separated by a channel region. A gate may be opposite to and separated from the channel region by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. A DRAM cell may include storage nodes, such as capacitor cells, coupled to digital lines via access means. Access means may be activated (e.g., to select a cell) via access lines coupled to access transistors. Capacitors may store charge (e.g., logic "1" or "0") corresponding to the data value of the corresponding cell. Summary of the Invention

[0004] One aspect of this disclosure relates to a method for forming an array of vertically stacked memory cells having horizontally oriented access means and vertically oriented access lines, the method comprising: repeatedly iteratively depositing alternating layers of dielectric and sacrificial materials to form a vertical stack; forming a first vertical opening using a first etching process to expose vertical sidewalls of a first portion of the sacrificial material in the vertical stack; selectively etching the first portion of the sacrificial material to form a first horizontal opening, the first horizontal opening removing the sacrificial material in a first region and being spaced apart from the first vertical opening by a first horizontal distance to form a first source / drain region and a second source / drain region horizontally separated by a channel region; and depositing multiple layers of first source / drain material, channel material, and second source / drain material in the first horizontal opening to form a three-node access means for the memory cells in the array of vertically stacked memory cells.

[0005] Another aspect of this disclosure relates to a method for forming an array of vertically stacked memory cells, the array having horizontally oriented access means and vertically oriented access lines, the method comprising: repeatedly iteratively depositing alternating layers of dielectric material and sacrificial material to form a vertical stack; forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction, extending through the vertical stack, and primarily in the second horizontal direction to form an elongated vertical column with sidewalls in the vertical stack; conformally depositing a first conductive material on the gate dielectric material in the first vertical openings; and removing portions of the first conductive material to form a plurality of individual vertical lines along the sidewalls of the elongated vertical column. Access lines; forming a second vertical opening to expose a vertical sidewall adjacent to a first portion of the sacrificial material in the vertical stack; selectively etching the first portion of the sacrificial material to form a first horizontal opening, the first horizontal opening removing the sacrificial material in a first region and spaced a first horizontal distance from the first vertical opening; and using a selective deposition process to deposit in the first horizontal opening: a multilayer first source / drain material electrically contacting a memory node at the distal end of the first horizontal opening relative to the first vertical opening; a channel material; and a multilayer second source / drain material for forming a three-node access means for memory cells in an array of vertically stacked memory cells.

[0006] Another aspect of this disclosure relates to a method for forming an array of vertically stacked memory cells, the array having horizontally oriented access means and vertically oriented access lines, the method comprising: repeatedly iteratively depositing alternating layers of dielectric material and sacrificial material to form a vertical stack; forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction, extending through the vertical stack, and primarily in the second horizontal direction to form an elongated vertical column with sidewalls in the vertical stack; conformally depositing a first conductive material on the gate dielectric material in the first vertical openings; removing portions of the first conductive material to form a plurality of individual vertical access lines along the sidewalls of the elongated vertical column; and forming second vertical openings using a first etching process. This exposes the vertical sidewalls of a first portion of the sacrificial material in the vertical stack; selectively etches the first portion of the sacrificial material to form a first horizontal opening, the first horizontal opening removing the sacrificial material in a first region and spaced a first horizontal distance from the first vertical opening; and deposits in the first horizontal opening using an atomic layer deposition (ALD) process: a first source / drain material electrically contacting a memory node at the distal end of the first horizontal opening relative to the first vertical opening; a channel material electrically contacting the first source / drain material; and a multilayer second source / drain material electrically contacting the channel material to form a three-node access device for memory cells in an array of vertically stacked memory cells.

[0007] Another aspect of this disclosure relates to a memory device comprising: an array of vertically stacked memory cells, the array of vertically stacked memory cells including: a horizontally oriented three-node access device having multiple layers of first source / drain regions and multiple layers of second source / drain regions separated by a channel region, and a gate opposite to and separated from the channel regions by a gate dielectric, wherein the three-node access device does not have direct electrical body contact with the body region of the three-node access device or the channel region; a vertically oriented access line coupled to the gate and separated from the channel regions by the gate dielectric; a horizontally oriented memory node electrically coupled to the multiple layers of first source / drain regions of the three-node access device; and a horizontally oriented digital line electrically coupled to the multiple layers of second source / drain regions of the three-node access device. Attached Figure Description

[0008] Figure 1 This is a schematic illustration of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0009] Figure 2 This is a perspective view illustrating a portion of a three-node access device in a vertical three-dimensional (3D) memory array according to several embodiments of the present disclosure.

[0010] Figure 3 This is a perspective view illustrating a portion of a three-node access device in a vertical three-dimensional (3D) memory cell according to several embodiments of the present disclosure.

[0011] Figure 4 Examples of methods for forming a vertically stacked memory cell array to form a three-node access device at a stage of a semiconductor manufacturing process are shown according to several embodiments of the present disclosure.

[0012] Figures 5A-5B Examples of methods for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, according to several embodiments of the present disclosure, are shown.

[0013] Figures 6A-6E Examples of methods for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, according to several embodiments of the present disclosure, are shown.

[0014] Figures 7A-7E Examples of methods for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, according to several embodiments of the present disclosure, are shown.

[0015] Figures 8A-8E Examples of methods for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, according to several embodiments of the present disclosure, are shown.

[0016] Figures 9A-9E Examples of methods for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, according to several embodiments of the present disclosure, are shown.

[0017] Figure 10A-10D Examples of source / drain integration in a horizontally oriented three-node access device coupled to a horizontally oriented memory node at a specific point in time during semiconductor manufacturing are illustrated according to several embodiments of the present disclosure.

[0018] Figure 11A-11D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure.

[0019] Figure 12A-12DExamples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure.

[0020] Figures 13A-13D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure.

[0021] Figures 14A-14D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure.

[0022] Figures 15A-15D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure.

[0023] Figure 16A-16D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure.

[0024] Figure 17 Examples of horizontally oriented three-node access devices are shown, which are coupled to horizontally oriented memory nodes and to vertically oriented access lines and horizontally oriented digital lines, according to several manufacturing techniques described herein.

[0025] Figure 18 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0026] Embodiments of this disclosure describe a three-node access device for a vertical three-dimensional (3D) memory. The three-node horizontal access device is configured without a body region contact. As used herein, three-node is intended to refer to an access device comprising: (1) a first source / drain region, (2) a second source / drain region separated by a channel region, and (3) one or more gates opposite the channel region. In the three-node access device, there is no direct electrical contact between the body contact line and the body region and / or channel of the access device to control the body region or channel of the access device. Therefore, the overhead of the semiconductor manufacturing process is reduced because such body contacts do not need to be formed.

[0027] The three-node horizontal access device is integrated with both the vertical access line and the horizontal digital line. According to an embodiment, the three-node horizontal access device can be formed with an alternative channel, resulting in fewer minority carriers in the channel region, allowing operation, for example, without minority carriers, and thus eliminating the need to control the body potential of the access device's main body region. The first and second source / drain regions can be formed using methods and material configurations that minimize the injection barrier at contact with other nodes and the alternative channel material, reduce contact resistance, and increase the output drive of the access device (e.g., a thin-film transistor (TFT)). The formation of dopant and silicide layers during source / drain region formation can also be avoided. A material configuration is provided to suppress leakage current in the back channel region. Advantages of the structures and processes described herein may include lower turn-off current (Ioff) and / or lower gate / drain induced leakage (GIDL) of the access device compared to silicon-based (Si-based) access devices, and increased drive current and current drain-source (IDS) induced input (IDS-Lin) under conditions of low drain-source-gate potential (VDS).

[0028] In some embodiments, the channel and / or source / drain region replacement fabrication steps can be performed after the capacitor cell formation process, thus reducing the thermal budget. Digital line integration can be more easily achieved during fabrication because no bulk contact with the body region of the access device is used. Additionally, the embodiments described herein achieve better lateral alignment paths compared to those achieved using channel regions based on doped polysilicon, due to shorter channel lengths and lower source / drain semiconductor fabrication overhead. Shorter access line (e.g., word line (WL)) lengths (L) can also be achieved due to lower turn-off current (Ioff). Another benefit is the elimination of gas phase doping (GPD) during source / drain region formation, i.e., the absence of gas phase doping.

[0029] The figures in this document follow a numbering convention, where the first one or the first few digits correspond to the figure number, and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. For example, figure numeral 104 can refer to... Figure 1 The element "04" in the text, and similar elements can be found in the text. Figure 2 The figure is represented as 204. Multiple similar elements in a single figure can be represented by a figure number followed by a hyphen and another number or letter. For example, 302-1 could refer to... Figure 3In this context, components 302-1 and 302-2 can refer to components 302-2 that are similar to component 302-1. Such similar components are typically represented without hyphens and additional numbers or letters. For example, components 302-1 and 302-2, or other similar components, can be collectively represented as 302.

[0030] Figure 1 This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 1 A circuit diagram according to an embodiment of the present disclosure is shown, illustrating a cell array of a three-dimensional (3D) semiconductor memory device. Figure 1 The diagram shows that the cell array may have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N may be arranged along a second direction (D2) 105. Each sub-cell array, such as sub-cell array 101-2, may contain multiple access lines 103-1, 103-2, ..., 103-Q (which may also be called word lines). Furthermore, each sub-cell array, such as sub-cell array 101-2, may contain multiple digital lines 107-1, 107-2, ..., 107-P (which may also be called bit lines, data lines, or sensing lines). Figure 1 In the diagram, digital lines 107-1, 107-2, ..., 107-P are shown extending in a first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q are shown extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered as being in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered as being in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, access lines 103-1, 103-2, ..., 103-Q extend in a vertical direction, for example, in a third direction (D3) 111.

[0031] For example, a memory cell of 110 may include access means such as access transistors and memory nodes located at the intersections of each access line 103-1, 103-2, ..., 103-Q and each digital line 107-1, 107-2, ..., 107-P. Memory cells can be written to or read from using access lines 103-1, 103-2, ..., 103-Q and digital lines 107-1, 107-2, ..., 107-P. Digital lines 107-1, 107-2, ..., 107-P can electrically interconnect memory cells along the horizontal columns of each sub-cell array 101-1, 101-2, ..., 101-N, and access lines 103-1, 103-2, ..., 103-Q can electrically interconnect memory cells along the vertical rows of each sub-cell array 101-1, 101-2, ..., 101-N. For example, a memory cell of 110 can be located between an access line of, for example, 103-2 and a digital line of, for example, 107-2. Each memory cell can be uniquely addressed by a combination of access lines 103-1, 103-2, ..., 103-Q and digital lines 107-1, 107-2, ..., 107-P.

[0032] Digital lines 107-1, 107-2, ..., 107-P may be or comprise conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Digital lines 107-1, 107-2, ..., 107-P may extend in a first direction (D1) 109. In, for example, a sub-cell array of 101-2, digital lines 107-1, 107-2, ..., 107-P may be spaced apart from each other in a vertical direction, for example, in a third direction (D3) 111.

[0033] Access lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending relative to the substrate in a vertical direction, for example, in a third direction (D3) 111. For example, access lines in a sub-cell array of 101-2 may be spaced apart from each other in a first direction (D1) 109.

[0034] For example, the gate of a memory cell in memory cell 110 may be connected to an access line, such as 103-2, and a first conductive node (e.g., a first source / drain region) of an access device, such as a transistor, of memory cell 110 may be connected to a digital line, such as 107-2. Each memory cell (e.g., memory cell 110) may be connected to a storage node, such as a capacitor. A second conductive node (e.g., a second source / drain region) of an access device, such as a transistor, of memory cell 110 may be connected to a storage node, such as a capacitor. Although the references to first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not expected that the source / drain regions referred to as “first” and / or “second” have any single meaning. Only one source / drain region is expected to be connected to a digital line, such as 107-2, while the other source / drain region may be connected to a storage node.

[0035] Figure 2 Perspective views are shown according to some embodiments of the present disclosure, which depict three-dimensional (3D) semiconductor memory devices (e.g., Figure 1 The sub-cell array 101-2 shown in the figure is shown as a vertically oriented stack of memory cells in the array. Figure 3 A perspective view is shown, which shows Figure 2 The unit cell of the 3D semiconductor memory device shown in the figure, for example Figure 1 The memory unit 110 shown in the figure.

[0036] like Figure 2 As shown, a bonding element can be formed on the substrate 200. Figure 1 One of the plurality of sub-unit arrays, such as 101-2. For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0037] like Figure 2 As shown in the example embodiment, memory cells extending in a vertical direction (e.g., third direction (D3) 211) may be fabricated on the substrate 200. Figure 1 The memory cells 110 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 1 The memory cells 110 are formed in multiple vertical levels, such as a first level (L1), a second level (L2), and a third level (L3). These repeating vertical levels L1, L2, and L3 can be in the vertical direction (e.g., Figure 1The three-node access devices (D3) 211 shown in the figure are arranged, for example, "stacked". Each of these repeating vertical levels L1, L2 and L3 may contain multiple components, such as areas, discrete with laterally oriented access devices 230 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 103-1, 103-2, ..., 103-Q connections and digital lines 107-1, 107-2, ..., 107-P connections. The three-node access devices (e.g., transistors) can be formed with laterally oriented access devices 230 (e.g., transistors) and memory nodes (e.g., capacitors) in multiple iterations of the vertical repeating layers within each level. Figure 1 The transistor 110 in the figure is a discrete component, as described below. Figure 4 More detailed descriptions are available, and these components can be described in similar... Figure 1 The second direction (D2) 105 shown in the figure extends horizontally on the second direction (D2) 205.

[0038] Multiple components discrete from the horizontally oriented three-node access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225, which extend laterally in a second direction (D2) 205. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise an n-type doped region, such as a semiconductor material, formed adjacent to a p-type doped channel region (e.g., a semiconductor material) of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise a p-type conductive region, such as a doped semiconductor material, formed adjacent to an n-type conductive channel region (e.g., a doped semiconductor material) of the access device to form a p-type conductive transistor. For example, but not as a limitation, an n-type dopant may contain phosphorus (P) atoms, and a p-type dopant may contain boron (B) atoms formed in the oppositely doped host region of the polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0039] Storage node 227 (e.g., a capacitor) can be connected to a corresponding end of the access device. For example... Figure 2 As shown, storage node 227 (e.g., a capacitor) may be connected to the second source / drain region 223 of the access device. A storage node may be or contain a memory element capable of storing data. Each storage node may be a memory element using one of the following: a capacitor, a magnetic tunnel junction mode, and / or a variable resistive body containing a phase change material, etc.; however, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g., Figure 1 Each memory node associated with an access device in memory cell 110 can be similarly located in a memory node with a memory node ... Figure 1It extends on the second direction (D2) 205 shown in the second direction (D2) 105.

[0040] like Figure 2 As shown, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P are similar to... Figure 1 The first direction (D1) 109 extends in the first direction (D1) 209. The plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P can be similar to... Figure 1 The digital lines 107-1, 107-2, ..., 107-P are shown in the figure. The plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P may be arranged along a third direction (D3) 211, for example, "stacked". The plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P may contain conductive materials. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.) and / or metal-semiconductor compounds (e.g., tungsten silicide), cobalt silicide, titanium silicide, etc. However, the embodiments are not limited to these examples.

[0041] In each of the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-M, the horizontally oriented memory cells (e.g., Figure 1 The memory cells 110 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, as described below... Figure 4As described in more detail, multiple components discrete from the laterally oriented access device 230 (e.g., a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225) extend laterally in a second direction (D2) 205, and the multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending laterally in a first direction (D1) 209 can be formed in different vertical layers within each level. For example, the multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 can be disposed on and electrically contacted on the top surface of the first source / drain region 221, and orthogonal to the laterally oriented access device 230 (e.g., a transistor) extending laterally in the second direction (D2) 205. In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 are formed in a higher vertical layer away from the substrate 200 within a certain level (e.g., within level (L1)). This higher vertical layer is not a layer in which discrete components of the laterally oriented access devices (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) are formed. In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0042] like Figure 2 As shown in the example embodiment, access lines 203-1, 203-2, ..., 203-Q extend vertically relative to substrate 200 (e.g., on third-direction (D3) 211). Furthermore, as... Figure 2 As shown, a sub-cell array (e.g., Figure 1 The access lines 203-1, 203-2, ..., 203-Q of the sub-cell array 101-2 in the array may be spaced apart from each other in a first direction (D1) 209. The access lines 203-1, 203-2, ..., 203-Q may be configured to extend vertically relative to the substrate 200 in a third direction (D3) 211 between a pair of horizontally oriented three-node access devices 230 (e.g., transistors), which extend laterally in a second direction (D2) 205 but are adjacent to each other in a certain level (e.g., a first level (L1)) in the first direction (D1) 209. Each of the access lines 203-1, 203-2, ..., 203-Q may extend vertically along a third direction (D3) on the sidewall of the corresponding one of the vertically stacked plurality of horizontally oriented three-node access devices 230 (e.g., transistors).

[0043] For example, and such Figure 3 As shown in more detail, the first of the vertically extending access lines (e.g., 203-1) may be adjacent to the sidewall of the channel region 225 of the first horizontally oriented three-node access device 230 (e.g., transistor) in the first level (L1) 213-1, the sidewall of the channel region 225 of the first horizontally oriented three-node access device 230 (e.g., transistor) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the first horizontally oriented three-node access device 230 (e.g., transistor) in the third level (L3) 213-M, etc. Similarly, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second horizontally oriented three-node access device 230 (e.g., transistor) in the first level (L1) 213-1, the second being spaced apart from the first horizontally oriented three-node access device 230 (e.g., transistor) in the first level (L1) 213-1 in the first direction (D1) 209. Furthermore, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second horizontally oriented three-node access device 230 (e.g., transistor) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the second horizontally oriented three-node access device 230 (e.g., transistor) in the third level (L3) 213-M, and so on. The embodiments are not limited to a specific number of levels.

[0044] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound. Access lines 203-1, 203-2, ..., 203-Q may correspond to a combination of... Figure 1 The word line (WL) of the description.

[0045] like Figure 2 As shown in the example embodiment, the insulating layer dielectric (ILD) 250 may be formed above the substrate 200 extending along a first direction (D1) 209 on the end surface of a horizontally oriented three-node access device 230 (e.g., a transistor) in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-M. The ILD 250 may isolate and space vertically stacked memory cell arrays along a second direction (D2) 205, for example... Figure 1 The ILD 250 may contain insulating materials, such as dielectric materials, such as oxide materials, silicon oxide (SiO2) materials, silicon nitride (SiN) materials, silicon oxynitride materials, and / or combinations thereof.

[0046] although Figure 2 Not shown, but insulating material can fill other spaces in the vertically stacked array of memory cells. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride, etc. However, the embodiments are not limited to these examples.

[0047] Figure 3 A vertically stacked array of memory cells according to some embodiments of the present disclosure is shown in more detail (e.g., Figure 1 The unit cells (e.g., within the sub-unit array 101-2) in the sub-unit array 101-2 Figure 1 (Memory unit 110 in the memory). For example Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of a horizontally oriented three-node access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may also include metals formed using atomic layer deposition processes and / or metal composites containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), and copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor materials are intended to mean semiconductor materials containing high doping levels and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.), such as polycrystalline silicon. In contrast, non-degenerate semiconductors contain moderate doping levels in which dopant atoms are well separated from each other in the semiconductor host lattice and their interactions are negligible. The first source / drain region 321 and the second source / drain region 323 may be similar to Figure 2 The first source / drain region 221 and the second source / drain region 223 are shown in the figure.

[0048] The first and second source / drain regions may be separated by a channel 325 (e.g., a channel region) of a horizontally oriented three-node access device 330 (e.g., a transistor). The channel 325 may be a lightly doped (p) polycrystalline silicon material. In some embodiments, the channel 325 may be a lightly doped (p) polycrystalline germanium (Ge) material. In some embodiments, the channel 325 may be a lightly doped (p) polycrystalline silicon germanium (multi-SiGe) material. However, in some embodiments, the channel 325 may be composed of a semiconductor oxide (also referred to herein as “oxide semiconductor” or “oxide semiconductor material”). The semiconductor oxide may include any suitable composition; and in some embodiments, it may contain one or more of indium, zinc, tin, and gallium. Examples of oxide semiconductor materials and / or compositions containing one or more of indium, zinc, tin, and gallium, as used herein, may include such materials as ZnO. x InO x SnO2, Zn x O y N, Mg x Zn y O z In x Zn y O z In x Zn y O z In x Ga y Zn z O a In x Ga y Si z O a Zr x In y Zn z O a Hf x In y Zn z O a Sn x In y Zn z O a Al x Sn y In z Zn a O b Si x In y Zn z O a Zn x Sn y O z Al x Zny Sn z O a Ga x Zn y Sn z O a and Zr x Zn y Sn z O a .

[0049] In an additional embodiment, the channel 325 may be composed of a two-dimensional (2D) material. The 2D material may include any suitable composition; and in some embodiments, it may contain one or more transition metal dichalcogenides, including molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum distelluride (MoTe2), tungsten disulfide (WS2), and tungsten diselenide (WSe2). However, the embodiments are not limited to these examples.

[0050] In some embodiments, channel 325 may comprise a composite material, such as indium gallium zinc oxide (In2Ga2ZnO7) (also referred to herein as "IGZO"). In some embodiments, channel 325 is a multilayer IGZO channel material, wherein the first layer closest to the surface of the channel opposite the gate dielectric is rich in indium (In). In some embodiments, channel 325 is a multilayer IGZO channel material, wherein the outermost layer of the multilayer layers furthest from the surface opposite the gate dielectric is rich in gallium (Ga). In some embodiments, channel 325 is a multilayer IGZO channel material, wherein the outermost layer of the multilayer layers furthest from the surface opposite the gate dielectric is rich in zinc (Zn), and so on. However, the embodiments are not limited to these examples.

[0051] Similar to Figure 2 The number lines 207-1, 207-2, ..., 207-P and Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown (e.g., 307-1) can be configured to make electrical contact with the first source / drain region 321. As used herein, the terms "first" and "second" source / drain designations simply indicate that they are separate and distinct source / drain regions, one connected to the digital line and the other to the memory node. Figure 3 As shown in the example embodiments, similar to Figure 2 Access lines 203-1, 203-2, ..., 203-Q and Figure 1Access lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) may extend vertically in a third direction (D3) 311 adjacent to the sidewall of the channel region 325 of a horizontally oriented three-node access device 330 (e.g., a transistor), the channel region being horizontally conductive between a first source / drain region 321 and a second source / drain region 323 along a second direction (D2) 305. A gate dielectric material 304 may be inserted between the access line 303-1 (which forms a portion of the gate of the horizontally oriented three-node access device 330 (e.g., a transistor)) and the channel region 325. The gate dielectric material 304 may comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof. Embodiments are not limited thereto. For example, in the high-k dielectric material example, the gate dielectric material 304 may include one or more of hafnium dioxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0052] Figure 4 The illustration shows the formation of horizontally oriented access devices and vertically oriented access lines (e.g., [missing information]) at a stage of the semiconductor manufacturing process according to several embodiments of the present disclosure. Figure 1-3 Example method of a vertically stacked memory cell array (shown in the diagram). Figure 4 In the example embodiments shown in the examples, the method includes: repeatedly iteratively depositing alternating layers of dielectric material 430-1, 430-2, ..., 430-N (also independently and / or collectively referred to herein as "430") and sacrificial material 432-1, 432-2, ..., 432-N (also independently and / or collectively referred to herein as "432") to form a vertical stack 401 on the working surface of semiconductor substrate 400. In one embodiment, dielectric material 430 may be deposited to have a thickness in the range of twenty (20) nanometers (nm) to sixty (60) nm, for example, a vertical height in a third direction (D3). In one embodiment, sacrificial material 432 may be deposited to have a thickness in the range of twenty (20) nm to one hundred (100) nm, for example, a vertical height. However, the embodiments are not limited to these examples.

[0053] In one example, the sacrificial materials 432-1, 432-2, ..., 432-N may include sacrificial semiconductor materials, such as polycrystalline silicon (Si), silicon nitride (SiN), or even oxide-based semiconductor compositions. Although the discussion herein refers to examples of sacrificial semiconductor materials, the embodiments are not limited to these examples. It is desirable that the sacrificial materials can be selectively etched relative to the alternating layers of dielectric materials 430-1, 430-2, ..., 430-N.

[0054] like Figure 4 As shown, the vertical direction 411 is indicated as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figure 1-3 The third direction (D3) is shown among the first, second, and third directions. Figure 4 In the example shown, four layers numbered 1, 2, 3, and 4 are depicted as repeated iterations of the vertical stack 401. However, the embodiment is not limited to this example and may contain more or fewer repeated iterations. A photolithographic hard mask (HM) layer 435 may be deposited as the top layer on the repeated iterations of the vertical stack 401.

[0055] In some embodiments, dielectric materials 430-1, 430-2, ..., 430-N may be interlayer dielectrics (ILDs). For example, but not as a limitation, dielectric materials 430-1, 430-2, ..., 430-N may include silicon dioxide (SiO2) material. In another example, dielectric materials 430-1, 430-2, ..., 430-N may include silicon nitride (Si3N4) material (also referred to herein as "SiN"). In yet another example, dielectric materials 430-1, 430-2, ..., 430-N may include silicon oxycarbide (SiO2). x C y The dielectric material (also referred to herein as "SiOC"). In another example, dielectric materials 430-1, 430-2, ..., 430-N may comprise silicon oxynitride (SiO2). x N y The materials used are silicon (Si) materials (also referred to herein as "SiON") and / or combinations thereof. Embodiments are not limited to these examples. In some embodiments, the sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may comprise silicon (Si) material in a polycrystalline and / or amorphous state. In another example, the sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may comprise silicon nitride (SiN) material. However, embodiments are not limited to these examples.

[0056] Alternating layers of dielectric material 430-1, 430-2, ..., 430-N and sacrificial semiconductor material 432-1, 432-2, ..., 432-N can be deposited according to a semiconductor manufacturing process (e.g., chemical vapor deposition (CVD) in a semiconductor manufacturing apparatus). However, the embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques can be used to iteratively deposit alternating layers of dielectric material 430-1, 430-2, ..., 430-N and sacrificial semiconductor material 432-1, 432-2, ..., 432-N to form a vertical stack 401, such as... Figure 4 As shown in the image.

[0057] Figure 5AThis illustrates, according to several embodiments of the present disclosure, the formation of horizontally oriented access devices and vertically oriented access lines (e.g., at another stage of the semiconductor manufacturing process). Figure 1-3 The vertically stacked memory cell array shown in the figure. Figure 5A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 5A In the example embodiment shown in the examples, the method includes using an etching process to form a plurality of access line vertical openings 500 (also referred to herein as "first" vertical openings) through the vertical stack to the substrate, having a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505. In one example, as Figure 5A As shown, the plurality of first vertical openings 500 extend primarily in the second horizontal direction (D2) 505 and can form an elongated column of vertical columns 513, wherein sidewalls 514 are in a vertical stack. Prior to etching the plurality of first vertical openings 500, the plurality of first vertical openings 500 can be formed by patterning a photomask 535 on the vertical stack using photolithography techniques, for example, to form a hard mask (HM).

[0058] Figure 5B It is along Figure 5A The cross-sectional view obtained by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time point in the semiconductor manufacturing process. Figure 5B The conductive materials 540-1, 540-2, ..., 540-4 are shown to be able to... Figure 5A The plurality of first vertical openings 500 shown are formed on a gate dielectric material 538. For example, but not as a limitation, the gate dielectric material 538 may be conformally deposited in the plurality of first vertical openings 500 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric 538 may be deposited to a specific thickness (t1) suitable for a particular design rule, for example, a gate dielectric thickness of approximately 10 nanometers (nm). However, embodiments are not limited to this example. For example, but not as a limitation, the gate dielectric 538 may include silicon dioxide (SiO2) material, aluminum oxide (Al2O3) material, high dielectric constant (k) (e.g., high k) dielectric material, and / or combinations thereof, as shown in [the original text]. Figure 3 The same description applies.

[0059] In addition, such as Figure 5BAs shown, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited on the surface of the gate dielectric material 538 in the plurality of first vertical openings 500. For example, but not as a limitation, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited on the surface of the gate dielectric material 538 in the plurality of first vertical openings 500 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings on the gate dielectric 538. Conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a specific thickness (t2) to form vertically oriented access lines, for example, as shown in... Figure 1 The access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines), etc., shown are adapted to specific design rules. For example, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. For example, but not as a limitation, conductive materials 540-1, 540-2, ..., 540-4 may include, for example, metals such as tungsten (W), metal compositions, titanium nitride (TiN), doped polycrystalline silicon, and / or some other combination thereof, such as... Figure 3 The same description applies.

[0060] like Figure 5B As shown, conductive materials 540-1, 540-2, ..., 540-4 can be recessed to maintain only along what is now in Figure 5B The cross-sectional view shows the vertical sidewalls of the elongated vertical columnar columns 542-1, 542-2, and 542-3. Multiple individual vertical access lines formed of conductive materials 540-1, 540-2, ..., 540-4 can be recessed by using a suitable selective anisotropic etching process from the first vertical opening (e.g., ...). Figure 5A The conductive materials 540-1, 540-2, ..., 540-4 are removed from the bottom surface of the 500, exposing the gate dielectric 538 on the bottom surface to form individual vertical access lines 540-1, 540-2, ..., 540-4. For example... Figure 5B As shown, a dielectric material 539, such as an oxide or other suitable spin dielectric (SOD), can then be deposited in the first vertical opening 500 using a process such as CVD to fill the first vertical opening 500. The dielectric can be planarized to a vertical semiconductor stack (e.g., as shown) using chemical mechanical planarization (CMP) or other suitable semiconductor fabrication techniques. Figure 4The top surface of the hard mask 535 (shown as 401). Subsequent photolithography material 536 (e.g., the hard mask) can be deposited using CVD and planarized using CMP to cover and close the first vertical openings 500 on the individual vertical access lines 540-1, 540-2, ..., 540-4. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0061] Figure 6A This illustrates, according to several embodiments of the present disclosure, the formation of horizontally oriented access devices and vertically oriented access lines (e.g., at another stage of the semiconductor manufacturing process). Figure 1-3 Example method of a vertically stacked memory cell array (as shown in the figure). Figure 6A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 6A In an example embodiment, the method includes using a photolithography process to process a photomask 636, Figure 5B The 536 in the middle is patterned. Figure 6A The method further illustrates the use of a selective isotropic etching process to remove portions of the exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, in order to separate and individually form the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, for example... Figure 1 The access lines 103-1, 103-2, ..., 103-Q, etc., are shown. Therefore, the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are shown as running along the sidewalls of an elongated vertical column, for example along... Figure 5B The sidewalls of the slender vertical columnar columns 542-1, 542-2 and 542-3 in the cross-sectional view.

[0062] like Figure 6A As shown in the examples, the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z can be removed back to the first vertical opening using a suitable selective isotropic etching process (e.g., Figure 5A The gate dielectric material 638 in (500) is as follows. Figure 6AAs shown, a subsequent dielectric material 641 (e.g., oxide or other suitable spin dielectric (SOD)) can then be deposited to fill the remaining openings from which the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z have been removed using processes such as CVD or other suitable techniques. The dielectric material 641 can be planarized to a vertical semiconductor stack (e.g., as shown) using processes such as CMP or other suitable techniques. Figure 4 The top surface of the previous hard mask 635 (shown as 401). In some embodiments, subsequent photolithography material 537 (e.g., the hard mask) can be deposited using CVD and planarized using CMP to form a vertical semiconductor stack ( Figure 4 The working surface of 401) covers and encloses the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, such that the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are protected along the sidewalls of the elongated vertical columnar column. However, the embodiments are not limited to these process examples.

[0063] Figure 6B Show along Figure 6A The cross-sectional view obtained by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 6B The cross-sectional view shown is away from the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and shows the semiconductor substrate 400 for forming vertical stacks (e.g., as shown in the figure). Figure 4 The alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N shown in Figure 401 are repeatedly iterated. Figure 6B As shown, the vertical direction 611 is indicated as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figure 1-3 The third direction (D3) 111 is shown among the first, second, and third directions. The plane extending left and right in the drawing is the first direction (D1) 609. Figure 6B In one example embodiment, dielectric material 641 is shown filling the vertical opening after the residual gate dielectric 638 has been deposited. The hard mask 637 described above encapsulates the illustrated structure.

[0064] Figure 6C Show along Figure 6AThe cross-sectional view obtained by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 6C The cross-sectional view shown illustrates a second direction (D2) 605 extending along the axis of repeated iterations of alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N. Access devices and horizontally oriented memory nodes (e.g., capacitor cells) can be formed within the layers of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N along these repeated iterations. Figure 6C In the middle, adjacent and opposite vertical access lines 640-3 are shown by dashed lines, indicating the position of the plane and orientation settings from the drawing.

[0065] Figure 6D Show along Figure 6A The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 6D The cross-sectional view shown illustrates a second direction (D2) 605 extending along the axis of repeated iterations of alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N, wherein horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) are formed extending outside the regions within the layers of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N. Figure 6C In the drawing, dielectric material 641 is shown filling the space between horizontally oriented access devices and horizontally oriented memory nodes. For a three-dimensional array of vertically oriented memory cells, the dielectric material may be spaced apart along a first direction (D1) and extend into and out of the drawing plane. At the left end of the drawing, a repeating iteration of alternating layers of dielectric materials 630-1, 630-2, ..., 630-(N+1) and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N is shown. This location can be used to integrate horizontally oriented digital lines (e.g., ...). Figure 1 The digital lines 107-1, 107-2, ..., 107-P, etc. shown in the figure are used to form an electrical contact with the second source / drain region, as described in more detail below.

[0066] Figure 6E Show along Figure 6A The cross-sectional view obtained by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 6EThe cross-sectional view shown in the drawing plane, from right to left, extends along a first direction (D1) 609 along the axis of repeated iterations of alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N, across the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and intersects with regions of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N in which channel regions may be formed, the channel regions being separated from the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) by gate dielectric 638. Figure 6E In the diagram, a first dielectric filler material 639 is shown as separating the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes. The first dielectric filler material may be formed to extend into and out of the drawing plane, as described in more detail below, and may be spaced along a first direction (D1) 609 and vertically stacked in an array extending along a third direction (D3) 611 in a three-dimensional (3D) memory.

[0067] Figure 7A This illustrates, according to several embodiments of the present disclosure, the formation of horizontally oriented access devices and vertically oriented access lines (e.g., at another stage of the semiconductor manufacturing process). Figure 1-3 Example method of a vertically stacked memory cell array (as shown in the figure). Figure 7A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 7A In example embodiments, the method includes using a photolithography process to process photomasks 735, 736, and / or 737 (e.g., Figures 6A-6E Patterning is performed on 635, 636 and / or 637. Figure 7A The method further illustrates the use of one or more etching processes in the memory node region 750 (and Figure 7A and 7C A vertical opening 751 is formed in 744) through the vertical stack and extending primarily in the first horizontal direction (D1) 709. The one or more etching processes form the vertical opening 751 to expose... Figures 7B-7E The vertically stacked arrangement of dielectric materials 730-1, 730-2, ..., 730-N and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N is illustrated in the diagram, showing the third sidewall of the second region adjacent to the sacrificial semiconductor material in a repeating iteration. Other numbered components can be similarly combined. Figures 6A-6E Those components that are shown and discussed.

[0068] According to embodiments, the second region of the sacrificial semiconductor materials 732-1, 732-2, ..., 732-N can be repeatedly and iteratively removed from alternating layers of dielectric materials 730-1, 730-2, ..., 730-N and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N in a vertically stacked manner to form a memory node. In some embodiments, this process is performed before selectively removing the access device regions (e.g., transistor regions) in the sacrificial semiconductor materials from which the first source / drain region, channel region, and second source / drain region of the horizontally oriented access device are to be formed. In other embodiments, this process is performed after selectively removing the access device regions in the sacrificial semiconductor materials from which the first source / drain region, channel region, and second source / drain region of the horizontally oriented access device are to be formed. Figures 7B-7E The illustrated example embodiment includes a method that selectively etches second regions of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N to form a second horizontal opening spaced a second horizontal distance from the vertical opening 751 in the vertical stack. In some embodiments, such as Figures 7B-7E As shown, the method includes forming capacitor cells as storage nodes in a second horizontal opening. For example, but not as a limitation, forming the capacitor includes sequentially depositing a first electrode 761 and a second electrode 756 separated by a cell dielectric 763 in the second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor fabrication techniques and / or storage node structures may be used.

[0069] Figure 7B Show along Figure 7A The cross-sectional view obtained by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 7B The cross-sectional view shown is away from the plurality of individual vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1) and shows repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1) for forming vertically stacked layers on a semiconductor substrate 700, these layers being separated by horizontally oriented capacitor cells having a first electrode 761 (e.g., bottom cell contact electrode), a cell dielectric 763, and a second electrode 756 (e.g., top common node electrode). Figure 7B As shown, the vertical direction 711 is indicated as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figure 1-3 The third direction (D3) 111 is shown among the first, second, and third directions. The plane extending left and right in the drawing is the first direction (D1) 709. Figure 7BIn an example embodiment, a first electrode 761 (e.g., a bottom electrode) and a second electrode 756 coupled to the source / drain regions of a horizontal access device are shown separated by a cell dielectric material 763 that extends into and out of the drawing plane in a second direction (D2) and along the oriented axis of the horizontal access device and horizontal memory nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0070] Figure 7C Show along Figure 7A The cross-sectional view obtained by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 7C The cross-sectional view shown is extended along the plane of the drawing as follows: It extends along the axis of repeated iterations of alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N in the second direction (D2) 705. Access devices and horizontally oriented storage nodes (e.g., capacitor cells) can be formed within the layers of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N in these repeated iterations. Figure 7C In an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown as having been formed during this semiconductor manufacturing process, and a first electrode 761 (e.g., a bottom electrode that will be coupled to the source / drain region of the horizontal access device) and a second electrode 756 (e.g., a top electrode that will be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 763 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 761 (e.g., a bottom electrode that will be coupled to the source / drain region of the horizontal access device) and the second electrode 756 (e.g., a top electrode that will be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 763 may be formed after the formation of the first source / drain region, the channel region, and the second source / drain region in the regions of the sacrificial semiconductor material 732-1, 732-2, ..., 732-N, intended for the positioning (e.g., layout formation) of the horizontally oriented access device described below.

[0071] exist Figure 7CIn an example embodiment, a horizontally oriented memory node having a first electrode 761 (e.g., a bottom electrode coupling to the source / drain region of a horizontal access device) and a second electrode 756 (e.g., a top electrode coupling to a common electrode plane, such as a ground plane) is shown formed in a second horizontal opening on the left and right sides of the drawing plane. This second horizontal opening extends in a second direction (D2) and is separated by a second distance from a vertical opening formed along the orientation axis of the horizontal access device and the horizontal memory node in a vertically stacked array of memory cells in a three-dimensional (3D) memory. Figure 7C In the drawing, adjacent and opposite vertical access lines 740-3 are shown by dashed lines, indicating the positions set inward from the plane and orientation of the drawing.

[0072] Figure 7D Show along Figure 7A The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 7D The cross-sectional view shown is displayed on the left and right sides of the drawing plane as an axis extending along the repeating iterations of alternating layers of dielectric materials 730-1, 730-2, ..., 730-N, 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N in the second direction (D2) 705, wherein horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) are formed extending outside the regions within the layers of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N. Figure 7C In the diagram, dielectric material 741 is shown filling the space between horizontally oriented access devices. For a three-dimensional array of vertically oriented memory cells, the dielectric material may be spaced along a first direction (D1) and extend into and out of the drawing plane. However, in Figure 7D In the cross-sectional view, a second electrode 756 (e.g., the top common electrode of a capacitor cell structure) is also shown in the space between horizontally adjacent devices. At the left end of the drawing, a repeating iteration of alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N is shown; this location can be used to integrate horizontally oriented digital lines (e.g., ...). Figure 1 The digital lines 107-1, 107-2, ..., 107-P, etc. shown in the figure are used to form an electrical contact with the second source / drain region, as described in more detail below.

[0073] Figure 7E Show along Figure 7AThe cross-sectional view obtained by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 7E The cross-sectional view shown in the drawing plane, from right to left, extends in a first direction (D1) 709 along the axis of repeated iterations of alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N, intersecting the plurality of individual vertical access lines 740-1, 740-2, ..., 740-4, and intersecting with regions of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N in which channel regions may be formed, the channel regions being separated from the plurality of individual vertical access lines 740-1, 740-2, ..., 740-4 by gate dielectric 738. Figure 7E In the diagram, a first dielectric filler 739 is shown as separating the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes. The first dielectric filler may be formed to extend into and out of the drawing plane, as described in more detail below, and may be spaced along a first direction (D1) 709 and vertically stacked in an array extending along a third direction (D3) 711 in a three-dimensional (3D) memory.

[0074] Figure 8A This illustrates, according to several embodiments of the present disclosure, the formation of horizontally oriented access devices and vertically oriented access lines (e.g., at another stage of the semiconductor manufacturing process). Figure 1-3 Example method of a vertically stacked memory cell array (as shown in the figure). Figure 8A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 8A In an example embodiment, the method includes patterning photolithographic masks 835, 836, and / or 837, etc., using a photolithography process, such as Figures 6A-6E As described in 7A-7E. Figure 8A The method further illustrates the use of one or more etching processes in the access device region (e.g., for replacing the channel and source / drain transistor regions) to replace the channel and source / drain transistor regions. Figure 7C 742 and Figure 8C Vertical openings 871-1 and 871-2 are formed through the vertical stack in 842). Vertical openings 871-1 and 871-2 are shown extending primarily in the first horizontal direction (D1) 709. The one or more etching processes form vertical openings 871-1 and 871-2 to expose... Figures 8B-8E The vertically stacked dielectric materials 830-1, 830-2, ..., 830-(N+1) and sacrificial semiconductor materials (e.g., combined with...) are shown. Figures 7A-7EThe third sidewall of the first region adjacent to the sacrificial semiconductor material in the repeated iterations of alternating layers of sacrificial materials 732-1, 732-2, ..., 732-N. Other numbered components can be similarly combined. Figures 6A-6E The components shown and discussed in 7A-7E.

[0075] According to an embodiment, the access device regions of the sacrificial semiconductor materials 732-1, 732-2, ..., 732-N are... Figure 8A and 8C The 842 region (e.g., a transistor region) can be removed from alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) and sacrificial semiconductor material 732-1, 732-2, ..., 732-N in a vertically stacked array to form an access device (e.g., a transistor). In some embodiments, this process is performed before selectively removing the memory node region in the sacrificial semiconductor material from which capacitor cells are to be formed. In other embodiments, this process is performed after selectively removing the memory node region in the sacrificial semiconductor material from which capacitor cells are to be formed. Figures 8B-8E The illustrated example embodiment includes a method that selectively etches access device regions of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N to form a first horizontal opening spaced a first horizontal distance from the vertical openings 871-1 and 871-2 in a vertical stack. In some embodiments, such as Figures 8B-8E As shown, the method includes forming a transistor having a first source / drain region, a channel region, and a second source / drain region in a first horizontal opening as an access device. For example, but not as a limitation, forming the first source / drain region, the channel region, and the second source / drain region includes sequentially depositing the first source / drain region, the channel region, and the second source / drain region in the first horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or memory node structures can be used.

[0076] Figure 8B Show along Figure 8A The cross-sectional view obtained by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 8BThe cross-sectional view shown is away from the plurality of individual vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1), and illustrates the repeated iteration of alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) for forming vertically stacked layers on a semiconductor substrate 800, the layers being separated by capacitor cells having a first electrode 861 (e.g., a bottom cell contact electrode), a cell dielectric 863, and a second electrode 856 (e.g., a top common node electrode). Figure 8B As shown, the vertical direction 811 is indicated as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figure 1-3 The third direction (D3) 111 is shown among the first, second, and third directions. The plane extending left and right in the drawing is the first direction (D1) 809. Figure 8B In an example embodiment, the first electrode 861 (e.g., the bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 856 are shown separated by a cell dielectric material 863 that extends into and out of the drawing plane in a second direction (D2) and along the oriented axis of the horizontal access device and horizontal memory node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0077] Figure 8C Show along Figure 8A The cross-sectional view obtained by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 8C The cross-sectional view shown is depicted along the plane of the drawing as an axis extending along the repeating iterations of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) in the second direction (D2) 805. However, it is now shown that in the access device region 842 of the vertically stacked alternating layers, sacrificial semiconductor material has been removed to form horizontal openings 833-1, 833-2, ..., 833-N, wherein horizontally oriented access devices having a first source / drain region, a channel region, and a second source / drain region can be formed between the vertically alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1). Figure 8CIn an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown as having already been formed in the memory node region 844 during this semiconductor fabrication process, and a first electrode 861 (e.g., a bottom electrode that will be coupled to the source / drain region of the horizontal access device) and a second electrode 856 (e.g., a top electrode that will be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 863 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 861 (e.g., a bottom electrode that will be coupled to the source / drain region of the horizontal access device) and the second electrode 856 (e.g., a top electrode that will be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 863 may be formed after the first source / drain region, the channel region, and the second source / drain region are formed in the regions of the sacrificial semiconductor material 732-1, 732-2, ... 732-N.

[0078] exist Figure 8C In an example embodiment, the horizontal openings 830-1, 830-2, ..., 830-N for forming access devices having a first source / drain region, a channel region, and a second source / drain region are shown left and right on the drawing plane as extending in a second direction 805 (D2) and spaced apart from the vertical openings 871-1 and 871-2 formed along the orientation axis of the horizontal access devices and horizontal memory nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory in the vertical stack. Figure 8C In the drawing, adjacent and opposite vertical access lines 840-3 are shown by dashed lines, indicating their positions set inward from the plane and orientation of the drawing, and the gate dielectric 838 is visible.

[0079] Figure 8D Show along Figure 8A The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 8D The cross-sectional view shown in the drawing plane is extended along the axis of repeated iterations of alternating layers of dielectric materials 830-1, 830-2, ..., 830-N, 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N in the second direction (D2) 805, and extends outside the area in which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) will be formed. Figure 8D In the diagram, dielectric material 841 is shown filling the space between horizontally oriented access devices. For a three-dimensional array of vertically oriented memory cells, the dielectric material may be spaced along a first direction (D1) and extend into and out of the drawing plane. However, in Figure 8DIn the cross-sectional view, a second electrode 856 (e.g., the top common electrode of a capacitor cell structure) is also shown in the space between horizontally adjacent devices. At the left end of the drawing, a repeating iteration of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N is shown; this location can be used to integrate horizontally oriented digital lines (e.g., ...). Figure 1 The digital lines 107-1, 107-2, ..., 107-P, etc. shown in the figure are used to form an electrical contact with the second source / drain region of the formed horizontal access device.

[0080] Figure 8E Show along Figure 8A The cross-sectional view obtained by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 8E The cross-sectional view shown in the drawing plane, from right to left, is an axis extending in a first direction (D1) 809 along the repeating iterations of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N, in which channel regions separated by gate dielectric 838 from the plurality of individual vertical access lines 840-1, 840-2, ..., 840-4 are formed. Figure 8E In the diagram, a first dielectric filler material 839 is shown as separating the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes. The first dielectric filler material may be formed to extend into and out of the drawing plane, as described in more detail below, and may be spaced along a first direction (D1) 809 and vertically stacked in an array extending along a third direction (D3) 811 in a three-dimensional (3D) memory.

[0081] Figure 9A This illustrates, according to several embodiments of the present disclosure, the formation of horizontally oriented access devices and vertically oriented access lines (e.g., at another stage of the semiconductor manufacturing process). Figure 1-3 Example method of a vertically stacked memory cell array (as shown in the figure). Figure 9A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 9A In the example embodiment, vertical openings 971-1 and 971-2 still exist. Figures 8A-8E In the middle. However, in Figures 9A-9E In the above, horizontal access devices 998-1, 998-2, ..., 998-N, having a first source / drain region, a channel region, and a second source / drain region, are... Figure 9CThe numbers 998-1A, 998-1B, and 998-1C are shown in the diagram, and they have already been... Figure 8C and 8D The horizontal openings 833-1, 833-2, ..., 833-N shown are formed. Horizontal access devices 998-1, 998-2, 998-N are formed to extend in the second direction 905 (D2) within the vertically stacked horizontal access device region 942. Additionally, horizontal digital lines 999-1, 999-2, 999-N have been formed and integrated to contact the second source / drain region (e.g., 998-1C), as shown. Figure 9C and 9D As shown in the diagram. Other numbered components can be combined similarly. Figures 6A-6E The components shown and discussed in 7A-7E and 8A-8E.

[0082] According to an embodiment, in the access device region 942 (e.g., transistor region), in Figures 8A-8E In the process, sacrificial semiconductor materials 732-1, 732-2, ..., 732-N have been removed, leaving... Figures 8A-8E Alternating layers of vertically stacked dielectric materials 830-1, 830-2, ..., 830-(N+1) and horizontally openable layers 833-1, 833-2, ..., 833-N are repeatedly iterated to form an access device (e.g., a transistor). In some embodiments, this process is performed before selectively removing the sacrificial semiconductor material from the storage node region 944 where capacitor cells are to be formed. In other embodiments, this process is performed after selectively removing the sacrificial semiconductor material from the storage node region 944 where capacitor cells are to be formed. Figure 9B-9E The example embodiments shown include methods using atomic layer deposition (ALD) processes or other suitable deposition techniques on... Figures 8A-8E In each of the horizontal openings 833-1, 833-2, ..., 833-N, a first source / drain region 938-1A, a channel region 938-1B, and a second source / drain region 938-1C are selectively deposited. For example, but not as a limitation, forming the first source / drain region, the channel region, and the second source / drain region includes sequentially depositing the first source / drain region, the channel region, and the second source / drain region in the first horizontal opening using an atomic layer deposition (ALD) process according to the processes and techniques described herein. Other suitable semiconductor fabrication techniques and / or memory node structures can be used.

[0083] Figure 9B Show along Figure 9A The cross-sectional view obtained by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 9BThe cross-sectional view shown is away from the plurality of individual vertical access lines 940-1, 940-2, ..., 940-N, 940-(N+1), ..., 940-(Z-1), and illustrates the repeated iteration of alternating layers of dielectric materials 930-1, 930-2, ..., 930-(N+1) for forming vertically stacked layers on a semiconductor substrate 900, the layers being separated by capacitor cells having a first electrode 961 (e.g., a bottom cell contact electrode), a cell dielectric 963, and a second electrode 956 (e.g., a top common node electrode). Figure 9B As shown, the vertical direction 911 is indicated as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figure 1-3 The third direction (D3) 111 is shown among the first, second, and third directions. The plane extending left and right in the drawing is the first direction (D1) 909. Figure 9B In an example embodiment, the first electrode 961 (e.g., the bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 956 are shown separated by a cell dielectric material 963 that extends into and out of the drawing plane in a second direction (D2) and along the oriented axis of the horizontal access device and horizontal memory node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0084] Figure 9C Show along Figure 9A The cross-sectional view obtained by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 9C The cross-sectional view shown is depicted along the plane of the drawing as an axis extending along the alternating layers of dielectric materials 930-1, 930-2, ..., 930-(N+1) in the second direction (D2)905. However, the first source / drain region material, the channel region material, and the second source / drain region materials 998-1, 998-2, ..., 998-N are now shown. Figures 8A-8E Horizontal openings 833-1, 833-2, ..., 833-N are deposited and extend in a second direction 905 (D2). As an example, the first source / drain region 998-1, channel region 998-1B, and 998-1C are clearly shown. Furthermore, horizontal digital lines 999-1, 999-2, ..., 999-N are integrated and contacted with the second source / drain region (e.g., 998-1C), which extends in a first direction (D1), for example, in a direction (D3) 911, extending into and out of the drawing plane in alternating layers of dielectric material 930-1, 930-2, ..., 930-(N+1).

[0085] Therefore, three-node horizontal access devices 938-1, 938-2, ..., 938-N have been formed and integrated into vertical access lines 940-1, 940-2, ..., 940-(Z+1), and into digital lines 999-1, 999-2, ..., 999-N, without body contacts. Advantages of the structure and process described herein may include lower turn-off current (Ioff) of the access devices compared to silicon-based (Si-based) access devices. The channel region of the access device (e.g., 938-1B) may be free of minority carriers, thus eliminating the need to control the body potential of the access device's body region, and / or reducing gate / drain induced leakage (GIDL) of the access device. In some embodiments, channel and / or source / drain region replacement fabrication steps can be performed after the capacitor cell formation process, thus reducing the thermal budget. Digital line integration can be more easily achieved during fabrication because no body contacts with the body region of the access device are used. Furthermore, compared to that achieved using channel regions based on doped polysilicon, the embodiments described herein can achieve better lateral adjustment paths because of the shorter channel length and lower forming overhead in the source / drain semiconductor manufacturing process.

[0086] Similarly, the integration of the first source / drain regions, channel regions, and second source / drain regions of the horizontal access devices 998-1, 998-2, ..., 998-N, and the horizontal digital lines 999-1, 999-2, ..., 999-N, can be performed according to the processes and techniques described herein and in U.S. Patent Application No. 16 / 986,466 (Micron Attorney General's No. 2020-0692), co-filed and co-pending with at least one co-inventor entitled "Channel Integration in a Three-Node Access Device for Vertical Three Dimensional (3D) Memory". According to various embodiments, another advantage is the elimination of gas phase doping (GPD) during the formation of the source / drain regions, for example, the absence of gas phase doping. Other suitable semiconductor fabrication techniques and / or memory node structures can be used.

[0087] exist Figure 9C In an example embodiment, horizontal access devices 998-1, 998-2, ..., 989-N having a first source / drain region, a channel region, and a second source / drain region are shown left and right on the drawing plane as extending in a second direction 905 (D2) and spaced apart from vertical openings 971-1 and 971-2 formed along the orientation axis of the horizontal access devices and horizontal memory nodes of the vertically stacked memory cell array in the three-dimensional (3D) memory. Figure 10A-10DAs shown, dielectric material can be deposited to fill the vertical openings 971-1 and 971-3. Figure 9C In the drawing, adjacent and opposite vertical access lines 940-3 are shown by dashed lines, indicating the positions set inward from the plane and orientation of the drawing.

[0088] Figure 9D Show along Figure 9A The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 9D The cross-sectional view shown in the drawing plane is shown on the left and right sides as an axis extending along the repeating iteration of alternating layers of dielectric materials 930-1, 930-2, ..., 930-N, 930-(N+1) and horizontal digital lines 999-1, 999-2, ..., 999-N in the second direction (D2) 905 (extending into and out of the drawing plane in the first direction (D1), and extending outside the areas forming horizontally oriented access devices 938-1, 938-2, ..., 938-N and horizontally oriented storage nodes (e.g., capacitor cells) in the access device area 942 and storage node area 944. Figure 9D In the diagram, dielectric material 941 is shown filling the space between horizontally oriented access devices. For a three-dimensional array of vertically oriented memory cells, the dielectric material may be spaced along a first direction (D1) and extend into and out of the drawing plane. However, in Figure 9D In the cross-sectional view, a second electrode 956 (e.g., the top common electrode of the capacitor cell structure) is also shown in the space between horizontally adjacent devices. Dielectric materials 930-1, 930-2, ..., 930-(N+1) and horizontal number lines 999-1, 999-2, ..., 999-N (e.g., ...) are shown at the left end of the drawing. Figure 1 The repeated iterations of alternating layers of digital lines (107-1, 107-2, ..., 107-P, etc.) shown in the figure are integrated to form an electrical contact with the second source / drain region (e.g., 938-1C) of the formed horizontal access device.

[0089] Figure 9E Show along Figure 9A The cross-sectional view obtained by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point during an example semiconductor manufacturing process according to an embodiment of this disclosure. Figure 9EThe cross-sectional view shown in the drawing plane, from right to left, extends in a first direction (D1) 909 along the axis of repeated iterations of alternating layers of dielectric materials 930-1, 930-2, ..., 930-(N+1) and horizontal access devices 998-1, 998-2, ..., 998-N, which are separated from the plurality of individual vertical access lines 940-1, 940-2, ..., 940-4 by gate dielectric 938. Figure 9E In the diagram, a first dielectric filler 939 is shown as separating the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes. The first dielectric filler may be formed to extend into and out of the drawing plane, as described in more detail below, and may be spaced along a first direction (D1) 909 and vertically stacked in an array extending along a third direction (D3) 911 in a three-dimensional (3D) memory.

[0090] Figure 10A-10D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure. Figure 10A and 10C The storage nodes (e.g., capacitor cells) are formed on a second direction 1005 (D2) extending laterally along the drawing plane (e.g., along...). Figure 8A A cross-sectional side view of the source / drain integration in the storage node area 1044 after the cutting line B-B' in the horizontal access device area 1042. Figure 10B and 10D It is an end view of the source / drain integration in the formation of a horizontally oriented three-node access device at a specific point in time during the semiconductor manufacturing process.

[0091] like Figure 10A-10D As shown, a memory node, such as a capacitor cell, has been formed in memory node region 1044. In this example, the memory node is a horizontally oriented memory node extending in a second direction (D2) 1005 adjacent to a horizontal access device region 1042 of a vertically oriented three-dimensional (3D) memory with vertically oriented access lines. The memory node (e.g., a capacitor) includes a first electrode 1061 (e.g., a bottom electrode) and a second electrode 1065 (e.g., a top electrode and / or a common node electrode) separated by cell dielectric material 1063. As described above, the structure can be formed herein as repeating alternating layers of dielectric materials 1030-1 and 1030-2 with a sacrificial material (not shown) that has been removed to form source / drain integration in the respective memory node region 1044 and now the horizontal access device region 1042. Also as described above, a first etching process can be used to form a first vertical opening, for example... Figure 8AIn step 871, the sidewalls of the first portion of the sacrificial material adjacent to the vertical stack are exposed, and the first portion of the sacrificial material is removed by a selective etching process to form a horizontal opening in the access device region 1042 adjacent to the cell side region 1044, for example... Figure 8C 833 in the middle.

[0092] Figure 10A and 10B The example illustrates the formation of a multilayer source / drain material 1071-1 by depositing a first conductive material 1071-1 in a first horizontal opening, thereby forming a layer of source / drain material 1071-1 at a distance from the first vertical opening. Figure 8A The first horizontal opening (D1 opening) of the first horizontal distance (871) in the middle. Figure 8C Electrical contacts of the storage node at the distal end of (833) in the example. In one example, the deposition of the first conductive material 1071-1 comprises a metallic material, such as a layer, deposited in contact with an oxide semiconductor material that does not oxidize. In the example described herein, a storage node (e.g., a capacitor) has been formed. In this example, the first electrode 1061 may be located in a sacrificial material (e.g., Figure 7C During the removal of 732), an etch stop layer is provided to form a first horizontal opening ( Figure 8C (833 in the document). However, in other embodiments, the storage node (e.g., a capacitor) may be formed after the three-node horizontal access device is formed, including the source / drain integration described herein. In this example embodiment, the first conductive material 1071-1 may be selected as used for forming the second horizontal opening in the storage node region 1044 ( Figure 8C (833 in the text) to remove sacrificial material during the formation of storage nodes (e.g., Figure 7C (732) and an etch stop layer for providing an electrical ohmic contact to the first electrode 1061 of the storage node.

[0093] In one example embodiment, depositing the first conductive metal material 1071-1 includes depositing a material containing ruthenium (Ru). In one example, depositing the first conductive metal material 1071-1 includes depositing a material containing molybdenum (Mo). In one example, depositing the first conductive metal material 1071-1 includes depositing a material containing nickel (Ni). In one example, depositing the first conductive metal material 1071-1 includes depositing a material containing titanium (Ti). In one example, depositing the first conductive metal material 1071-1 includes depositing a material containing copper (Cu). In one example, depositing the first conductive metal material 1071-1 includes depositing a material containing tin (Sn). However, the embodiments are not limited to these examples.

[0094] In another example, depositing the first conductive material 1071-1 includes depositing a metallic material, such as a layer, that forms a conductive oxide upon contact with an oxide semiconductor material. For example, in one embodiment, depositing the first conductive material 1071-1 includes depositing a highly doped degenerate semiconductor. In one example, depositing the first conductive material 1071-1 includes depositing an indium oxide (In₂O₃) composition as the first conductive material 1071-1. In one example, depositing the first conductive material 1071-1 includes depositing indium tin oxide (In₂O₃). 2-x Sn x The O3 composition is used as the first conductive material 1071-1. However, the embodiments are not limited to these examples.

[0095] Conductive material 1071-1 can be deposited such that it fills the entire opening and is deposited on the area outside the opening, for example, deposited on... Figure 8A The first vertical opening in the middle is 871. Figure 10B This shows an end view of a three-node horizontal access device formed at this particular stage of the semiconductor manufacturing process.

[0096] In one example, depositing the first conductive material 1071-1 includes using an atomic layer deposition (ALD) process to fill a first horizontal opening to the distal end to form an electrical ohmic contact with the first electrode 1061. For example... Figure 10A and 10B As shown, the ALD deposition process of the first conductive contact material 1071-1 can also fill the first vertical opening.

[0097] like Figure 10C and 10D As shown, the method includes removing a portion of the first conductive contact material 1071-1 such that the first conductive contact material 1071-1 is recessed to maintain electrical ohmic contact with the first electrode 1061 only at the distal end of the horizontal opening. In one example, the removal process can be performed using an atomic layer etching (ALE) process. However, the embodiments are not limited to this example. In one example, the first conductive material 1071-1 may be recessed back into the horizontal opening ( Figure 8C In the 833), an electrical ohmic contact with the first electrode 1061 is formed with a thickness of approximately ten (10) nanometers (nm). However, the embodiments are not limited to this example, and other thicknesses may be appropriate depending on the specific design rules and / or size of the three-node horizontal access device. Figure 10D This shows an end view of a three-node horizontal access device formed at this particular stage of the semiconductor manufacturing process.

[0098] Figure 11A-11DExamples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure. Figure 11A and 11C The storage nodes (e.g., capacitor cells) are formed on a second direction 1005 (D2) extending laterally along the drawing plane (e.g., along...). Figure 8A A cross-sectional side view of the source / drain integration in the storage node area 1044 after the cutting line B-B' in the horizontal access device area 1042. Figure 11B and 11D This is an end view of the source / drain integration during the formation of a horizontally oriented three-node access device at a specific point in the semiconductor manufacturing process. According to an embodiment, Figure 11A-11D The time points shown in the semiconductor manufacturing process can be... Figure 10A-10D The structures and time points shown are as described. However, the embodiments are not limited to this.

[0099] like Figure 11A and 11B As shown, the method may include depositing a second conductive material 1173-1 and electrically contacting it with a first conductive material 1171-1, the first conductive material being electrically ohmic in contact with a first electrode 1161 of a horizontally oriented storage node (e.g., a capacitor cell). In one example, depositing the second conductive material 1173-1 includes depositing a degenerate semiconductor material. As used herein, a degenerate semiconductor material is intended to mean a semiconductor material containing a high level of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.), such as polycrystalline silicon. In contrast, a non-degenerate semiconductor contains a moderate level of doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and their interactions are negligible.

[0100] In one example, depositing the second conductive material 1173-1 includes depositing a second conductive material having an electronic band gap lower than that of the channel material. In one embodiment, depositing the second conductive material 1173-1 includes depositing a second conductive material having a conduction band offset (e.g., an offset relative to the Fermi level of the implanted electrode (the first electrode 1161 of the capacitor cell)) between the conduction band offset of the first conductive material 1171-1 and the conduction band offset of the channel material. Furthermore, in some embodiments, the conductive material 1173-1 may be a metallic material. In some embodiments, the conductive material 1173-1 may include indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). The electronic band gap of conductive material 1173-1 may be lower than that of subsequent conductive materials (e.g., combined with O3). Figures 13A-13DThe electronic band gap of the channel material 1398 shown is lower than the conduction band shift of the subsequent conductive material. Additionally, the electronic band gap of the conductive material 1173-1 may be lower than the electronic band gap of the conductive channel region.

[0101] For example, in one instance, depositing the second conductive material 1173-1 includes depositing a material containing ruthenium (Ru). In one instance, depositing the second conductive material 1173-1 includes depositing a material containing molybdenum (Mo). In one instance, depositing the second conductive material 1173-1 includes depositing a material containing nickel (Ni). In one instance, depositing the second conductive material 1173-1 includes depositing a material containing titanium (Ti). In one instance, depositing the second conductive material 1173-1 includes depositing a material containing copper (Cu). In one instance, depositing the second conductive material 1173-1 includes depositing a material containing tin (Sn).

[0102] In another example, depositing the second conductive material 1173-1 includes depositing a metallic material, such as a layer, that forms a conductive oxide upon contact with an oxide semiconductor material. For example, in one embodiment, depositing the second conductive material 1173-1 includes depositing a highly doped degenerate semiconductor. In one example, depositing the second conductive material 1173-1 includes depositing an indium oxide (In2O3) composition as the second conductive material 1173-1. In one example, depositing the second conductive material 1173-1 includes depositing indium tin oxide (In... 2-x Sn x The O3 composition is used as the second conductive material 1173-1. However, the embodiments are not limited to these examples.

[0103] A second conductive material 1173-1 can be deposited such that the second conductive material 1173-1 fills the entire opening and is deposited on the area outside the opening, for example, deposited on... Figure 8A The first vertical opening in the middle is 871. Figure 11B This shows an end view of a three-node horizontal access device formed at this particular stage of the semiconductor manufacturing process.

[0104] In one example, depositing the second conductive material 1173-1 includes filling the first horizontal opening using an atomic layer deposition (ALD) process. For example... Figure 11A and 11B As shown, the ALD deposition process of the second conductive contact material 1173-1 can also fill the first vertical opening.

[0105] like Figure 11C and 11DAs shown, the method includes removing a portion of the second conductive contact material 1173-1, causing the second conductive contact material 1173-1 to be recessed. In one example, the removal process can be performed using an atomic layer etching (ALE) process. However, the embodiments are not limited to this example. In one example, the second conductive material 1173-1 may be recessed back into a horizontal opening ( Figure 8C In the 833), and may have a thickness of approximately ten (10) nanometers (nm). However, the embodiments are not limited to this example, and other thicknesses may be appropriate depending on the specific design rules and / or size of the three-node horizontal access device. Figure 11D This shows an end view of a three-node horizontal access device formed at this particular stage of the semiconductor manufacturing process.

[0106] Figure 12A-12D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure. Figure 12A and 12C The storage nodes (e.g., capacitor cells) are formed on a second direction 1205 (D2) extending laterally along the drawing plane (e.g., along...). Figure 8A A cross-sectional side view of the source / drain integration in the storage node area 1244 after the cutting line B-B' in the horizontal access device area 1242. Figure 12B and 12D This is an end view of the source / drain integration during the formation of a horizontally oriented three-node access device at a specific point in the semiconductor manufacturing process. According to an embodiment, Figure 12A-12D The time points shown in the semiconductor manufacturing process can be... Figure 11A-11D The structures and time points shown are as described. However, the embodiments are not limited to this.

[0107] like Figure 12A and 12B As shown, the method may include depositing an Nth (e.g., third) conductive material 1275-1 and electrically contacting it with an N-1th (e.g., second) conductive material 1273-1, the second conductive material 1273-1 being electrically contacted with a first conductive material 1271-1. In one example, depositing the third conductive material 1275-1 includes depositing a degenerate semiconductor material. As used herein, a degenerate semiconductor material is intended to mean a semiconductor material containing a high level of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.), such as polycrystalline silicon. In contrast, a non-degenerate semiconductor contains a moderate level of doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and their interactions are negligible.

[0108] In one example, depositing the third conductive material 1275-1 includes depositing a third conductive material having an electronic band gap between the electronic band gap of a previous (e.g., second) conductive material 1171-1 and the electronic band gap of the channel material. In one embodiment, depositing the third conductive material 1275-1 includes depositing a third conductive material 1275-1 having a conduction band offset between the conduction band offset of the second conductive material 1273-1 and the conduction band offset of the channel material (e.g., an offset relative to the Fermi level of the implanted electrode (the first electrode 1261 of the capacitor cell)). Furthermore, in some embodiments, the conductive material 1275-1 may be a metallic material. In some embodiments, the conductive material 1275-1 may include indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). The electronic band gap of conductive material 1275-1 may be lower than that of subsequent conductive materials (e.g., combined with O3). Figures 13A-13D The electronic band gap of the channel material 1398 shown is lower than that of the subsequent conductive material.

[0109] For example, in one instance, depositing the third conductive material 1275-1 includes depositing a material containing ruthenium (Ru). In one instance, depositing the third conductive material 1275-1 includes depositing a material containing molybdenum (Mo). In one instance, depositing the third conductive material 1275-1 includes depositing a material containing nickel (Ni). In one instance, depositing the third conductive material 1275-1 includes depositing a material containing titanium (Ti). In one instance, depositing the third conductive material 1275-1 includes depositing a material containing copper (Cu). In one instance, depositing the third conductive material 1275-1 includes depositing a material containing tin (Sn).

[0110] In another example, depositing the third conductive material 1275-1 includes depositing a metallic material, such as a layer, that forms a conductive oxide upon contact with an oxide semiconductor material. For example, in one embodiment, depositing the third conductive material 1275-1 includes depositing a highly doped degenerate semiconductor. In one example, depositing the third conductive material 1275-1 includes depositing an indium oxide (In₂O₃) composition as the third conductive material 1275-1. In one example, depositing the third conductive material 1275-1 includes depositing indium tin oxide (In₂O₃). 2-x Sn x The O3 composition is used as the third conductive material 1275-1. However, the embodiments are not limited to these examples.

[0111] A third conductive material 1275-1 can be deposited onto the conductive contacts of a multilayer source / drain electrode, such that the third conductive material 1275-1 fills the entire opening and is deposited on the area outside the opening, for example, deposited on... Figure 8AThe first vertical opening in the middle is 871. Figure 12B This shows an end view of a three-node horizontal access device formed at this particular stage of the semiconductor manufacturing process.

[0112] In one example, depositing the third conductive material 1275-1 includes using an ALD process to fill the first horizontal opening and bring it into contact with the second conductive material 1273-1. For example... Figure 12A and 12B As shown, the ALD deposition process of the third conductive material 1275-1 can also fill the first vertical opening. In some embodiments, the third conductive material 1275-1 can be deposited in conjunction with the deposition of a prior (e.g., second) conductive contact material to form a compositionally hierarchical contact material.

[0113] like Figure 12C and 12D As shown, the method includes removing a portion of the third conductive contact material 1275-1, causing the third conductive contact material 1275-1 to be recessed. In one example, the removal process may be performed using an ALE process. However, the embodiments are not limited to this example. In one example, the third conductive material 1275-1 may be recessed back into a horizontal opening ( Figure 8C In 833), an electrical contact is formed with the second conductive material 1273-1, and a thickness of approximately ten (10) nanometers (nm) is achieved. However, the embodiments are not limited to this example, and other thicknesses may be appropriate depending on the specific design rules and / or size of the three-node horizontal access device.

[0114] Figures 13A-13D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure. Figure 13A and 13C The storage nodes (e.g., capacitor cells) are formed on a second direction 1305 (D2) extending laterally along the drawing plane (e.g., along...). Figure 8A A cross-sectional side view of the source / drain integration in the storage node area 1344 after the cutting line B-B' in the horizontal access device area 1342. Figure 13B and 13D This is an end view of the source / drain integration during the formation of a horizontally oriented three-node access device at a specific point in the semiconductor manufacturing process. According to an embodiment, Figures 13A-13D The time points shown in the semiconductor manufacturing process can be... Figure 12A-12D The structures and time points shown are as described. However, the embodiments are not limited to this.

[0115] like Figure 13A and 13BAs shown, the method may include depositing a conductive channel material 1398 and electrically contacting it with a third conductive material 1375-1, which in turn is electrically contacted with a second conductive material 1373-1. In one example, depositing the conductive channel material 1398 comprises depositing a degenerate semiconductor material. As used herein, a degenerate semiconductor material is intended to mean a semiconductor material containing a high level of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.), such as polycrystalline silicon. In contrast, a non-degenerate semiconductor contains a moderate level of doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and their interactions are negligible.

[0116] In one example, depositing conductive channel material 1398 includes depositing conductive channel material 1398 having an electronic band gap higher than that of subsequent conductive materials. In one embodiment, depositing conductive channel material 1398 includes depositing conductive channel material 1398 having a conduction band offset higher than that of the third conductive material 1375-1 and higher than that of subsequent conductive materials (e.g., an offset relative to the Fermi level of the implanted electrode (the first electrode 1361 of the capacitor cell)). Furthermore, in some embodiments, conductive channel material 1398 may be a metallic material. In some embodiments, conductive channel material 1398 may include indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). The electronic band gap of the conductive channel material 1398 may be higher than that of the subsequent conductive material (e.g., combined with O3). Figures 14A-14D The conductive material 1475-2 shown has an electronic band gap, and its conduction band offset is lower than that of the subsequent conductive material.

[0117] In some embodiments, a multilayer conductive channel material with feedback channel passivation can be deposited as the conductive channel material 1398. For example, an indium (In)-rich indium gallium zinc oxide (IGZO) conductive channel material 1398 is deposited to form a first layer of conductive channel material 1398, and then a portion of a low-indium (In) material is deposited relative to the first layer as the IGZO conductive channel material to form a leakage suppression layer. In one example, a gallium (Ga)-rich layer is deposited relative to the first layer as a portion of the IGZO conductive channel material to form a leakage suppression layer. In one example, a zinc (Zn)-rich layer is deposited relative to the first layer as a portion of the IGZO conductive channel material to form a leakage suppression layer. In one example, gallium oxide (GaO) is deposited... xThe layer serves as part of the IGZO conductive channel material to form a leakage suppression layer. In one embodiment, the leakage suppression layer is an oxide layer. An example of channel region formation using the ALD process is disclosed in co-filed and co-pending U.S. Patent Application No. 16 / 986,466 (Attorney General No. 1013.0560001), entitled "Channel Integration in Three-Node Access Device for Vertical Three Dimensional (3D) Memory," with at least one co-inventor. This application is incorporated herein by reference in its entirety. Other suitable semiconductor fabrication techniques can be used to form the conductive channel material 1398.

[0118] Conductive channel material 1398 can be deposited such that it fills the entire opening and is deposited on the area outside the opening, for example, deposited on... Figure 8A The first vertical opening in the middle is 871. Figure 13B This shows an end view of a three-node horizontal access device formed at this particular stage of the semiconductor manufacturing process.

[0119] In one example, depositing conductive channel material 1398 includes using an ALD process to fill a first horizontal opening to form an electrical contact with a third conductive material 1375-1. For example... Figure 13A and 13B As shown, the ALD deposition process of conductive channel material 1398 can also fill the first vertical opening.

[0120] like Figure 13C and 13D As shown, the method includes a portion of the conductive channel material 1398 such that the conductive channel material is recessed. In one example, the removal process can be performed using an ALE process. However, the embodiments are not limited to this example. In one example, the conductive channel material 1398 may be recessed back into a horizontal opening ( Figure 8C In 833), to form an electrical contact with the third conductive material 1375-1 and having a length (L) of approximately fifty (50) nanometers (nm) (e.g., Figure 17 (1778 in the example). However, the embodiments are not limited to this example, and other lengths (L) of the conductive channel material 1375-1 may be appropriate depending on the specific design rules and / or size of the three-node horizontal access device.

[0121] Figures 14A-14D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure. Figure 14A and 14C The storage nodes (e.g., capacitor cells) are formed on a second direction 1405 (D2) extending laterally along the drawing plane (e.g., along...). Figure 8A A cross-sectional side view of the source / drain integration in the storage node area 1444 after the cutting line B-B' in the horizontal access device area 1442. Figure 14B and 14D This is an end view of the source / drain integration during the formation of a horizontally oriented three-node access device at a specific point in the semiconductor manufacturing process. According to an embodiment, Figures 14A-14D The time points shown in the semiconductor manufacturing process can be... Figures 13A-13D The structures and time points shown are as described. However, the embodiments are not limited to this.

[0122] Figures 14A-14D The source / drain integration methods shown in 15A-15D and 16A-16D can be used to form a second source / drain region associated with the digital line contact side of a three-node horizontal access device structure. Therefore, for convenience but not as a limitation, the second source / drain is referred to as the digital line contact conductive material in this discussion.

[0123] like Figure 14A and 14B As shown, the method may include depositing a first digital line contact conductive material 1475-2 and bonding it with a conductive channel material (e.g., in combination). Figures 13A-13D The described channel material 1398 is electrically contacted with a third conductive material 1475-1, forming an earlier-formed source / drain integration (e.g., a first source / drain region). In one example, depositing the first digital line contact conductive material 1475-2 includes depositing a degenerate semiconductor material. As used herein, a degenerate semiconductor material is intended to mean a semiconductor material containing a high level of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.), such as polycrystalline silicon. In contrast, a non-degenerate semiconductor contains a moderate level of doping, where dopant atoms are well separated from each other in the semiconductor host lattice and their interactions are negligible.

[0124] In one example, depositing the first digital line conductive material 1475-2 includes depositing a material having a lower conductivity than the channel material (e.g., Figures 13A-13D The first digital line conductive material 1475-2 has an electronic bandgap of 1398. In one embodiment, depositing the first digital line conductive material 1475-2 includes depositing a conduction band offset (e.g., relative to the Fermi level of the injection electrode, which is 1398) between the conduction band offset of the conductive channel material 1498 and the conduction band offset of the subsequent digital line contact conductive material. Figure 16A-16DThe first digital line of the offset (1699) in the digital line contacts the conductive material 1475-2.

[0125] In some embodiments, the first digital line contact conductive material 1475-2 may include indium oxide (In2O3) or indium tin oxide (In). 2-x Sn x At least one of O3). The electronic band gap of the digital line contact conductive material 1475-2 may be higher than that of the subsequent digital line contact conductive material (e.g., combined with O3). Figures 15A-15D The electronic bandgap of the digital line contact conductive material 1573-2 shown is higher than the conduction bandgap of the subsequent digital line contact conductive material. In some embodiments, the electronic bandgap of the first digital line contact conductive material 1475-2 may be greater than that of the conductive channel material (e.g., Figures 13A-13D The electronic band gap between 1398 in the middle and the subsequent digital line contact conductive material formed in electrical contact with the first digital line conductive material 1475-2.

[0126] In another example, depositing the first digital line contact conductive material 1475-2 includes depositing a metallic material, such as a layer, that forms a conductive oxide upon contact with an oxide semiconductor material. For example, in one embodiment, depositing the first digital line contact conductive material 1475-2 includes depositing a highly doped degenerate semiconductor. In one example, depositing the first digital line contact conductive material 1475-2 includes depositing an indium oxide (In₂O₃) composition as the first digital line contact conductive material 1475-2. In one example, depositing the first digital line contact conductive material 1475-2 includes depositing indium tin oxide (In₂O₃). 2-x Sn x The O3 composition is used as the first digital line contact conductive material 1475-2. However, the embodiments are not limited to these examples.

[0127] The first digital line contact conductive material 1475-2 can be deposited such that the first digital line contact conductive material 1475-2 fills the entire opening and is deposited on the area outside the opening, for example, deposited on... Figure 8A The first vertical opening in the middle is 871. Figure 14B This shows an end view of a three-node horizontal access device formed at this particular stage of the semiconductor manufacturing process.

[0128] In one example, depositing the first digital line contact conductive material 1475-2 includes using an ALD process to fill the first horizontal opening. For example... Figure 14A and 14BAs shown, the ALD deposition process of the first digital line contact conductive material 1475-2 can also fill the first vertical opening. In some embodiments, the digital line contact conductive material 1475-2 may have a composition including one or more of In, Zn and Ga combinations (which have different ratios or different stoichiometry compared to the IGZO channel material).

[0129] like Figure 14C and 14D As shown, the method includes removing a portion of the first digital line contact conductive material 1475-2, causing the first conductive contact material to be recessed. In one example, the removal process can be performed using an ALE process. However, the embodiment is not limited to this example. In one example, the first digital line contact conductive material 1475-2 may be recessed back into a horizontal opening ( Figure 8C In 833), an electrical contact is formed with the conductive channel material and a thickness of approximately ten (10) nanometers (nm) is achieved. However, the embodiments are not limited to this example, and other thicknesses may be appropriate depending on the specific design rules and / or size of the three-node horizontal access device.

[0130] Figures 15A-15D Examples of methods for source / drain integration (e.g., digital line contact conductive material) in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure. Figure 15A and 15C The storage nodes (e.g., capacitor cells) are formed on a second direction 1505 (D2) extending laterally along the drawing plane (e.g., along...). Figure 8A A cross-sectional side view of the source / drain integration in the storage node area 1544 after the cutting line B-B' in the horizontal access device area 1542. Figure 15B and 15D This is an end view of the source / drain integration during the formation of a horizontally oriented three-node access device at a specific point in the semiconductor manufacturing process. According to an embodiment, Figures 15A-15D The time points shown in the semiconductor manufacturing process can be... Figures 14A-14D The structures and time points shown are as described. However, the embodiments are not limited to this.

[0131] like Figure 15A and 15B As shown, the method may include depositing a second digital line contact conductive material 1573-2 and making it electrically contact a first digital line contact conductive material 1575, wherein the first digital line contact conductive material 1575 and the conductive channel material ( Figures 13A-13D(1398) Electrical contact. In one example, the deposition of the second digital line contact conductive material 1573-2 includes the deposition of a degenerate semiconductor material. As used herein, a degenerate semiconductor material is intended to mean a semiconductor material containing a high level of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.), such as polycrystalline silicon. In contrast, a non-degenerate semiconductor contains a moderate level of doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and the interactions are negligible.

[0132] In one example, depositing the second digital line conductive material 1573-2 includes depositing a second digital line contact conductive material 1573-2 having an electronic bandgap lower than that of the first digital line contact conductive material 1575. In one embodiment, depositing the second digital line contact conductive material 1573-2 includes depositing a conduction band offset (e.g., relative to the Fermi level of the injection electrode, which is 1573-2 in this example) between the conduction band offset of the first digital line contact conductive material 1575 and the conduction band offset of the subsequent digital line material. Figure 16A-16D The second conductive material 1573-2 is offset from the digital line 1699 in the circuit. Furthermore, in some embodiments, the second digital line contact conductive material 1573-2 may be a metallic composition material. In some embodiments, the digital line contact conductive material 1573-2 may include indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). The electronic band gap of the second digital line contact conductive material 1573-2 may be higher than that of the subsequent digital line material (e.g., combined with O3). Figure 16A-16D The electronic bandgap of the digital line material 1699 shown is higher than that of subsequent digital line materials.

[0133] In another example, depositing the second digital line contact conductive material 1573-2 includes depositing a metal composition material, such as a layer, that forms a conductive oxide upon contact with an oxide semiconductor material. For example, in one embodiment, depositing the second digital line contact conductive material 1573-2 includes depositing a highly doped degenerate semiconductor. In one example, depositing the second digital line contact conductive material 1573-2 includes depositing an indium oxide (In2O3) composition as the second digital line contact conductive material 1573-2. In one example, depositing the second digital line contact conductive material 1573-2 includes depositing indium tin oxide (In... 2- x Sn x The O3 composition is used as the conductive material 1573-2 for the second digital line contact. However, the embodiments are not limited to these examples.

[0134] The second digital line contact conductive material 1573-2 can be deposited such that the second digital line contact conductive material 1573-2 fills the entire opening and is deposited on the area outside the opening, for example, deposited on... Figure 8A The first vertical opening in the middle is 871. Figure 15B This shows an end view of a three-node horizontal access device formed at this particular stage of the semiconductor manufacturing process.

[0135] In one example, depositing the second digital line contact conductive material 1573-2 includes using an ALD process to fill a first horizontal opening to form an electrical contact with the first digital line contact conductive material 1575. For example... Figure 15A and 15B As shown, the ALD deposition process of the second digital line contact conductive material 1573-2 can also fill the first vertical opening.

[0136] like Figure 15C and 15D As shown, the method includes removing a portion of the second digital line contact conductive material 1573-2, causing the second digital line contact conductive material 1573-2 to be recessed. In one example, the removal process can be performed using an ALE process. However, the embodiment is not limited to this example. In one example, the second digital line contact conductive material 1573-2 may be recessed back into a horizontal opening (e.g., Figure 8C In 833), an electrical contact is formed with the conductive material 1575-2 that contacts the first digital line, and the thickness is approximately ten (10) nanometers (nm). However, the embodiments are not limited to this example, and other thicknesses may be appropriate depending on the specific design rules and / or size of the three-node horizontal access device.

[0137] Figure 16A-16D Examples of source / drain integration in a horizontally oriented three-node access device at a specific point in time during a semiconductor manufacturing process are illustrated according to several embodiments of the present disclosure. In one example, Figure 16A-16D An example method is shown for forming a digital line contact 1699 to a second digital line contact conductive material. The digital line 1699 can be formed into a horizontally oriented digital line leading to a horizontally oriented three-node access device, similar to... Figure 1-3 The numbers shown are 107, 207, and 307.

[0138] Figure 16A and 16C The storage nodes (e.g., capacitor cells) are formed on a second direction 1605 (D2) extending laterally along the drawing plane (e.g., along...). Figure 8A A cross-sectional side view of the source / drain integration in the storage node area 1644 after the cutting line B-B' in the horizontal access device area 1642. Figure 16B and16D This is an end view of the source / drain integration during the formation of a horizontally oriented three-node access device at a specific point in the semiconductor manufacturing process. According to an embodiment, Figure 16A-16D The time points shown in the semiconductor manufacturing process can be... Figures 15A-15D The structures and time points shown are as described. However, the embodiments are not limited to this.

[0139] like Figure 16A and 16B As shown, the method may include depositing a digital line material 1699 and electrically contacting it with a second digital line contact conductive material 1673-2, which is electrically contacting a first digital line contact conductive material 1675-2. In one example, the deposited digital line material 1699 includes a deposited metallic digital line material 1699.

[0140] For example, the deposited digital line material 1699 may include depositing a digital line material 1699 containing ruthenium (Ru). In one example, the deposited digital line material 1699 includes depositing a material containing molybdenum (Mo). In one example, the deposited digital line material 1699 includes depositing a material containing nickel (Ni). In one example, the deposited digital line material 1699 includes depositing a material containing titanium (Ti). In one example, the deposited digital line material 1699 includes depositing a material containing copper (Cu). In one example, the deposited digital line material 1699 includes depositing a material containing tin (Sn). However, the embodiments are not limited to these examples.

[0141] In one example, the deposited digital line material 1699 includes using an ALD process to fill the remaining first horizontal opening (e.g., Figure 8C (833) to form an electrical contact with the conductive material 1673-2 of the second digital line contact. For example... Figure 16A-16D As shown, the ALD deposition process of digital line material 1699 can also fill the first vertical opening (e.g., Figure 8A (871 in the middle).

[0142] In some embodiments, the vertically oriented access line 1640-3 may be formed having a width (W) 1679, which is greater than the horizontal length (L) 1678 of the vertically oriented access line 1640-3 extending horizontally in a second direction (D2) 1605. In some embodiments, for example Figure 16CAs shown, the length (L) 1678-2 of the vertically oriented access line 1640-3 may horizontally overlap with both the multilayer digital line contact conductive material (e.g., 1675-2) and the multilayer source / drain material (e.g., 1675-1 on the cell side). In some embodiments, the digital line material 1699 is integrated to form an electrical contact with the digital line contact conductive material 1673-2. The vertical access line 1640-3 (e.g., word line (WL)) may be integrated opposite to and separated from the conductive channel material by the gate dielectric to form a three-node access device for the memory cell without a body contact.

[0143] Based on the source / drain integration embodiment described herein, similar to Figure 1-3 The access lines 103, 203, and 303 shown, the vertically oriented access line 1640-3 can be formed with a shorter length 1678-1(L) because the materials and techniques provide a smaller turn-off current (Ioff) for the horizontally oriented three-node access device. Figure 16A In the example embodiment shown, the vertical access line 1640-3 may have a length of 1678-1 (L), which is less than the channel material (e.g., combined with...). Figures 13A-13D The channel material 1398 shown extends horizontally in the second direction (D2) 1605. Therefore, the vertically oriented access line 1640-3 can horizontally partially overlap with both the multilayer digital line contact conductive material 1675-2 and the Nth layer (on the capacitor cell side) of the multilayer source / drain material 1675-1.

[0144] Figure 17 A horizontally oriented three-node access device 1042, according to an embodiment of the present disclosure, is shown coupling a vertical three-dimensional (3D) memory to a horizontally oriented storage node 1744. Figure 17 In the diagram, the horizontally oriented three-node access device 1742 is shown extending in a second direction (D2) 1705 on the left and right sides of the drawing plane. The horizontally oriented access device 1742 is shown having a first multilayer source / drain region 1798-1A electrically contacting a first electrode 1761 (e.g., bottom electrode) of a horizontally oriented storage node 1744 (e.g., a capacitor cell). The storage node 1744 may include a capacitor cell having a first horizontally oriented electrode 1761 electrically coupled to the first source / drain region 1798-1A of the three-node access device 1742 and a second electrode 1756 separated from the first horizontally oriented electrode 1761 by a cell dielectric 1763. In some embodiments, the horizontally oriented storage node 1744 and the first source / drain region 1798-1A of the three-node access device 1742 are in direct electrical contact on the same plane flush with the first source / drain region 1798-1A.

[0145] Channel region 1798-1B is shown as electrically contacting the first source / drain region 1798-1A. Vertically oriented access line 1740-3 is opposite to channel region 1798-1B and separated from it by a gate dielectric. Vertically oriented access line 1740-2 is shown by dashed lines, indicating that the vertically oriented access line is positioned within and / or outside the drawing plane. According to specific design rules, the vertically oriented access line 1740 may extend in the second direction (D2) 1705 longer and / or shorter than the channel region, for example, with source / drain overlap and / or partial overlap.

[0146] The second source / drain region 1798-1C (e.g., a multilayer digital line contact conductive material) is shown as electrically contacting and integrated with the channel region 1798-1B and with the horizontally oriented digital line 1799 extending into and out of the drawing plane. In some embodiments, the first and second source / drain regions 1798-1A / C may be formed of one or more of a combination of indium (In), zinc (Zn), and gallium (Ga) (which have different ratios or different stoichiometry compared to the IGZO channel material).

[0147] like Figure 17 As shown, the horizontally oriented access device 1742 and the horizontally oriented memory node 1744 are horizontally spaced from adjacent memory cells along a second direction (D2) 1705 via an interlayer dielectric material 1780, and are vertically spaced from stacked adjacent cells in a three-dimensional (3D) memory via dielectric layers 1730-1 and 1730-2. In some embodiments, the horizontally oriented digital line 1799 may be integrated to form an electrical contact with a multilayer second source / drain material 1798-1C. The multilayer first source / drain region 1798-1A may contain a first conductive material to form an electrical contact with the memory node of the three-node access device 1742. In some embodiments, a vertically oriented access line opposite to and separated from the channel material 1798-1B by a gate dielectric may be integrated to form a three-node access device 1742 of the memory cell without body contact. In some embodiments, the horizontally oriented digital line 1799 is in direct electrical contact with the second source / drain region 1798-1C of the three-node access device 1742 on the same plane as the second source / drain region 1798-1C.

[0148] Figure 18This is a block diagram of a device in the form of a computing system 1800 including a memory device 1803, according to several embodiments of the present disclosure. As used herein, for example, the memory device 1803, the memory array 1810, and / or the host 1802 may also be considered individually as a "device". According to an embodiment, the memory device 1802 may include at least one memory array 1810 having a three-node access means of vertical three-dimensional (3D) memory, as already described herein.

[0149] In this example, system 1800 includes a host 1802 coupled to memory device 1803 via interface 1804. The computing system 1800 may be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, as well as various other types of systems. Host 1802 may include several processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory 1803. System 1800 may include a separate integrated circuit, or both host 1802 and memory device 1803 may be on the same integrated circuit. For example, host 1802 may be a system controller for a memory system including multiple memory devices 1803, wherein system controller 1805 provides access to the respective memory devices 1803 by another processing resource, such as a central processing unit (CPU).

[0150] exist Figure 18 In the example shown, host 1802 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., loaded from memory device 1803 via controller 1805). The OS and / or various applications can be loaded from memory device 1803 by providing access commands from host 1802 to memory device 1803 to access data including the OS and / or various applications. Host 1802 can also access said data by providing access commands to memory device 1803 to retrieve data used by the OS and / or various applications during execution.

[0151] For clarity, system 1800 has been simplified to focus on features particularly relevant to this disclosure. Memory array 1810 may be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and / or NOR flash array, including at least one three-node access device of three-dimensional (3D) memory. For example, memory array 1810 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 1810 may include memory cells arranged in rows coupled via word lines (which may be referred to herein as access lines or select lines) and columns coupled via digital lines (which may be referred to herein as sense lines or data lines). Although in Figure 1 A single array 1810 is shown, but embodiments are not limited thereto. For example, memory device 1803 may include several arrays 1810 (e.g., arrays of DRAM cells).

[0152] Memory device 1803 includes an address circuitry 1806 for latching address signals provided via interface 1804. The interface may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). Such a protocol may be custom or proprietary, or interface 1804 may employ a standardized protocol, such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z, CCIX, etc. Address signals are received and decoded by row decoder 1808 and column decoder 1812 to access memory array 1810. Data can be read from memory array 1810 by sensing voltage and / or current changes on sensing lines using sensing circuitry 1811. Sensing circuitry 1811 may include, for example, a sensing amplifier that can read and latch data pages (e.g., rows) from memory array 1810. I / O circuitry 1807 can be used for bidirectional data communication with host 1802 via interface 1804. The read / write circuitry 1813 is used to write data to or read data from the memory array 1810. As an example, the circuitry 1813 may include various drivers, latching circuitry, etc.

[0153] The control circuitry system 1805 decodes signals provided by the host 1802. These signals may be commands provided by the host 1802. These signals may include chip enable signals, write enable signals, and address latch signals, which are used to control operations performed on the memory array 1810, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry system 1805 is responsible for executing instructions from the host 1802. The control circuitry system 1805 may include a state machine, a sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination of these. In some instances, the host 1802 may be a controller external to the memory device 103. For example, the host 1802 may be a memory controller coupled to the processing resources of a computing device.

[0154] The term semiconductor can refer to, for example, a material, a wafer, or a substrate, and includes any basic semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a basic semiconductor structure, and other semiconductor structures. Furthermore, when semiconductors are mentioned in the preceding description, regions / junctions may have been formed in the basic semiconductor structure using previous process steps, and the term semiconductor may include a base material containing such regions / junctions.

[0155] The figures in this document follow a numbering convention, wherein the first one or the first few digits correspond to the figure number, and the remaining digits identify elements or components in the figures. Similar (e.g., identical) elements or components between different figures may be identified by using similar digits. As will be understood, elements shown in the various embodiments herein may be added, interchanged, and / or removed to provide several additional embodiments of this disclosure. Furthermore, as will be understood, the scale and relative proportions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be construed as limiting.

[0156] As used herein, “several” or “a certain number” of something can refer to one or more of such things. For example, “several” or “a certain number” of memory cells can refer to one or more memory cells. “A certain number” of something is intended to be two or more. As used herein, multiple actions performed in parallel means actions that at least partially overlap within a specific time period. As used herein, the term “coupling” can include electrical coupling, direct coupling and / or direct connection without intermediate elements (e.g., through direct physical contact), indirect coupling and / or connection with intermediate elements, or wireless coupling. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., according to causality). An element coupled between two elements can be between and coupled to each of the two elements.

[0157] It should be recognized that due to variations in routine manufacturing, measurement, and / or assembly, the term "vertical" takes into account variations relative to "fully" vertical, and those skilled in the art should understand the meaning of the term "vertical." For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be above or laterally to the other element, and / or may be in direct physical contact with the other element. Lateral may refer to, for example, a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0158] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the foregoing description. The scope of the various embodiments of this disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and their full range of equivalents.

Claims

1. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access means and vertically oriented access lines, comprising: Alternating layers of dielectric and sacrificial materials are repeatedly deposited in an iterative manner to form a vertical stack; A first vertical opening is formed using a first etching process, thereby exposing the vertical sidewalls of a first portion of the vertical stack adjacent to the sacrificial material; A first portion of the sacrificial material is selectively etched to form a first horizontal opening, the first horizontal opening removing the sacrificial material in a first region and being spaced a first horizontal distance from the first vertical opening, to form a first source / drain region and a second source / drain region horizontally separated by the channel region. as well as A multilayer source / drain material, a channel material, and a second source / drain material are deposited in the first horizontal opening to form a three-node access device for memory cells in the array of vertically stacked memory cells.

2. The method of claim 1, wherein depositing the multilayer first source / drain material comprises depositing a first material to form an electrical contact with the storage node at the distal end of the first horizontal opening relative to the first vertical opening.

3. The method according to any one of claims 1 to 2, wherein depositing the multilayer first source / drain material comprises depositing a metal layer in the first horizontal opening that does not oxidize when in contact with the oxide semiconductor channel material as a first material.

4. The method according to any one of claims 1 to 2, wherein depositing the multilayer first source / drain material comprises depositing a metal layer as a first material in the first horizontal opening that forms a conductive oxide upon contact with the oxide channel material.

5. The method of claim 2, further comprising depositing a second material in electrical contact with the first material in the first horizontal opening using an atomic layer deposition (ALD) process, wherein the second material is a second semiconductor material having an electronic bandgap lower than that of the channel material.

6. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access means and vertically oriented access lines, comprising: Alternating layers of dielectric and sacrificial materials are repeatedly deposited in an iterative manner to form a vertical stack; Multiple first vertical openings are formed, having a first horizontal direction and a second horizontal direction, passing through the vertical stack, and extending primarily in the second horizontal direction to form an elongated vertical columnar column with sidewalls in the vertical stack; A first conductive material is conformally deposited on the gate dielectric material in the first vertical opening; A portion of the first conductive material is removed to form a plurality of individual vertical access lines along the sidewalls of the elongated vertical column; A second vertical opening is formed, thereby exposing the vertical sidewalls of the first portion of the sacrificial material in the vertical stack; The first portion of the sacrificial material is selectively etched to form a first horizontal opening, the first horizontal opening removing the sacrificial material in a first region and being separated from the first vertical opening by a first horizontal distance; as well as A selective deposition process is used to deposit in the first horizontal opening: A multilayer first source / drain material, which is electrically contacted with the storage node at the distal end of the first horizontal opening relative to the first vertical opening; Channel materials; as well as Multilayer second source / drain material for forming a three-node access device for memory cells in the array of vertically stacked memory cells.

7. The method of claim 6, further comprising: The Nth source / drain material of the multilayer first source / drain material has an electronic band gap between the electronic band gap of the previous (N-1) source / drain material and the electronic band gap of the channel material. as well as The Nth source / drain material of the multilayer first source / drain material is deposited, having a conduction band offset between the conduction band offset of the previous (N-1) source / drain material and the conduction band offset of the channel material.

8. The method of claim 7, further comprising depositing the Nth source / drain material of the multilayer first source / drain material in conjunction with depositing a previous (N-1)th source / drain material to form a compositionally hierarchical contact material.

9. The method according to any one of claims 6 to 7, further comprising depositing a channel material having a feedback channel passivation material and being in electrical contact with the Nth source / drain material.

10. The method of claim 9, further comprising: Deposit indium gallium zinc oxide (IGZO) channel material rich in indium to form a first layer of the channel material in contact with the gate dielectric; as well as A smaller amount of indium material is deposited relative to the first layer to form a leakage suppression layer.

11. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access means and vertically oriented access lines, comprising: Alternating layers of dielectric and sacrificial materials are repeatedly deposited in an iterative manner to form a vertical stack; Multiple first vertical openings are formed, having a first horizontal direction and a second horizontal direction, passing through the vertical stack, and extending primarily in the second horizontal direction to form an elongated vertical columnar column with sidewalls in the vertical stack; A first conductive material is conformally deposited on the gate dielectric material in the first vertical opening; A portion of the first conductive material is removed to form a plurality of individual vertical access lines along the sidewalls of the elongated vertical column; The first etching process is used to form a second vertical opening, thereby exposing the vertical sidewalls of the first portion of the vertical stack adjacent to the sacrificial material; The first portion of the sacrificial material is selectively etched to form a first horizontal opening, the first horizontal opening removing the sacrificial material in a first region and being separated from the first vertical opening by a first horizontal distance; as well as Deposited in the first horizontal opening using an atomic layer deposition (ALD) process: The first source / drain material is in electrical contact with the storage node at the distal end of the first horizontal opening relative to the first vertical opening. The channel material is in electrical contact with the first source / drain material; as well as A three-node access device for memory cells in an array of multilayer second source / drain materials electrically contacted with the channel material to form vertically stacked memory cells.

12. The method of claim 11, wherein depositing the multilayer second source / drain material comprises depositing a first semiconductor material having the following: The electronic band gap between the electronic band gap of the channel material and the electronic band gap of the subsequent semiconductor material, wherein the subsequent semiconductor material is formed to be in electrical contact with the first semiconductor material; and The conduction band offset occurs between the conduction band offset of the channel material and the conduction band offset of the subsequent semiconductor material, wherein the subsequent semiconductor material is formed to be in electrical contact with the first semiconductor material.

13. The method of claim 12, wherein depositing the multilayer second source / drain material comprises: Deposit the first semiconductor material; Deposit a second semiconductor material that is in electrical contact with the first semiconductor material; as well as The deposition is based on a second semiconductor material selected having an electronic band gap between the electronic band gap of the first semiconductor material and the electronic band gap of the subsequent semiconductor material, the subsequent semiconductor material being formed to be in electrical contact with the second semiconductor material.

14. The method of claim 12, wherein depositing the multilayer second source / drain material comprises: Deposit the first semiconductor material; Deposit a second semiconductor material that is in electrical contact with the first semiconductor material; as well as The deposition is based on a second semiconductor material selected having a conduction band offset between the conduction band offset of the first semiconductor material and the conduction band offset of a subsequent semiconductor material, the subsequent semiconductor material being formed to be in electrical contact with the second semiconductor material.

15. The method according to any one of claims 11 to 12, further comprising integrating horizontally oriented digital lines to form electrical contacts with the multilayer second source / drain material, thereby forming the three-node access device of the memory cell without physical contact.

16. The method according to any one of claims 11 to 12, further comprising forming the vertically oriented access line having a horizontal width (W) greater than the horizontal length (L) of the channel material and horizontally overlapping both the multilayer second source / drain material and the first source / drain material.

17. The method according to any one of claims 11 to 12, further comprising forming the vertically oriented access line to have a horizontal width (W), the horizontal width being less than the horizontal length (L) of the channel material and horizontally partially overlapping both the multilayer second source / drain material and the first source / drain material.

18. A memory device comprising: An array of vertically stacked memory cells, the array of vertically stacked memory cells comprising: A horizontally oriented three-node access device has multiple layers of first source / drain regions and multiple layers of second source / drain regions separated by a channel region, and a gate opposite to and separated from the channel region by a gate dielectric, wherein the three-node access device does not have direct electrical body contact with the body region of the three-node access device or the channel region, wherein the order of the layers of the multiple layers of the first source / drain regions is different from the order of the layers of the multiple layers of the second source / drain regions in the horizontal direction, and wherein the multiple layers of the first source / drain regions have a first number of layers and the multiple layers of the second source / drain regions have a second number of layers different from the first number of layers; A vertically oriented access line coupled to the gate and separated from the channel by the gate dielectric; A horizontally oriented storage node electrically coupled to the multilayer first source / drain region of the three-node access device; and A horizontally oriented digital line electrically coupled to the multilayer second source / drain region of the three-node access device.

19. The memory device of claim 18, wherein the three-node access device has three nodes, including the multilayer first source / drain region, the multilayer second source / drain region and the gate opposite to the channel region, and does not have the direct electrical body contact.

20. The memory device according to any one of claims 18 to 19, wherein the channel region comprises a two-dimensional 2D material comprising one or more transition metal dichalcogenides.

21. The memory device of any one of claims 18-19, wherein the channel region comprises a first layer of indium gallium zinc oxide (IGZO) channel material with indium enrichment in contact with the gate dielectric and gallium oxide (GaO) as a feedback channel passivation material. x leakage suppression layer.

22. The memory device according to any one of claims 18 to 19, wherein the horizontally oriented memory node is in direct electrical contact with the first source / drain region of the three-node access device on the same plane as the first source / drain region.

23. The memory device according to any one of claims 18 to 19, wherein the horizontally oriented digital line is in direct electrical contact with the second source / drain region of the three-node access device on the same plane as the second source / drain region.

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