Non-volatile semiconductor memory device and current-assisted voltage-controlled resistor element

Abstract

The present invention provides a non-volatile semiconductor memory device and a current-assisted voltage-controlled resistor that can supply an optimal voltage to each memory cell according to the state of the memory cell. [Solution] The non-volatile semiconductor memory device has a resistor element 10 and a current assist element arranged in parallel between the first voltage control line VCL1 and the second voltage control line VCL2, so that the optimal voltage can be supplied to each antifuse memory M arranged in the row direction via either the resistor element 10 or the current assist element depending on the state of the antifuse memory M.

Description

[Technical Field]

[0001] The present invention relates to a non-volatile semiconductor memory device and a current-assisted voltage-controlled resistor element. [Background technology]

[0002] Non-volatile memories include resistive random-access memory and phase-change memory, which store data by applying voltage. Additionally, antifuse memory is a known type of one-time programmable non-volatile memory that writes data by applying a high voltage to a gate insulating film to cause dielectric breakdown.

[0003] For example, Patent Document 1 discloses an antifuse memory in which a switch transistor and a memory capacitor are connected and arranged on the active region. The memory capacitor has a memory gate electrode formed on the active region via a memory gate insulating film. During a data writing operation, the memory gate insulating film is broken down by the voltage difference between the breakdown word voltage applied to the memory gate electrode from the write word line and the dielectric breakdown bit voltage applied to the bit line of the switch transistor. As a result, the memory gate electrode, which was previously isolated from the active region, becomes electrically connected to the active region. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 6,667,902 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] However, in semiconductor memory devices where such antifuse memories are arranged in a matrix, the state of each memory cell may differ, and the voltage required to cause dielectric breakdown of the memory gate insulating film may also differ. Therefore, it is necessary to control the voltage applied during writing to ensure that the memory gate insulating film is reliably broken down for each antifuse memory while preventing excessive current from flowing.

[0006] The present invention has been made in consideration of the above points, and aims to provide a non-volatile semiconductor memory device and a current-assisted voltage-controlled resistor that can supply an optimal voltage to each memory cell according to the state of the memory cell. [Means for solving the problem]

[0007] The non-volatile semiconductor memory device of the present invention comprises a voltage control line extending in a first direction and a memory array including a plurality of memory cells arranged in the first direction, wherein each memory cell includes a first terminal and a second terminal, the voltage control line includes a first voltage control line and a second voltage control line, the first voltage control line is connected to a voltage control circuit, the second voltage control line is connected to the first terminal of the plurality of memory cells arranged in the first direction, and a resistive element and a current assist element are connected in parallel between the first voltage control line and the second voltage control line.

[0008] Furthermore, the current-assisted voltage-controlled resistor element of the present invention comprises a resistor element and a current-assisted element, and the resistor element and the current-assisted element are connected in parallel to the voltage control line of a non-volatile semiconductor memory device. [Effects of the Invention]

[0009] According to the present invention, by providing a resistive element and a current assist element in parallel between the first voltage control line and the second voltage control line, the optimal voltage can be supplied to each memory cell via either the resistive element or the current assist element depending on the state of the memory cell. [Brief explanation of the drawing]

[0010] [Figure 1] It is a schematic diagram showing the circuit configuration of a non-volatile semiconductor memory device. [Figure 2] FIG. 1 is a schematic diagram showing the circuit configuration of one row of the anti-fuse memories arranged in a matrix shown in FIG. 1. [Figure 3] FIG. 8 is a schematic diagram showing an example of the planar layout configuration of the non-volatile semiconductor memory device shown in FIG. 1. [Figure 4] FIG. 11 is a schematic diagram showing the circuit configuration of one row of the anti-fuse memories arranged in a matrix in the non-volatile semiconductor memory device according to the second embodiment. [Figure 5] FIG. 14 is a schematic diagram showing an example of the planar layout configuration of the non-volatile semiconductor memory device according to the second embodiment. [Figure 6] FIG. 17 is a schematic diagram showing the circuit configuration of one row of the resistive change memories arranged in a matrix in the non-volatile semiconductor memory device according to the third embodiment. [Figure 7] FIG. 20 is a schematic diagram showing the circuit configuration of one row of the resistive change memories arranged in a matrix in the non-volatile semiconductor memory device according to the fourth embodiment.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

[0012] (1) First Embodiment (1-1) Circuit Configuration of Non-Volatile Semiconductor Memory Device FIG. 1 is a schematic diagram showing the circuit configuration of the non-volatile semiconductor memory device 1. The non-volatile semiconductor memory device 1 includes a memory array CA, a bit line selection circuit 2, a word line selection circuit 3, a voltage control circuit $4$, a plurality of bit lines BL, a plurality of word lines WL, and a plurality of voltage control lines VCL. In the example of this embodiment, the bit lines BL extend in the column direction, the word lines WL and the voltage control lines VCL extend in the row direction, and are orthogonal to each other.

[0013] The memory array CA has multiple antifuse memories M arranged in a matrix as memory cells. Each antifuse memory M (described later) in the memory array CA has the same configuration. To distinguish between individual antifuse memories M, i and j are designated as 1, 2, 3, etc., and the one in the i-th row and j-th column is designated as antifuse memory M. ij It will be described as such, and unless otherwise specified, it will simply be described as antifuse memory M. The antifuse memory M has a memory capacitor 7 and a selectable MOS transistor 8.

[0014] Furthermore, when distinguishing between antifuse memory M that is subject to data writing and reading and antifuse memory M that is not subject to data writing and reading, the former will be referred to as selected antifuse memory M, and the latter as unselected antifuse memory M. Additionally, rows in which selected antifuse memory M exists will be referred to as selected rows, and rows in which selected antifuse memory M does not exist will be referred to as unselected rows. Finally, columns in which selected antifuse memory M exists will be referred to as selected columns, and columns in which selected antifuse memory M does not exist will be referred to as unselected columns.

[0015] Bit lines BL are provided for each column of the antifuse memory M. Each bit line BL is connected to each antifuse memory M in its corresponding column. That is, multiple antifuse memories M arranged in the column direction share one bit line BL. Each bit line BL is connected to a bit line selection circuit 2. A predetermined voltage is selectively applied to each bit line BL from the bit line selection circuit 2. Each bit line BL applies the predetermined voltage applied from the bit line selection circuit 2 to each antifuse memory M in its corresponding column. When distinguishing the bit line BL of a particular column, the bit line BL of the j-th column is referred to as bit line BL. j This will be explained as follows.

[0016] The word lines WL and voltage control lines VCL are provided, corresponding to each row of the antifuse memory M.

[0017] Each word line WL is connected to each antifuse memory M in the corresponding row. Each word line WL is connected to a word line selection circuit 3. That is, multiple antifuse memories M arranged in the row direction share one word line WL. A predetermined voltage is selectively applied to each word line WL from the word line selection circuit 3. Each word line WL applies the predetermined voltage applied from the word line selection circuit 3 to each antifuse memory M in the corresponding row. When distinguishing the word line WL of a particular row, the word line WL of the i-th row is referred to as word line WL WL i This will be explained as follows.

[0018] Each voltage control line VCL is connected to each antifuse memory M in the corresponding row. That is, multiple antifuse memories M arranged in the row direction share one voltage control line VCL. Each voltage control line VCL is connected to a voltage control circuit 4. A predetermined voltage is selectively applied to each voltage control line VCL from the voltage control circuit 4. Each voltage control line VCL applies the predetermined voltage applied from the voltage control circuit 4 to each antifuse memory M in the corresponding row. When distinguishing the voltage control lines VCL of a particular row, the voltage control line VCL of the i-th row is referred to as voltage control line VCL i This will be explained as follows.

[0019] Figure 1 shows an example where the rows of odd-numbered antifuse memories M and the rows of even-numbered antifuse memories M are arranged symmetrically. In the example in Figure 1, a matrix-like antifuse memory M is arranged between the odd-numbered and even-numbered voltage control lines VCL, with the odd-numbered and even-numbered antifuse memories M arranged in the row direction. The selection MOS transistors 8 of the odd-numbered antifuse memories M and the selection MOS transistors 8 of the even-numbered antifuse memories M are directly connected between the odd-numbered and even-numbered voltage control lines VCL, and are arranged in the column direction.

[0020] In the embodiments described above, a configuration in which the row direction is applied as the first direction in which the voltage control line VCL extends is explained as an example. However, the present invention is not limited to this, and for example, a configuration in which the column direction is applied as the first direction in which the voltage control line VCL extends may also be used.

[0021] (1-2) Configuration of antifuse memory Next, the configuration of the antifuse memory M will be described. The antifuse memory M has a selection MOS transistor 8 and a memory capacitor 7. In this embodiment, the selection MOS transistor 8 is an N-type MOS transistor provided in a P-type well (not shown), and has a gate electrode 8a (see Figure 2), a source 8b (see Figure 2), and a drain 8c (see Figure 2). Also in this embodiment, the memory capacitor 7 is an N-type MOS half-transistor provided in a P-type well, and has a memory gate electrode 7a (see Figure 2), a diffusion layer region 7b (see Figure 2), and a memory gate insulating film (not shown) provided between the memory gate electrode 7a and the well. Antifuse memory M in the i-th row and j-th column ij This is the word line WL i Voltage control line VCL i and bit line BL j It connects to the network.

[0022] The antifuse memory M has the gate electrode 8a of the selected MOS transistor 8 connected to the word line WL, the source 8b of the selected MOS transistor 8 connected to the diffusion layer region 7b of the memory capacitor 7, and the drain 8c of the selected MOS transistor 8 connected to the bit line BL.

[0023] In the anti-fuse memory M, the memory gate electrode 7a of the memory capacitor 7 is connected to the voltage control line VCL. The memory capacitor 7 non-volatilely holds 1-bit data depending on whether or not the memory gate insulating film has been broken down. The memory capacitor 7 has an insulating state in which the memory gate insulating film has not been broken down and the memory gate electrode 7a and the surface of the well where a channel is formed during data writing or reading are electrically insulated from each other, and a short-circuit state in which the memory gate insulating film has been broken down and the memory gate electrode 7a and the surface of the well are electrically short-circuited, which respectively correspond to "0" or "1" of 1-bit data.

[0024] In this example, breaking down the memory gate insulating film to bring it into a short-circuit state is referred to as writing data to the anti-fuse memory M. Also, reading data means detecting whether the memory capacitor 7 is in an insulating state or a short-circuit state. The voltage of the bit line BL, word line WL, and voltage control line VCL of the anti-fuse memory M is controlled by the bit line selection circuit 2, word line selection circuit 3, and voltage control circuit 4, and data writing and reading are performed.

[0025] (1-3) Outline of data writing operation Next, an outline of the data writing operation to the selected anti-fuse memory M in the non-volatile semiconductor memory device 1 will be described. Here, among the plurality of anti-fuse memories M shown in FIG. 1 ij an example in which data is written with the anti-fuse memory M at the first row and first column (M 11 ) as the selected anti-fuse memory M will be described. In this case, the bit line selection circuit 2 applies a selected bit line voltage of 0 [V] to the selected bit line BL (BL1) of the column to which the selected anti-fuse memory M 11 is connected, and applies a non-selected bit line voltage of 3 [V] to the non-selected bit lines BL of the other columns. The word line selection circuit 3 applies a selected word line voltage of 3 [V] to the selected word line WL (WL1) of the row to which the selected anti-fuse memory M 11 is connected, and applies a non-selected word line voltage of 0 [V] to the non-selected word lines WL of the other rows.

[0026] The voltage control circuit 4 has a select antifuse memory M 11 A select voltage of 7[V] is applied as the write voltage to the select voltage control line VCL(VCL1) of the connected row, and a deselect voltage of 0[V] is applied to the deselect voltage control lines VCL of the other rows. 0[V] is applied to the well.

[0027] In this embodiment, the selected MOS transistor 8 is an enhancement-type transistor. Selected antifuse memory M 11 Then, 3[V] is applied from the selection word line WL1 to the gate electrode 8a of the selection MOS transistor 8, and 0[V] is applied from the selection bit line BL1 to the drain 8c of the selection MOS transistor 8. As a result, the selection MOS transistor 8 turns on, and the voltage across the diffusion layer region 7b of the memory capacitor 7 via the selection MOS transistor 8 becomes the selection bit line voltage of 0[V].

[0028] Select Antifuse Memory M 11 Then, when 7[V] is applied to the memory gate electrode 7a of the memory capacitor 7 from the selective voltage control line VCL (VCL1), and the voltage in the diffusion layer region 7b is 0[V], a channel is formed on the surface of the well below the memory gate electrode 7a, and the channel potential becomes the same potential as the voltage in the diffusion layer region 7b. As a result, the selective antifuse memory M 11 As a result, the potential difference between the channel and the memory gate electrode 7a becomes 7[V], causing dielectric breakdown of the memory gate insulating film at the bottom of the memory gate electrode 7a and writing the data.

[0029] Deselected antifuse memory M in the selected row and deselected column (for example, deselected antifuse memory M 12The selected MOS transistor 8 has 3V applied to its gate electrode 8a from the selected word line WL1, and 3V applied to its drain 8c from the selected bit line BL2. As a result, the selected MOS transistor 8 is turned off, and the non-selected bit line voltage is not supplied to the diffusion layer region 7b of the memory capacitor 7, resulting in a floating state.

[0030] Non-selective antifuse memory M 12 In the memory capacitor 7, a voltage of 7[V] is applied to the memory gate electrode 7a from the selective voltage control line VCL (VCL1), but because the diffusion layer region 7b is floating, the surface of the well below the memory gate electrode 7a becomes depleted, resulting in a voltage midway between the well's potential of 0[V] and the memory gate electrode 7a's potential of 7[V]. As a result, the non-selective antifuse memory M 12 Therefore, the potential difference between the well below the memory gate electrode 7a and the memory gate electrode 7a is a voltage between 0[V] and 7[V], so the memory gate insulating film at the bottom of the memory gate electrode 7a does not undergo dielectric breakdown and data is not written.

[0031] Non-selected row non-selected antifuse memory M (for example, non-selected antifuse memory M 21 The selected MOS transistor 8 is turned off when 0[V] is applied to the gate electrode 8a from the non-selected word line WL2. Non-selected antifuse memory M 21 In the memory capacitor 7, a non-selective voltage of 0[V] is applied to the memory gate electrode 7a from the non-selective voltage control line VCL(VCL2). As a result, no potential difference is generated between the memory gate electrode 7a and the surface of the well, the memory gate insulating film does not undergo dielectric breakdown, and no data is written.

[0032] (1-4) Overview of data reading operations Next, the data read operation of the selective antifuse memory M in the non-volatile semiconductor memory device 1 will be described. When reading data, for example, the word line selection circuit 3 applies a selected word line voltage of 3 [V] to the selected word line WL and a non-selected word line voltage of 0 [V] to the non-selected word line WL. The voltage control circuit 4 applies a selected voltage of 3 [V] to the selected voltage control line VCL and a non-selected voltage of 0 [V] to the non-selected voltage control line VCL. The non-volatile semiconductor memory device 1 detects the current of the bit line BL.

[0033] When data is being written to the selective antifuse memory M, the memory gate insulating film of the memory capacitor 7 is broken down, and 3V is applied to the gate electrode 8a, causing current to flow through the selected MOS transistor 8, which is turned ON, to the bit line BL. By detecting the current flowing through the bit line BL, the writing of data to the selective antifuse memory M can be detected.

[0034] On the other hand, if no data is written to the selective antifuse memory M, the memory gate insulating film of the memory capacitor 7 has not broken down, and therefore no current flows through the bit line BL to which the selective antifuse memory M is connected. By detecting that no current flows through the bit line BL, it is possible to detect that no data has been written to the selective antifuse memory M.

[0035] (1-5) Configuration of voltage control lines and current-assisted voltage control resistors In this case, the non-volatile semiconductor memory device 1 typically writes data to multiple antifuse memories M simultaneously. To ensure that the memory gate insulating film of the memory capacitor 7 is reliably broken down and sufficient current flows through the bit line BL when reading data, it is necessary to ensure a current of 100 [μA] or more at the time of the memory gate insulating film breakdown. For example, when writing data to 16-bit antifuse memories M in the same row simultaneously, a current of 1.6 [mA] is required.

[0036] The current required to break down the memory gate insulating film of the memory capacitor 7 is supplied from the voltage control circuit 4. The voltage control circuit 4 is designed to have sufficient current supply capability to handle simultaneous data writing to all antifuse memories M (maximum number of bits) located in the same row.

[0037] However, when the number of antifuse memory M (number of bits written) that write data in the same row is small, the voltage control circuit 4, which is designed with a high current supply capability, may supply more current than necessary, potentially applying excessive current to the antifuse memory M being written to.

[0038] If excessive current flows through the antifuse memory M during data writing, the memory gate electrode 7a may melt due to heat generated at the dielectric breakdown point of the memory gate insulating film. In this case, the melted electrode material of the memory gate electrode 7a may flow into a region of the well deeper than the channel formed on the surface of the well, potentially making it impossible to read the data.

[0039] Furthermore, due to variations in the manufacturing process, the current required to break down the memory gate insulating film of the memory capacitor 7 varies among the multiple antifuse memories M in the non-volatile semiconductor memory device 1. In antifuse memories M where the current required to break down the memory gate insulating film is small, excessive current flows during data writing, which may cause the memory gate electrode 7a to melt.

[0040] Considering the above points, in this embodiment, a current-assisted voltage-controlled resistor element 20a (see Figure 2) is provided for each row, and when writing data to the selected antifuse memory M, the voltage from the voltage control circuit 4 is supplied to the antifuse memory M of the same row via the current-assisted voltage-controlled resistor element 20a.

[0041] Next, the voltage control line VCL will be explained. Figure 2 is a schematic diagram showing the circuit configuration of one row of the antifuse memory M arranged in a matrix as shown in Figure 1, and the antifuse memory M from the 1st column to the jth column of the 1st row. 1j The configuration is shown below. As shown in Figure 2, the voltage control line VCL has a first voltage control line VCL1 and a second voltage control line VCL2. The first voltage control line VCL1 is connected to the voltage control circuit 4. The second voltage control line VCL2 is connected to the memory gate electrode 7a of each memory capacitor 7 of a plurality of corresponding antifuse memories M arranged in the row direction.

[0042] In addition to the above configuration, the voltage control line VCL according to this embodiment is provided with a current-assisted voltage control resistor element 20a. The current-assisted voltage control resistor element 20a comprises a resistor element 10 and a diode-connected MOS (Metal-Oxide Semiconductor) transistor 11. The resistor element 10 and the diode-connected MOS transistor 11 are connected in parallel between the first voltage control line VCL1 and the second voltage control line VCL2. In this embodiment, one current-assisted voltage control resistor element 20a is provided for each row of the antifuse memory M.

[0043] The resistive element 10 has one end connected to the first voltage control line VCL1 and the other end connected to the second voltage control line VCL2. In this embodiment, the diode-connected MOS transistor 11 has its gate electrode 11a and drain 11b connected to the first voltage control line VCL1, and its source 11c connected to the second voltage control line VCL2.

[0044] In this embodiment, a diode-connected MOS transistor 11 is described as an example of a current assist element, but the present invention is not limited to this, and for example, a MOS transistor may also be used. In this embodiment, the gate electrode of the MOS transistor is connected to a separate voltage control line independent of the first voltage control line VCL1 and the second voltage control line VCL2. By independently controlling the gate electrode with a separate voltage control line, the voltage of the gate electrode can be set higher than the drain voltage, thereby improving the function of the current assist element.

[0045] When writing data to the selective antifuse memory M, excessive current may flow depending on the state of the antifuse memory M. For example, immediately after the dielectric breakdown of the memory gate insulating film, the resistance of the breakdown point is small, which may cause excessive current to flow. In this case, the resistor element 10 of the current-assisted voltage-controlled resistor element 20a reduces the voltage of the second voltage control line VCL2 from the voltage of the first voltage control line VCL1, thereby reducing the voltage applied to the memory gate electrode 7a. As a result, the current flowing to the dielectric breakdown point of the memory gate insulating film in the memory capacitor 7 is suppressed, and excessive current is not applied. Consequently, it is possible to prevent the memory gate electrode 7a from melting due to heat generated by excessive current, and furthermore, it is possible to prevent the melted electrode material from flowing into a deep well region, causing the gate electrode and the well to be electrically connected, which would prevent current from flowing into the channel formed on the surface of the well during reading and make it impossible to read the data.

[0046] Furthermore, the length of the voltage control line VCL wiring from the voltage control circuit 4 to the antifuse memory M changes depending on the position of the antifuse memory M in the memory array CA. Therefore, when writing data to a selected antifuse memory M, the closer the antifuse memory M is to the voltage control circuit 4 in the memory array CA, the lower the wiring resistance value of the voltage control line VCL becomes, potentially causing excessive current to flow and resulting in a failure where the memory gate electrode 7a melts. In this case, the resistor element 10 of the current-assisted voltage control resistor element 20a reduces the voltage applied to the memory gate electrode 7a of the antifuse memory M that is closer to the voltage control circuit 4. As a result, the problem of the memory gate electrode 7a melting due to heat generated by excessive current can be prevented. In particular, the above problem can be effectively prevented by making the resistance value of the resistor element 10 greater than the wiring resistance value of the first voltage control line VCL1.

[0047] On the other hand, the resistance of the selective antifuse memory M may be high, and it may not be possible to supply sufficient voltage to cause dielectric breakdown at the memory gate electrode 7a. In this case, the current-assisted voltage-controlled resistor element 20a turns on the diode-connected MOS transistor 11 when the voltage drop by the resistor element 10 exceeds the threshold voltage of the diode-connected MOS transistor 11. As a result, the voltage of the second voltage control line VCL2 is maintained at a voltage lower than the voltage of the first voltage control line VCL1 by the threshold voltage of the diode-connected MOS transistor 11. A voltage lower than the voltage of the first voltage control line VCL1 by the threshold voltage of the diode-connected MOS transistor 11 is applied to the memory gate electrode 7a, ensuring that the current necessary for dielectric breakdown of the memory gate insulating film is reliably secured. Furthermore, even if the resistance value of the resistor element 10 increases due to variations in the manufacturing process, the diode-connected MOS transistor 11 will turn on, ensuring that the current necessary for dielectric breakdown of the memory gate insulating film is reliably secured. This makes it possible to suppress the voltage drop applied to the memory gate electrode 7a by the resistor element 10 while supplementing the current flowing to the antifuse memory M with the diode-connected MOS transistor 11.

[0048] (1-6) Planar layout configuration of non-volatile semiconductor memory device Next, the planar layout configuration of the non-volatile semiconductor memory device 1 will be described. Figure 3 is a schematic diagram showing an example of the planar layout configuration of the non-volatile semiconductor memory device 1 shown in Figure 1. Figure 3 shows the planar layout configuration of the second row antifuse memory M, the second and third rows of voltage control lines VCL, and the third row antifuse memory M in the region of part E1 in Figure 1.

[0049] In Figure 3, among the antifuse memories M arranged in a matrix, each antifuse memory M adjacent to another in the column direction is arranged symmetrically with respect to the column direction. Multiple active regions AA1 defined by an element isolation film are formed in a well (not shown) provided in the semiconductor substrate. The active regions AA1 are rectangular in shape, elongated in the column direction, and are arranged in the row direction with predetermined intervals between them. An antifuse memory M is formed in each of the matrix-arranged active regions AA1.

[0050] Word lines WL are formed by polysilicon layers extending in the row direction, intersecting the active regions AA1 which are arranged in the row direction. The word lines WL are shared by the antifuse memories M which are also arranged in the row direction. The portion of the word lines WL that is on the active regions AA1 becomes the gate electrode 8a of each selected MOS transistor 8. A gate insulating film (not shown) is provided between the active regions AA1 and the gate electrode 8a.

[0051] At one end of the longitudinal direction of each active region AA1 arranged in the row direction, a memory gate line MGL is formed by a polysilicon layer extending in the row direction, intersecting each active region AA1. The memory gate line MGL is shared by the antifuse memory M arranged in the row direction. The portion of the memory gate line MGL on the active region AA1 becomes the memory gate electrode 7a of the memory capacitor 7. A memory gate insulating film (not shown) is provided between the active region AA1 and the memory gate electrode 7a. The portion of the active region AA1 that overlaps with the memory gate line MGL becomes a well of the memory capacitor 7, where a channel is formed on its surface during data writing and reading. A diffusion layer region 7b of the memory capacitor 7 is provided in the active region AA1 adjacent to the well.

[0052] The source 8b of the selected MOS transistor 8 is provided in the region between the portion of the active region AA1 that intersects with the word line WL and the portion that overlaps with the memory gate line MGL, and is connected to the diffusion layer region 7b of the memory capacitor 7. The drain 8c of the selected MOS transistor 8 is provided in the region of the active region AA1 opposite the source 8b, with the word line WL in between. A contact C1 is formed on the drain 8c, and the bit line BL (not shown) is electrically connected to the drain 8c via the contact C1. The active region AA1 is formed by integrating the active region AA1 of one antifuse memory M adjacent in the column direction and the active region AA1 of another antifuse memory M (for example, an antifuse memory M located below the antifuse memory M shown by the dotted line), and the contact C1 is shared by the one and the other antifuse memory M adjacent in the column direction.

[0053] A contact C2 is formed on the memory gate line MGL, and the second voltage control line VCL2, described later, is electrically connected to the memory gate electrode 7a via contact C2.

[0054] Next, the formation region of the current-assisted voltage-controlled resistor element 20a will be described. In Figure 3, multiple antifuse memories M in the lower row are connected to the current-assisted voltage-controlled resistor element 20a on the left side of the page, and multiple antifuse memories M in the upper row are connected to the current-assisted voltage-controlled resistor element 20a on the right side of the page. The current-assisted voltage-controlled resistor element 20a on the left side of the page and the current-assisted voltage-controlled resistor element 20a on the right side of the page are formed with a left-right symmetrical structure that is inverted vertically. The following explanation will focus on the current-assisted voltage-controlled resistor element 20a on the left side of the page.

[0055] The active region AA2 constituting the current-assisted voltage-controlled resistor element 20a is located between the active region AA1 arranged in the row direction of the lower row and the active region AA1 arranged in the row direction of the upper row. The active region AA2 is formed in a rectangular shape that is long in the row direction. A rectangular pattern PL1 made of a polysilicon layer is formed in the active region AA2 so as to intersect the active region AA2 and extend in the row direction.

[0056] Pattern PL1 constitutes the resistor element 10 of the current-assisted voltage-controlled resistor element 20a. Pattern PL1 also constitutes the gate electrode 11a of the diode-connected MOS transistor 11, which acts as the current assist element for the current-assisted voltage-controlled resistor element 20a.

[0057] A contact C3 is formed at one longitudinal end of pattern PL1, and a contact C4 is formed at the other end. In the active region AA2, a contact C5 is formed on one lower side of pattern PL1, and a contact C6 is formed on the other upper side.

[0058] A wiring M1 formed in the first metal layer is connected to contacts C2 and C5, and contact C3 at one end of pattern PL1, which are formed on the memory gate line MGL. Wiring M1 constitutes the second voltage control line VCL2.

[0059] A wiring M2 formed of the first metal layer is connected to contact C4 at the other end of pattern PL1 and to contact C6 on the upper side of the active region AA2. A via V1 is formed on wiring M2, and a wiring M3 formed of the second metal layer is formed on via V1. Wiring M3 is connected to the voltage control circuit 4. Wirings M2 and M3 constitute the first voltage control line VCL1.

[0060] Thus, the first voltage control line VCL1 is connected to the other end of pattern PL1 via contact C4, and the second voltage control line VCL2 is connected to the one end of pattern PL1 via contact C3. The polysilicon layer of pattern PL1 between contact C4 and contact C3 acts as a resistor, and a resistive element 10 is connected between the first voltage control line VCL1 and the second voltage control line VCL2.

[0061] Pattern PL1 also functions as the gate electrode 11a of the diode-connected MOS transistor 11, and a gate insulating film (not shown) of the diode-connected MOS transistor 11 is provided between the active region AA2 and pattern PL1. The active region AA2 on which contact C5 is formed becomes the source 11c of the diode-connected MOS transistor 11. The active region AA2 on the opposite side (upper side) of contact C5 and pattern PL1, on which contact C6 is formed, becomes the drain 11b of the diode-connected MOS transistor 11. The drain 11b of the diode-connected MOS transistor 11 is connected to pattern PL1, which is the gate electrode 11a of the diode-connected MOS transistor 11, via contact C6, wiring M2, and contact C4.

[0062] The source 11c of the diode-connected MOS transistor 11 is connected to the second voltage control line VCL2 via contact C5. The drain 11b and gate electrode 11a of the diode-connected MOS transistor 11 are connected to the first voltage control line VCL1 via contact C6. The diode-connected MOS transistor 11 is connected between the first voltage control line VCL1 and the second voltage control line VCL2. In the circuit diagram, as shown in Figure 1, the resistor element 10 and the diode-connected MOS transistor 11 are connected in parallel between the first voltage control line VCL1 and the second voltage control line VCL2.

[0063] (1-7) Action and Effects The non-volatile semiconductor memory device 1 according to this embodiment includes a voltage control line VCL extending in a row direction which is a first direction, and a memory array CA including a plurality of antifuse memories M arranged in the row direction. The antifuse memory M includes a memory capacitor 7 having a memory gate electrode 7a, a diffusion layer region 7b provided in a well, and a memory gate insulating film formed between the memory gate electrode 7a and the well.

[0064] In this embodiment, the antifuse memory M has the memory gate electrode 7a of the memory capacitor 7 as the first terminal, and the diffusion layer region 7b of the memory capacitor 7 and the well below the memory gate electrode 7a as the second terminal. The voltage control line VCL includes a first voltage control line VCL1 and a second voltage control line VCL2, with the first voltage control line VCL1 connected to the voltage control circuit 4. The second voltage control line VCL2 is connected to the memory gate electrode 7a (first terminal) of each memory capacitor 7 of the plurality of antifuse memories M arranged in the row direction. A current-assisted voltage-controlled resistor element 20a is provided between the first voltage control line VCL1 and the second voltage control line VCL2. The resistor element 10 and the diode-connected MOS transistor 11 of the current-assisted voltage-controlled resistor element 20a are connected in parallel between the first voltage control line VCL1 and the second voltage control line VCL2.

[0065] When the non-volatile semiconductor memory device 1 writes data to the selective antifuse memory M, if the resistance of the antifuse memory M is low, there is a risk of excessive current flowing. In this case, the resistance element 10 of the current-assisted voltage-controlled resistor element 20a reduces the voltage of the second voltage control line VCL2 from the voltage of the first voltage control line VCL1, thereby reducing the voltage applied to the memory gate electrode 7a. As a result, the current flowing to the dielectric breakdown portion of the memory gate insulating film in the memory capacitor 7 is suppressed, and excessive current is not applied. Consequently, it is possible to prevent the memory gate electrode 7a from melting due to heat generated by excessive current, and furthermore, it is possible to prevent the molten electrode material from flowing into the deep well region, making it impossible to read the data.

[0066] Furthermore, in the non-volatile semiconductor memory device 1, the resistance of the selective antifuse memory M is high, and it may not be possible to supply sufficient voltage to cause dielectric breakdown to the memory gate electrode 7a. In this case, the current-assisted voltage-controlled resistor element 20a turns on the diode-connected MOS transistor 11 when the voltage drop by the resistor element 10 exceeds the threshold voltage of the diode-connected MOS transistor 11. As a result, the voltage of the second voltage control line VCL2 is maintained at a voltage lower than the voltage of the first voltage control line VCL1 by the threshold voltage of the diode-connected MOS transistor 11. A voltage lower than the voltage of the first voltage control line VCL1 by the threshold voltage of the diode-connected MOS transistor 11 is applied to the memory gate electrode 7a, ensuring that the current necessary for dielectric breakdown of the memory gate insulating film is reliably secured. This makes it possible to suppress the voltage drop applied to the memory gate electrode 7a by the resistor element 10 while supplementing the current flowing to the antifuse memory M with the diode-connected MOS transistor 11.

[0067] As described above, the non-volatile semiconductor memory device 1 has a resistor 10 and a diode-connected MOS transistor 11 in parallel between the first voltage control line VCL1 and the second voltage control line VCL2. This allows the optimal voltage to be supplied to each antifuse memory M arranged in the row direction via either the resistor 10 or the diode-connected MOS transistor 11, depending on the state of the antifuse memory M. This enables stable writing to each antifuse memory M.

[0068] In the planar layout configuration of the non-volatile semiconductor memory device 1, as shown in Figure 3, the first row of antifuse memory M and the second row of antifuse memory M are arranged symmetrically along the row direction to which a voltage control line VCL extends. The non-volatile semiconductor memory device 1 has current-assisted voltage-controlled resistor elements 20a connected to the antifuse memory M for each row arranged in a row direction between the first row of antifuse memory M and the second row of antifuse memory M. This allows two current-assisted voltage-controlled resistor elements 20a for two rows to be placed between the first row of antifuse memory M and the second row of antifuse memory M, thereby suppressing an increase in layout area.

[0069] (2) Second Embodiment In the first embodiment described above, a case was described in which a diode-connected MOS transistor 11 was provided as a current assist element. However, the present invention is not limited to this, and as shown in Figure 4, a diode 31 may be provided as a current assist element. Figure 4 has the same configuration as the non-volatile semiconductor memory device 1 according to the first embodiment, except that the diode-connected MOS transistor 11 shown in Figure 2 is replaced with a diode 31. Here, in order to avoid repetition of explanation, only the diode 31 will be described below.

[0070] (2-1) Configuration of a current-assisted voltage-controlled resistor element according to the second embodiment Figure 4, which uses the same reference numerals as Figure 2, is a schematic diagram showing the circuit configuration of one row of antifuse memory M arranged in a matrix, similar to Figure 1, and shows the antifuse memory M from the 1st column to the jth column of the 1st row. 1j The configuration is shown below.

[0071] The voltage control line VCL is provided with a current-assisted voltage control resistor element 20b according to the second embodiment. The current-assisted voltage control resistor element 20b comprises a resistor element 10 and a diode 31. The resistor element 10 and the diode 31 are connected in parallel between the first voltage control line VCL1 and the second voltage control line VCL2. In this embodiment, one current-assisted voltage control resistor element 20b is provided for each row of the antifuse memory M. The diode 31 has its anode 31a connected to the first voltage control line VCL1 and its cathode 31b connected to the second voltage control line VCL2.

[0072] (2-2) Planar layout configuration of non-volatile semiconductor memory device according to the second embodiment Next, the planar layout configuration of the non-volatile semiconductor memory device according to the second embodiment will be described. Figure 5 is a schematic diagram showing an example of the planar layout configuration of the non-volatile semiconductor memory device, similar to Figure 3. Figure 5 shows the planar layout configuration of the second row antifuse memory M, the second and third rows of voltage control lines VCL, and the third row antifuse memory M in the region of part E1 in Figure 1, similar to Figure 3. The explanation of the planar layout configuration of the antifuse memory M in Figure 5 is the same as in Figure 3, so the explanation will be omitted, and the following explanation will focus on the planar layout configuration of the current-assisted voltage-controlled resistor element 20b, which differs from that in Figure 3.

[0073] In Figure 5, multiple antifuse memories M in the lower row are connected to the current-assisted voltage-controlled resistor element 20b on the left, and multiple antifuse memories M in the upper row are connected to the current-assisted voltage-controlled resistor element 20b on the right. The current-assisted voltage-controlled resistor element 20b on the left and the current-assisted voltage-controlled resistor element 20b on the right are formed with a left-right symmetrical structure that is inverted vertically. The following explanation will focus on the current-assisted voltage-controlled resistor element 20b on the left.

[0074] A rectangular pattern PL2 made of a polysilicon layer is formed on an element isolation film (not shown) provided on a semiconductor substrate, extending in the row direction. Pattern PL2 constitutes the resistive element 10 of the current-assisted voltage-controlled resistive element 20b. Pattern PL2 also constitutes a PN junction diode, which acts as the current assist element of the current-assisted voltage-controlled resistive element 20b.

[0075] A P-type polysilicon layer 32a, in which P-type impurities have been introduced into the polysilicon layer, is formed on one longitudinal end of pattern PL2. An N-type polysilicon layer 32b, in which N-type impurities have been introduced into the polysilicon layer, is formed on the other longitudinal end of pattern PL2. In the P-type polysilicon layer 32a of pattern PL2, a contact C7 is formed on one end away from the N-type polysilicon layer 32b, and a contact C9 is formed on the other end closer to the N-type polysilicon layer 32b. A contact C8 is formed in the N-type polysilicon layer 32b of pattern PL2.

[0076] A wiring M4 formed in the first metal layer is connected to contact C2 formed on the memory gate line MGL and to contacts C7 and C8 formed on pattern PL2. Wiring M4 constitutes the second voltage control line VCL2.

[0077] A wiring M5 formed in the first metal layer is connected to a contact C9 formed in the P-type polysilicon layer 32a of pattern PL2. A via V2 is formed on wiring M5, and a wiring M6 formed in the second metal layer is formed on via V2. Wiring M6 is connected to the voltage control circuit 4. Wirings M5 and M6 constitute the first voltage control line VCL1.

[0078] In pattern PL2, a second voltage control line VCL2 is connected via contact C7 to one end of the P-type polysilicon layer 32a that is separated from the N-type polysilicon layer 32b. In the region of the P-type polysilicon layer 32a that is separated from contact C7 and close to the N-type polysilicon layer 32b, a first voltage control line VCL1 is connected via contact C9. The P-type polysilicon layer 32a between contact C7 and contact C9 acts as a resistor, and a resistive element 10 is connected between the first voltage control line VCL1 and the second voltage control line VCL2.

[0079] A second voltage control line VCL2 is connected to the N-type polysilicon layer 32b via a contact C8 at its right end, which is separated from the P-type polysilicon layer 32a. A PN junction diode (hereinafter simply referred to as a diode) 31 is provided between the contact C9 of the P-type polysilicon layer 32a to which the first voltage control line VCL1 is connected and the contact C8 of the N-type polysilicon layer 32b to which the second voltage control line VCL2 is connected. As a result, the diode 31 is connected between the first voltage control line VCL1 and the second voltage control line VCL2. In the circuit diagram, as shown in Figure 4, a resistor 10 and a diode 31 are connected in parallel between the first voltage control line VCL1 and the second voltage control line VCL2.

[0080] In this embodiment, a PN junction diode composed of a P-type polysilicon layer 32a and an N-type polysilicon layer 32b is used as the diode 31, which serves as a current assist element. For example, the work function of the P-type polysilicon layer 32a at the anode 31a is approximately 0.7 [eV] greater than the work function of the N-type polysilicon layer 32b at the cathode 31b.

[0081] (2-3) Action and Effects The current-assisted voltage-controlled resistor element 20b according to the second embodiment is provided with a diode 31 as a current-assisted element. The diode 31 has its anode 31a connected to the first voltage control line VCL1 and its cathode 31b connected to the second voltage control line VCL2.

[0082] In the non-volatile semiconductor memory device according to the second embodiment, when writing data to the selective antifuse memory M, if the resistance of the antifuse memory M is small, there is a risk of excessive current flowing. In this case, the resistance element 10 of the current-assisted voltage-controlled resistor element 20b reduces the voltage of the second voltage control line VCL2 from the voltage of the first voltage control line VCL1, thereby reducing the voltage applied to the memory gate electrode 7a. As a result, the current flowing to the dielectric breakdown portion of the memory gate insulating film in the memory capacitor 7 is suppressed, and excessive current is not applied. Consequently, it is possible to prevent the memory gate electrode 7a from melting due to heat generated by excessive current, and furthermore, it is possible to prevent the molten electrode material from flowing into a deep well region, making it impossible to read the data.

[0083] Furthermore, in the non-volatile semiconductor memory device according to the second embodiment, the resistance of the selective antifuse memory M is high, and it may not be possible to supply a sufficient voltage to cause dielectric breakdown at the memory gate electrode 7a. In this case, when the voltage drop amount by the resistor element 10 exceeds the difference in work function between the anode 31a and cathode 31b of the diode 31, the current-assisted voltage-controlled resistor element 20b allows a forward current to flow from the anode 31a to the cathode 31b. As a result, the voltage of the second voltage control line VCL2 is maintained at a voltage lower than the voltage of the first voltage control line VCL1 by the work function difference between the anode 31a and cathode 31b of the diode 31. A voltage lower than the voltage of the first voltage control line VCL1 by the work function difference between the anode 31a and cathode 31b of the diode 31 is applied to the memory gate electrode 7a, ensuring that the current necessary for dielectric breakdown of the memory gate insulating film is reliably secured. Furthermore, even if the resistance value of the resistive element 10 increases due to variations in the manufacturing process, forward current flows through the diode 31, ensuring that the current necessary for dielectric breakdown of the memory gate insulating film is reliably secured. Since the amount of current can be controlled by the width, length, and height of the diode 31's pattern PL2, the current necessary for dielectric breakdown of the memory gate insulating film can be reliably secured. This allows the diode 31 to supplement the current flowing through the antifuse memory M while suppressing the voltage drop applied to the memory gate electrode 7a due to the resistive element 10.

[0084] As described above, the non-volatile semiconductor memory device according to the second embodiment has a resistor 10 and a diode 31 arranged in parallel between the first voltage control line VCL1 and the second voltage control line VCL2, so that the optimal voltage can be supplied to each antifuse memory M arranged in the row direction via either the resistor 10 or the diode 31 depending on the state of the antifuse memory M. As a result, stable writing can be performed to each antifuse memory M.

[0085] Furthermore, in the planar layout configuration of the semiconductor memory device according to the second embodiment, as shown in Figure 5, current-assisted voltage-controlled resistor elements 20b connected to the antifuse memory M for each row are arranged in a row direction between the first row antifuse memory M and the second row antifuse memory M. This allows two current-assisted voltage-controlled resistor elements 20b for two rows to be placed between the first row antifuse memory M and the second row antifuse memory M, thereby suppressing an increase in layout area.

[0086] In the second embodiment, the case described was a PN junction diode in which the diode 31 as a current assist element is composed of a P-type polysilicon layer 32a and an N-type polysilicon layer 32b. However, the invention is not limited to this, and other diodes may be used as long as a configuration can be obtained in which the work function of the anode is greater than the work function of the cathode. For example, a Schottky barrier diode may be used. For example, by using tungsten W as the anode and N-type silicon as the cathode, or by using P-type silicon as the anode and tungsten W as the cathode, the work function difference can be made smaller compared to a PN junction diode. In this case, when the resistance of the antifuse memory M is high and a sufficient voltage to cause dielectric breakdown at the memory gate electrode 7a cannot be supplied, a higher voltage to cause dielectric breakdown at the memory gate electrode 7a can be supplied more stably.

[0087] Furthermore, as a current assist element, a device with a rectifying effect may be applied by forming a junction with two materials having different work functions and placing the material with the relatively larger work function on the anode side. For example, a current assist element may be formed by utilizing the difference in work functions between materials such as tantalum Ta (work function: 3.9 [eV]), hafnium Hf (work function: 3.9 [eV]), titanium Ti (work function: 4.3 [eV]), aluminum (work function: 4.3 [eV]), tungsten W (work function: 4.6 [eV]), ruthenium Ru (work function: 4.8 [eV]), and iridium Ir (work function: 5.3 [eV]), or their nitrides (e.g., TiN) or silicides (e.g., TaSiN), listed in descending order of work function.

[0088] In the second embodiment, a case was described in which the resistive element 10 and the diode 31 are constructed using a single polysilicon layer pattern PL2. However, the invention is not limited to this, and the pattern constituting the resistive element 10 and the pattern constituting the diode 31 may be formed using separate, independent patterns and connected by wiring.

[0089] (3) Third Embodiment In the first and second embodiments described above, a non-volatile semiconductor memory device 1 was described using an antifuse memory M having a memory capacitor 7 and a selectable MOS transistor 8 as a memory cell. However, the present invention is not limited to these embodiments and may also be applied to a crosspoint type non-volatile semiconductor memory device. Figure 6 shows a crosspoint type non-volatile semiconductor memory device using a resistive random access memory (ReRAM) RM as a two-terminal memory cell. Here, to avoid repetition in the explanation, the following description will mainly focus on the resistive random access memory RM. Note that the non-volatile semiconductor memory device according to the third embodiment differs from the non-volatile semiconductor memory device 1 according to the first embodiment described above in that it does not have a selectable MOS transistor 8 and a word line WL.

[0090] Figure 6, which uses the same reference numerals as Figure 2, is a schematic diagram showing the circuit configuration of one row of resistive change memory RM arranged in a matrix, similar to Figure 1, and shows the resistive change memory RM from the 1st column to the jth column of the 1st row. 1j The configuration is shown. Note that the resistive random-access memory RM 1j Unless otherwise specified, it will simply be described as resistive change memory (RM).

[0091] The resistive random-access memory RM comprises a first terminal 35a and a second terminal 35b. In the resistive random-access memory RM, the first terminal 35a is connected to the second voltage control line VCL2, and the second terminal 35b is connected to the bit line BL of the corresponding row. In the resistive random-access memory RM, writing is performed to the selected non-volatile memory based on the potential difference between the selected voltage applied to the voltage control line VCL as the write voltage and the selected bit line voltage applied to the bit line BL.

[0092] In the non-volatile semiconductor memory device according to the third embodiment, similar to the first embodiment, a resistor element 10 and a diode-connected MOS transistor 11 are provided in parallel between the first voltage control line VCL1 and the second voltage control line VCL2. This allows the optimal voltage to be supplied to each resistance change memory RM arranged in the row direction via either the resistor element 10 or the diode-connected MOS transistor 11, depending on the state of the resistance change memory RM. This enables stable writing to each resistance change memory RM.

[0093] (4) Fourth Embodiment In the third embodiment described above, a case was described in which a diode-connected MOS transistor 11 was provided as a current assist element. However, the present invention is not limited to this, and as shown in the fourth embodiment in Figure 7, the diode 31 shown in the second embodiment may be provided as a current assist element. Even with this configuration according to the fourth embodiment, as in the first embodiment, the optimal voltage can be supplied to each resistance change memory RM arranged in the row direction via either the resistor element 10 or the diode 31 depending on the state of the resistance change memory RM. This enables stable writing to each resistance change memory RM.

[0094] (5) Others In addition to the resistive random access memory RM described above, other types of two-terminal memory cells with a first terminal and a second terminal may also be used, such as phase-change memory (PCM), ferroelectric random access memory (FeRAM), or magnetoresistive random access memory (MRAM). Furthermore, an antifuse capacitor, such as the memory capacitor 7 of the antifuse memory M, may also be used as a two-terminal memory cell with a first terminal and a second terminal.

[0095] Furthermore, a three-dimensional memory cell structure such as a FIN structure or a GAA (Gate All Around) structure may be used as a two-terminal memory cell. In this case, the diode-connected MOS transistor 11, which serves as a current assist element, does not need to be configured on the semiconductor substrate plane, and a FIN structure, FD-SOI (Fully Depleted Silicon-On-Insulator) structure, or GAA structure may be used instead.

[0096] Furthermore, in other embodiments, transistors with reversed N-type and P-type conductivity may be used for the memory capacitor 7, selected MOS transistor 8, and diode-connected MOS transistor 11 that constitute the non-volatile semiconductor memory device 1. [Explanation of Symbols]

[0097] 1. Non-volatile semiconductor memory 4. Voltage control circuit 7 Memory Capacitors 8 Selectable MOS Transistors 10 Resistor elements 11. Diode-connected MOS transistor (current assist element, MOS transistor) 20a, 20b Current-assisted voltage-controlled resistor element 31 PN junction diode (current assist element) BL bit line CA Memory Array M Antifuse memory (memory cell) RM Resistive random-access memory (memory cell) VCL voltage control line VCL1 First voltage control line VCL2 Second Voltage Control Line

Claims

1. A voltage control line extending in the first direction, A memory array comprising a plurality of memory cells arranged in the first direction, The memory cell comprises a first terminal and a second terminal, The voltage control line includes a first voltage control line and a second voltage control line. The first voltage control line is connected to the voltage control circuit, The second voltage control line is connected to the first terminal of the plurality of memory cells arranged in the first direction, A resistive element and a current assist element are connected in parallel between the first voltage control line and the second voltage control line. The memory cell is an antifuse memory, The antifuse memory comprises a memory capacitor having a memory gate electrode, a diffusion layer region provided in a well, and a memory gate insulating film formed between the memory gate electrode and the well. The first terminal is the memory gate electrode, and the second terminal is the diffusion layer region and the well. A write voltage is applied to the voltage control line that causes dielectric breakdown of the memory gate insulating film. Non-volatile semiconductor memory device.

2. The current assisting element is a MOS transistor, The drain is connected to the first voltage control line, and the source is connected to the second voltage control line. The non-volatile semiconductor memory device according to claim 1.

3. The gate electrode of the MOS transistor is connected to the first voltage control line. The non-volatile semiconductor memory device according to claim 2.

4. A voltage control line extending in a first direction, A memory array comprising a plurality of memory cells arranged in the first direction, The memory cell comprises a first terminal and a second terminal, The voltage control line includes a first voltage control line and a second voltage control line. The first voltage control line is connected to the voltage control circuit, The second voltage control line is connected to the first terminal of the plurality of memory cells arranged in the first direction, A resistive element and a current assist element are connected in parallel between the first voltage control line and the second voltage control line. The current assisting element is an element in which a junction is formed between a first material having a first work function and a second material having a second work function smaller than the first work function. The first material is connected to the first voltage control line, and the second material is connected to the second voltage control line. Non-volatile semiconductor memory device.

5. The current assisting element is a diode, The anode is connected to the first voltage control line, and the cathode is connected to the second voltage control line. The non-volatile semiconductor memory device according to claim 1.

6. It comprises a resistive element and a current assisting element, The resistive element and the current assisting element are connected in parallel between the first voltage control line and the second voltage control line that constitute the voltage control line of the non-volatile semiconductor memory device. The current assisting element is a MOS transistor, The resistive element is formed from the gate electrode of the MOS transistor. The first voltage control line is a voltage control line connected to the voltage control circuit of the non-volatile semiconductor memory device, and the second voltage control line is a voltage control line connected to the memory cell of the non-volatile semiconductor memory device. The drain of the MOS transistor is connected to the first voltage control line, and the source of the MOS transistor is connected to the second voltage control line. Current-assisted voltage-controlled resistor element.

7. comprising a resistive element and a current assisting element, The resistive element and the current assisting element are connected in parallel between the first voltage control line and the second voltage control line that constitute the voltage control line of the non-volatile semiconductor memory device. The current assisting element is an element in which a junction is formed between a first material having a first work function and a second material having a second work function smaller than the first work function. The first voltage control line is a voltage control line connected to the voltage control circuit of the non-volatile semiconductor memory device, and the second voltage control line is a voltage control line connected to the memory cell of the non-volatile semiconductor memory device. The first material is connected to the first voltage control line, and the second material is connected to the second voltage control line. Current-assisted voltage-controlled resistor element.

8. comprising a resistive element and a current assisting element, The resistive element and the current assisting element are connected in parallel between the first voltage control line and the second voltage control line that constitute the voltage control line of the non-volatile semiconductor memory device. The current assisting element is a PN junction diode formed of a P-type polysilicon layer and an N-type polysilicon layer. The resistive element is formed from the P-type polysilicon layer, The first voltage control line is a voltage control line connected to the voltage control circuit of the non-volatile semiconductor memory device, and the second voltage control line is a voltage control line connected to the memory cell of the non-volatile semiconductor memory device. The P-type polysilicon layer is connected to the first voltage control line, and the N-type polysilicon layer is connected to the second voltage control line. Current-assisted voltage-controlled resistor element.

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