Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The preparation method comprises: forming a stack structure on a substrate, the stack structure comprising a first array region, a second array region and a first connection region, the first connection region comprising a plurality of functional regions arranged in a first direction, and each functional region comprising two sub-connection regions arranged in a second direction; etching the stack structure on the plurality of sub-connection regions to form a plurality of initial step blocks, the plurality of initial step blocks being arranged in two rows, in the first direction, each initial step block having a height difference between a first initial part and a second initial part, and in the second direction, the two adjacent initial step blocks having a height difference; and etching the plurality of initial step blocks to form a plurality of sequentially arranged step blocks, the step blocks being arranged in two rows in the second direction, and each step block comprising at least four stack pairs. According to the application, no residues are left in the corner of the step, and the subsequent operation space of the step block is larger.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a three-dimensional memory and a preparation method thereof. BACKGROUND

[0002] By improving process technology, circuit design, programming algorithm and manufacturing process, the planar storage unit is reduced to a smaller size. However, as the feature size of the storage unit approaches the lower limit, the planar process and manufacturing technology become challenging and costly. As a result, the storage density of the planar storage unit approaches the upper limit.

[0003] In order to solve the density limitation in the planar storage unit and reduce the development cost of the storage unit, a three-dimensional memory device is developed. SUMMARY

[0004] The present application provides a preparation method of a semiconductor device, comprising: providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of stack pairs, wherein the stack structure comprises a first array region, a second array region and a first connection region arranged between the first array region and the second array region, the first connection region comprising a plurality of functional regions arranged in a first direction in sequence, each of the functional regions comprising two sub-connection regions arranged in a second direction; etching the stack structure on the plurality of sub-connection regions to form a plurality of initial step blocks, the plurality of initial step blocks being arranged in two rows, in the first direction, each of the initial step blocks comprising a first initial part and a second initial part, the first initial part and the second initial part having a height difference; in the second direction, there is a height difference between two adjacent initial step blocks; etching the plurality of initial step blocks to form a plurality of step blocks arranged in sequence, in the second direction, the step blocks are arranged in two rows, and the steps in the step blocks comprise at least four stack pairs.

[0005] In the first direction, the step block comprises a first step part and a second step part, the first step part and the second step part are arranged oppositely, and the steps in the first step part and the steps in the second step part are arranged in staggered manner.

[0006] In the second direction, each of the step blocks comprises a rear step block and a front step block, the steps of the rear step block are higher than the steps of the adjacent front step block by two heights of the stack pairs.

[0007] In the first direction, the step set comprises adjacent first step set and second step set, the starting step of the second step set is at least higher than the bottom end step of the first step set by one height of the stack pairs.

[0008] wherein, in the first direction, the first initial portion of the initial stepped block is higher than the second initial portion by three heights of the stacked pairs.

[0009] wherein, in the second direction, two rows of the initial stepped blocks are a rear row of initial stepped blocks and a front row of initial stepped blocks, and a step of the rear row of initial stepped blocks is higher than a step of the adjacent front row of initial stepped blocks by two heights of the stacked pairs.

[0010] wherein, the etching the plurality of initial stepped blocks to form a plurality of sequentially arranged stepped blocks comprises: etching the plurality of initial stepped blocks in units of at least four heights of the stacked pairs to form a plurality of intermediate stepped blocks, the plurality of intermediate stepped blocks being arranged in two rows, a first stepped portion of the initial stepped block being etched to form a first stepped portion of the intermediate stepped block, a second stepped portion of the initial stepped block being etched to form a second stepped portion of the intermediate stepped block, the first stepped portion of the intermediate stepped block being arranged opposite to the second stepped portion of the intermediate stepped block, and a step of the first stepped portion of the intermediate stepped block being arranged in a staggered manner with a step of the second stepped portion of the intermediate stepped block, the first stepped portion being higher than the second stepped portion by three heights of the stacked pairs.

[0011] wherein, the first connection region further comprises a first top gate region and a second top gate region, and the plurality of functional regions are connected between the first top gate region and the second top gate region in the first direction; before etching the stacked structure on the plurality of sub-connection regions, the preparation method further comprises: etching the stacked structure on the first top gate region in units of one height of the stacked pairs to form a first top selection gate stepped block, and / or etching the stacked structure on the second top gate region in units of one height of the stacked pairs to form a second top selection gate stepped block, wherein a starting step of the stepped set at the top is at least one height of the stacked pairs higher than a tail end step of the first top selection gate stepped block and / or the second top selection gate stepped block.

[0012] The stack structure further comprises a second connection region and a third connection region, the second connection region is located on a side of the first array region away from the first connection region in the first direction, and the third connection region is located on a side of the second array region away from the first connection region, the second connection region comprises a first bottom gate region, and the third connection region comprises a second bottom gate region; after the intermediate step block is formed and before the step block is formed, the preparation method further comprises: etching the stack structure on the first bottom gate region with a height of one stack pair as an etching unit to form a first initial bottom selection gate step block; and / or etching the stack structure on the second bottom gate region with a height of one stack pair as an etching unit to form a second initial bottom selection gate step block; wherein, two adjacent intermediate step blocks in the two rows form an intermediate step set, and a bottom end step of the intermediate step set is at least four stack pair heights higher than a tail end step of the first initial bottom selection gate step block and / or the second initial bottom selection gate step block.

[0013] After the intermediate step block, the first initial bottom selection gate step block and / or the second initial bottom selection gate step block are formed and before the step block is formed, the preparation method further comprises: performing etching process on a plurality of intermediate step blocks to form a plurality of sequentially arranged step blocks; and performing etching process on the first initial bottom selection gate step block to form a first bottom selection gate step block; and / or performing etching process on the second initial bottom selection gate step block to form a second bottom selection gate step block; wherein, a top end step of the first bottom selection gate step block and / or the second bottom selection gate step block is at least one stack pair height higher than a tail end step of the step set at the bottom.

[0014] After the step block is formed, the preparation method further comprises: forming a channel structure in the stack structure on the first array region and in the stack structure on the second array region, wherein the channel structure penetrates into the substrate through a plurality of stack pairs.

[0015] The stack structure further comprises a plurality of bridge regions, the bridge regions are located between the sub-connection regions in the second direction; before etching the stack structure on a plurality of the sub-connection regions, the preparation method further comprises: forming a mask layer on the stack structure, wherein the mask layer covers the stack structure on a plurality of the bridge regions.

[0016] The present application provides a semiconductor device, comprising: a substrate; a plurality of step blocks sequentially arranged in a first direction, the step blocks are arranged in two rows in a second direction, located on the substrate, and a step in the step blocks comprises at least four stack pairs.

[0017] In the first direction, the step block comprises a first step portion and a second step portion, the first step portion and the second step portion are oppositely arranged, and the steps in the first step portion and the steps in the second step portion are staggered.

[0018] In the second direction, two rows of step blocks are a rear row of step blocks and a front row of step blocks, respectively, and the steps of the adjacent rear row of step blocks are two stack pairs higher than the steps of the front row of step blocks.

[0019] In the first direction, two rows of step blocks form a step set, the step set comprises an adjacent first step set and a second step set, and the starting step of the second step set is at least one stack pair higher than the bottom step of the first step set.

[0020] The semiconductor device further comprises a first top selection gate step block and a second top selection gate step block, and a plurality of step blocks are located between the first top selection gate step block and the second top selection gate step block in the first direction; the starting step of the step set at the top is at least one stack pair higher than the tail end step of the first top selection gate step block and / or the second top selection gate step block.

[0021] The semiconductor device further comprises a first bottom selection gate step block and a second bottom selection gate step block, the first bottom selection gate step block is located on the side of the first top selection gate step block away from the step blocks, and the second bottom selection gate step block is located on the side of the second top selection gate step block away from the step blocks; the top end step of the first bottom selection gate step block and / or the second bottom selection gate step block is at least one stack pair higher than the tail end step of the step set at the bottom.

[0022] The semiconductor device further comprises a first storage array and a second storage array, the first storage array is located between the first bottom selection gate step block and the first top selection gate step block, and the second storage array is located between the second bottom selection gate step block and the second top selection gate step block; a channel structure is formed on the first storage array and the second storage array, and the channel structure penetrates through a plurality of stack pairs and extends into the substrate.

[0023] The semiconductor device further comprises a plurality of bridge structures, and in the second direction, a plurality of bridge structures are arranged at intervals, and a plurality of step blocks are located between the plurality of bridge structures.

[0024] In conclusion, the present application sets that each step of the step block includes four stack pairs, that is, in the process of etching the stack structure, etching is carried out every time with four stack pairs as the etching unit, four stack pairs form a step, and there is no residual in the corner of the adjacent step, and the subsequent operation space of the step block is larger. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0026] Figure 1 is a flowchart of the preparation method of the semiconductor device provided by the embodiments of the present application.

[0027] Figure 2 is a top view structural schematic diagram of the semiconductor device of the present application.

[0028] Figure 3 is Figure 2 a structural schematic diagram of the initial step block in

[0029] Figure 4 is Figure 2 a structural schematic diagram of the multiple step sets in

[0030] Figure 5 is Figure 2 a structural schematic diagram of one step set in

[0031] Figure 6 is a first kind of structural schematic diagram of the first top selection step block or the second top selection step block.

[0032] Figure 7 is a second kind of structural schematic diagram of the first top selection step block or the second top selection step block.

[0033] Figure 8 is a structural schematic diagram of the intermediate step set.

[0034] Figure 9 is a structural schematic diagram of 3 adjacent step sets and the first top selection gate step block.

[0035] Figure 10 is a layer structural schematic diagram of the bottom step set and the first bottom selection gate step block.

[0036] Figure 11 is a top view schematic diagram of the first kind of mask layer for forming the semiconductor device of the present application.

[0037] Figure 12 is a top view schematic diagram of forming a second mask layer of the semiconductor device of the present application.

[0038] Figure 13 is a top view schematic diagram of forming a third mask layer of the semiconductor device of the present application.

[0039] Figure 14 is a top view schematic diagram of forming a fourth mask layer of the semiconductor device of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0041] The present application provides a preparation method of a three-dimensional memory. Please refer to Figure 1 , Figure 1 The present application provides a flowchart of a preparation method of a three-dimensional memory. In the present application, each step of the step block includes four stacked pairs 120, that is, in the process of etching the stacked structure, etching is performed every time with four stacked pairs 120 as the etching unit, four stacked pairs 120 form a step, and there is no residual material remaining in the corner of the adjacent step. The subsequent operation space of the step block is larger. The present application improves the technical problem that the subsequent operation space of the step block is smaller when the residual material in the corner of the step formed by a single stacked pair 120 and multiple stacked pairs 120 (such as three stacked pairs and N stacked pairs 120) is removed, and the residual material in the corner of the step formed by a single stacked pair 120 still exists when the residual material in the corner of the step formed by multiple stacked pairs 120 (such as three stacked pairs and N stacked pairs 120) is completely removed.

[0042] The preparation method of the three-dimensional memory is shown in Figure 1 . As shown in Figure 1 , the method can be roughly summarized as follows: providing a substrate 110 (S1), forming a stacked structure on the substrate 110, the stacked structure including multiple stacked pairs 120 (S2), etching the stacked structure on multiple sub-connection regions 101 to form multiple initial step blocks 500 (S3), and etching the multiple initial step blocks 500 to form multiple step blocks arranged in sequence (S4). The following will be described respectively.

[0043] Please refer to Figure 1 , the method first performs the operations of S1-S4:

[0044] S1, a substrate 110 is provided. The substrate 110 is made of silicon, and can also be made of other silicon-containing substrates 110 such as Silicon On Insulator (SOI), SiGe, Si:C, etc. The substrate 110 can be formed with various deep or shallow potential wells of p-type / n-type required by devices by ion implantation or other processes.

[0045] S2, referring to Figure 2 , a stack structure is formed on the substrate 110, the stack structure includes a plurality of stack pairs 120, wherein the stack structure includes a first array region 50, a second array region 60, and a first connection region 10 disposed between the first array region 50 and the second array region 60, the first connection region 10 includes a plurality of functional areas disposed in sequence in the first direction X, each functional area includes two sub-connection areas 101 disposed in the second direction Y. It can be understood that the plurality of stack pairs 120 are stacked in the third direction Z. The stack pair 120 is a stack of an insulating layer and a gate sacrificial layer, i.e., each stack pair 120 includes an insulating layer and a gate sacrificial layer. Chemical vapor deposition (CV), atomic layer deposition (AL), or other suitable deposition methods can be used to deposit the insulating layer and the gate sacrificial layer alternately on the substrate 110. The insulating layer is made of silicon oxide, and the gate sacrificial layer is made of silicon nitride, which will be replaced by metal as a gate layer in subsequent processes. The insulating layer can also be silicon oxynitride, and the gate sacrificial layer can also be amorphous silicon, polysilicon, aluminum oxide, etc.

[0046] S3, referring to Figure 3 , the stack structure on the plurality of sub-connection areas 101 is etched to form a plurality of initial stepped blocks 500, the plurality of initial stepped blocks 500 are arranged in two rows, in the first direction X, each initial stepped block 500 includes a first initial portion 501 and a second initial portion 502, the first initial portion 501 and the second initial portion 502 have a height difference; in the second direction Y, there is a height difference between adjacent two initial stepped blocks 500;

[0047] S4, referring to Figure 4 , the plurality of initial stepped blocks 500 are etched to form a plurality of stepped blocks arranged in sequence, the stepped blocks are arranged in two rows in the second direction Y, and the steps in the stepped blocks include at least four stack pairs 120. Optionally, the steps of the stepped blocks include four stack pairs 120.

[0048] In the present application, each step of the step block includes four stack pairs 120, that is, during the etching of the stack structure, etching is performed four stack pairs 120 as an etching unit each time, four stack pairs 120 form a step, and there is no residue left in the corner of the adjacent step. The subsequent operation space of the step block is larger. The present application improves the technical problem that the subsequent operation space of the step block formed by a single stack pair 120 and multiple stack pairs 120 (such as three stacks and N stack pairs 120) is smaller when the residue in the corner of the step is removed. The residue in the corner of the step formed by a single stack pair 120 still exists when the residue in the corner of the step formed by multiple stack pairs 120 (such as three stacks and N stack pairs 120) is completely removed.

[0049] Please refer to Figure 5 In a specific embodiment, in the first direction X, the step block includes a first step portion 201 and a second step portion 202, the first step portion 201 and the second step portion 202 are oppositely arranged, and the steps in the first step portion 201 and the steps in the second step portion 202 are arranged in staggered manner.

[0050] Two rows of two adjacent step blocks form a step set 20, and in the second direction Y, each step set 20 includes a rear row step block 700 and a front row step block 600, the steps of the rear row step block 700 are two stack pairs 120 higher than the steps of the adjacent front row step block 600. For example, the steps of the first step portion 201 of the rear row step block 700 are 1, 5, 9, 13, and 17 in sequence, the steps of the second step portion 202 of the rear row step block 700 are 4, 8, 8, 12, and 16 in sequence, and the steps of the first step portion 201 and the second step portion 202 of the rear row step block 700 are arranged in staggered manner. The steps of the first step portion 201 of the front row step block 600 are 3, 7, 11, 15, and 19 in sequence, the steps of the second step portion 202 of the front row step block 600 are 6, 10, 14, 18, and 20 in sequence, and the steps of the first step portion 201 and the second step portion 202 of the front row step block 600 are arranged in staggered manner. The steps of the front row step block 600 and the steps of the rear row step block 700 can form continuous steps in the step set 20. It can be understood that the first initial portion 501 of the initial step block 500 forms the first step portion 201 after etching, and the second initial portion 502 of the initial step block 500 forms the second step portion 202 after etching. The first step portion 201 and the second step portion 202 of the two rows of step blocks can form continuous steps in the middle region.

[0051] In one embodiment, in the first direction X, the step set 20 comprises a first step set and a second step set adjacent to the first step set, and the starting step of the second step set is at least one height of a stack pair 120 higher than the bottom end step of the first step set. Alternatively, the starting step of the second step set is one height of a stack pair 120 higher than the bottom end step of the first step set. As in the first step set, the steps of the first step portion 201 of the back row step block 700 are 1, 5, 9, 13, 17 in sequence, the steps of the second step portion 202 are 4, 8, 12, 16, 20 in sequence, the steps of the first step portion 201 of the front row step block 600 are 3, 7, 11, 15, 19 in sequence, and the steps of the second step portion 202 are 6, 10, 14, 18, 22 in sequence; in the second step set, the steps of the first step portion 201 of the back row step block 700 are 19, 23, 27, 31, 35 in sequence, the steps of the second step portion 202 are 22, 26, 30, 34, 38 in sequence, the steps of the first step portion 201 of the front row step block 600 are 21, 25, 29, 33, 37 in sequence, and the steps of the second step portion 202 are 24, 28, 32, 36, 40 in sequence; the step 19 in the second step set can form a continuous step with the steps 18, 20 in the first step set. The starting step of the second step set being at least one height of a stack pair 120 higher than the bottom end step of the first step set can make the steps in the two adjacent step sets 20 form continuous steps, which facilitates the leading out of all the steps.

[0052] Please continue to refer to Figure 3 In one embodiment, in the first direction X, the first initial portion 501 of the initial step block 500 is three heights of a stack pair 120 higher than the second initial portion 502. It can be understood that the first initial portion 501 is a structure with edges flush, and no steps are formed on the first initial portion 501; the second initial portion 502 is a structure with edges flush, and no steps are formed on the second initial portion 502. It can be understood that before the initial step block 500 is formed, the blocking layer 801 is formed on the stack structure on the sub-connection region 101, and part of the stack structure is exposed by the blocking layer 801, such as Figure 13 In one embodiment, the blocking layer 801 on the sub-connection region 101 is in the shape of a spaced strip, so that part of the stack structure on the sub-connection region 101 is exposed. After etching the stack structure with the blocking layer 801 as a mask, the initial step block 500 can be formed.

[0053] In the present application, by setting the first initial part 501 of the initial stepped block 500 to be three heights of the stacked pairs 120 higher than the second initial part 502, the steps in the first stepped part 201 of the subsequently formed stepped block can be arranged staggered with the steps in the second stepped part 202. Moreover, by etching 4 stacked pairs 120 each time on the initial stepped block 500, the formation of steps of a single stacked pair 120 is avoided. There is no residue in the corner of the step, and the subsequent operation space of the stepped block is larger.

[0054] In a specific embodiment, in the second direction Y, the two rows of initial stepped blocks 500 are respectively the rear row of initial stepped blocks 500 and the front row of initial stepped blocks 500, and the steps of the rear row of initial stepped blocks 500 are two heights of the stacked pairs 120 higher than the steps of the adjacent front row of initial stepped blocks 500. In this way, on the basis that each step includes at least four stacked pairs 120, the steps of the subsequently formed stepped set 20 can be continuous steps.

[0055] Please refer to Figure 8 In a specific embodiment, the "etching the plurality of initial stepped blocks 500 to form a plurality of sequentially arranged stepped blocks" includes:

[0056] The plurality of initial stepped blocks 500 are etched in units of at least four heights of the stacked pairs 120 to form a plurality of intermediate stepped blocks, the plurality of intermediate stepped blocks are arranged in two rows, the first initial part 501 of the initial stepped block 500 is etched to form the first stepped part 201 of the intermediate stepped block, the second initial part 502 of the initial stepped block 500 is etched to form the second stepped part 202 of the intermediate stepped block, the first stepped part 201 and the second stepped part 202 of the intermediate stepped block are oppositely arranged, and the steps of the first stepped part 201 and the second stepped part 202 of the intermediate stepped block are arranged staggered, the first stepped part 201 is three heights of the stacked pairs 120 higher than the second stepped part 202. It can be understood that the first initial part 501 and the second initial part 502 of the initial stepped block 500 are etched in this step, the first stepped part 201 of the intermediate stepped block is formed after the first initial part 501 is etched to form steps, and the second stepped part 202 of the intermediate stepped block is formed after the second initial part 502 is etched to form steps.

[0057] In a specific embodiment, the first connection region 10 further includes a first top gate region 102 and a second top gate region 103, and the plurality of functional regions are connected between the first top gate region 102 and the second top gate region 103 in the first direction X; before etching the stacked structure on the plurality of sub-connection regions 101, the preparation method further includes:

[0058] Please refer to Figure 2 , Figure 4In one embodiment, the stack structure on the first top gate region 102 is etched by an etching unit with a height of one stack pair 120 to form the first top select gate step block 70. Please refer to Figure 12 It is understood that, before etching, a barrier layer 801 is formed on the stack structure on the first top gate region 102, the stack structure on the first top gate region 102 is etched by etching the barrier layer 801, and the stack structure on the first top gate region 102 is etched by taking the etched barrier layer 801 as a mask to form the first top select gate step block 70. The first top select gate step block 70 can be a symmetrical structure, and the first top select gate step block 70 can also be an asymmetrical structure with more steps on one side than on the other side. Figure 6 Figure 7

[0059] In one embodiment, the stack structure on the second top gate region 103 is etched by an etching unit with a height of one stack pair 120 to form the second top select gate step block. Please refer to Figure 12 It is understood that, before etching, a barrier layer is formed on the stack structure on the second top gate region 103, the stack structure on the second top gate region 103 is etched by etching the barrier layer, and the stack structure on the second top gate region 103 is etched by taking the etched barrier layer as a mask to form the second top select gate step block. The second top select gate step block can be a symmetrical structure, and the second top select gate step block can also be an asymmetrical structure with more steps on one side than on the other side.

[0060] In one embodiment, the starting step of the top step set 20 is at least one stack pair 120 higher than the tail end step of the first top select gate step block 70 and / or the second top select gate step block. Alternatively, the starting step of the top step set 20 is one stack pair 120 higher than the bottom end step of the first top select gate step block 70 and / or the second top select gate step block. It is understood that the steps of the first top select gate step block 70 and / or the second top select gate step block can be continuous steps, such as steps of 1, 2, 3, 4, 5, 6, and so on.

[0061] In one embodiment, the discontinuous steps of the top step set 20 can be supplemented by the steps in the first top select gate step block 70 and / or the second top select gate step block.

[0062] In one embodiment, the stack structure further includes a second connection region 30 and a third connection region 40, the second connection region 30 is located on the side of the first array region 50 away from the first connection region 10 in the first direction X, the third connection region 40 is located on the side of the second array region 60 away from the first connection region 10, the second connection region 30 includes a first bottom gate region 130, and the third connection region 40 includes a second bottom gate region 140; after forming the intermediate step block and before forming the step block, the preparation method further includes: ​​

[0063] with one height of the stack pair 120 as an etching unit, the stack structure on the first bottom gate region 130 is etched to form a first initial bottom select gate step block;

[0064] and / or, with one height of the stack pair 120 as an etching unit, the stack structure on the second bottom gate region 140 is etched to form a second initial bottom select gate step block;

[0065] wherein two adjacent middle step blocks in the two rows form a middle step set 520, and the bottom end step of the middle step set 520 is at least four heights of the stack pair 120 higher than the tail end step of the first initial bottom select gate step block and / or the second initial bottom select gate step block. It can be understood that the stack structure on the first bottom gate region 130 is etched by 7 stack pairs 120 to form the first initial bottom select gate step block, and / or the stack structure on the second bottom gate region 140 is etched by 7 stack pairs 120 to form the second initial bottom select gate step block.

[0066] In a specific embodiment, after forming the middle step block, the first initial bottom select gate step block and / or the second initial bottom select gate step block, and before forming the step block, the preparation method further comprises:

[0067] performing an etching process on the plurality of middle step blocks to form a plurality of sequentially arranged step blocks;

[0068] and performing an etching process on the first initial bottom select gate step block to form a first bottom select gate step block;

[0069] and / or, performing an etching process on the second initial bottom select gate step block to form a second bottom select gate step block;

[0070] wherein the top end step of the first bottom select gate step block and / or the second bottom select gate step block is at least one height of the stack pair 120 higher than the tail end step of the bottom located step set 20.

[0071] It can be understood that after the first initial bottom selection step block, the second initial bottom selection step block and the intermediate step block are formed, the first initial bottom selection step block, the second initial bottom selection step block and the intermediate step block are etched synchronously. Since the tail end step of the intermediate step block is at least four stack pairs 120 higher than the tail end step of the first initial bottom selection gate step block and / or the second initial bottom selection gate step block, the first initial bottom selection gate step block and / or the second initial bottom selection gate step block is etched to the bottom first, that is, the first initial bottom selection gate step block and / or the second initial bottom selection gate step block is etched to the preset position first, such as etching to the substrate 110. At this time, the bottom end step of the bottommost step set 20 is four stack pairs 120 higher than the substrate 110. Since the step of the step block includes four stack pairs 120, the first step part 201 of the rear step block 700 of the bottommost step set 20 can be 7, 11, 15, 19, 23, and the second step part 202 can be 4, 8, 12, 16, 20. The first step part 201 of the front step block 600 can be 9, 13, 17, 21, 25, and the second step part 202 can be 6, 10, 14, 18, 22. The step of the first bottom selection gate step block and / or the second bottom selection gate step block can be 1, 2, 3, 4, 5, 6, 7. The step 5 of the first bottom selection gate step block and / or the second bottom selection gate step block can supplement the missing step 5 between the steps 4 and 6 of the intermediate step set 520.

[0072] In this application, the discontinuous steps of the step set 20 at the bottom can be supplemented by the steps in the first bottom selection gate step block and / or the second bottom selection gate step block.

[0073] That is, the missing steps in the topmost step set 20 in the plurality of step sets 20 of the application can be supplemented by the steps of the first top selection gate step block 70 and / or the second top selection gate step block, the missing steps in the bottommost step set 20 can be supplemented by the steps of the first bottom selection gate step block and / or the second bottom selection gate step block, and the steps of the step set 20 between the topmost and the bottommost are mutually supplemented to form continuous steps.

[0074] As Figure 4 In, Figure 4The first connection region 10 in the first connection region 10 has six step sets 20, each step set 20 includes a front row of step blocks 600 and a rear row of step blocks 700, each step block has 13 steps in the first direction X, the first step part 201 is 3 stack pairs 120 higher than the second step part 202 in the first direction X; in the second direction Y, the steps of the rear row of step blocks 700 are 2 stack pairs 120 higher than the steps of the adjacent front row of step blocks 600. As shown in Figure 9 The first step part 201 of the rear row of step blocks 700 of the step set B has steps from top to bottom in the order of 249, 245, 241, 237, 233, 229, 225, 221, 217, 213, 209, 205, 201, 197; the first step part 201 of the front row of step blocks 600 of the step set B has steps from top to bottom in the order of 247, 243, 239, 235, 231, 227, 223, 219, 215, 211, 207, 203, 199, 195; the second step part 202 of the rear row of step blocks 700 of the step set B has steps from bottom to top in the order of 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252; the second step part 202 of the front row of step blocks 600 of the step set B has steps from bottom to top in the order of 198, 202, 206, 210, 214, 218, 222, 226, 230, 234, 238, 242, 246, 250. According to the step set B, it can be known that the step set B lacks the step 251 and the step 196, and the step 252 exists.

[0075] The step set 2020 adjacent to the step set B is the step set A and the step set C.

[0076] The first step part 201 of the rear row step block 700 of the step set A has steps from top to bottom in turn 308, 304, 300, 296, 292, 288, 284, 280, 276, 272, 268, 264, 260, 256; the first step part 201 of the front row step block 600 of the step set A has steps from top to bottom in turn 306, 302, 298, 294, 290, 286, 282, 278, 274, 270, 266, 262, 258, 254; the second step part 202 of the rear row step block 700 of the step set A has steps from bottom to top in turn 253, 257, 261, 265, 269, 273, 277, 281, 285, 289, 293, 297, 301, 305; the second step part 202 of the front row step block 600 of the step set A has steps from bottom to top in turn 251, 255, 259, 263, 267, 271, 275, 279, 283, 287, 291, 295, 299, 303. According to the step set A, it is known that the step set A lacks the step 307 and the step 252, and the step 251 exists.

[0077] The first step part 201 of the rear row step block 700 of the step set C has steps from top to bottom in turn 193, 189, 185, 181, 177, 173, 169, 165, 161, 157, 153, 149, 145, 141; the first step part 201 of the front row step block 600 of the step set C has steps from top to bottom in turn 191, 187, 183, 179, 175, 171, 167, 163, 159, 155, 151, 147, 143, 139; the second step part 202 of the rear row step block 700 of the step set C has steps from bottom to top in turn 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, 192, 196; the second step part 202 of the front row step block 600 of the step set C has steps from bottom to top in turn 142, 146, 150, 154, 158, 162, 166, 170, 174, 178, 182, 186, 190, 194. According to the step set C, it is known that the step set C lacks the step 195 and the step 140, and the step 196 exists.

[0078] That is, the step 251 missing in the step set B can be supplemented by the step 251 of the step set A, and the step 196 missing in the step set B can be supplemented by the step 196 of the step set C.

[0079] The present application not only improves the step formed by a single stack pair 120 and a plurality of stack pairs 120 (such as three stacks and N stack pairs 120), but also solves the technical problem of less space for subsequent operation of the step block when the residues in the corner of the step formed by a plurality of stack pairs 120 (such as three stacks and N stack pairs 120) are cleaned up, while the residues in the corner of the step formed by a single stack pair 120 still exist. Moreover, the plurality of step sets 20 of the present application can compensate for each other, and the step structure of the three-dimensional memory is complete.

[0080] As Figure 9 In the embodiment, the top step set 20 is step set A, the steps of the first step portion 201 of the first top select gate (TSG) step block 70 from top to bottom are 309, 308, 307, and 306 in turn, and the steps of the second step portion 202 of the first top select gate (TSG) step block 70 from bottom to top are 306, 307, 308, and 309 in turn. That is, the step 307 of the first top select gate (TSG) step block 70 can supplement the missing step 307 of the step set A. Of course, the steps of the second top select gate (TSG) step block 20 can also supplement the steps of the step set A.

[0081] Therefore, even if the missing step of the topmost step set 20 is supplemented by any one of the first top select gate (TSG) step block 70 and the second top select gate (TSG) step block, the step structure of the semiconductor device is complete.

[0082] As Figure 10In the specific embodiment, the first step portion 201 of the back row step block 700 of the bottom step set E has the steps from top to bottom in order of 58, 54, 50, 46, 42, 38, 34, 30, 26, 22, 18, 14, 10, 6, the first step portion 201 of the front row step block 600 of the bottom step set E has the steps from top to bottom in order of 56, 52, 48, 44, 40, 36, 32, 28, 24, 20, 16, 12, 8, 4, the second step portion 202 of the back row step block 700 of the bottom step set E has the steps from bottom to top in order of 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, and the second step portion 202 of the front row step block 600 of the bottom step set E has the steps from bottom to top in order of 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59. The two missing steps of the bottom step set E are step 5 and step 60, and the steps of the first bottom select gate (BSG) step block 90 and the second bottom select gate (BSG) step block can be 0, 1, 2, 3, 4, 5, 6, 7. The step 5 of the first bottom select gate (BSG) step block 90 and the second bottom select gate (BSG) step block can supplement the step 5 of the bottom step set E. The missing step 60 of the bottom step set E can be supplemented by the step set 20 adjacent to the bottom set E.

[0083] Therefore, even if the bottom step set E is missing steps, the missing steps can be supplemented by any one of the first bottom select gate (BSG) step block 90 and the second bottom select gate (BSG) step block, and the integrity of the step structure of the three-dimensional memory is achieved.

[0084] In a specific embodiment, after the step block 20 is formed, the preparation method further comprises:

[0085] forming a channel structure in the stack structure on the first array area 50 and the stack structure on the second array area 60, wherein the channel structure penetrates into the substrate 110 through the plurality of stack pairs 120. It can be understood that the first array area 50 and the second array area 60 are mainly used for storage.

[0086] Please refer to Figure 11 In a specific embodiment, the stack structure further comprises a plurality of bridge regions 802 located between the sub-connection regions 101 in the second direction Y; before etching the stack structure on the plurality of sub-connection regions 101, the preparation method further comprises:

[0087] A mask layer 320 is formed on the stack structure, wherein the mask layer 320 covers the stack structure on the plurality of bridge regions 802. It can be understood that the second direction Y is perpendicular to the first direction X. The plurality of step sets 20 are located in the space between the bridge structures, the first array region 50 is connected to the step set 20 through the bridge structure, and the second array region 60 is connected to the step set 20 through the bridge structure. The word lines in the bridge structure bridge the step set 20 and the word line contacts on the array region (the first array region 50 and the second array region 60) so as to realize a bidirectional word line driving scheme. As shown in FIG. 1, the bridge structure is a first bridge structure 170 and a second bridge structure 180. Figure 14 In the embodiment, the first array region 50 and the second array region 60 can be formed by the mask layer 320, and the bridge structure can be formed by the mask layer 320. Figure 2 In the embodiment, the bridge structure is the first bridge structure 170 and the second bridge structure 180. The first top select gate (TSG) step block 70 and the second top select gate (TSG) step block can be formed in the gap 330 between the mask layer 320. The step block can be formed in the gap 340 between the mask layer 320.

[0088] In one specific embodiment, the preparation method further comprises:

[0089] A separation structure is formed in the first direction X through the second connection region 30, the first array region 50, the first connection region 10, the second array region 60, and the third connection region 40, wherein the separation structure extends into the substrate 110. It can be understood that the separation structure is used to separate the stack structure into at least two memory blocks. Figure 2 In the embodiment, the separation structure is the first separation structure 210, the second separation structure 220, and the third separation structure 230. The structure between the first separation structure 210 and the second separation structure 220 is a first memory block, and the structure between the second separation structure 220 and the third separation structure 230 is a second memory block. The plurality of step blocks can be separated into a first connection step block 240 and a second connection step block 250 by the second separation structure 220. The first connection step block 240 is connected to the first array region 50 through the first bridge structure 170, and the second connection step block 250 is connected to the second array region 60 through the second bridge structure 180. The separation structure (for example, the first separation structure 210) can be formed in the dashed line 350 in Figure 14 Therefore, the plurality of memory blocks can be defined by the separation structure.

[0090] Please refer to Figure 3In addition to the method for manufacturing the semiconductor device, the embodiment of the present application also provides a semiconductor device. The semiconductor device and the method for manufacturing the semiconductor device can realize the advantages of the present application, and can be used together, or can be used separately, and the present application does not have special limitations. In a specific embodiment, the semiconductor device is manufactured by the method for manufacturing the semiconductor device. Optionally, the semiconductor device is a three-dimensional memory.

[0091] The semiconductor device comprises: a substrate 110; a plurality of step blocks arranged in sequence in a first direction X, the step blocks are arranged in two rows in a second direction Y, and are located on the substrate 110, and steps in the step blocks comprise at least four stack pairs 120.

[0092] In the present application, each step of the step block comprises four stack pairs 120, that is, during etching of the stack structure, etching is performed four stack pairs 120 as an etching unit each time, four stack pairs 120 form a step, and there is no residue in the corner of the adjacent step. The subsequent operation space of the step block is larger. The present application improves the technical problem that the subsequent operation space of the step block is smaller when the residue in the corner of the step formed by a single stack pair 120 and a plurality of stack pairs 120 (such as three stack pairs and N stack pairs 120) is removed, and the residue in the corner of the step formed by a single stack pair 120 still exists when the residue in the corner of the step formed by a plurality of stack pairs 120 (such as three stack pairs and N stack pairs 120) is removed.

[0093] In a specific embodiment, in the first direction X, the step block comprises a first step part 201 and a second step part 202, the first step part 201 and the second step part 202 are arranged opposite to each other, and the steps in the first step part 201 and the steps in the second step part 202 are arranged in a staggered manner. The steps in the first step part 201 and the steps in the second step part 202 are arranged in a staggered manner, so that the steps in the step block form continuous steps.

[0094] In a specific embodiment, in the second direction Y, two adjacent step blocks form a step set 20, and in the second direction Y, each step set 20 comprises a rear step block 700 and a front step block 600, and the steps of the rear step block 700 are higher than the steps of the adjacent front step block 600 by two heights of the stack pairs 120. In this way, the steps of the step set 20 form continuous steps.

[0095] In one embodiment, in the first direction X, the set of steps 20 includes a first set of steps 20 and a second set of steps 20 adjacent to the first set of steps 20, the starting step of the second set of steps 20 is at least one height of a stack pair 120 higher than the ending step of the first set of steps 20. The starting step of the second set of steps 20 being at least one height of a stack pair 120 higher than the ending step of the first set of steps 20 can allow the steps in the two adjacent sets of steps 20 to form a continuous set of steps, facilitating the routing of all the steps.

[0096] In one embodiment, the semiconductor device further includes a first top select gate step block 70 and a second top select gate step block, the plurality of step blocks are located between the first top select gate step block and the second top select gate step block in the first direction X, and the starting step of the top set of steps 20 is at least one height of a stack pair 120 higher than the ending step of the first top select gate step block 70 and / or the second top select gate step block. In this application, the discontinuous steps of the top set of steps 20 can be supplemented by the steps in the first top select gate step block 70 and / or the second top select gate step block. It is understood that the first top select gate (TSG) step block 70, the plurality of step blocks, and the second top select gate (TSG) step block are arranged in sequence along the first direction X. The first top select gate (TSG) step block 70, the plurality of step blocks, and the second top select gate (TSG) step block are also arranged between the first bridge structure 170 and the second bridge structure 180 along the second direction Y of the substrate 110. The first top select gate (TSG) step block 70 and the second top select gate (TSG) step block can be formed in the second group of stack pairs 120, for example, in one or more top word line layers and top insulating layers. In addition, each of the plurality of step blocks can be formed in a corresponding word line layer and insulating layer of the plurality of stack pairs 120.

[0097] In one embodiment, the semiconductor device further includes a first bottom select gate step block and a second bottom select gate step block, the first bottom select gate step block is located on a side of the first top select gate step block 70 away from the step block, and the second bottom select gate step block is located on a side of the second top select gate step block away from the step block; a top step of the first bottom select gate step block and / or the second bottom select gate step block is at least one height of a stack pair 120 higher than a tail step of the bottom set of steps 20. In this application, the discontinuous steps of the bottom set of steps 20 can be supplemented by steps in the first bottom select gate step block and / or the second bottom select gate step block. It can be understood that the first bottom select gate (BSG) step block 90 is formed in the stack pair 120 adjacent to the substrate 110, for example, in one or more bottommost word line layers and bottommost insulating layers adjacent to the substrate 110. Similarly, the second bottom select gate (BSG) step block can also be formed in the first group of stack pairs 120 adjacent to the substrate 110.

[0098] In one embodiment, the semiconductor device further includes a first memory array and a second memory array, the first memory array is located between the first bottom select gate step block and the first top select gate step block 70, and the second memory array is located between the second bottom select gate step block and the second top select gate step block, each of the first memory array and the second memory array is formed with a channel structure, and the channel structure extends into the substrate 110 through the plurality of stack pairs 120. The first memory array and the second memory array are used for storage. Each of the channel structures 150 can further include a channel layer, a tunnel layer surrounding the channel layer, a charge trapping layer surrounding the tunnel layer, and a blocking layer surrounding the charge trapping layer. In addition, the channel structure 150 can be in direct contact with the word line layer.

[0099] In one embodiment, the semiconductor device further includes a plurality of bridge structures, the plurality of bridge structures are spaced apart in the second direction Y, and the plurality of step blocks are located between the plurality of bridge structures. The word lines in the bridge structures are bridged to the word line contacts on the step blocks and the array regions (the first array region 50 and the second array region 60) in order to implement a bidirectional word line driving scheme.

[0100] The semiconductor device can include a first separation structure 210. The first separation structure 210 can extend into the substrate 110 through the plurality of stack pairs 120 and extend along the first direction X.

[0101] The semiconductor device can also have a second separation structure 220. The second separation structure 220 can be formed along the first direction X and extend through the plurality of stack pairs 120 into the substrate 110. In some embodiments, the plurality of stepped blocks can be separated into a first connection stepped block 240 and a second connection stepped block 250 by the second separation structure 220. The second separation structure 220 can further divide the first bottom select gate (BSG) stepped block 90 into a first sub-BSG stepped block 901 and a second sub-BSG stepped block 902. The second separation structure 220 can further divide the first top select gate (BSG) stepped block 70 into a first sub-TSG stepped block 701 and a second sub-TSG stepped block 702.

[0102] The semiconductor device can include a third separation structure 230. The third separation structure 230 can further extend through the plurality of stack pairs 120 into the substrate 110 110 and along the first direction X.

[0103] In some embodiments, the first separation structure 210, the second separation structure 220, and the third separation structure 230 can be gate-last-silicon (GLS) structures. In some embodiments, the GLS structures can be made of a conductive material and positioned on an array common source (ACS) region formed in the substrate 110 to function as a contact, where the ACS region is formed in the substrate 110 to function as a common source. In some embodiments, the GLS structures can be made of a dielectric material to function as a separation structure. In some embodiments, the semiconductor device is formed using a gate-last manufacturing technique. Thus, the GLS structures are formed to help remove sacrificial word line layers (also referred to as sacrificial layers) as well as form true gate electrodes.

[0104] In some embodiments, the first separation structure 210, the second separation structure 220, and the third separation structure 230 can be formed in a gate-last-silicon (GLS) process. Figure 2 In some embodiments, two memory blocks can be formed in the semiconductor device, where a first memory block can be defined between the first separation structure 210 and the second separation structure 220, and a second memory block can be defined between the second separation structure 220 and the third separation structure 230. For example, as shown in FIG. 1, the first bridge structure 170, the first connection stepped block 240, and the first sub-BSG stepped block 901 are included in the first memory block. The second bridge structure 180, the second connection stepped block 250, and the second sub-BSG stepped block 902 are included in the second memory block. Figure 2

[0105] The above disclosure is merely preferred embodiments of the application and thus is not to be taken in a limiting sense. Those skilled in the art can understand that all or part of the above-mentioned processes can be implemented, and equivalent variations of the present application made in accordance with the claims of the application, still fall within the scope of the application.​

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of stack pairs, wherein the stack structure comprises a first array region, a second array region, and a first connection region disposed between the first array region and the second array region, the first connection region comprising a plurality of functional regions disposed in sequence in a first direction, each of the functional regions comprising two sub-connection regions disposed in a second direction; etching the stack structure on the plurality of sub-connection regions to form a plurality of initial step blocks, the plurality of initial step blocks being arranged in two rows, in the first direction, each of the initial step blocks comprising a first initial part and a second initial part, the first initial part and the second initial part having a height difference; in the second direction, there is a height difference between two adjacent initial step blocks; etching the plurality of initial step blocks by taking the height of at least four stack pairs as an etching unit to form a plurality of intermediate step blocks, and then forming a plurality of step blocks arranged in sequence, the plurality of intermediate step blocks being arranged in two rows, the first initial part of the initial step block being etched to form a first step part of the intermediate step block, the second initial part of the initial step block being etched to form a second step part of the intermediate step block, the first step part and the second step part of the intermediate step block being oppositely arranged, and the steps of the first step part and the second step part of the intermediate step block being arranged in a staggered manner, the first step part being higher than the second step part by three heights of stack pairs; in the second direction, the step blocks are arranged in two rows, and the steps in the step blocks comprise at least four stack pairs.

2. The production method according to claim 1, characterized by, In the first direction, the step blocks comprise a first step part and a second step part, the first step part and the second step part are oppositely arranged, and the steps in the first step part and the second step part are arranged in a staggered manner.

3. The preparation method according to claim 1, characterized in that, Two adjacent step blocks in the two rows form a step set, in the second direction, each of the step sets comprises a rear row step block and a front row step block, the steps of the rear row step block being higher than the steps of the adjacent front row step block by two heights of stack pairs.

4. The production method according to claim 3, characterized by, In the first direction, the step sets comprise adjacent first step sets and second step sets, the starting step of the second step set being higher than the bottom end step of the first step set by at least one height of stack pairs.

5. The preparation method according to claim 1, characterized in that, In the first direction, the first initial part of the initial step block is higher than the second initial part by three heights of the stack pairs.

6. The method of claim 1, wherein, In the second direction, the two rows of initial step blocks are respectively rear row initial step blocks and front row initial step blocks, the steps of the rear row initial step blocks being higher than the steps of the adjacent front row initial step blocks by two heights of stack pairs.

7. The production method according to claim 3, characterized by, The first connection region further comprises a first top gate region and a second top gate region, and the plurality of functional regions are connected between the first top gate region and the second top gate region in the first direction; Before etching the stack structure on the plurality of sub-connection regions, the preparation method further comprises: The stack structure is etched on the first top gate region by an etching unit with a height of one stack pair to form a first top select gate step block, and / or, the stack structure is etched on the second top gate region by an etching unit with a height of one stack pair to form a second top select gate step block, wherein a starting step of the step set at the top is at least one stack pair higher than a tail step of the first top select gate step block and / or the second top select gate step block.

8. The preparation method according to claim 7, characterized in that, The stack structure further comprises a second connection region and a third connection region, the second connection region is located on a side of the first array region away from the first connection region in the first direction, and the third connection region is located on a side of the second array region away from the first connection region, the second connection region comprises a first bottom gate region, and the third connection region comprises a second bottom gate region; after forming the intermediate step block and before forming the step block, the preparation method further comprises: The stack structure is etched on the first bottom gate region by an etching unit with a height of one stack pair to form a first initial bottom select gate step block; and / or, the stack structure is etched on the second bottom gate region by an etching unit with a height of one stack pair to form a second initial bottom select gate step block; wherein two adjacent intermediate step blocks in the two rows form an intermediate step set, and a bottom end step of the intermediate step set is at least four stack pairs higher than a tail step of the first initial bottom select gate step block and / or the second initial bottom select gate step block.

9. The preparation method according to claim 8, characterized in that, After forming the intermediate step block, the first initial bottom select gate step block and / or the second initial bottom select gate step block, and before forming the step block, the preparation method further comprises: performing etching process on a plurality of the intermediate step blocks to form a plurality of the step blocks arranged in sequence; and performing etching process on the first initial bottom select gate step block to form a first bottom select gate step block; and / or, performing etching process on the second initial bottom select gate step block to form a second bottom select gate step block; wherein a top end step of the first bottom select gate step block and / or the second bottom select gate step block is at least one stack pair higher than a tail step of the step set at the bottom.

10. The method of claim 1, wherein, After forming the step block, the preparation method further comprises: forming a channel structure in the stack structure on the first array region and in the stack structure on the second array region, wherein the channel structure penetrates into the substrate through a plurality of the stack pairs.

11. The method of claim 1, wherein, The stack structure further comprises a plurality of bridge regions between the sub-connection regions in the second direction; Before etching the stack structure on a plurality of the sub-connection regions, the preparation method further comprises: forming a mask layer on the stack structure, wherein the mask layer covers the stack structure on a plurality of the bridge regions.

12. A semiconductor device, characterized by comprising: comprises: a substrate; A plurality of step blocks arranged in sequence in a first direction, the step blocks arranged in two rows in a second direction on a substrate, steps in the step blocks comprising at least four stacked pairs; Two rows of two adjacent step blocks form a step set, each step set comprising a back row of step blocks and a front row of step blocks in the second direction, steps of the back row of step blocks being two stacked pair heights higher than steps of the adjacent front row of step blocks; The semiconductor device further comprises a first top select gate step block and a second top select gate step block, a plurality of the step blocks being located between the first top select gate step block and the second top select gate step block in the first direction; a starting step of the step set located at the top is at least one stacked pair height higher than a tail step of the first top select gate step block and / or the second top select gate step block; The semiconductor device further comprises a first bottom select gate step block and a second bottom select gate step block, the first bottom select gate step block being located on a side of the first top select gate step block away from the step blocks, and the second bottom select gate step block being located on a side of the second top select gate step block away from the step blocks; a top step of the first bottom select gate step block and / or the second bottom select gate step block is at least one stacked pair height higher than a tail step of the step set located at the bottom.

13. The semiconductor device of claim 12, wherein, In the first direction, the step blocks comprise a first step portion and a second step portion, the first step portion and the second step portion being oppositely arranged, and steps in the first step portion and steps in the second step portion being staggered.

14. The semiconductor device of claim 12, wherein, In the first direction, the step set comprises a first step set and a second step set adjacent to each other, a starting step of the second step set being at least one stacked pair height higher than a tail step of the first step set.

15. The semiconductor device of claim 12, wherein, The semiconductor device further comprises a first memory array and a second memory array, the first memory array being located between the first bottom select gate step block and the first top select gate step block, and the second memory array being located between the second bottom select gate step block and the second top select gate step block, a channel structure being formed on the first memory array and the second memory array, the channel structure penetrating into the substrate through a plurality of the stacked pairs.

16. The semiconductor device of claim 12, wherein, The semiconductor device further comprises a plurality of bridge structures, the plurality of bridge structures being spaced apart in the second direction, and the plurality of step blocks being located between the plurality of bridge structures.

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