A silicon back-etched FBAR resonator and its preparation method

Abstract

The present invention provides a silicon back-etched FBAR resonator and a preparation method thereof, the resonator comprises a silicon substrate, a support layer and a piezoelectric layer in order from bottom to top; a cavity is formed below the support layer, and the support layer is partially exposed in the cavity, and the sidewall of the cavity is formed by the silicon substrate; a lower electrode layer is provided between the support layer and the piezoelectric layer, and an upper electrode layer is provided above the piezoelectric layer; the resonator further comprises an upper load layer and a lower load layer; the upper load layer and the lower load layer are respectively arranged along the edges of the upper electrode layer and the lower electrode layer, and the lower load layer penetrates the support layer and extends into the cavity; the upper load layer and the lower load layer are symmetrically distributed up and down. The present invention can reduce the acoustic wave energy consumption of the transverse mode in the piezoelectric layer by adopting a symmetrical load layer design, effectively reduce the parasitic waveform of the FBAR resonator at the resonance peak position, and is conducive to the construction of a high-quality bulk acoustic wave filter with low insertion loss.

Description

Technical Field

[0001] The invention relates to the technical field of bulk acoustic wave resonators, and in particular to a silicon back-etched FBAR resonator and a preparation method thereof. Background Art

[0002] Filters are mainly used to selectively filter the receiving and transmitting signals of specific frequency bands to reduce the impact of interference signals. Low-frequency surface acoustic wave (SAW) filters and large-volume dielectric filters cannot meet the high-frequency and miniature requirements of mobile terminals, micro base stations, etc. The film bulk acoustic wave resonator (FBAR) filter has the advantages of small size, low loss, integration, high quality factor, high out-of-band suppression, high operating frequency and high power handling capacity. It is currently the only 5G RF filter that can meet the high-frequency requirements of 5G and meet the modular integration of RF front-ends. The FBAR bulk acoustic wave filter is an irreplaceable core component of the RF communication front end. It undertakes the main filtering and frequency selection functions. It is one of the key devices in the field of mobile communications and is also one of the most promising third-generation semiconductor devices generally recognized by the industry.

[0003] The current mainstream cavity FBAR resonators have the following defects: (1) The parasitic coupling phenomenon is relatively serious, interfering with the normal main resonance peak curve. (2) The filter composed of ordinary cavity FBAR resonators has serious insertion loss in the band, and the process device results are inconsistent with the simulation. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a silicon back-etched FBAR resonator and a preparation method thereof, which solves the problems of parasitic resonance, low quality factor and large insertion loss existing in the existing single crystal thin film bulk acoustic wave resonator. The technical solution of the present invention is:

[0005] In a first aspect, the present invention provides a silicon back-etched FBAR resonator, which comprises a silicon substrate, a support layer and a piezoelectric layer in order from bottom to top; a cavity is formed below the support layer, and a portion of the support layer is exposed in the cavity, and a sidewall of the cavity is formed by the silicon substrate; a lower electrode layer is provided between the support layer and the piezoelectric layer, and an upper electrode layer is provided above the piezoelectric layer;

[0006] The resonator further includes an upper load layer and a lower load layer; the upper load layer and the lower load layer are respectively arranged along the edges of the upper electrode layer and the lower electrode layer, and the lower load layer penetrates the support layer and extends into the cavity; the upper load layer and the lower load layer are symmetrically distributed up and down.

[0007] Furthermore, the silicon substrate has a thickness of 575 μm and a cross section of an inverted right-angled trapezoidal structure.

[0008] Furthermore, the support layer is made of silicon dioxide and has a thickness of 2 to 3.5 μm.

[0009] Furthermore, the piezoelectric layer is made of AlN material and has a thickness of 500nm to 4μm.

[0010] Furthermore, the upper electrode layer and the lower electrode layer are made of any one of Mo, Pt, Ti and Au, and have a thickness of 50 nm to 1 μm.

[0011] Furthermore, the upper load layer and the lower load layer are made of any one of Mo, Pt, Ti and Au, with a thickness of 50 nm to 2 μm and a width of 50 nm to 10 μm.

[0012] Furthermore, the number of the upper load-bearing layer and the number of the lower load-bearing layer are both one or more, presenting a polyhedral frame structure.

[0013] Furthermore, when there are multiple upper load layers and multiple lower load layers, the multiple polyhedral framework structures are arranged in a nested manner, one surrounding another, and adjacent polyhedral framework structures are spaced a certain distance apart. The outermost polyhedral framework structure is respectively arranged along the edges of the upper electrode layer and the lower electrode layer, and the other layers of polyhedral framework structures are respectively arranged on the upper electrode layer and the lower electrode layer.

[0014] Furthermore, the polyhedral framework structure is a regular pentahedral framework structure.

[0015] In a second aspect, the present invention provides a method for preparing a silicon back-etched FBAR resonator, comprising the following steps:

[0016] Step S1, depositing a support layer on a silicon substrate;

[0017] Step S2, based on step S1, a lower electrode metal film is grown on the support layer and patterned to obtain a lower electrode layer;

[0018] Step S3, based on step S2, epitaxially growing a piezoelectric film on the lower electrode layer and performing photolithography patterning to obtain a piezoelectric layer;

[0019] Step S4, based on step S3, continuing to grow an upper electrode metal film on the piezoelectric layer and performing a patterning process to obtain an upper electrode layer;

[0020] Step S5, preparing an upper load layer on the piezoelectric layer based on step S4, so that the upper load layer is arranged along the edge of the upper electrode layer;

[0021] Step S6, growing a silicon dioxide protective layer on the upper electrode layer and the upper support layer based on step S5;

[0022] Step S7, using a back etching process to remove silicon in the working area of ​​the silicon substrate resonator to form a cavity, while partially exposing the support layer;

[0023] Step S8, preparing a lower load layer on the support layer based on step S7, so that one end of the lower load layer is arranged along the edge of the lower electrode layer and the other end extends into the cavity;

[0024] Step S9, removing the top silicon dioxide protective layer to obtain a FBAR bulk acoustic wave resonator.

[0025] Furthermore, the method for depositing the support layer in step S1 is plasma enhanced chemical vapor deposition (PECVD).

[0026] Furthermore, the method for growing the lower electrode metal film in step S2 is deposition or sputtering, preferably magnetron sputtering.

[0027] Optionally, the method for growing the piezoelectric film in step S3 includes one or more combinations of PVD, MOCVD, PLD, and ALD.

[0028] Furthermore, the method for growing the upper electrode metal film in step S4 is deposition or sputtering, preferably magnetron sputtering.

[0029] The resonator of the present invention forms a piezoelectric oscillation sandwich structure through the upper electrode, the piezoelectric layer and the lower electrode, which can reduce the performance loss introduced by the external circuit. And by adopting a symmetrical load layer design, the acoustic wave energy consumption of the transverse mode in the piezoelectric layer can be reduced, and the acoustic wave of the transverse mode in the piezoelectric layer is reflected from the edge of the device back to the inside of the piezoelectric oscillation stack, so the parasitic waveform of the FBAR resonator at the resonance peak position is effectively reduced, which is conducive to the construction of a high-quality bulk acoustic wave filter with low insertion loss. The load layer can also be set to a first-order or multi-order complex layer array to further balance the stray factors introduced by the load layer. The setting of the cavity is conducive to utilizing the different acoustic impedances of air and piezoelectric materials to effectively form total reflection of bulk acoustic waves. In addition, the present invention only needs to prepare a load layer of the same material on the upper electrode and the lower electrode, and does not need to prepare an additional functional film layer or external capacitors and resistors, which reduces the difficulty of preparation and thus reduces the preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic structural diagram of depositing a support layer on a silicon substrate in step S1 in the process of preparing an FBAR resonator in a specific embodiment of the present invention.

[0031] Figure 2 It is a schematic structural diagram of growing a lower electrode on a supporting layer in step S2 in the process of preparing an FBAR resonator according to a specific embodiment of the present invention.

[0032] Figure 3This is a schematic diagram of the structure of the silicon substrate, the support layer, the piezoelectric layer, and the lower electrode in step S3 of the FBAR resonator preparation process in a specific embodiment of the present invention.

[0033] Figure 4 This is a schematic diagram of the structure of the silicon substrate, support layer, piezoelectric layer, lower electrode and upper electrode in step S4 of the FBAR resonator preparation process in a specific embodiment of the present invention.

[0034] Figure 5 It is a schematic structural diagram of preparing an upper load layer in step S5 during the preparation process of an FBAR resonator according to a specific embodiment of the present invention.

[0035] Figure 6 It is a structural schematic diagram of growing a silicon dioxide protective layer on the upper electrode layer and the upper load layer in step S6 in the process of preparing the FBAR resonator in a specific embodiment of the present invention.

[0036] Figure 7 It is a schematic structural diagram of forming a cavity in step S7 during the preparation process of an FBAR resonator according to a specific embodiment of the present invention.

[0037] Figure 8 It is a structural schematic diagram of forming a lower electrode load layer in step S8 during the preparation process of an FBAR resonator according to a specific embodiment of the present invention.

[0038] Fig. 9 It is a schematic structural diagram of the silicon back-etched FBAR resonator of the present invention.

[0039] Fig.10 This is a schematic diagram of the top view of the structure of the support layer of the present invention, and the electrode layer is surrounded in the middle and is shown here with a white background to avoid confusion.

[0040] Fig.11 This is a schematic diagram of the structure of the FBAR resonator using two sets of upper and lower load layers in the present invention.

[0041] Fig.12 This is a schematic diagram of a top view of the structure of the present invention using multiple groups of upper and lower load layers.

[0042] Fig.13 This is the admittance curve of the resonator obtained in Example 1 of the present invention.

[0043] Fig.14 This is the admittance curve of the resonator obtained in Example 2 of the present invention.

[0044] Fig.15 This is the admittance curve of the resonator obtained in Comparative Example 1 of the present invention.

[0045] Fig.16 This is the admittance curve of the resonator obtained in Comparative Example 2 of the present invention.

[0046] Figures 1 to 8 Explanation of the reference numerals: 101 silicon dioxide supporting layer; 102 silicon substrate; 103 lower electrode layer; 104 piezoelectric layer; 105 upper electrode layer; 106 upper load layer; 107 silicon dioxide protective layer; 108 lower load layer; 109 cavity. DETAILED DESCRIPTION

[0047] In the description of the present invention, it should be noted that, if the specific conditions are not specified in the examples, the experiments were carried out according to conventional conditions or the conditions recommended by the manufacturer. The reagents or instruments used, if the manufacturer is not specified, are all conventional products that can be purchased commercially.

[0048] The present invention is further described in detail below in conjunction with specific implementation methods to help those skilled in the art have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention. The protection scope of the present invention includes but is not limited to the following embodiments. Any modifications made to the details and forms of the technical solution of the present invention without departing from the spirit and scope of the present application shall fall within the protection scope of the present invention.

[0049] Example 1

[0050] like Figure 9-10 As shown, this embodiment provides a silicon back-etched FBAR resonator, including a high-grade silicon substrate 102, a silicon dioxide support layer 101 and an AlN single crystal piezoelectric film layer 104; a cavity 109 is formed below the silicon dioxide support layer 101, and a portion of the silicon dioxide support layer 101 is exposed in the cavity 109, and the sidewall of the cavity 109 is formed by the silicon substrate 102; between the silicon dioxide support layer 101 and the single crystal piezoelectric film layer 104 A lower electrode layer 103 is provided, and an upper electrode layer 105 is provided above the single crystal piezoelectric film layer 104; the upper electrode layer 105 and the lower electrode layer 103 are respectively surrounded by an upper load layer 106 and a lower load layer 108 along the edges of the upper electrode layer 105 and the lower electrode layer 103; and the lower load layer 108 penetrates the silicon dioxide support layer 101 and extends into the cavity 109; the upper load layer 106 and the lower load layer 108 are symmetrically distributed up and down.

[0051] Specifically, in this embodiment, the material of the upper load layer 106 and the lower load layer 108 is Mo, the number is 1, and they are regular pentahedral frame structures. The width is set to 1.25μm. The width is based on the simulation calculation results. The wavelength of the laterally transmitted sound wave is analyzed by analyzing the scattering of each sound wave in the resonator and taking one quarter of its wavelength as the width of the load layer. The thickness is 50nm.

[0052] Specifically, in this embodiment, the thickness of the silicon dioxide support layer 101 is 2 μm. The thickness of the single crystal piezoelectric film layer 104 is 2 μm. By adopting high-quality AlN piezoelectric film 104, it can be better adapted to the frequency band above 3 GHz. The silicon substrate 102 is 575 μm thick and has a right-angle trapezoidal structure in cross section. The material of the resonator upper electrode layer 105 and the lower electrode layer 103 is Mo, and the thickness is 300 nm.

[0053] The preparation method of the resonator is as follows:

[0054] Step S1, select a high-resistance Si substrate as an epitaxial substrate, perform pickling and organic cleaning on the epitaxial substrate to clean the substrate surface, and first use a PECVD method to prepare a silicon dioxide support layer on the substrate; Figure 1 shown.

[0055] Step S2, based on step S1, sputtering or evaporating a lower electrode metal film on the support layer and performing a patterning process to obtain a lower electrode layer having a pentagonal structure; Figure 2 shown.

[0056] Step S3, based on step S2, sputtering a piezoelectric film on the lower electrode layer using PVD technology and performing photolithography patterning to obtain a piezoelectric layer; Figure 3 shown.

[0057] Step S4, based on step S3, continuing magnetron sputtering of the upper electrode metal film on the piezoelectric layer and performing patterning to obtain an upper electrode layer; Figure 4 shown.

[0058] Step S5, preparing an upper load layer on the piezoelectric layer based on step S4, so that the upper load layer is arranged along the edge of the upper electrode layer; Figure 5 shown.

[0059] Step S6, growing a silicon dioxide protective layer on the upper electrode layer and the upper support layer based on step S5; Figure 6 shown.

[0060] Step S7, using an in-situ etching process (ICP) to remove silicon in the working area of ​​the silicon substrate resonator to form a cavity, while partially exposing the support layer; Figure 7 shown.

[0061] Step S8, based on step S7, a lower load layer is prepared on the support layer, so that one end of the lower load layer is arranged along the edge of the lower electrode layer and the other end extends into the cavity; Figure 8 shown.

[0062] Step S9, removing the silicon dioxide protective layer on the top, etching the electrode connection through holes by using ICP etching technology, and making electrical connections by evaporating metal to obtain the FBAR bulk acoustic wave resonator of this embodiment.

[0063] Fig.13 This is the resonator admittance curve of Example 1. There is no stray peak in the resonance region. The parasitic parameters are small. The resonator has resonance points at 2306 MHz and 2400 MHz, and a quality factor of 1472.

[0064] Example 2

[0065] like Figure 9-10 As shown, this embodiment provides a silicon back-etched FBAR resonator, which differs from Embodiment 1 in that: the thickness of the silicon dioxide support layer 101 is 3.5 μm, the thickness of the upper load layer 108 is 500 nm; the thickness of the lower load layer 106 is 500 nm; the thickness of the single crystal piezoelectric film layer 104 is 500 nm. The thickness of the silicon substrate 102 is 575 μm, the thickness of the upper electrode 105 of the resonator is 800 nm, and the thickness of the lower electrode 103 of the resonator is 800 nm. The upper electrode and the lower electrode are made of Pt, and the upper load layer and the lower load layer are made of Pt.

[0066] Fig.14 This is the resonator admittance curve of Example 2. There is no stray peak in the resonance region. The parasitic parameters are small. The resonant points of the resonator are 4503MHz and 4621MHz, and the quality factor is 1590.

[0067] Example 3

[0068] This embodiment provides a silicon back-etched FBAR resonator, which is different from the first embodiment in that: the number of upper load layers and lower load layers are 2, and they are arranged in a nested manner of one surrounding another, and the interval between adjacent polyhedral frame structures is 0.25 μm, and the innermost polyhedral frame structure is arranged along the edges of the upper electrode layer and the lower electrode layer. The structural schematic diagram is shown in FIG. Fig.11 and 12 As shown, the resonator obtained in this embodiment uses two load layers, which can also effectively reduce the parasitic waveform of the resonance peak and improve the quality factor.

[0069] Comparative Example 1

[0070] The difference between this comparative example and Example 1 is that there is no cavity at the bottom. The resonator without a cavity has poor sound reflection ability and cannot form an effective resonance point. Fig.15 As shown, there is no resonance point in the resonator admittance curve.

[0071] Comparative Example 2

[0072] The difference between this comparative example and Example 1 is that there is no upper supporting layer and lower supporting layer. Fig.16 This is the resonator admittance curve of comparative example 1. As shown in the figure, more clutter interference appears near the resonance point.

[0073] In summary, the resonator of the present invention forms a piezoelectric oscillation sandwich structure through the upper electrode, the piezoelectric layer and the lower electrode, which can reduce the performance loss introduced by the external circuit. And by adopting a symmetrical load layer design, the acoustic wave energy consumption of the transverse mode in the piezoelectric layer can be reduced, and the acoustic waves of the transverse mode in the piezoelectric layer are reflected from the edge of the device back to the inside of the piezoelectric oscillation stack, so the parasitic waveform of the FBAR resonator at the resonance peak position is effectively reduced, which is conducive to the construction of a high-quality bulk acoustic wave filter with low insertion loss. In addition, the present invention only needs to prepare a load layer of the same material on the upper electrode and the lower electrode, and does not need to prepare an additional functional film layer or an external capacitor and resistor, which reduces the difficulty of preparation and thus reduces the preparation cost.

[0074] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A silicon back-etched FBAR resonator, characterized in that: The invention comprises a silicon substrate, a supporting layer and a piezoelectric layer in order from bottom to top; a cavity is formed below the supporting layer, and part of the supporting layer is exposed in the cavity, and the sidewall of the cavity is formed by the silicon substrate; a lower electrode layer is arranged between the supporting layer and the piezoelectric layer, and an upper electrode layer is arranged above the piezoelectric layer; the resonator further comprises an upper load layer and a lower load layer; the upper load layer and the lower load layer are respectively arranged along the edges of the upper electrode layer and the lower electrode layer, and the lower load layer penetrates the supporting layer and extends into the cavity; the upper load layer and the lower load layer are symmetrically distributed up and down.

2. The silicon back-etched FBAR resonator according to claim 1, characterized in that: The silicon substrate has a thickness of 575 μm and a cross section in an inverted right-angle trapezoidal structure.

3. The silicon back-etched FBAR resonator according to claim 1, characterized in that: The support layer is made of silicon dioxide and has a thickness of 2 to 3.5 μm.

4. The silicon back-etched FBAR resonator according to claim 1, characterized in that: The piezoelectric layer is made of AlN material and has a thickness of 500nm-4μm.

5. The silicon back-etched FBAR resonator according to claim 1, characterized in that: The upper electrode layer and the lower electrode layer are made of any one of Mo, Pt, Ti and Au, and have a thickness of 50 nm to 1 μm.

6. The silicon back-etched FBAR resonator according to claim 1, characterized in that: The upper support layer and the lower support layer are made of any one of Mo, Pt, Ti and Au, with a thickness of 50 nm to 2 μm and a width of 50 nm to 10 μm.

7. The silicon back-etched FBAR resonator according to claim 6, characterized in that: The number of the upper load-bearing layer and the number of the lower load-bearing layer are both one or more, presenting a polyhedral frame structure.

8. The silicon back-etched FBAR resonator according to claim 7, characterized in that: When there are multiple upper load layers and multiple lower load layers, the multiple polyhedral framework structures are arranged in a nested manner, one surrounding another, and adjacent polyhedral framework structures are spaced a certain distance apart. The outermost polyhedral framework structure is respectively arranged along the edges of the upper electrode layer and the lower electrode layer, and the other layers of polyhedral framework structures are respectively arranged on the upper electrode layer and the lower electrode layer.

9. The silicon back-etched FBAR resonator according to claim 8, characterized in that: The polyhedral framework structure is a regular pentahedral framework structure.

10. The method for preparing a silicon back-etched FBAR resonator according to any one of claims 1 to 9, characterized in that: The following steps are involved: Step S1, depositing a support layer on a silicon substrate; Step S2, based on step S1, a lower electrode metal film is grown on the support layer and patterned to obtain a lower electrode layer; Step S3, based on step S2, epitaxially growing a piezoelectric film on the lower electrode layer and performing photolithography patterning to obtain a piezoelectric layer; Step S4, based on step S3, continuing to grow an upper electrode metal film on the piezoelectric layer and performing a patterning process to obtain an upper electrode layer; Step S5, preparing an upper load layer on the piezoelectric layer based on step S4, so that the upper load layer is arranged along the edge of the upper electrode layer; Step S6, growing a silicon dioxide protective layer on the upper electrode layer and the upper support layer based on step S5; Step S7, using a back etching process to remove silicon in the working area of ​​the silicon substrate resonator to form a cavity, while partially exposing the support layer; Step S8, preparing a lower load layer on the support layer based on step S7, so that one end of the lower load layer is arranged along the edge of the lower electrode layer and the other end extends into the cavity; Step S9, removing the top silicon dioxide protective layer to obtain a FBAR bulk acoustic wave resonator.

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