chip

Abstract

A chip is disclosed, belonging to the field of electronic technology. The chip includes a dedicated scheduler, a general scheduler, and a plurality of hardware accelerators. The plurality of hardware accelerators are connected by soft connections, at least one hardware accelerator is connected to the dedicated scheduler, and at least one hardware accelerator is connected to the general scheduler. The processing flow of the dedicated scheduler is relatively fixed and the processing efficiency is relatively high. The processing flow of the general scheduler is relatively flexible and can overcome hardware design defects and improve performance through software programming. Therefore, it can provide processing flexibility while ensuring the processing efficiency of the chip.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to a chip. Background Art

[0002] Wireless local area network (WLAN) technology is a popular wireless communication technology, and the WLAN technology standard has been updated for several generations. For chip manufacturers, when launching a new WLAN chip, in order to ensure competitiveness, they hope to achieve: 1. Be compatible with existing technology standards and make the best use of existing devices; 2. Support the update of technology standards. Summary of the Invention

[0003] This application provides a chip that can provide processing flexibility while maintaining processing efficiency.

[0004] The chip includes a dedicated scheduler, a general scheduler, and multiple hardware accelerators. Any two of the multiple hardware accelerators are coupled. At least one of the multiple hardware accelerators is coupled to the dedicated scheduler. At least one of the multiple hardware accelerators is coupled to the general scheduler.

[0005] The chip provided by this application can be a communication chip, such as a WLAN chip, a base station chip, etc.

[0006] A hardware accelerator (HAC) is a functional circuit used to implement a certain function. For example, the multiple hardware accelerators can include one or more of the following: fast Fourier transform (FFT) circuit, channel estimator, linear equalizer, maximum likelihood estimation equalizer, low density parity code (LDPC) decoder, binary convolutional code (BCC) decoder, etc.

[0007] The dedicated scheduler is a processing circuit designed for a specific purpose, and its processing flow cannot be changed and can only be selected from a limited combination. For example, the dedicated scheduler can include an application-specific integrated circuit (ASIC), etc. The processing flow of the dedicated scheduler is relatively fixed, and its processing efficiency is relatively high. The dedicated scheduler can support the already released technology standards.

[0008] The dedicated scheduler includes multiple circuits, each of which is used to complete a different fixed processing flow, and each circuit in the multiple circuits is used to sequentially call at least two hardware accelerators among the multiple hardware accelerators according to the corresponding fixed processing flow.

[0009] The general scheduler is a processing circuit, and its processing flow can be changed by software programming. For example, the general processor may include a processor with a software-programmable microprocessor core such as a central processing unit (CPU) or a field programmable gate array (FPGA). The processing flow of the general scheduler is relatively flexible, and it can overcome hardware design defects and improve performance by means of software programming. The general scheduler can support the update of technical standards.

[0010] The general scheduler includes a processor and a memory. The memory is used to store the scheduling program, and the processor is used to execute the scheduling program to sequentially call at least two hardware accelerators among the multiple hardware accelerators according to the processing flow indicated by the scheduling program.

[0011] Any two of the multiple hardware accelerators are coupled. For example, the multiple hardware accelerators are soft-connected, that is, any two of the multiple hardware accelerators are connectable. For example, all of the multiple hardware accelerators are connected to a bus.

[0012] At least one of the multiple hardware accelerators is coupled to the dedicated scheduler. For example, at least one of the multiple hardware accelerators and the dedicated scheduler may be hard-connected or soft-connected. For example, at least one of the multiple hardware accelerators is connected to the dedicated scheduler through a wire; or at least one of the multiple hardware accelerators and the dedicated scheduler are both connected to a bus.

[0013] At least one of the multiple hardware accelerators is coupled to the general scheduler. For example, at least one of the multiple hardware accelerators and the general scheduler may be hard-connected or soft-connected. For example, at least one of the multiple hardware accelerators is connected to the general scheduler through a wire; or at least one of the multiple hardware accelerators and the general scheduler are both connected to a bus.

[0014] In this application, the processing flow of the dedicated scheduler is relatively fixed and the processing efficiency is high. The processing flow of the general scheduler is relatively flexible and can overcome hardware design defects and improve performance through software programming. Therefore, it can provide processing flexibility while ensuring the processing efficiency of the chip. Moreover, both the dedicated scheduler and the general scheduler can schedule multiple hardware accelerators. Since the dedicated scheduler can be compatible with the released technical standards and the general scheduler can support the update of technical standards, the adaptability of the chip's application scenarios and the performance stability can be enhanced.

[0015] Furthermore, the dedicated scheduler can be coupled with the general scheduler, and the dedicated scheduler and the general scheduler are used to cooperatively schedule multiple hardware accelerators.

[0016] The dedicated scheduler is coupled with the general scheduler. For example, the dedicated scheduler and the general scheduler can be hard-wired or soft-wired. For instance, the dedicated scheduler and the general scheduler are connected by a wire; or, both the dedicated scheduler and the general scheduler are connected to the bus.

[0017] Optionally, the dedicated scheduler is used to determine whether to continue the hardware accelerator scheduling by the dedicated scheduler or to instruct the general scheduler to perform the hardware accelerator scheduling according to the data status information sent by the first hardware accelerator among the multiple hardware accelerators.

[0018] In this application, the dedicated scheduler and the general scheduler perform cooperative scheduling. In ordinary application scenarios, the dedicated scheduler is used for scheduling, and in special application scenarios, the general scheduler is used for scheduling. In this way, the dedicated scheduler can ensure timing and processing speed, and the general scheduler can handle special problems and enhance functions. In this case, since the general scheduler is only responsible for scheduling in special application scenarios, the load of the general scheduler is small and the performance is relatively stable. Moreover, for special application scenarios that cannot be fully covered in the chip design stage, they can also be processed by the general scheduler through software simulation and other means, thereby improving the chip performance. At the same time, even if there are design defects in the hardware accelerator, the output data of the hardware accelerator with design defects can be corrected by the general scheduler, thereby reducing the chip development difficulty, reducing the technical risk, and shortening the chip development cycle.

[0019] Exemplarily, the dedicated scheduler is used to start the second hardware accelerator among the multiple hardware accelerators according to the data status information when the data status information meets the first condition, and instruct the first hardware accelerator to send the output data to the second hardware accelerator.

[0020] The first condition is used to indicate that the dedicated scheduler is capable of processing the output data in this data state. For example, the first condition can be that the data processing is error-free, or the data processing has an error and the cause of the error is a specified reason, etc. When the data state information meets the first condition, it indicates that the dedicated scheduler has the ability to continue scheduling the hardware accelerator to process the output data of the first hardware accelerator. Therefore, at this time, the dedicated scheduler can select a second hardware accelerator that can continue to process the output data from multiple hardware accelerators according to the data state information, and instruct the first hardware accelerator to send the output data to the second hardware accelerator for continued processing.

[0021] Exemplarily, the dedicated scheduler is used to send the data state information to the general scheduler when the data state information meets the second condition; the general scheduler is used to perform hardware accelerator scheduling according to the data state information.

[0022] The second condition is used to indicate that the dedicated scheduler is not capable of processing the output data in this data state. For example, the second condition can be that the data processing has an error and the cause of the error is other reasons than the specified reason, etc. When the data state information meets the second condition, it indicates that the dedicated scheduler does not have the ability to continue scheduling the hardware accelerator to process the output data of the first hardware accelerator. Therefore, at this time, the dedicated scheduler can send the data state information to the general scheduler, and the general scheduler will continue to perform hardware accelerator scheduling based on this. Description of the Drawings

[0023] Figure 1 is a schematic structural diagram of the first chip provided by an embodiment of the present application;

[0024] Figure 2 is a schematic structural diagram of the second chip provided by an embodiment of the present application;

[0025] Figure 3 is a schematic structural diagram of the third chip provided by an embodiment of the present application;

[0026] Figure 4 is a schematic structural diagram of the fourth chip provided by an embodiment of the present application. Detailed Embodiments

[0027] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0028] It should be understood that the "at least one" mentioned in this application may be one or more, and the "multiple" mentioned refers to two or more; the "including" mentioned means inclusive inclusion, that is, in addition to including the mentioned elements, other elements may also be included; the "A and / or B" mentioned means one or all of A or B; the "coupled" mentioned means electrical connection or electrical coupling, which includes being directly connected by wires or being connected through other components. In addition, for the convenience of clearly describing the technical solutions of this application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and roles. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and terms such as "first" and "second" do not necessarily limit being different.

[0029] Before explaining the embodiments of this application in detail, the concepts related to the embodiments of this application will be described first.

[0030] Hard scheduler: It can be called a dedicated scheduler. It is designed for a specific purpose. Once designed, its processing flow cannot be changed and can only be selected from limited combinations.

[0031] Soft scheduler: It can be called a general scheduler. After being designed, the processing flow can be changed by software programming.

[0032] Hard connection: The modules are connected by physical wires. Once the connection relationship is determined, it cannot be changed arbitrarily and can only be selected from limited combinations. For example, the modules are connected by wires.

[0033] Soft connection: The connection relationship between the modules is changeable, and the connection relationship can be changed by software programming. For example, the modules are all connected to the bus and configured with different addresses, and the modules can communicate based on the addresses.

[0034] The application scenarios related to the embodiments of this application will be described below:

[0035] WLAN technology is a popular wireless communication technology, and the WLAN technology standard has been updated for several generations. Currently, there are two implementation schemes for chip manufacturers to manufacture WLAN chips.

[0036] One is a fully hardened implementation scheme. Specifically, the chip includes multiple hardware accelerators and a dedicated scheduler. The multiple hardware accelerators are connected to each other by wires, and each of the multiple hardware accelerators is connected to the dedicated scheduler by wires. The dedicated scheduler can schedule the multiple hardware accelerators.

[0037] In this implementation solution, the chip has a high energy efficiency ratio, that is, the same function can be implemented in the most area-saving way. However, there are the following problems with this implementation solution: 1. High development difficulty: For chips with complex technical standards, it is necessary to carefully understand the technical standards and every test detail; 2. High technical risk: It is necessary to consider the application scenarios of the chip at the beginning of the design. Once there is a minor mistake, it needs to be redesigned; 3. Unable to upgrade: For application scenarios not considered at the beginning of the design, once the chip performance deteriorates, it cannot be compensated, and only the next generation of chips can be promoted, resulting in a short chip life cycle.

[0038] Another is the fully soft implementation solution. Specifically, the chip includes multiple hardware accelerators and a general scheduler, and both the multiple hardware accelerators and the general scheduler are connected to the internal bus of the chip. The general scheduler can schedule multiple hardware accelerators.

[0039] In this implementation solution, if there are design defects in the hardware accelerators, the general scheduler can remedy them through software intervention. Moreover, if the original design fails to cover certain application scenarios, the general scheduler can improve the performance through software simulation. However, there are the following problems with this implementation solution: 1. The software processing delay of the general scheduler is related to the internal operating system and is unpredictable, resulting in jitter; 2. In some application scenarios with tight timing requirements, the software processing may not meet the standards, resulting in a high cost in later debugging and problem location.

[0040] Therefore, the embodiments of the present application provide a chip, which can solve the problems of high development difficulty, high technical risk, and inability to upgrade in the fully hard implementation solution, and solve the problems of too high load and unstable performance in the fully soft implementation solution.

[0041] Next, the chip provided by the embodiments of the present application will be described in detail.

[0042] Figure 1 Or Figure 2 is a schematic structural diagram of a chip provided by the embodiments of the present application. Refer to Figure 1 Or Figure 2 The chip includes: a dedicated scheduler 101, a general scheduler 102, and multiple hardware accelerators 103.

[0043] Any two of the multiple hardware accelerators 103 are coupled. At least one of the multiple hardware accelerators 103 is coupled to the dedicated scheduler 101. At least one of the multiple hardware accelerators 103 is coupled to the general scheduler 102.

[0044] The hardware accelerator 103 is a functional circuit for implementing a certain function. For example, multiple hardware accelerators 103 may include one or more of the following: FFT circuit, channel estimator, linear equalizer, maximum likelihood estimation equalizer, LDPC decoder, BCC decoder, etc.

[0045] The dedicated scheduler 101 is a processing circuit designed for a specific purpose, and its processing flow cannot be changed and can only be selected from limited combinations. For example, the dedicated scheduler 101 may include an ASIC, etc. The processing flow of the dedicated scheduler 101 is relatively fixed, and its processing efficiency is relatively high. The dedicated scheduler 101 can support the published technical standards.

[0046] The general-purpose scheduler 102 is a processing circuit whose processing flow can be changed by software programming. For example, the general-purpose processor 102 may include a processor with a software-programmable microprocessor core such as a CPU, FPGA, etc. The processing flow of the general-purpose scheduler 102 is relatively flexible, and hardware design defects can be overcome and performance can be improved by means of software programming. The general-purpose scheduler 102 can support the update of technical standards.

[0047] Any two of the multiple hardware accelerators 103 are coupled. For example, the multiple hardware accelerators 103 are soft-connected, that is, any two of the multiple hardware accelerators 103 are connectable. For example, as Figure 1 or Figure 2 shown, all of the multiple hardware accelerators 103 are connected to the bus. In this case, the multiple hardware accelerators 103 can be configured with different addresses, and any two of the multiple hardware accelerators 103 can communicate based on each other's addresses. Of course, the soft connection between the multiple hardware accelerators 103 can also be implemented in other ways, and the embodiments of the present application do not make a unique limitation in this regard.

[0048] At least one of the multiple hardware accelerators 103 is coupled to the dedicated scheduler 101. For example, at least one of the multiple hardware accelerators 103 and the dedicated scheduler 101 can be hard-connected or soft-connected. For example, as Figure 1 shown, at least one of the multiple hardware accelerators 103 is connected to the dedicated scheduler 101 through a wire. In this case, for any one of the at least one hardware accelerator 103, this hardware accelerator 103 and the dedicated scheduler 101 can communicate through the wire connecting them. For another example, as Figure 2As shown, at least one of the multiple hardware accelerators 103 and the dedicated scheduler 101 are both connected to the bus. In this case, the at least one hardware accelerator 103 and the dedicated scheduler 101 can be configured with different addresses, and the at least one hardware accelerator 103 and the dedicated scheduler 101 can communicate based on each other's addresses. Of course, the hard connection or soft connection between at least one of the multiple hardware accelerators 103 and the dedicated scheduler 101 can also be achieved in other ways, and the embodiments of the present application do not make a unique limitation on this.

[0049] At least one of the multiple hardware accelerators 103 is coupled to the general scheduler 102. For example, at least one of the multiple hardware accelerators 103 and the general scheduler 102 can be hard-connected or soft-connected. For instance, as Figure 1 shown, at least one of the multiple hardware accelerators 103 is connected to the general scheduler 102 through a wire. In this case, for any one of the at least one hardware accelerator 103, this hardware accelerator 103 and the general scheduler 102 can communicate through the wire connecting them. Another example, as Figure 2 shown, at least one of the multiple hardware accelerators 103 and the general scheduler 102 are both connected to the bus. In this case, the at least one hardware accelerator 103 and the general scheduler 102 can be configured with different addresses, and the at least one hardware accelerator 103 and the general scheduler 102 can communicate based on each other's addresses. Of course, the hard connection or soft connection between at least one of the multiple hardware accelerators 103 and the general scheduler 102 can also be achieved in other ways, and the embodiments of the present application do not make a unique limitation on this.

[0050] Furthermore, referring to Figure 2 or Figure 3 , the dedicated scheduler 101 can be coupled to the general scheduler 102. For example, the dedicated scheduler 101 and the general scheduler 102 can be hard-connected or soft-connected. For instance, as Figure 3 shown, the dedicated scheduler 101 is connected to the general scheduler 102 through a wire. In this case, the dedicated scheduler 101 and the general scheduler 102 can communicate through the wire connecting them. Another example, as Figure 2As shown, both the dedicated scheduler 101 and the general scheduler 102 are connected to the bus. In this case, the dedicated scheduler 101 and the general scheduler 102 can be configured with different addresses, and the dedicated scheduler 101 and the general scheduler 102 can communicate based on each other's addresses. Of course, the hard connection or soft connection between the dedicated scheduler 101 and the general scheduler 102 can also be achieved in other ways, and the embodiments of this application do not make a unique limitation on this.

[0051] For the case where there is a hard connection between the above two modules, the hard connection between these two modules is only used for communication between them, and one of the two modules can directly send data to the other module through this hard connection. For example, for the case where two modules are connected by a wire, such as the hardware accelerator 103 is connected to the dedicated scheduler 101 by a wire, or the hardware accelerator 103 is connected to the general scheduler 102 by a wire, or the dedicated scheduler 101 is connected to the general scheduler 102 by a wire, the wire connecting these two modules is only used for communication between them, and one of the two modules can directly send data to the other module through the connected wire.

[0052] For the case where there is a soft connection between the above modules, for example, for the case where all the hardware accelerators 103 among multiple hardware accelerators 103 are connected to the bus, if a certain hardware accelerator 103 and the dedicated scheduler 101 are also connected to the bus, the bus to which all the hardware accelerators 103 among the multiple hardware accelerators 103 are connected and the bus to which this hardware accelerator 103 and the dedicated scheduler 101 are connected can be the same bus. Of course, they can also be different buses, and the embodiments of this application do not make a unique limitation on this.

[0053] For the case where there is a soft connection between the above modules, for example, for the case where all the hardware accelerators 103 among multiple hardware accelerators 103 are connected to the bus, if a certain hardware accelerator 103 and the general scheduler 102 are also connected to the bus, the bus to which all the hardware accelerators 103 among the multiple hardware accelerators 103 are connected and the bus to which this hardware accelerator 103 and the general scheduler 102 are connected can be the same bus. Of course, they can also be different buses, and the embodiments of this application do not make a unique limitation on this.

[0054] For the case where there is a soft connection between the above modules, for example, for the case where all the hardware accelerators 103 among multiple hardware accelerators 103 are connected to the bus, if the dedicated scheduler 101 and the general scheduler 102 are also connected to the bus, the bus to which all the hardware accelerators 103 among the multiple hardware accelerators 103 are connected and the bus to which the dedicated scheduler 101 and the general scheduler 102 are connected can be the same bus. Of course, they can also be different buses, and the embodiments of this application do not make a unique limitation on this.

[0055] For the case where the above modules are soft-connected, for example, when all the hardware accelerators 103 among multiple hardware accelerators 103 are connected to the bus, if a certain hardware accelerator 103 and the dedicated scheduler 101 are also connected to the bus, and this hardware accelerator 103 and the general scheduler 102 are also connected to the bus, and the dedicated scheduler 101 and the general scheduler 102 are also connected to the bus, then the bus to which all the hardware accelerators 103 among the multiple hardware accelerators 103 are connected, the bus to which this hardware accelerator 103 and the dedicated scheduler 101 are connected, the bus to which this hardware accelerator 103 and the general scheduler 102 are connected, and the bus to which the dedicated scheduler 101 and the general scheduler 102 are connected can be the same bus. Of course, they can also be different buses. The embodiments of the present application do not make a unique limitation on this.

[0056] For the case where the above modules are connected to the bus, for example, when the hardware accelerator 103 is connected to the bus, or the dedicated scheduler 101 is connected to the bus, or the general scheduler 102 is connected to the bus, the way this module is connected to the bus can refer to the related art, and the embodiments of the present application do not elaborate on this in detail. For example, the bus can include a bus controller, a bus transceiver, and a physical bus. This module can be connected to the bus controller, and the bus controller can be connected to the physical bus through the bus transceiver, so as to realize the connection of this module on the bus.

[0057] For a certain hardware accelerator 103 among multiple hardware accelerators 103, this hardware accelerator 103 can not only include interfaces for communicating with other hardware accelerators 103, interfaces for communicating with the dedicated scheduler 101, and interfaces for communicating with the general scheduler 102, but also include other interfaces, such as a network interface for communicating with the outside of the chip.

[0058] Moreover, for the first hardware accelerator 103 among multiple hardware accelerators 103, the input end of the first hardware accelerator 103 can be the input interface of the chip, which is used to receive data input from the outside of the chip. For the last hardware accelerator 103 among multiple hardware accelerators 103, the output end of the last hardware accelerator 103 can be the output interface of the chip, which is used to output data to the outside of the chip.

[0059] Both the dedicated scheduler 101 and the general scheduler 102 can schedule the hardware accelerator 103. The process of the dedicated scheduler 101 and the general scheduler 102 scheduling the hardware accelerator 103 is described below:

[0060] The dedicated scheduler 101 includes multiple circuits, which are respectively used to complete multiple different fixed processing flows. Each of the multiple circuits is used to sequentially call at least two of the multiple hardware accelerators 103 according to the corresponding fixed processing flow.

[0061] The general-purpose scheduler 102 includes a processor and a memory. The memory is used to store a scheduling program, and the processor is used to execute the scheduling program to sequentially call at least two of the multiple hardware accelerators 103 according to the processing flow indicated by the scheduling program.

[0062] In the embodiment of the present application, both the dedicated scheduler 101 and the general-purpose scheduler 102 can schedule multiple hardware accelerators 103. Since the dedicated scheduler 101 can be compatible with the released technical standards, and the general-purpose scheduler 102 can support the update of technical standards, the adaptability of the chip's application scenarios and the performance stability can be enhanced.

[0063] The dedicated scheduler 101 or the general-purpose scheduler 102 can start the hardware accelerator 103. After the hardware accelerator 103 is started, it can process the input data. The dedicated scheduler 101 or the general-purpose scheduler 102 can instruct the hardware accelerator 103 to output the processed data to other hardware accelerators 103 or to the outside of the chip.

[0064] The dedicated scheduler 101 and the general-purpose scheduler 102 independently schedule multiple hardware accelerators 103. The following describes this scheduling method:

[0065] If a certain data needs to be input into the chip for processing, the data may include indication information, which is used to indicate whether it is necessary to use the dedicated scheduler 101 for hardware accelerator scheduling or the general-purpose scheduler 102 for hardware accelerator scheduling. Exemplarily, when processing data that conforms to the released technical standards, the dedicated scheduler 101 can be used for hardware accelerator scheduling, and when processing data that conforms to the latest updated technical standards, the general-purpose scheduler 102 can be used for hardware accelerator scheduling.

[0066] In this case, if the indication information in the data indicates that the dedicated scheduler 101 is required for hardware accelerator scheduling, after the data is input into the chip, the dedicated scheduler 101 can schedule multiple hardware accelerators 103 to control the multiple hardware accelerators 103 to complete the processing of the data.

[0067] For example, for any one of the multiple hardware accelerators 103, if this hardware accelerator 103 receives input data, then this hardware accelerator 103 processes the input data to obtain output data and data status information. This hardware accelerator 103 sends the data status information to the dedicated scheduler 101. The dedicated scheduler 101 starts another one of the multiple hardware accelerators 103 according to the data status information, and instructs this hardware accelerator 103 to send the output data to the other hardware accelerator 103 as the input data of the other hardware accelerator 103, and the other hardware accelerator 103 continues to process. The data status information may include a data processing status and a data parameter status, etc. The data processing status is used to indicate whether the data processing of this hardware accelerator 103 is in error. When the data processing of this hardware accelerator 103 is in error, the data processing status may further include the reason for the error, etc. The data parameter status includes various parameter situations of the output data of this hardware accelerator 103, such as the signal-to-noise ratio, the number of streams, etc. of the output data of this hardware accelerator 103.

[0068] As an example, the dedicated scheduler 101 may select and switch a data processing path according to the data status information. That is, the dedicated scheduler 101 may select to start the next hardware accelerator 103 of this hardware accelerator 103 according to the data status information, or select to skip the next hardware accelerator 103 of this hardware accelerator 103 and start other subsequent hardware accelerators 103.

[0069] As an example, the dedicated scheduler 101 may adjust the working parameters of the subsequent hardware accelerator 103 for continuing to process data according to the data status information. That is, after the dedicated scheduler 101 starts another hardware accelerator 103 according to the data status information, it may first adjust the working parameters of the other hardware accelerator 103, and then instruct this hardware accelerator 103 to send the output data to the other hardware accelerator 103 to continue processing.

[0070] If the indication information in the data indicates that the general scheduler 102 is required for hardware accelerator scheduling, after the data is input into the chip, the general scheduler 102 may schedule the multiple hardware accelerators 103 to control the multiple hardware accelerators 103 to complete the processing of the data.

[0071] For example, for any one of the multiple hardware accelerators 103, if this hardware accelerator 103 receives input data, then this hardware accelerator 103 processes the input data to obtain output data and data status information. This hardware accelerator 103 sends the data status information to the general scheduler 102.

[0072] In one possible implementation, after receiving the data status information, the general scheduler 102 may start another one of the multiple hardware accelerators 103 according to the data status information, and instruct this hardware accelerator 103 to send the output data to the other hardware accelerator as the input data of the other hardware accelerator 103, and the other hardware accelerator 103 continues to process it.

[0073] As an example, the general scheduler 102 may select to switch the data processing path according to the data status information. That is, the general scheduler 102 may select to start the next hardware accelerator 103 of this hardware accelerator 103 according to the data status information, or select to skip the next hardware accelerator 103 of this hardware accelerator 103 and start other subsequent hardware accelerators 103.

[0074] As an example, the general scheduler 102 may adjust the working parameters of the subsequent hardware accelerator 103 for continuing to process the data according to the data status information. That is, after the general scheduler 102 starts another hardware accelerator 103 according to the data status information, it may first adjust the working parameters of the other hardware accelerator 103, and then instruct this hardware accelerator 103 to send the output data to the other hardware accelerator 103 to continue processing.

[0075] In another possible implementation, the general scheduler 102 may obtain the output data of this hardware accelerator 103 according to the data status information, process the output data to obtain the processed data, and then start another one of the multiple hardware accelerators 103 according to the processed data, and send the processed data to the other hardware accelerator 103 to continue processing.

[0076] As an example, the general scheduler 102 may select to switch the data processing path according to the processed data. That is, the general scheduler 102 may select to start the next hardware accelerator 103 of this hardware accelerator 103 according to the processed data, or select to skip the next hardware accelerator 103 of this hardware accelerator 103 and start other subsequent hardware accelerators 103.

[0077] As an example, the general scheduler 102 may adjust the working parameters of the subsequent hardware accelerator 103 for continuing to process the data according to the processed data. That is, after the general scheduler 102 starts another hardware accelerator 103 according to the processed data, it may first adjust the working parameters of the other hardware accelerator 103, and then send the processed data to the other hardware accelerator 103 to continue processing.

[0078] The dedicated scheduler 101 and the general scheduler 102 can cooperate to schedule multiple hardware accelerators 103. At this time, the dedicated scheduler 101 needs to be coupled with the general scheduler 102. The following describes this scheduling method:

[0079] The dedicated scheduler 101 can schedule multiple hardware accelerators 103 in ordinary application scenarios. For example, the dedicated scheduler 101 can schedule multiple hardware accelerators 103 under the already released technical standards. Multiple hardware accelerators 103 cooperate with the dedicated scheduler 101 and can work together to achieve basic functions. For example, the dedicated scheduler 101 sequentially calls multiple hardware accelerators 103 to work. After each hardware accelerator 103 completes data processing, it notifies the dedicated scheduler 101, and the dedicated scheduler 101 then starts the subsequent hardware accelerator 103 based on this.

[0080] The general scheduler 102 can schedule multiple hardware accelerators 103 in special application scenarios. For example, the general scheduler 102 can schedule multiple hardware accelerators 103 under the latest updated technical standards. Special application scenarios can be application scenarios not considered during the design of the dedicated scheduler 101 or application scenarios that the dedicated scheduler 101 is not capable of handling. For example, when the dedicated scheduler 101 detects that the current data processing status of the hardware accelerator 103 is abnormal, it notifies the general scheduler 102 to perform subsequent scheduling of the hardware accelerator 103.

[0081] That is to say, in the embodiments of this application, the dedicated scheduler 101 and the general scheduler 102 cooperate to schedule. The dedicated scheduler 101 performs scheduling in ordinary application scenarios, and the general scheduler 102 performs scheduling in special application scenarios. In this way, the dedicated scheduler 101 can ensure timing and processing speed, and the general scheduler 102 can handle special problems and enhance functions. In this case, since the general scheduler 102 is only responsible for scheduling in special application scenarios, the load of the general scheduler 102 is small and the performance is relatively stable. Moreover, for special application scenarios that cannot be fully covered during the chip design stage, they can also be processed by the general scheduler 102 through software simulation and other means, thereby improving the chip performance. At the same time, even if there are design defects in the hardware accelerator 103, the general scheduler 102 can correct the output data of the hardware accelerator 103 with design defects, thereby reducing the chip development difficulty, reducing the technical risk, and shortening the chip development cycle.

[0082] The following describes the specific operations of the dedicated scheduler 101 and the general scheduler 102 in cooperating to schedule multiple hardware accelerators 103:

[0083] For the data input to the chip this time, under the scheduling of the dedicated scheduler 101, it can be processed by multiple hardware accelerators 103 in sequence. That is, after a hardware accelerator 103 processes the input data to obtain output data, under the control of the dedicated scheduler 101, the output data is sent to the next hardware accelerator 103 as the input data of the next hardware accelerator 103, and the next hardware accelerator 103 continues to process it.

[0084] In this case, for any one of the multiple hardware accelerators 103, such as for the first hardware accelerator 103, if the first hardware accelerator 103 obtains output data and data status information after processing the input data, the first hardware accelerator 103 can send the data status information to the dedicated scheduler 101. When the first hardware accelerator 103 sends the data status information to the dedicated scheduler 101, it can be sent to the dedicated scheduler 101 by means of interruption or message, and the embodiments of the present application do not make a unique limitation on this.

[0085] The dedicated scheduler 101 can determine whether to continue the hardware accelerator scheduling by the dedicated scheduler 101 or instruct the general scheduler 102 to continue the hardware accelerator scheduling according to the data status information sent by the first hardware accelerator 103. The specific operations are as follows:

[0086] When the data status information meets the first condition, the dedicated scheduler 101 can start the second hardware accelerator 103 among the multiple hardware accelerators 103 according to the data status information, and instruct the first hardware accelerator 103 to send the output data to the second hardware accelerator 103.

[0087] The first condition is used to indicate that the dedicated scheduler 101 is capable of processing the output data in this data status. For example, the first condition can be that the data processing is error-free, or the data processing is in error and the error cause is a specified cause, etc. When the data status information meets the first condition, it indicates that the dedicated scheduler 101 has the ability to continue scheduling the hardware accelerator 103 to process the output data of the first hardware accelerator 103. Therefore, at this time, the dedicated scheduler 101 can select the second hardware accelerator 103 that can continue to process the output data from the multiple hardware accelerators 103 according to the data status information, and instruct the first hardware accelerator 103 to send the output data to the second hardware accelerator 103 for continued processing.

[0088] As an example, the dedicated scheduler 101 may select to switch the data processing path according to the data status information. That is, the dedicated scheduler 101 may, according to the data status information, select to start the next hardware accelerator 103 of the first hardware accelerator 103 (regarding this next hardware accelerator 103 as the second hardware accelerator 103), or select to skip the next hardware accelerator 103 of the first hardware accelerator 103 and start other subsequent hardware accelerators 103 (regarding this other subsequent hardware accelerator 103 as the second hardware accelerator 103).

[0089] As an example, the dedicated scheduler 101 may adjust the working parameters of the subsequent hardware accelerator 103 for continuing to process the data according to the data status information. That is, after the dedicated scheduler 101 starts the second hardware accelerator 103 according to the data status information, it may first adjust the working parameters of the second hardware accelerator 103, and then instruct the first hardware accelerator 103 to send the output data to the second hardware accelerator 103 for further processing.

[0090] When the data status information meets the second condition, the dedicated scheduler 101 may send the data status information to the general scheduler 102. The general scheduler 102 may perform hardware accelerator scheduling according to the data status information.

[0091] The second condition is used to indicate that the dedicated scheduler 101 is unable to process the output data in this data state. For example, the second condition may be that a data processing error occurs and the cause of the error is other reasons except for the specified reasons. When the data status information meets the second condition, it indicates that the dedicated scheduler 101 does not have the ability to continue scheduling the hardware accelerator 103 to process the output data of the first hardware accelerator 103. Therefore, at this time, the dedicated scheduler 101 may send the data status information to the general scheduler 102, and the general scheduler 102 may continue with the hardware accelerator scheduling based on this.

[0092] After receiving the data status information, the general scheduler 102 may select an appropriate scheduling method according to the data status information.

[0093] In a possible implementation, the general scheduler 102 may start the third hardware accelerator 103 among the multiple hardware accelerators 103 according to the data status information, and instruct the first hardware accelerator 103 to send the output data to the third hardware accelerator 103 for further processing.

[0094] As an example, the general scheduler 102 may select to switch the data processing path according to the data status information. That is, the general scheduler 102 may select to start the next hardware accelerator 103 of the first hardware accelerator 103 (regarding this next hardware accelerator 103 as the third hardware accelerator 103) according to the data status information, or select to skip the next hardware accelerator 103 of the first hardware accelerator 103 and start other subsequent hardware accelerators 103 (regarding this other subsequent hardware accelerator 103 as the third hardware accelerator 103).

[0095] As an example, the general scheduler 102 may adjust the working parameters of the subsequent hardware accelerator 103 for continuing to process data according to the data status information. That is, after the general scheduler 102 starts the third hardware accelerator 103 according to the data status information, it may first adjust the working parameters of the third hardware accelerator 103, and then instruct the first hardware accelerator 103 to send the output data to the third hardware accelerator 103 for further processing.

[0096] In another possible implementation, the general scheduler 102 may obtain the output data of the first hardware accelerator 103 according to the data status information, process the output data to obtain processed data, and then start the fourth hardware accelerator 103 among the multiple hardware accelerators 103 according to the processed data, and send the processed data to the fourth hardware accelerator 103 for further processing.

[0097] As an example, the general scheduler 102 may select to switch the data processing path according to the processed data. That is, the general scheduler 102 may select to start the next hardware accelerator 103 of the first hardware accelerator 103 (regarding this next hardware accelerator 103 as the fourth hardware accelerator 103) according to the processed data, or select to skip the next hardware accelerator 103 of the first hardware accelerator 103 and start other subsequent hardware accelerators 103 (regarding this other subsequent hardware accelerator 103 as the fourth hardware accelerator 103).

[0098] As an example, the general scheduler 102 may adjust the working parameters of the subsequent hardware accelerator 103 for continuing to process data according to the processed data. That is, after the general scheduler 102 starts the fourth hardware accelerator 103 according to the processed data, it may first adjust the working parameters of the fourth hardware accelerator 103, and then send the processed data to the fourth hardware accelerator 103 for further processing.

[0099] Note that for a certain hardware accelerator 103, if the dedicated scheduler 101 starts this hardware accelerator 103, then this hardware accelerator 103 sends data status information to the dedicated scheduler 101; if the general scheduler 102 starts this hardware accelerator 103, then this hardware accelerator 103 sends data status information to the general scheduler 102.

[0100] For each piece of data input to the chip, it is first the dedicated scheduler 101 that schedules the hardware accelerator 103 to process the input data. If during this data processing, the dedicated scheduler 101 selects to instruct the general scheduler 102 to perform hardware accelerator scheduling based on the data status information sent by the hardware accelerator 103, then subsequently the general scheduler 102 continues to perform hardware accelerator scheduling to complete this data processing.

[0101] The chip provided by the embodiment of the present application may be a communication chip, such as a WLAN chip, a base station chip, etc., and the embodiment of the present application does not make a unique limitation thereto.

[0102] In the embodiment of the present application, the chip includes a dedicated scheduler 101, a general scheduler 102, and multiple hardware accelerators 103. The multiple hardware accelerators 103 are connected by soft connections, and at least one hardware accelerator 103 is connected to the dedicated scheduler 101, and at least one hardware accelerator 103 is connected to the general scheduler 102. The processing flow of the dedicated scheduler 101 is relatively fixed and the processing efficiency is high. The processing flow of the general scheduler 102 is relatively flexible and can overcome hardware design defects and improve performance through software programming. Therefore, it can provide processing flexibility while ensuring the processing efficiency of the chip.

[0103] For ease of understanding, the following will be combined with Figure 4 the shown chip for an example. Refer to Figure 4 , this chip includes multiple hardware accelerators 103, a dedicated scheduler 101, and a general scheduler 102. The multiple hardware accelerators 103 include an FFT circuit, a channel estimator, a linear equalizer, a maximum likelihood estimation equalizer, an LDPC decoder, and a BCC decoder. The dedicated scheduler 101 may be an ASIC, and the general scheduler 102 may be a CPU. The multiple hardware accelerators 103, the dedicated scheduler 101, and the general scheduler 102 are all connected to the bus.

[0104] In a general application scenario, the dedicated scheduler 101 coordinates the collaborative work of each hardware accelerator 103. Specifically, the FFT circuit sends data status information to the ASIC in the form of an interrupt or a message. First, the ASIC determines to continue the hardware accelerator scheduling by itself according to the data processing status in the data status information. Then, the ASIC can select one of the subsequent linear equalizer and maximum likelihood estimation equalizer modules according to the data parameter status in the data status information, and then instruct the FFT circuit to send the output data to the selected module for further processing.

[0105] In a special application scenario, the general scheduler 102 takes over the scheduling of each hardware accelerator 103 under the instruction of the dedicated scheduler 101. Specifically, after the FFT circuit sends data status information to the ASIC in the form of an interrupt or a message, the ASIC determines that the CPU will continue the hardware accelerator scheduling according to the data processing status in the data status information, and the ASIC sends the data status information to the CPU. The CPU performs the hardware accelerator scheduling according to the data status information. For example, the CPU can select one of the subsequent linear equalizer and maximum likelihood estimation equalizer modules according to the data parameter status in the data status information to continue the data processing. Alternatively, the CPU can software-simulate an equalizer to process the output data of the FFT circuit through this equalizer, and then skip the existing linear equalizer and maximum likelihood estimation equalizer, and directly call the subsequent LDPC decoder or BCC decoder to continue the data processing.

[0106] The above are the embodiments provided by the present application, which are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the scope of the present application shall be included in the protection scope of the present application.

Claims

1. A chip, characterized in that, the chip includes: a dedicated scheduler, a general scheduler, and a plurality of hardware accelerators; any two of the plurality of hardware accelerators are coupled; at least one of the plurality of hardware accelerators is coupled to the dedicated scheduler; at least one of the plurality of hardware accelerators is coupled to the general scheduler; wherein, the processing flow of the dedicated scheduler is one of at least one different fixed processing flows and the dedicated scheduler supports the published technical standards, and the processing flow of the general scheduler can be changed through software programming and the general scheduler supports technical standard updates.

2. The chip according to claim 1, characterized in that, all of the plurality of hardware accelerators are connected to a bus.

3. The chip according to claim 1 or 2, characterized in that, the coupling of at least one of the plurality of hardware accelerators to the dedicated scheduler includes: at least one of the plurality of hardware accelerators is connected to the dedicated scheduler through a wire; or, at least one of the plurality of hardware accelerators and the dedicated scheduler are both connected to the bus.

4. The chip according to claim 1 or 2, characterized in that, the coupling of at least one of the plurality of hardware accelerators to the general scheduler includes: at least one of the plurality of hardware accelerators is connected to the general scheduler through a wire; or, at least one of the plurality of hardware accelerators and the general scheduler are both connected to the bus.

5. The chip according to claim 1 or 2, characterized in that, the dedicated scheduler is coupled to the general scheduler, and the dedicated scheduler and the general scheduler are used to cooperatively schedule the plurality of hardware accelerators.

6. The chip according to claim 5, characterized in that, the coupling of the dedicated scheduler to the general scheduler includes: the dedicated scheduler is connected to the general scheduler through a wire; or, the dedicated scheduler and the general scheduler are both connected to the bus.

7. The chip according to claim 5, characterized in that, the dedicated scheduler is used to determine whether to continue hardware accelerator scheduling by the dedicated scheduler or to instruct the general scheduler to perform hardware accelerator scheduling according to the data status information sent by the first hardware accelerator among the plurality of hardware accelerators.

8. The chip according to claim 7, characterized in that, the dedicated scheduler is used to, when the data status information meets the first condition, start the second hardware accelerator among the plurality of hardware accelerators according to the data status information, and instruct the first hardware accelerator to send the output data to the second hardware accelerator.

9. The chip according to claim 7 or 8, characterized in that, the dedicated scheduler is used to, when the data status information meets the second condition, send the data status information to the general scheduler; the general scheduler is used to perform hardware accelerator scheduling according to the data status information.

10. The chip according to any one of claims 1-2, 6-8, characterized in that, the chip is a wireless local area network (WLAN) chip.

11. The chip according to any one of claims 1-2, 6-8, characterized in that, the multiple hardware accelerators include one or more of the following: fast Fourier transform circuit, channel estimator, linear equalizer, maximum likelihood estimation equalizer, low density parity check (LDPC) decoder, binary convolutional code decoder.

12. The chip according to any one of claims 1-2, 6-8, characterized in that, the dedicated scheduler includes multiple circuits, the multiple circuits are respectively used to complete multiple different fixed processing flows, and each circuit in the multiple circuits is used to sequentially call at least two hardware accelerators among the multiple hardware accelerators according to the corresponding fixed processing flow.

13. The chip according to any one of claims 1-2, 6-8, characterized in that, the general scheduler includes a processor and a memory, the memory is used to store a scheduling program, and the processor is used to execute the scheduling program to sequentially call at least two hardware accelerators among the multiple hardware accelerators according to the processing flow indicated by the scheduling program.

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