Display substrate, preparation method thereof and display device

Abstract

A display substrate (20) and its fabrication method, and a display device (10) thereof. The display substrate (20) includes a display area (201) and a peripheral area (202) surrounding the display area (201). The display area (201) includes an opening, and the peripheral area (202) includes an opening peripheral area (203) at least partially located in the opening. The display substrate (20) includes a substrate (210) and a semiconductor pattern (220), a first conductive pattern (230), and a second conductive pattern (240) located in the opening peripheral area (203). The first conductive pattern (230) is configured to transmit electrical signals for the display area (201), and the first conductive pattern (230) includes a plurality of first trace groups (2301) arranged side by side along a first direction (R1), each of which... A trace group (2301) includes at least two first traces (231) arranged side by side along a first direction (R1); in a direction perpendicular to the substrate (210), the first traces (231) are respectively spaced and insulated from the semiconductor pattern (220) and the second conductive pattern (240) to form a capacitor; the semiconductor pattern (220) and the second conductive pattern (240) are electrically connected through a plurality of vias (250) disposed in the opening peripheral region (203), the plurality of vias (250) being located between adjacent first trace groups (2301) in the first direction (R1).

Description

Technical Field

[0001] The embodiments of this disclosure relate to a display substrate and its preparation method, as well as a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display devices have advantages such as thinness, light weight, wide viewing angle, active light emission, continuously adjustable emission color, low cost, fast response speed, low power consumption, low driving voltage, wide operating temperature range, simple manufacturing process, high luminous efficiency, and flexible display. Therefore, they are increasingly widely used in display fields such as mobile phones, tablets, and digital cameras. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a display substrate, the display substrate including a display area and a peripheral area surrounding the display area; wherein the display area includes an opening, and the peripheral area includes an opening peripheral area at least partially located in the opening; the display substrate includes a substrate substrate and a semiconductor pattern, a first conductive pattern, and a second conductive pattern located in the opening peripheral area; the semiconductor pattern is located on the substrate substrate, the first conductive pattern is located on a side of the semiconductor pattern away from the substrate substrate, and the second conductive pattern is located on a side of the first conductive pattern away from the semiconductor pattern; the first conductive pattern is configured to transmit an electrical signal for the display area, the first conductive pattern including a plurality of first trace groups arranged side by side along a first direction, each first trace group including at least two first traces arranged side by side along the first direction, the first traces being spaced and insulated from the semiconductor pattern and the second conductive pattern respectively in a direction perpendicular to the substrate substrate to form a capacitor; the semiconductor pattern and the second conductive pattern are electrically connected through a plurality of vias disposed in the opening peripheral area, the plurality of vias being located between adjacent first trace groups in the first direction.

[0004] For example, in a display substrate provided in at least one embodiment of this disclosure, among the plurality of first trace groups, there is a region in which the arrangement of vias is substantially the same between adjacent first trace groups in the first direction.

[0005] For example, in a display substrate provided in at least one embodiment of this disclosure, the spacing between adjacent first trace groups in the first direction is greater than the spacing between adjacent first traces in the first trace group in the first direction.

[0006] For example, in a display substrate provided in at least one embodiment of this disclosure, in the plurality of first trace groups, the spacing between adjacent first trace groups in the first direction is approximately the same.

[0007] For example, in the display substrate provided in at least one embodiment of this disclosure, in the plurality of first trace groups, the arrangement of at least two first traces in each group is the same in the first direction.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, in each of the first trace groups, the spacing between adjacent first traces in the first direction is approximately the same.

[0009] For example, in a display substrate provided in at least one embodiment of this disclosure, vias located on both sides of a first trace group in the first direction are arranged approximately symmetrically with respect to the first trace group along the extension direction of the first trace.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, at least one row of vias arranged along the extension direction of the first traces is provided between adjacent first trace groups in the first direction.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the semiconductor pattern includes a plurality of conductive blocks arranged in parallel along a second direction, the plurality of conductive blocks being electrically connected to the second conductive pattern through the plurality of vias, the second direction being different from the first direction.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of conductive blocks have approximately the same width in the second direction, and the spacing between adjacent conductive blocks in the second direction is approximately the same.

[0013] For example, in a display substrate provided in at least one embodiment of this disclosure, the second conductive pattern is continuously disposed in the area surrounding the opening.

[0014] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer are at least located in the peripheral region of the opening, the first insulating layer is located on the side of the semiconductor pattern away from the substrate, the first conductive pattern is located on the side of the first insulating layer away from the semiconductor pattern, the second insulating layer is located on the side of the first conductive pattern away from the first insulating layer, the second conductive pattern is located on the side of the second insulating layer away from the first conductive pattern, and the plurality of vias are at least located within the first insulating layer and the second insulating layer and at least penetrate the first insulating layer and the second insulating layer.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the display area includes a first display area and a second display area located on opposite sides of the opening. The first display area, the opening, and the second display area are arranged sequentially along the extension direction of the first trace. The first trace extends sequentially through the first display area, the peripheral area of ​​the opening, and the second display area to transmit electrical signals for the first display area and the second display area.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, the display area further includes a third display area, which is connected to one of the two opposite edges of the first display area in the first direction and to one of the two opposite edges of the second display area in the first direction; the display substrate includes a plurality of third traces located in the third display area, the extension direction of the plurality of third traces being the same as the extension direction of the first traces and configured to transmit electrical signals for the third display area, and the plurality of third traces being disposed on the same layer as the first conductive pattern.

[0017] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a power trace pattern, wherein the power trace pattern is disposed on the same layer as the second conductive pattern, or is located on the side of the second conductive pattern away from the substrate, and the power trace pattern is electrically connected to the second conductive pattern to provide an electrical signal.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the power trace pattern is located in the display area and is disposed on the same layer as the second conductive pattern, and the power trace pattern is configured to provide a high voltage signal.

[0019] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a plurality of pixel units located in the display area, wherein the pixel unit includes a pixel driving circuit located on the substrate, the pixel driving circuit including a thin film transistor and a storage capacitor; the thin film transistor includes a gate, an active layer, a source, and a drain, the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode; the semiconductor pattern is disposed on the same layer as the active layer, the second conductive pattern is disposed on the same layer as the source and the drain, and the first conductive pattern is disposed on the same layer as at least one of the second capacitor electrode, the gate, and the first capacitor electrode.

[0020] For example, in a display substrate provided in at least one embodiment of the present disclosure, the first traces in a plurality of first trace groups of the first conductive pattern are configured to transmit scan signals for the pixel driving circuit, respectively.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel unit further includes a light-emitting element, the light-emitting element being electrically connected to the pixel driving circuit on the side of the pixel driving circuit away from the substrate, and the pixel driving circuit being configured to drive the light-emitting element to operate.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, the first conductive pattern further includes at least one fourth trace, which is spaced and insulated from at least one of the semiconductor pattern and the second conductive pattern in a direction perpendicular to the substrate to form a capacitor.

[0023] For example, in a display substrate provided in at least one embodiment of this disclosure, the peripheral region of the opening includes a first dam region, a second dam region, and a spacing region. The first dam region at least partially surrounds the display area, the spacing region at least partially surrounds the first dam region, and the second dam region at least partially surrounds the spacing region. The orthogonal projection of the semiconductor pattern, the first conductive pattern, the second conductive pattern, and the plurality of vias on the substrate includes portions that do not overlap with the first dam region.

[0024] At least one embodiment of this disclosure also provides a display device, including the display substrate described in any embodiment of this disclosure.

[0025] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, comprising: providing a substrate; forming a semiconductor pattern on the substrate; forming a first conductive pattern on the semiconductor pattern; and forming a second conductive pattern on the first conductive pattern, wherein the display substrate includes a display area and a peripheral area surrounding the display area, the display area includes an opening, the peripheral area includes an opening peripheral area at least partially located in the opening, the semiconductor pattern, the first conductive pattern and the second conductive pattern are located in the opening peripheral area, the first conductive pattern is configured to transmit an electrical signal for the display area, the first conductive pattern includes a plurality of first trace groups arranged in parallel along a first direction, each first trace group including at least two first traces arranged in parallel along the first direction, the first traces being spaced and insulated from the semiconductor pattern and the second conductive pattern respectively in a direction perpendicular to the substrate to form a capacitor, the semiconductor pattern and the second conductive pattern being electrically connected through a plurality of vias disposed in the opening peripheral area, the plurality of vias being located between adjacent first trace groups in the first direction.

[0026] For example, in a method for preparing a display substrate provided in at least one embodiment of this disclosure, forming the first conductive pattern on the semiconductor pattern includes: forming a first insulating layer on the semiconductor pattern, and forming the first conductive pattern on the first insulating layer; forming the second conductive pattern on the first conductive pattern includes: forming a second insulating layer on the first conductive pattern, and forming the second conductive pattern on the second insulating layer.

[0027] For example, at least one embodiment of the present disclosure provides a method for fabricating a display substrate, which further includes: forming a pixel driving circuit for a pixel unit on the substrate in the display area, wherein the pixel driving circuit includes a thin film transistor and a storage capacitor, the thin film transistor includes a gate, an active layer, a source, and a drain, the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode, the semiconductor pattern is disposed in the same layer as the active layer, the second conductive pattern is disposed in the same layer as the source and the drain, and the first conductive pattern is disposed in the same layer as at least one of the second capacitor electrode, the gate, and the first capacitor electrode. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0029] Figure 1 This is a planar schematic diagram of an OLED display device;

[0030] Figure 2A This is a plan view of a display substrate provided for some embodiments of the present disclosure;

[0031] Figure 2B A schematic diagram of a partial planar structure within the opening periphery of a display substrate provided in some embodiments of this disclosure;

[0032] Figure 2C A schematic diagram of a partial cross-sectional structure of the area surrounding an opening in a display substrate provided in some embodiments of this disclosure;

[0033] Figure 3 This is a planar schematic diagram of the pixel unit arrangement near the opening periphery of a display substrate provided in some embodiments of the present disclosure;

[0034] Figure 4 A plan view of another display substrate provided in some embodiments of this disclosure;

[0035] Figure 5AA schematic diagram illustrating a specific example of a partial cross-sectional structure within the opening periphery region of a display substrate provided in some embodiments of this disclosure;

[0036] Figure 5B A schematic diagram illustrating a specific example of a partial cross-sectional structure in the periphery region of an opening of another display substrate provided in some embodiments of this disclosure;

[0037] Figure 6 A schematic diagram of a partial planar structure in the area surrounding an opening of another display substrate provided in some embodiments of this disclosure;

[0038] Figure 7A This is a schematic diagram of a partial cross-sectional structure of a display substrate provided in some embodiments of the present disclosure;

[0039] Figure 7B This is a schematic diagram of a partial cross-sectional structure of another display substrate provided in some embodiments of the present disclosure;

[0040] Figure 8 An equivalent circuit diagram of a pixel driving circuit in a display substrate provided for some embodiments of this disclosure;

[0041] Figures 9A-9E A schematic diagram of each layer of a pixel driving circuit in a display substrate provided for some embodiments of this disclosure; and

[0042] Figure 10 This is a schematic diagram of the layers of a pixel driving circuit in another display substrate provided for some embodiments of this disclosure. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0045] Currently, with the increasing popularity of electronic display products, users have higher requirements for their functionality and appearance. In order to meet the different practical needs of users, the appearance or display area of ​​electronic display products sometimes needs to be designed with irregular or special shapes.

[0046] Figure 1 This is a planar schematic diagram of an OLED display device. For example, such as... Figure 1 As shown, the OLED display device 10 includes a display area 101 and a border area 102 surrounding the display area 101. The display area 101 is designed to have an irregular shape, for example, having a notch 103 on at least one side. The display device 10 can arrange devices such as cameras and proximity sensors in the area of ​​the notch 103, thereby helping to realize a narrow-bezel display device.

[0047] Since the display area 101 has a notch 103, multiple metal traces are typically provided along the edge of the display area 101 outside the frame area 102 within the notch 103 to electrically connect multiple rows of pixel units in the display area 101 located on both sides of the notch 103, providing electrical signals such as scan signals for these multiple rows of pixel units. Furthermore, since the load on the metal traces connecting the display areas on both sides of the notch 103 is lower than that on the portion of the display area not corresponding to the notch 103, multiple signal compensation traces are typically designed below the metal traces to form a capacitor between the signal compensation traces and the metal traces. This increases the transmission load of the metal traces, compensates for the signal transmission effect of the metal traces, and thus prevents display abnormalities in the pixel units in the display area 101 located on both sides of the notch 103.

[0048] Typically, auxiliary electrodes are provided in the frame region 102 to electrically connect the multiple signal compensation traces to power signal lines that provide, for example, drive current signals or drive voltage signals, so that the multiple signal compensation traces receive the electrical signals required to form compensation capacitors. The auxiliary electrodes are usually located above the multiple signal compensation traces and the metal traces, and are electrically connected to the signal compensation traces through multiple vias provided in the frame region 102. This allows the capacitance formed between the auxiliary electrodes and the metal traces to further increase the transmission load of the metal traces, thereby better compensating for the electrical signal transmission effect of the metal traces.

[0049] At least one embodiment of this disclosure provides a display substrate, the display substrate including a display area and a peripheral area surrounding the display area. The display area includes an opening, and the peripheral area includes an opening peripheral area at least partially located in the opening; the display substrate includes a substrate substrate and a semiconductor pattern, a first conductive pattern, and a second conductive pattern located in the opening peripheral area; the semiconductor pattern is located on the substrate substrate, the first conductive pattern is located on a side of the semiconductor pattern away from the substrate substrate, and the second conductive pattern is located on a side of the first conductive pattern away from the semiconductor pattern; the first conductive pattern is configured to transmit electrical signals for the display area, and the first conductive pattern includes a plurality of first trace groups arranged side by side along a first direction, each first trace group including at least two first traces arranged side by side along the first direction; in a direction perpendicular to the substrate substrate, the first traces are respectively spaced and insulated from the semiconductor pattern and the second conductive pattern to form a capacitor; the semiconductor pattern and the second conductive pattern are electrically connected through a plurality of vias disposed in the opening peripheral area, the plurality of vias being located between adjacent first trace groups in the first direction.

[0050] In the display substrate provided in the above embodiments of this disclosure, a plurality of vias that electrically connect the semiconductor pattern and the second conductive pattern are respectively disposed between adjacent first trace groups. That is, the plurality of vias are arranged in a manner that is at least two first traces apart in the first direction, thereby reducing the arrangement density of vias in the area surrounding the opening and reducing the overall size required by the plurality of first traces in the first direction. Thus, by optimizing the arrangement of vias in the area surrounding the opening, capacitance can be formed between the semiconductor pattern and the second conductive pattern and the first trace respectively to compensate for the electrical signal transmission effect, while reducing the size required by the area surrounding the opening in the first direction, thereby facilitating the design of a narrow bezel on the display substrate.

[0051] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same elements described in different drawings.

[0052] Figure 2A This is a plan view of a display substrate provided in some embodiments of the present disclosure.Figure 2B This is a schematic diagram of a partial planar structure within the area surrounding an opening of a display substrate, provided in some embodiments of this disclosure. Figure 2C This is a schematic diagram of a partial cross-sectional structure within the area surrounding an opening in a display substrate, provided for some embodiments of this disclosure. For example, Figure 2B It can be Figure 2A The diagram shows the arrangement of multiple vias in the area surrounding the opening of the display substrate. Figure 2C It can be Figure 2A The diagram shows a partial cross-sectional structure of the display substrate along line A-A'.

[0053] It should be noted that, for ease of explanation, Figure 2B and Figure 2C The diagram only shows the arrangement relationship between the semiconductor pattern, the first conductive pattern, and the second conductive pattern. The design of other structures or functional layers in the display substrate can refer to the conventional arrangement methods in the art, and will not be described in detail here.

[0054] For example, combining Figures 2A-2C As shown, the display substrate 20 includes a display area 201 and a peripheral area 202 surrounding the display area 201. The display area 201 includes an opening, which can be a closed opening or a non-closed opening. Devices such as cameras and proximity sensors can be arranged in the area where the opening is located, thereby helping to realize a narrow bezel display device. For example, the opening can be... Figure 2A The recess (example of a non-closed opening) formed on at least one side of the display area 201 shown in the figure includes an opening peripheral area 203 that is at least partially located in the opening.

[0055] The display substrate 20 includes a substrate 210 and a semiconductor pattern 220, a first conductive pattern 230, and a second conductive pattern 240 located in the peripheral region 203 of the opening. The semiconductor pattern 220 is located on the substrate 210, the first conductive pattern 230 is located on the side of the semiconductor pattern 220 away from the substrate 210, and the second conductive pattern 240 is located on the side of the first conductive pattern 230 away from the semiconductor pattern 220. The first conductive pattern 230 is configured to transmit electrical signals for the display area 201, such as one or more of a gate scan signal, a light emission control signal, a reset signal, etc., for a pixel driving circuit in the display area 201. The first conductive pattern 230 includes a plurality of first trace groups 2301 arranged in parallel along a first direction R1, and each first trace group 2301 includes two first traces 231 arranged in parallel along the first direction R1. In a direction perpendicular to the substrate 210, the first traces 231 are respectively spaced and insulated from the semiconductor pattern 220 and the second conductive pattern 240 to form a capacitor. Semiconductor pattern 220 and second conductive pattern 240 are electrically connected by a plurality of vias 250 disposed in the peripheral region 203 of the opening, and the plurality of vias 250 are located between adjacent first trace groups 2301 in the first direction R1.

[0056] In the display substrate 20 provided in the above embodiments of this disclosure, a plurality of vias 250 electrically connecting the semiconductor pattern 220 and the second conductive pattern 240 are respectively disposed between adjacent first trace groups 2301. The plurality of vias 250 are arranged in the first direction R1 with a spacing of two first traces 231. This reduces the density of the vias 250 in the opening peripheral region 203 and reduces the overall size required by the multiple first traces 231 in the multiple first trace groups 2301 in the first direction R1. Therefore, by optimizing the arrangement of the vias 250 in the opening peripheral region 203, it is possible to form capacitors between the semiconductor pattern 220 and the second conductive pattern 240 and the first traces 231 to compensate for the electrical signal transmission effect, while reducing the size required by the opening peripheral region 203 in the first direction R1, thereby facilitating the design of a narrow bezel in the display substrate 20.

[0057] For example, combining Figure 2A and Figure 2CAs shown, among the multiple first trace groups 2301, adjacent first trace groups 2301 in the first direction R1 include a region where the arrangement of vias 250 is approximately the same. For example, among the multiple first trace groups 2301, adjacent first trace groups 2301 in the first direction R1 have the same or substantially the same arrangement of vias 250. That is, among the multiple first trace groups 2301, adjacent first trace groups 2301 in the first direction R1 include a region where, within a unit length, at least one of the following is substantially the same: number, density, spacing, arrangement, etc., of vias 250. This can help improve the consistency of the capacitive environment of each first trace 231, thereby improving the consistency of the signal transmission load of the first trace 231 and further improving the compensation effect. At the same time, it also helps improve the electrical connection effect between the semiconductor pattern 220 and the second conductive pattern 240, so as to better compensate for the signal transmission effect of the first trace 231.

[0058] For example, the spacing D1 between adjacent first trace groups 2301 in the first direction R1 is greater than the spacing D2 between adjacent first traces 231 in the first trace group 2301 in the first direction R1. As a result, the overall size required by multiple first traces 231 in the first direction R1 can be further reduced, thereby reducing the size required by the opening periphery area 203 in the first direction R1, which is more conducive to the display substrate 20 to achieve a narrow bezel design.

[0059] Furthermore, compared to the arrangement of multiple vias in the area surrounding the opening with a first trace spaced apart in the first direction R1, in the display substrate 20 provided in this embodiment, the reduced spacing between two adjacent first traces 231 in the first trace group 2301 in the first direction R1 increases the capacitance formed between the two adjacent first traces 231, thereby further improving the transmission load of the first traces 231 to achieve a better compensation effect, and thus enabling the display substrate 20 to provide a higher quality display image.

[0060] For example, in multiple first trace groups 2301, the spacing D1 between adjacent first trace groups 2301 in the first direction R1 is the same or approximately the same. This can improve the consistency of the capacitive environment of the first trace 231 in the first trace group 2301, improve the consistency of the signal transmission load of the first trace 231, and further improve the compensation effect for electrical signal transmission. It also helps to improve the uniformity of etching of the first trace 231 in the first trace group 2301, which facilitates the fabrication and processing of the first trace 231.

[0061] For example, in multiple first wiring groups 2301, the two first wirings 231 in each group are arranged in the same way in the first direction R1.

[0062] For example, in each first wiring group 2301, the extension directions of the two first wirings 231 are approximately parallel to each other, for example, both first wirings 231 extend approximately along the second direction R2 shown in the figure.

[0063] For example, in each first trace group 2301, the spacing D2 between adjacent first traces 231 in the first direction R1 can be the same or approximately the same. This ensures that the capacitive environment of the multiple first traces 231 in the multiple first trace groups 2301 is approximately consistent, making the signal transmission load of the multiple first traces 231 approximately the same, thereby further optimizing the compensation effect on the signal transmission of the first traces 231.

[0064] It should be noted that, in Figure 2B In the illustrated embodiment, for ease of explanation, both first traces 231 are represented as elongated strips. For example, the widths of the two first traces 231 in the first direction R1 may be the same. In other embodiments of this disclosure, depending on actual needs, the two first traces 231 may also be bent shapes, for example, having corner areas and straight edge areas, and the edges of the first traces 231 may be straight, curved, serrated, etc. The embodiments of this disclosure do not limit this.

[0065] It should be noted that, in Figure 2B In the embodiments shown, for ease of explanation, only the first trace 231 is shown in each first trace group 2301; however, in some other embodiments of this disclosure, each first trace group 2301 may include other types of traces or structures, etc., depending on actual needs, and the embodiments of this disclosure do not limit this.

[0066] For example, vias 250 located on both sides of a first trace group 2301 in the first direction R1 are arranged approximately symmetrically with respect to the first trace group 2301 along the extension direction of the first trace 231 (e.g., the second direction R2 shown in the figure). This not only improves the consistency of the capacitance environment of the first trace 231, but also facilitates the processing and fabrication of vias 250, and also helps to improve the electrical connection effect between the semiconductor pattern 220 and the second conductive pattern 240.

[0067] For example, combining Figures 2A-2CAs shown, the semiconductor pattern 220 includes a plurality of conductive blocks 221 arranged in parallel along the second direction R2. The plurality of conductive blocks 221 are electrically connected to the second conductive pattern 240 through a plurality of vias 250. The first direction R1 is different from the second direction R2. For example, the first direction R1 can be perpendicular to the second direction R2, so that the plurality of first traces 231 and the plurality of conductive blocks 221 are arranged in a cross pattern, which is beneficial to the consistency of the capacitance formed between the plurality of conductive blocks 221 and the plurality of first traces 231, further improving the consistency of the transmission load of the first traces 231 and optimizing the compensation effect.

[0068] For example, each first trace 231 partially overlaps with multiple conductive blocks 221, and each conductive block 221 partially overlaps with multiple first traces 231. For example, a via 250 can be provided in the part of the conductive block 221 that does not overlap with the first trace 231, that is, in the gap between adjacent first trace groups 2301.

[0069] For example, multiple conductive blocks 221 have the same width in the second direction R2, and the spacing between adjacent conductive blocks 221 in the second direction R2 can be the same or approximately the same. This can further improve the consistency of the capacitance formed between the multiple conductive blocks 221 and the multiple first traces 231, improve the consistency of the transmission load of the first traces 231, and thus optimize the compensation effect of the signal transmission of the first traces 231.

[0070] For example, the second conductive pattern 240 is continuously disposed in the peripheral region 203 of the opening, for example, it can be disposed as a whole, which helps the electrical connection between the second conductive pattern 240 and the plurality of conductive blocks 221.

[0071] For example, in the display substrate 20 provided in the embodiments of this disclosure, a row of vias 250 arranged along the extension direction of the first trace 231 (e.g., the second direction R2) is provided between adjacent first trace groups 2301 in the first direction R1; while in some other embodiments of this disclosure, multiple rows of vias 250 arranged along the extension direction of the first trace 231, such as two rows or three rows, may also be provided between adjacent first trace groups 2301 in the first direction R1, that is, multiple vias 250 can be arranged in an array between adjacent first trace groups 2301, and the embodiments of this disclosure do not limit this.

[0072] It should be noted that, in the embodiments disclosed herein, Figure 2BThe specific number of vias 250 between adjacent first trace groups 2301 shown is merely illustrative. For example, in some other embodiments of this disclosure, the number of vias 250 between adjacent first trace groups 2301 can be determined according to different actual needs, such as the width of the conductive block 221 in the second direction R2 or the manufacturing process precision, etc. The embodiments of this disclosure do not limit this.

[0073] For example, combining Figures 2A-2C As shown, the display substrate 20 further includes a first insulating layer 261 and a second insulating layer 262. The first insulating layer 261 and the second insulating layer 262 are located at least in the opening peripheral region 203. The first insulating layer 261 is located on the side of the semiconductor pattern 220 away from the substrate 210, the first conductive pattern 230 is located on the side of the first insulating layer 261 away from the semiconductor pattern 220, the second insulating layer 262 is located on the side of the first conductive pattern 230 away from the first insulating layer 261, and the second conductive pattern 240 is located on the side of the second insulating layer 262 away from the first conductive pattern 230. A plurality of vias 250 are located at least within the first insulating layer 261 and the second insulating layer 262 and at least penetrate both the first insulating layer 261 and the second insulating layer 262.

[0074] For example, multiple conductive blocks 221 in semiconductor pattern 220 and multiple first traces 231 in first conductive pattern 230 use first insulating layer 261 as dielectric material to form capacitors, and multiple first traces 231 in second conductive pattern 240 and first conductive pattern 230 use second insulating layer 262 as dielectric material to form capacitors, thereby increasing the transmission load of multiple first traces 231, compensating for the electrical signal transmission effect on multiple first traces 231, and ensuring that the display effect of each part in the display area 201 of display substrate 20 remains uniform.

[0075] It should be noted that, in Figures 2A-2CIn the embodiments of this disclosure shown, only a first insulating layer 261 is provided between the semiconductor pattern 220 and the first conductive pattern 230, and only a second insulating layer 262 is provided between the first conductive pattern 230 and the second conductive pattern 240. In other embodiments of this disclosure, in addition to the first insulating layer 261, other insulating layers, structural layers, or functional layers may be provided between the semiconductor pattern 220 and the first conductive pattern 230. Similarly, in addition to the second insulating layer 262, other insulating layers, structural layers, or functional layers may also be provided between the first conductive pattern 230 and the second conductive pattern 240, as long as the via 250 can penetrate the corresponding insulating layer to allow the semiconductor pattern 220 to be electrically connected to the second conductive pattern 240, thereby forming compensation capacitors between the first conductive pattern 230 and the semiconductor pattern 220, and between the first conductive pattern 230 and the second conductive pattern 240, respectively. The embodiments of this disclosure do not impose specific limitations on this.

[0076] For example, some embodiments of the present disclosure provide a display substrate 20 that also includes a power trace pattern. The power trace pattern may be disposed on the same layer as the second conductive pattern 240, or it may be located on the side of the second conductive pattern 240 away from the substrate 210. The power trace pattern is electrically connected to the second conductive pattern 240 to provide an electrical signal. For example, a semiconductor pattern 220 is electrically connected to the second conductive pattern 240 through a via 250 and further electrically connected to the power trace pattern. For example, the electrical signal provided by the power trace pattern can be a high-voltage signal or a low-voltage signal.

[0077] For example, the power supply trace pattern can be configured to receive a low-voltage signal (e.g., a cathode signal provided to the pixel unit in the display area 201, which can be represented by VSS). The power supply trace pattern can be located on the side of the second conductive pattern 240 away from the substrate 210 and electrically connected to the second conductive pattern 240 via a direct contact or via structure to provide the low-voltage signal. Furthermore, by applying a low-voltage signal to the second conductive pattern 240 and the plurality of conductive blocks 221 in the semiconductor pattern 220, the first trace 231 transmitting electrical signals such as gate scan signals can form capacitances with the conductive blocks 221 and the second conductive pattern 240 respectively, thereby achieving a compensation effect.

[0078] For example, the power trace pattern can be configured to receive a high-voltage signal (e.g., a high-voltage signal provided to the pixel units in the display area 201, which can be represented by VDD). The power trace pattern can be disposed on the same layer as the second conductive pattern 240. For example, the power trace pattern is located in the display area 201 and connected to the second conductive pattern 240 located in the peripheral area 202 on the same layer to provide the high-voltage signal. Furthermore, by applying a high-voltage signal to the second conductive pattern 240 and the plurality of conductive blocks 221 in the semiconductor pattern 220, the first trace 231 transmitting electrical signals such as gate scan signals can form capacitances with the conductive blocks 221 and the second conductive pattern 240 respectively, thereby achieving a compensation effect.

[0079] It should be noted that in some other embodiments of this disclosure, the display substrate may also include other structural or functional layers in the area surrounding the opening, besides, for example, a semiconductor pattern, a first conductive pattern, a second conductive pattern, a first insulating layer, and a second insulating layer, as long as these layers can respectively form capacitors between the first conductive pattern and the semiconductor pattern, and between the first conductive pattern and the second conductive pattern, to achieve a compensation effect. The embodiments of this disclosure do not impose any limitations on this.

[0080] For example, the substrate 210 can be a glass plate, a quartz plate, a metal plate, or a resin-based plate. For example, the material of the substrate 210 can include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For example, the substrate 210 can be a flexible substrate or a non-flexible substrate; the embodiments disclosed herein are not limited in this regard.

[0081] For example, the materials of the first insulating layer 261 and the second insulating layer 262 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or organic insulating materials such as polyimide, polyphthalamide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of this disclosure do not specifically limit the materials of the first insulating layer and the second insulating layer. For example, the materials of the first insulating layer and the second insulating layer may be the same as each other, partially the same, or different from each other; the embodiments of this disclosure do not impose any limitations in this regard.

[0082] For example, the material of the plurality of conductive blocks 221 of the semiconductor pattern 220 may include polycrystalline silicon or oxide semiconductor (e.g., indium gallium zinc oxide).

[0083] For example, the material of the plurality of first traces 231 of the first conductive pattern 230 may include metallic or alloy materials, such as single-layer or multi-layer metal structures formed of molybdenum, aluminum, and titanium. For example, the plurality of first traces 231 of the first conductive pattern 230 may all be made of the same material, or they may be formed by alternating different materials, and the embodiments disclosed herein are not limited in this respect.

[0084] For example, multiple first traces 231 can be formed on the same layer as a structure in the pixel unit of the display area 201. Multiple first traces 231 can also be formed on the same layer as two structures in the pixel unit of the display area 201, that is, a portion of the first traces 231 are formed on the same layer as one structure in the pixel unit, and another portion of the first traces 231 are formed on the same layer as another structure in the pixel unit; in some embodiments, these two portions of the first traces 231 are alternately arranged to form multiple first traces 231. Alternatively, multiple first traces 231 can also be formed on the same layer as three structures in the pixel unit of the display area 201, that is, a first portion of the first traces 231 are formed on the same layer as the first structure in the pixel unit, a second portion of the first traces 231 are formed on the same layer as the second structure in the pixel unit, and a third portion of the first traces 231 are formed on the same layer as the third structure in the pixel unit. The embodiments of this disclosure do not limit this.

[0085] For example, the first trace 231 can be formed on the same layer as the signal line in the display area 201 that transmits corresponding electrical signals (e.g., gate scan signal, light emission control signal, reset signal, etc.), thereby enabling electrical signal transmission by connecting it to the signal line on the same layer; or, the first trace 231 can be located on a different layer from the signal line in the display area 201 that transmits corresponding electrical signals (e.g., gate scan signal, light emission control signal, reset signal, etc.), and can be electrically connected to the signal line through, for example, a via structure to enable electrical signal transmission. The embodiments of this disclosure do not limit this.

[0086] For example, the material of the second conductive pattern 240 may include metallic or alloy materials, such as a single-layer or multi-layer metal structure formed of molybdenum, aluminum and titanium, for example, the multi-layer structure is a multi-metal stack (e.g., a titanium, aluminum and titanium three-layer metal stack (Al / Ti / Al)).

[0087] For example, combining Figures 2A-2CAs shown, the display area 201 includes a first display area 2011 and a second display area 2012 located on opposite sides of the opening. The first display area 2011, the opening, and the second display area 2012 are arranged sequentially along the extension direction of the first trace 231 (e.g., the second direction R2). The first trace 231 extends sequentially through the first display area 2011, the peripheral area 203 of the opening, and the second display area 2012 to transmit electrical signals for the first display area 2011 and the second display area 2012. For example, in the peripheral area 203 of the opening, the first trace 231 extends along the edge of the display area 201 that forms the opening.

[0088] For example, by forming capacitances between multiple first traces 231 and multiple conductive blocks 221 and the second conductive pattern 240, the transmission load of the first traces 231 can be increased, compensating for the electrical signal transmission effect of the first traces 231. This allows the display effect of the pixel units in the first display area 2011 and the second display area 2012 to be consistent with the display effect of other pixel units in the display area 201 (e.g., the pixel units in the third display area 2013 described below), avoiding or reducing display abnormalities at different gray levels, thereby improving the display effect of the display substrate 20.

[0089] For example, a first trace 231 can be provided for each row of pixel units located in the first display area 2011 and the second display area 2012 to transmit one of the electrical signals, such as a gate scan signal, a light emission control signal, and a reset signal. For example, the gate lines of each row of pixel units located in the first display area 2011 and the second display area 2012 can be electrically connected through the first trace 231 to transmit the gate scan signal. For example, multiple first traces 231 can be provided for each row of pixel units located in the first display area 2011 and the second display area 2012 to transmit the above-mentioned multiple electrical signals respectively. For example, the gate lines and light emission control lines of each row of pixel units located in the first display area 2011 and the second display area 2012 can be electrically connected through the first trace 231 to transmit the gate scan signal and the light emission control signal respectively. The embodiments of this disclosure do not limit this.

[0090] For example, the display area 201 also includes a third display area 2013, which is connected to one of the two opposite edges of the first display area 2011 in the first direction R1, and to one of the two opposite edges of the second display area 2012 in the first direction R1.

[0091] For example, the two opposite edges of the third display area 2013 in a direction perpendicular to the first direction R1 (e.g., the second direction R2) are respectively aligned with the edges of the first display area 2011 in a direction perpendicular to the first direction R1 and away from the opening, and with the edges of the second display area 2012 in a direction perpendicular to the first direction R1 and away from the opening. For example, one of the two opposite edges of the third display area 2013 in the second direction R2 is aligned with and connected to the edge of the first display area 2011 in the second direction R2 away from the opening, and the other is aligned with and connected to the edge of the second display area 2012 in the second direction R2 away from the opening, thereby forming a complete and continuous display area 201.

[0092] For example, the display substrate 20 includes multiple third traces located in the third display area 2013. The extension direction of these third traces is the same as that of the first trace 231, and they are configured to transmit electrical signals for the third display area 2013. For example, the signal type transmitted by the third trace is the same as the electrical signal type transmitted by the first trace 231, such as one or more of a gate scan signal, a light emission control signal, or a reset signal for the pixel driving circuit in the display area 201, thereby enabling the display substrate 20 to perform a display function. For example, these multiple third traces can be disposed on the same layer as the first trace.

[0093] For example, Figure 3 Six rows of pixel units are shown near the opening perimeter region 203. For example, in some examples, such as Figure 3 As shown, assuming the sixth row of pixel units is a full row of pixel units, for example, the sixth row of pixel units can be located at... Figure 2A The sixth row of pixel units in the third display area 2013 shown has a total transmission load of M. The first to fifth rows of pixel units are pixel units located on either side of the opening; for example, the first to fifth rows of pixel units could be located in... Figure 2A In the first display area 2011 and the second display area 2012 shown, the pixel units in the first to fifth rows are not full rows of pixel units, and the number of pixel units gradually increases from the first row to the fifth row. At this time, by compensating the transmission load of the first trace 231 that transmits multiple electrical signals corresponding to the pixel units in the first to fifth rows, the total transmission load of each row of pixel units can be made closer to or basically equal to M.

[0094] For example, in some examples, due to the limited space of the opening periphery region 203, such as from the first row to the fifth row, the lengths of the opening periphery region 203 in the second direction R2 are A, B, C, D, and E, respectively. Since the total transmission load of each row of pixel units from the first to the fifth row may still be difficult to reach M after compensation, the total transmission load of the pixel units from the first to the fifth row can be gradually increased. That is, a compensation scheme with gradually changing total transmission load is adopted, so that the compensation effect of the electrical signals corresponding to the pixel units from the first to the fifth row can gradually increase, thereby allowing the display effect of the non-full-row pixel units after compensation to gradually approach the display effect of the full-row pixel units. Thus, the impact of the signal transmission load of the non-full-row pixel units on the display effect is reduced, thereby facilitating the narrow bezel design of the display substrate 20 while enabling the display substrate 20 to provide a higher quality display image.

[0095] For example, after compensation, the total transmission load of the pixel units from the first to the fifth row are V / 100×M, U / 100×M, T / 100×M, S / 100×M and R / 100×M, respectively, where R>S>T>U>V, R≤100, and R, S, T, U and V are the fractions of the transmission load of the pixel units from the first to the fifth row when M is 100.

[0096] It should be noted that, in the display substrate 20 provided in this embodiment, Figure 2B and Figure 2C Only the case where the semiconductor pattern 220 and the second conductive pattern 240 each form a capacitor with a plurality of first traces 231 is shown. In other embodiments of this disclosure, the first conductive pattern 230 may also include a trace that is spaced apart and insulated from only one of the semiconductor pattern 220 and the second conductive pattern 240 in a direction perpendicular to the substrate 210 to form a capacitor. The embodiments of this disclosure do not limit this.

[0097] For example, in some embodiments of this disclosure, the first conductive pattern 230 further includes at least one fourth trace. In a direction perpendicular to the substrate 210, the fourth trace is spaced and insulated from at least one of the semiconductor pattern 220 and the second conductive pattern 240 to form a capacitor. For example, the fourth trace may be spaced and insulated only from the semiconductor pattern 220 to form a capacitor, or only from the second conductive pattern 240 to form a capacitor; alternatively, the fourth trace may be configured similarly to the first trace 231, spaced and insulated from both the semiconductor pattern 220 and the second conductive pattern 240 to form a capacitor. The embodiments of this disclosure do not limit this arrangement.

[0098] For example, the fourth trace can also be used for signal transmission of pixel units in the first display area 2011 and the second display area 2012 located on both sides of the opening. By utilizing at least one of the semiconductor pattern 220 and the second conductive pattern 240 to form a capacitor with the fourth trace, the signal transmission effect can be compensated, thereby improving the display effect of the screen. For example, the fourth trace can be disposed on the same layer as the first trace 231 and use the same material or structure as the first trace 231. The structure, material, and function of the fourth trace can be referred to the above description of the first trace 231, and will not be repeated here.

[0099] It should be noted that, Figure 2C The cross-sectional structure shown can be corresponding to Figure 2A The cross-sectional structure of the display substrate 20 shown along line A-A'; or in some other embodiments of this disclosure, Figure 2C The cross-sectional structure shown can also correspond to, for example, Figure 4 The cross-sectional structure of the display substrate 30 (including the display area 301) along line B-B' shown is as follows. Figure 4 The opening of the display substrate 30 shown is closed. That is, the embodiments of this disclosure do not limit the specific shape or location of the opening in the display area of ​​the display substrate.

[0100] It should be noted that the present disclosure does not limit the shape or outline of the display substrate. For example, the display substrate provided in the embodiments of the present disclosure can be as follows: Figure 2A or Figure 4 The square shown can also be other suitable regular or irregular shapes, such as circles, regular hexagons, regular octagons, etc. The embodiments disclosed herein do not limit this.

[0101] In some embodiments of this disclosure, the opening periphery region 203 includes a first dam region, a second dam region, and a spacing region. The first dam region at least partially surrounds the display region 201, the spacing region at least partially surrounds the first dam region, and the second dam region at least partially surrounds the spacing region. The orthographic projection of the semiconductor pattern 220, the first conductive pattern 230, the second conductive pattern 240, and the plurality of vias 250 on the substrate 210 includes portions that do not overlap with the first dam region.

[0102] For example, the orthographic projections of the semiconductor pattern 220, the first conductive pattern 230, and the second conductive pattern 240 used to form the compensation structure onto the substrate 210 do not overlap with the first dam region, nor with the interval region or the second dam region. That is, the semiconductor pattern 220, the first conductive pattern 230, and the second conductive pattern 240 are not disposed in the first dam region, the interval region, and the second dam region that form the dam structure, so as to avoid mutual interference with such as power lines disposed in the first dam region, the interval region, and the second dam region, thereby further improving the stability of the display substrate.

[0103] In some embodiments of this disclosure, a portion of the semiconductor pattern 220, the first conductive pattern 230, the second conductive pattern 240, and a plurality of vias 250 may be disposed in the first cofferdam area, or further disposed in the interval area and the second cofferdam area, thereby optimizing the layout structure of the display substrate and facilitating the realization of a narrow bezel design.

[0104] Figure 5A This is a schematic diagram illustrating a specific example of a partial cross-sectional structure of a display substrate provided in some embodiments of this disclosure. Figure 5B This is a schematic diagram illustrating a specific example of a partial cross-sectional structure within the opening periphery region of another display substrate provided in some embodiments of this disclosure. For example, Figure 5A and Figure 5B All can be Figure 2A The diagram shown is a cross-sectional view of the display substrate along line A-A', or it could also be... Figure 4 The diagram shows a cross-sectional structure of the display substrate along line B-B'.

[0105] It should be noted that, Figure 5A and Figure 5B The example shown differs only in the placement of the first conductive pattern 430 (e.g., including multiple first traces 431) and the corresponding semiconductor pattern 420 (e.g., including multiple conductive blocks 421) and the second conductive pattern 440 in the peripheral region 403 of the opening. For example, in Figure 5A In the example shown, in the opening periphery region 403, the first conductive pattern 430 is located in the first cofferdam region 404 and further in the spacer region 406, while the semiconductor pattern 420 and the second conductive pattern 440 are located in the first cofferdam region 404, the spacer region 406, and the second cofferdam region 405; and while Figure 5B In the example shown, in the opening periphery region 403, the first conductive pattern 430, the semiconductor pattern 420, and the second conductive pattern 440 are located only in the first cofferdam region 404. The embodiments of this disclosure do not limit the placement of the first conductive pattern 430, the semiconductor pattern 420, and the second conductive pattern 440 in the opening periphery region 403. The following examples illustrate this. Figure 5AThe example shown will be used to specifically explain the display substrate 40. Figure 5B The example shown can be found in the section on Figure 5A The corresponding description will not be repeated here.

[0106] For example, Figure 5A The display substrate 40 shown can be Figures 2A-2C A specific example of the display substrate 20 shown, such as the planar structure of the display substrate 40 and the arrangement of vias 450 in the opening peripheral region 403, can be referred to the corresponding descriptions in the above embodiments of the display substrate 20, and will not be repeated here.

[0107] For example, the substrate 410, semiconductor pattern 420 (e.g., including multiple conductive blocks 421), first conductive pattern 430 (e.g., including multiple first traces 431), second conductive pattern 440, first insulating layer 461 and second insulating layer 462 of the display substrate 40 are basically the same as or similar to the substrate 210, semiconductor pattern 220, first conductive pattern 230, second conductive pattern 240, first insulating layer 261 and second insulating layer 262 of the display substrate 20, and will not be described in detail here.

[0108] For example, such as Figure 5A As shown, the peripheral region 403 of the opening includes a first dam region 404, a second dam region 405, and a spacing region 406. The first dam region 404 at least partially surrounds the display area of ​​the display substrate 40, the spacing region 406 at least partially surrounds the first dam region 404, and the second dam region 405 at least partially surrounds the spacing region 406. A semiconductor pattern 420, a first conductive pattern 430, a second conductive pattern 440, and a plurality of vias 450 are at least located in the first dam region 404.

[0109] For example, in Figure 5A In the display substrate 40 shown, the semiconductor pattern 420 and the second conductive pattern 440 are located in the first dam region 404, the second dam region 405, and the spacer region 406; the first conductive pattern 430 is located in the first dam region 404 and the spacer region 406; and a plurality of vias 450 are located in the first dam region 404 and the spacer region 406. In other embodiments of this disclosure, the first conductive pattern 430 may also be located in the first dam region 404, the second dam region 405, and the spacer region 406; the plurality of vias 450 may be located in the first dam region 404, the second dam region 405, and the spacer region 406, or in the first dam region 404 and the second dam region 405. The embodiments of this disclosure do not limit this.

[0110] For example, in Figure 5AIn the example shown, the display substrate 40 also includes a power trace pattern (not shown) located in the display area. This power trace pattern can be disposed on the same layer as and connected to the second conductive pattern 440 to provide the required electrical signal to the second conductive pattern 440 and further to the semiconductor pattern 420. For example, the electrical signal can be a high voltage signal, or it can be a low voltage signal or a ground signal, etc. The embodiments of this disclosure are not limited in this regard.

[0111] For example, in some other examples, the power trace pattern may also be located in the opening periphery region 403 and on the side of the second conductive pattern 440 away from the substrate 410. The power trace pattern may be electrically connected to the second conductive pattern 440 by means of direct contact or via structure to provide corresponding electrical signals. The embodiments of this disclosure do not limit this.

[0112] For example, the material of the power trace pattern may include at least one conductive oxide material, such as inert tin oxide (ITO), inert zinc oxide (IZO), zinc oxide (ZnO), etc., or may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0113] For example, such as Figure 5A As shown, the display substrate 40 also includes a first encapsulation layer 481, which is located on the side of the second conductive pattern 440 away from the substrate 410.

[0114] For example, such as Figure 5A As shown, the display substrate 40 also includes a first cofferdam structure and a second cofferdam structure. The first cofferdam structure is located within a first cofferdam region 404, and the second cofferdam structure is located within a second cofferdam region 405. In the first cofferdam region 404, the first cofferdam structure is located on the side of the second conductive pattern 440 away from the substrate 410, and the first encapsulation layer 481 is located on the side of the first cofferdam structure away from the second conductive pattern 440 and covers the first cofferdam structure. In the second cofferdam region 405, the second cofferdam structure is located on the side of the second conductive pattern 440 away from the substrate 410, and the second cofferdam structure partially covers the second conductive pattern 440. The first encapsulation layer 481 is located on the side of the second conductive pattern 440 and the second cofferdam structure away from the substrate 410 and covers both the second conductive pattern 440 and the second cofferdam structure.

[0115] For example, such as Figure 5AAs shown, the maximum distance L1 between the surface of the first encapsulation layer 481 located in the first dam region 404 on the side facing away from the substrate 410 and the substrate 410 is greater than the maximum distance L3 between the surface of the first encapsulation layer 481 located in the spacer region 406 on the side facing away from the substrate 410 and the substrate 410. Similarly, the maximum distance L2 between the surface of the first encapsulation layer 481 located in the second dam region 405 on the side facing away from the substrate 410 and the substrate 410 is greater than the maximum distance L3 between the surface of the first encapsulation layer 481 located in the spacer region 406 on the side facing away from the substrate 410 and the substrate 410. Thus, the display substrate 40 forms a "groove" in the opening periphery region 403 through the first and second dam structures, effectively preventing substances such as moisture or oxygen from penetrating into the interior of the display device after encapsulation, thus avoiding adverse effects on the functional or structural layers of the display device.

[0116] For example, such as Figure 5A As shown, the maximum distance L1 between the surface of the first encapsulation layer 481 located in the first dam region 404 on the side facing away from the substrate 410 and the substrate 410 is smaller than the maximum distance L2 between the surface of the first encapsulation layer 481 located in the second dam region 405 on the side facing away from the substrate 410 and the substrate 410. Therefore, by using the first dam structure and the second dam structure at different heights from the substrate 410, it is possible to more effectively prevent substances such as moisture or oxygen from penetrating into the interior of the display device on the display substrate 40 after encapsulation, further avoiding adverse effects on the functional or structural layers of the display device.

[0117] For example, such as Figure 5A As shown, the display substrate 40 also includes a third insulating layer 463, a fourth insulating layer 464, and a fifth insulating layer 465 located in the peripheral region 403 of the opening, excluding the spacer region 406. The first dam structure includes a stack of the fourth insulating layer 464 and the fifth insulating layer 465, and the second dam structure includes a stack of the third insulating layer 463, the fourth insulating layer 464, and the fifth insulating layer 465.

[0118] In the first cofferdam area 404, the fourth insulating layer 464 is located on the side of the second conductive pattern 440 away from the substrate 410, the fifth insulating layer 465 is located on the side of the fourth insulating layer 464 away from the second conductive pattern 440, and the first encapsulation layer 481 is located on the side of the fifth insulating layer 465 away from the fourth insulating layer 464, and covers the surface of the fifth insulating layer 465 away from the substrate 410, at least one side surface of the fifth insulating layer 465, and at least one side surface of the fourth insulating layer 464.

[0119] In the second dam region 405, the third insulating layer 463 is located on the side of the second conductive pattern 440 away from the substrate 410, the fourth insulating layer 464 is located on the side of the third insulating layer 463 away from the second conductive pattern 440, the fifth insulating layer 465 is located on the side of the fourth insulating layer 464 away from the third insulating layer 463, and the first encapsulation layer 481 is located on the side of the fifth insulating layer 465 away from the fourth insulating layer 464, and covers the surface of the fifth insulating layer 465 away from the substrate 410, at least one side surface of the fifth insulating layer 465, at least one side surface of the fourth insulating layer 464, a portion of the surface of the third insulating layer 463 away from the substrate 410, and a portion of the side surface of the third insulating layer 463 away from the first dam region 404 and close to the first dam region 404. The third insulating layer 463 covers a portion of the surface of the second conductive pattern 440 away from the substrate 410.

[0120] For example, such as Figure 5A As shown, the display substrate 40 further includes a second encapsulation layer 482. The second encapsulation layer 482 is located on the side of the first encapsulation layer 481 away from the substrate 410 and covers the first encapsulation layer 481. For example, both the first encapsulation layer 481 and the second encapsulation layer 482 can be organic encapsulation layers. The stacking of the first encapsulation layer 481 and the second encapsulation layer 482 can further prevent substances such as water vapor or oxygen from penetrating into the interior of the display device of the display substrate 40.

[0121] For example, the materials of the third insulating layer 463, the fourth insulating layer 464, and the fifth insulating layer 465 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or organic insulating materials such as polyimide, polyphthalamide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of this disclosure do not specifically limit the materials of the third, fourth, and fifth insulating layers. For example, the materials of the third, fourth, and fifth insulating layers may be the same as each other, partially the same, or different from each other; the embodiments of this disclosure do not impose any limitations in this regard.

[0122] For example, the materials of the first encapsulation layer 461 and the second encapsulation layer 462 may include insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.

[0123] Figure 6 This is a schematic diagram of a partial planar structure within the opening periphery region of another display substrate provided in some embodiments of this disclosure, for example... Figure 6 This can be a schematic diagram showing the arrangement of multiple vias within the area surrounding the opening on the display substrate. It should be noted that, for ease of explanation, Figure 6Only the arrangement relationship between the semiconductor pattern 520, the first conductive pattern 530, and the second conductive pattern 540 is shown. The design of other structures or functional layers in the display substrate 50 can refer to conventional arrangement methods in the art, and will not be described in detail here. For example, Figure 6 The structure of the display substrate 50 shown, except for the arrangement of the first conductive pattern 530 and the via 550, is the same as that of the others. Figures 2A-2C The display substrates 20 shown are basically the same or similar, and will not be described in detail here.

[0124] For example, such as Figure 6 As shown, the first conductive pattern 530 includes multiple first trace groups 5301 arranged in parallel along the first direction R1. Each first trace group 5301 includes three first traces 531 arranged in parallel along the first direction R1. Multiple vias 550 are located between adjacent first trace groups 5301 in the first direction R1. Therefore, by arranging the multiple vias 550 in the first direction R1 at intervals of three first traces 531, the density of the vias 550 in the area surrounding the opening can be reduced, and the overall size required by the multiple first traces 531 in the multiple first trace groups 5301 in the first direction R1 can be reduced. Thus, by optimizing the arrangement of the vias 550 in the area surrounding the opening, capacitors can be formed between the semiconductor pattern 520 and the second conductive pattern 540 and the first traces 531 to compensate for the electrical signal transmission effect, while simultaneously reducing the size required by the area surrounding the opening in the first direction R1. This facilitates the design of a narrow bezel on the display substrate 50.

[0125] It should be noted that the arrangement of the multiple vias 550 between adjacent first trace groups 5301 can be referred to the corresponding description in the above embodiment regarding the display substrate 20, and will not be repeated here.

[0126] For example, in the display substrate 50 provided in the embodiments of this disclosure, a row of vias 550 arranged along the extension direction of the first trace 531 (e.g., the second direction R2) is provided between adjacent first trace groups 5301 in the first direction R1; while in some other embodiments of this disclosure, multiple rows of vias 550 arranged along the extension direction of the first trace 531, such as two rows or three rows, may also be provided between adjacent first trace groups 5301 in the first direction R1, that is, multiple vias 550 can be arranged in an array between adjacent first trace groups 5301, and the embodiments of this disclosure do not limit this.

[0127] It should be noted that in some other embodiments of this disclosure, each first trace group of the first conductive pattern of the display substrate may also include more first traces arranged in parallel along the first direction R1. For example, each first trace group may also include 4 or 5 first traces arranged in parallel along the first direction R1. The embodiments of this disclosure do not limit this.

[0128] For example, in some embodiments of this disclosure, the display substrate further includes a plurality of pixel units located in the display area. Each pixel unit includes a pixel driving circuit located on the substrate, the pixel driving circuit including a thin-film transistor and a storage capacitor; the thin-film transistor includes a gate, an active layer, a source, and a drain; the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode; a semiconductor pattern is disposed on the same layer as the active layer, a second conductive pattern is disposed on the same layer as the source and drain, and the first conductive pattern is disposed on the same layer as at least one of the second capacitor electrode, the gate, and the first capacitor electrode. This simplifies the fabrication process of the display substrate and reduces its fabrication cost.

[0129] For example, in some embodiments of the display substrate provided in this disclosure, the gate electrode and the first capacitor electrode may be disposed on the same layer, and the second capacitor electrode and the first conductive pattern may be disposed on the same layer. Alternatively, the first conductive pattern may also be disposed on the same layer as the gate electrode and the first capacitor electrode; or, a portion of the first conductive pattern may be disposed on the same layer as the second capacitor electrode, and another portion of the first conductive pattern may be disposed on the same layer as the gate electrode and the first capacitor electrode, that is, the first conductive pattern includes two alternately formed portions, and the embodiments of this disclosure do not limit this.

[0130] It should be noted that, in the embodiments disclosed herein, "same-layer configuration" means that two functional layers or structural layers are formed on the same layer and with the same material in the layered structure of the display substrate. That is, in the manufacturing process, the two functional layers or structural layers can be formed from the same material layer, and the required pattern and structure can be formed through the same patterning process. For example, the material layer can be formed first, and then the material layer can be formed through the patterning process.

[0131] For example, in some embodiments of this disclosure, the first traces in a plurality of first trace groups of a first conductive pattern are configured to transmit scan signals for a pixel driving circuit, respectively.

[0132] For example, when the first trace and the signal line for transmitting the scan signal of the pixel driving circuit in the display area are formed on the same layer, the first trace can be connected to the signal line on the same layer to realize signal transmission; or, when the first trace and the signal line for transmitting the scan signal of the pixel driving circuit in the display area are located on different layers, the first trace can be electrically connected to the signal line through, for example, a via structure to realize signal transmission. The embodiments of this disclosure do not limit this.

[0133] For example, in some embodiments of this disclosure, the pixel unit further includes a light-emitting element, which is located on the side of the pixel driving circuit away from the substrate and is electrically connected to the pixel driving circuit, which is configured to drive the light-emitting element to operate.

[0134] The following is based on Figure 5A and Figure 5B Taking the cross-sectional structure of the opening peripheral region 403 of the display substrate 40 shown as an example, the display area of ​​the display substrate provided in this embodiment will be described.

[0135] Figure 7A This is a schematic diagram of a partial cross-sectional structure of a display substrate provided in some embodiments of this disclosure. Figure 7B This is a schematic diagram of a partial cross-sectional structure of another display substrate provided in some embodiments of this disclosure. For example, Figure 7A and Figure 7B The portion of the opening periphery region 703 of the display substrate 70 shown is respectively with Figure 5A and Figure 5B The portion of the opening periphery region 403 of the display substrate 40 shown is basically the same or similar, and will not be described in detail here.

[0136] It should be noted that, in Figure 7A and Figure 7B In the embodiments shown, the display areas 701 of the display substrate 70 are substantially the same or similar, and will be described below as follows: Figure 7A Taking the structure shown in the figure as an example, the display substrate 70 will be described. Figure 7B The structure shown can be referenced from... Figure 7A The corresponding description will not be repeated here.

[0137] For example, such as Figure 7A As shown, the display substrate 70 also includes pixel units located in the display area 701 for functions such as light emission driving and control. The pixel unit includes a pixel driving circuit 7120, a first planarization layer 7150, and a light-emitting element 7140 located on the substrate 710.

[0138] For example, the pixel driving circuits 7120 in the multiple rows of pixel units located on the left and right sides of the opening in the display area 701 can be electrically connected through the first conductive pattern 730 (e.g., multiple first traces 731 in the first conductive pattern 730) to transmit one or more electrical signals for the pixel driving circuits 7120, such as gate scan signals, light emission control signals, reset signals, etc.

[0139] For example, a first trace 731 can be provided for each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 to transmit one of the above-mentioned electrical signals. For example, the gate lines of each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 can be electrically connected through the first trace 731 to transmit the gate scan signal. Alternatively, multiple first traces 731 can be provided for each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 to transmit the above-mentioned multiple electrical signals respectively. For example, the gate lines and light emission control lines of each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 can be electrically connected through the first trace 731 to transmit the gate scan signal and the light emission control signal respectively. The embodiments of this disclosure do not limit this.

[0140] For example, by setting a semiconductor pattern 720 (e.g., multiple conductive blocks 721 in the semiconductor pattern 720) below the first conductive pattern 730, capacitance can be formed between the multiple conductive blocks 721 and the multiple first traces 731, thereby increasing the transmission load of the first traces 731 and compensating for the electrical signal transmission effect of the first traces 731. Thus, the display effect of the pixel units located on the left and right sides of the opening in the display area 701 can be kept consistent with the display effect of other pixel units in the display area 701, avoiding or reducing display abnormalities at different gray levels, thereby improving the display effect of the display substrate 70.

[0141] For example, the semiconductor pattern 720 is electrically connected to the second conductive pattern 740 via a via 750 and further electrically connected to a power trace pattern (not shown). For example, the power trace pattern can be configured to receive low-voltage signals (e.g., a cathode signal or a ground signal provided to the light-emitting element 7140) or high-voltage signals, thereby applying corresponding electrical signals to the second conductive pattern 740 and the plurality of conductive blocks 721 in the semiconductor pattern 720. This allows the first trace 731, which transmits electrical signals such as a gate scan signal, to form capacitances with the conductive blocks 721 and the second conductive pattern 740 respectively, achieving a compensation effect.

[0142] For example, in Figure 7A and Figure 7B In the embodiment shown, the power trace pattern can be located in the display area 701 and disposed on the same layer as the second conductive pattern 740, thereby enabling the second conductive pattern 740 to be connected on the same layer as the power trace pattern to receive the corresponding electrical signal.

[0143] In the following embodiment of the present disclosure, a first trace 731 is provided for each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 to transmit gate scan signals (that is, the gate lines of each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 are electrically connected through the first trace 731 to transmit gate scan signals), and the display substrate 70 will be described in conjunction with the specific structure of the pixel driving circuit 7120.

[0144] Figure 8 This is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided in some embodiments of the present disclosure. Figures 9A-9E This is a schematic diagram of each layer of a pixel driving circuit in a display substrate provided for some embodiments of this disclosure. For example, Figure 7A and Figure 7B For including Figure 8 and Figure 9A This is a schematic diagram of a partial cross-sectional structure of the display substrate 70 showing the pixel driving circuit 7120. It should be noted that... Figure 8 and Figure 9A The specific structure of the pixel driving circuit 7120 shown is merely illustrative, and the embodiments of this disclosure include, but are not limited to, this.

[0145] In some embodiments, such as Figure 8 As shown, the pixel driving circuit 7120 includes multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7, multiple signal lines connected to the multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cst. The multiple signal lines include a gate line GL, a light emission control line EM, an initialization line RL, a data line DAT, and a first power supply line VDD. The gate line GL may include a first gate line GLn and a second gate line GLn-1. For example, the first gate line GLn can be used to transmit a gate scan signal, and the second gate line GLn-1 can be used to transmit a reset signal. The light emission control line EM can be used to transmit a light emission control signal. Thus, the pixel driving circuit 7120 is a pixel driving circuit of 7T1C.

[0146] It should be noted that the embodiments disclosed herein include, but are not limited to, the pixel driving circuit 7120 may also adopt other types of circuit structures, such as 7T2C structure or 9T2C structure, etc., and the embodiments disclosed herein do not limit this.

[0147] For example, the first gate line GLn of each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 can be electrically connected through the first trace 731 to transmit the gate scan signal, thereby achieving the compensation effect of the gate scan signal.

[0148] For example, since the first trace 731 and the first gate line GLn are located in different layers relative to the substrate 710, the first trace 731 can be electrically connected to the first gate line GLn through, for example, via structures (e.g., jumper connections) to transmit the corresponding gate scan signal.

[0149] For example, such as Figure 8 As shown, the first gate G1 of the first thin-film transistor T1 is electrically connected to the third drain D3 of the third thin-film transistor T3 and the fourth drain D4 of the fourth thin-film transistor T4. The first source S1 of the first thin-film transistor T1 is electrically connected to the second drain D2 of the second thin-film transistor T2 and the fifth drain D5 of the fifth thin-film transistor T5. The first drain D1 of the first thin-film transistor T1 is electrically connected to the third source S3 of the third thin-film transistor T3 and the sixth source S6 of the sixth thin-film transistor T6.

[0150] For example, such as Figure 8 As shown, the second gate G2 of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive the gate scan signal, the second source S2 of the second thin film transistor T2 is configured to be electrically connected to the data line DAT to receive the data signal, and the second drain D2 of the second thin film transistor T2 is electrically connected to the first source S1 of the first thin film transistor T1.

[0151] For example, such as Figure 8 As shown, the third gate G3 of the third thin-film transistor T3 is configured to be electrically connected to the first gate line GLn, the third source S3 of the third thin-film transistor T3 is electrically connected to the first drain electrode D1 of the first thin-film transistor T1, and the third drain D3 of the third thin-film transistor T3 is electrically connected to the first gate G1 of the first thin-film transistor T1.

[0152] For example, such as Figure 8 As shown, the fourth gate G4 of the fourth thin-film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal, the fourth source S4 of the fourth thin-film transistor T4 is configured to be electrically connected to the initialization line RL to receive an initialization signal, and the fourth drain D4 of the fourth thin-film transistor T4 is electrically connected to the first gate G1 of the first thin-film transistor T1.

[0153] For example, such as Figure 8 As shown, the fifth gate G5 of the fifth thin-film transistor T5 is configured to be electrically connected to the light-emitting control line EM to receive the light-emitting control signal, the fifth source S5 of the fifth thin-film transistor T5 is configured to be electrically connected to the first power supply line VDD to receive the first power supply signal, and the fifth drain D5 of the fifth thin-film transistor T5 is electrically connected to the first source S1 of the first thin-film transistor T1.

[0154] For example, such as Figure 8As shown, the sixth gate G6 of the sixth thin-film transistor T6 is configured to be electrically connected to the light-emitting control line EM to receive the light-emitting control signal, the sixth source S6 of the sixth thin-film transistor T6 is electrically connected to the first drain D1 of the first thin-film transistor T1, and the sixth drain D6 of the sixth thin-film transistor T6 is electrically connected to the first display electrode (e.g., anode) of the light-emitting element 7140.

[0155] For example, such as Figure 8 As shown, the seventh gate G7 of the seventh thin-film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal, the seventh source S7 of the seventh thin-film transistor T7 is electrically connected to the first display electrode (e.g., anode) of the light-emitting element 7140, and the seventh drain D7 of the seventh thin-film transistor T7 is configured to be electrically connected to the initialization line RL to receive an initialization signal. For example, the seventh drain D7 of the seventh thin-film transistor T7 can be connected to the fourth source S4 of the fourth thin-film transistor T4 to achieve electrical connection with the initialization line RL.

[0156] For example, such as Figure 8 As shown, the storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2. The second capacitor electrode CE2 is electrically connected to the first power line VDD, and the first capacitor electrode CE1 is electrically connected to the first gate G1 of the first thin-film transistor T1 and the third drain D3 of the third thin-film transistor T3.

[0157] For example, such as Figure 8 As shown, the second display electrode (e.g., cathode) of the light-emitting element 7140 is electrically connected to the second power line VSS.

[0158] It should be noted that one of the first power line VDD and the second power line VSS is a high-voltage power line, and the other is a low-voltage power line. In such cases... Figure 10 In the illustrated embodiment, the first power line VDD provides a constant first voltage, which is a positive voltage; while the second power line VSS provides a constant second voltage, which can be a negative voltage, etc. For example, in some examples, the second voltage can be ground voltage.

[0159] For example, the power trace pattern may include the first power line VDD and / or the second power line VSS, or may be configured to be electrically connected to the first power line VDD and / or the second power line VSS. The embodiments of this disclosure do not limit this.

[0160] For example, such as Figure 10As shown, the first power lines VDD in the multiple pixel driving circuits 7120 can be connected to each other. For example, in the extension direction of the first power line VDD, multiple first power lines VDD are connected to each other to form a region VDDR that can transmit electrical signals to form one pole of a capacitor. This can not only facilitate the storage of electrical signals, but also reduce the voltage drop of electrical signals during transmission.

[0161] It should be noted that, Figure 9A The layers of the pixel driving circuit 7120 shown are connected to... Figure 9A The layers of the pixel driving circuit 7120 shown are basically the same or similar; please refer to the section on... Figure 10 The corresponding descriptions in the illustrated embodiments will not be repeated here.

[0162] It should be noted that, for the sake of clarity and conciseness, Figure 9A Only three pixel driving circuits 7120 are shown to illustrate the connection relationship between the multiple first power lines VDD in the multiple pixel driving circuits 7120, but this does not constitute a limitation of this disclosure.

[0163] It should be noted that the reset signal and the initialization signal mentioned above can be the same signal.

[0164] For example, the power trace pattern of the display substrate 70 can be configured to provide the aforementioned first voltage or second voltage, thereby applying the first voltage or second voltage to the second conductive pattern 740 electrically connected to the power trace pattern and the semiconductor pattern 720 electrically connected to the second conductive pattern 740. This allows the first trace 731 electrically connected to the first gate line GLn and transmitting the gate scan signal to form capacitances between the conductive blocks 721 in the second conductive pattern 740 and the semiconductor pattern 720, respectively, to achieve a compensation effect.

[0165] It should be noted that, according to their characteristics, transistors can be divided into N-type transistors and P-type transistors. For clarity, the embodiments of this disclosure use P-type transistors (e.g., P-type MOS transistors) as an example to illustrate the technical solutions of this disclosure. That is, in the description of this disclosure, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors. However, the transistors in the embodiments of this disclosure are not limited to P-type transistors. Those skilled in the art can also use N-type transistors (e.g., N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of this disclosure according to actual needs.

[0166] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, the source and drain of all or some of the transistors can be interchanged as needed.

[0167] In some embodiments, such as Figure 8 As shown, the pixel driving circuit 7120 includes the aforementioned thin-film transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, a first gate line GLn, a second gate line GLn-1 connected to the multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7, an emission control line EM, an initialization line RL, a data line DAT, and a first power supply line VDD. Below, in conjunction with... Figures 9A-9E and Figure 9A The structure of the pixel driving circuit 7120 is described.

[0168] For example, Figure 9B This is a schematic diagram showing the stacking position relationship of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer of the pixel driving circuit 7120.

[0169] Figure 9B The semiconductor layer of the pixel driving circuit 7120 is shown. For example, Figure 8 The semiconductor layer shown can be Figure 9B The active layer 7122 is shown. Figure 7A As shown, the semiconductor layer can be formed by patterning semiconductor materials. The semiconductor layer can be used to fabricate the active layers of the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7. Each active layer may include a source region, a drain region, and a channel region between the source and drain regions. For example, the semiconductor layer can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.

[0170] In some embodiments of the display substrate provided in this disclosure, a gate insulating layer (e.g., a gate insulating layer) is formed on the semiconductor layer described above. Figure 7B and Figures 9A-9E The gate insulating layer 7128 shown is Figure 9C (Not shown in the image) is used to protect the aforementioned semiconductor layer.

[0171] Figure 9CThe first conductive layer of the pixel driving circuit 7120 is shown. For example, as... Figure 9B As shown, the first conductive layer of the pixel driving circuit 7120 is disposed on the gate insulating layer, thereby connecting with... Figure 9C The semiconductor layer shown is insulating. The first conductive layer may include the first capacitor electrode CE1 of the storage capacitor Cst, the first gate line GLn, the second gate line GLn-1, the light-emitting control line EM, and the gates of the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7 (e.g., the first gate G1, the second gate G2, the third gate G3, the fourth gate G4, the fifth gate G5, the sixth gate G6, and the seventh gate G7 mentioned above). Figure 7A As shown, the gates of the second thin-film transistor T2, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7 are the overlapping portions of the first gate line GLn, the second gate line GLn-1, and the semiconductor layer. The third thin-film transistor T3 can be a dual-gate thin-film transistor, with one gate being the overlapping portion of the first gate line GLn and the semiconductor layer, and the other gate being a protrusion extending from the first gate line GLn. The gate of the first thin-film transistor T1 can be the first capacitor electrode CE1. The fourth thin-film transistor T4 can be a dual-gate thin-film transistor, with its two gates being the overlapping portions of the second gate line GLn-1 and the semiconductor layer, respectively.

[0172] In some embodiments of the display substrate provided in this disclosure, a first interlayer insulating layer (e.g., ...) is formed on the first conductive layer described above. Figure 7B and Figures 9A-9E The first interlayer insulating layer 7129 shown is shown. Figure 9D (Not shown in the image) is used to protect the first conductive layer described above.

[0173] Figure 9D The second conductive layer of the pixel driving circuit 7120 is shown. For example, as... Figure 7A As shown, the second conductive layer of the pixel driving circuit 7120 includes a second capacitor electrode CE2 of the storage capacitor Cst and an initialization line RL. The second capacitor electrode CE2 at least partially overlaps with the first capacitor electrode CE1 to form the storage capacitor Cst.

[0174] In some embodiments, the second conductive layer may further include a first light-shielding portion 791 and a second light-shielding portion 792. The orthographic projection of the first light-shielding portion 791 onto the substrate 710 covers the active layer between the active layer of the second thin-film transistor T2, the drain of the third thin-film transistor T3, and the drain of the fourth thin-film transistor T4, thereby preventing external light from affecting the active layers of the second thin-film transistor T2, the third thin-film transistor T3, and the fourth thin-film transistor T4. The orthographic projection of the second light-shielding portion 792 onto the substrate 710 covers the active layer between the two gates of the third thin-film transistor T3, thereby preventing external light from affecting the active layer of the third thin-film transistor T3. The first light-shielding portion 791 may be integrally formed with the second light-shielding portion 792 of an adjacent pixel driving circuit and is electrically connected to the first power line VDD through a via penetrating the second interlayer insulating layer.

[0175] In some embodiments of the display substrate provided in this disclosure, a second interlayer insulating layer (e.g., ...) is formed on the second conductive layer described above. Figure 7B and Figures 9A-9E The second interlayer insulating layer 7131 shown is Figure 9E (Not shown in the image) is used to protect the second conductive layer described above.

[0176] Figure 9E The third conductive layer of the pixel driving circuit 7120 is shown. For example, as... Figure 9A As shown, the third conductive layer of the pixel driving circuit 7120 includes the data line DAT and the first power line VDD. Combined with... Figure 9E and Figure 7A As shown, the data line DAT is connected to the source region of the second thin-film transistor T2 in the semiconductor layer through at least one via (e.g., via VH1) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power line VDD is connected to the source region of the corresponding fifth thin-film transistor T5 in the semiconductor layer through at least one via (e.g., via VH2) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power line VDD is connected to the second capacitor electrode CE2 in the second conductive layer through at least one via (e.g., via VH3) in the second interlayer insulating layer.

[0177] For example, the third conductive layer further includes a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3. One end of the first connection portion CP1 is connected to the drain region of the corresponding third thin-film transistor T3 in the semiconductor layer through at least one via (e.g., via VH4) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The other end of the first connection portion CP1 is connected to the gate of the first thin-film transistor T1 in the first conductive layer through at least one via (e.g., via VH5) in the first interlayer insulating layer and the second interlayer insulating layer. One end of the second connection portion CP2 is connected to the initialization line RL through one via (e.g., via VH6) in the second interlayer insulating layer. The other end of the second connection portion CP2 is connected to the source region of the seventh thin-film transistor T7 and the source region of the fourth thin-film transistor T4 in the semiconductor layer through at least one via (e.g., via VH7) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The third connection portion CP3 is connected to the drain region of the sixth thin-film transistor T6 in the semiconductor layer through at least one via (e.g., via VH8) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.

[0178] In some embodiments of the display substrate provided in this disclosure, a protective layer (e.g., ...) is formed on the third conductive layer described above. Figure 7B and Figures 9A-9E The first planarization layer 7150 shown is... Figure 8 (Not shown in the image) is used to protect the aforementioned third conductive layer. The first display electrode (e.g., anode) of the light-emitting element 7140 in the pixel unit may be disposed on the protective layer.

[0179] For example, the first trace 731 in the first conductive pattern 730 can be disposed in the same layer as the second capacitor electrode CE2 in the second conductive layer, and the first trace 731 can be connected to the first gate line GLn in the first conductive layer through at least one via in the first interlayer insulating layer.

[0180] For example, combining Figure 9A and Figure 7A The pixel driving circuit 7120 shown is... Figure 7B and Figure 8 For including Figure 9A and Figure 7A This is a schematic diagram of a partial cross-sectional structure of the display substrate 70 of the pixel driving circuit 7120 shown.

[0181] In some embodiments, such as Figure 7B and Figure 9B As shown, the pixel unit also includes a buffer layer 7121 located on the substrate 710, and the pixel driving circuit 7120 may include an active layer 7122 located on the buffer layer 7121 (e.g., Figure 9CThe semiconductor layer of the pixel driving circuit 7120 shown), the gate insulating layer 7128 located on the side of the active layer 7122 away from the substrate 710, and the gate 7130 located on the gate insulating layer 7128 (e.g., located on the side away from the substrate 710). Figure 7A The pixel driving circuit 7120 shown includes a first conductive layer, a first interlayer insulating layer 7129 located on the side of the gate 7130 away from the substrate 710, a second interlayer insulating layer 7131 located on the first interlayer insulating layer 7129, and a source 7125 and a drain 7126 located on the second interlayer insulating layer 7131.

[0182] For example, the semiconductor pattern 720 (e.g., a plurality of conductive blocks 721 in the semiconductor pattern 720) can be disposed on the same layer as the active layer 7122. For example, the first insulating layer 761 can be disposed on the same layer as the first interlayer insulating layer 7129, and the second insulating layer 762 can be disposed on the same layer as the second interlayer insulating layer 7131. For example, the source electrode 7125 and the drain electrode 7126 can be disposed on the same layer as the second conductive pattern 740. For example, the above-mentioned co-located structural or functional layers can be formed on the same layer in the fabrication process, for example, by using the same material layer to form them through a patterning process, thereby simplifying the fabrication process of the display substrate 70 and reducing the fabrication cost of the display substrate 70.

[0183] For example, the buffer layer 7121 serves as a transition layer, which can prevent harmful substances in the substrate 710 from penetrating the interior of the display substrate 710, and can also increase the adhesion of the film layer in the display substrate 710 to the substrate 710. For example, the material of the buffer layer 7121 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. For example, one or more of the materials of the first interlayer insulating layer 7129, the second interlayer insulating layer 7131, and the gate insulating layer 7128 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The materials of the first interlayer insulating layer 7129, the second interlayer insulating layer 7131, and the gate insulating layer 7128 may be the same or different from each other, and the embodiments disclosed herein are not limited in this respect.

[0184] For example, such as Figure 7B and Figure 7A As shown, the active layer 7122 may include a source region 7123, a drain region 7124, and a channel region located between the source region 7123 and the drain region 7124. Vias are provided in the first interlayer insulating layer 7129, the second interlayer insulating layer 7131, and the gate insulating layer 7128 to expose the source region 7123 and the drain region 7124. Sources 7125 and 7126 are electrically connected to the source region 7123 and the drain region 7124, respectively, through vias. The gate 7130 overlaps with the channel region located between the source region 7123 and the drain region 7124 in the active layer 7122 in a direction perpendicular to the substrate 710.

[0185] For example, the first planarization layer 7150 is located above the source 7125 and the drain 7126 to planarize the surface of the pixel driving circuit 7120 away from the substrate 710. The first planarization layer 7150 can planarize the uneven surface caused by the pixel driving circuit 7120, and thus prevent defects in the light-emitting element 7140 caused by the bumps and dips caused by the pixel driving circuit 7120.

[0186] For example, the first planarization layer 7150 can be disposed in the same layer as the third insulating layer 763 in the opening peripheral region 703. Therefore, the two can be formed in the same layer during the manufacturing process, for example, by using the same material layer through a patterning process.

[0187] For example, the active layer 7122 may be made of polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The gate 7130 may be made of a metallic or alloy material, such as a single-layer or multi-layer metal structure formed of molybdenum, aluminum, and titanium, for example, a multi-layer structure being a multi-metal stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Al / Ti / Al)). The source 7125 and drain 7126 may be made of metallic or alloy materials, such as a single-layer or multi-layer metal structure formed of molybdenum, aluminum, and titanium, for example, a multi-layer structure being a multi-metal stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Al / Ti / Al)). The embodiments of this disclosure do not specifically limit the materials of each structural or functional layer.

[0188] For example, such as Figure 7B and Figure 7A As shown, vias are formed in the first planarization layer 7150 to expose the source 7125 or the drain 7126. Figure 7B and Figure 7A (The diagram shows the case where the drain 7126 is exposed). A light-emitting element 7140 is formed on the first planarization layer 7150. The light-emitting element 7140 includes a first display electrode 7141 (e.g., an anode), a light-emitting layer 7142, and a second display electrode 7143 (e.g., a cathode). The first display electrode 7141 of the light-emitting element 7140 is electrically connected to the drain 7126 through a via in the first planarization layer 7150. A pixel defining layer 7144 is formed on the first display electrode 7141. The pixel defining layer 7144 includes a plurality of openings to define a plurality of pixel units. Each of the plurality of openings exposes the first display electrode 7141, and the light-emitting layer 7142 is disposed in the plurality of openings of the pixel defining layer 7144. The second display electrode 7143 may, for example, be disposed in part or the entire display area 701, so that it can be formed over the entire surface during the fabrication process.

[0189] For example, the first display electrode 7141 can be disposed in the same layer as the power supply trace pattern. Therefore, the two can be formed in the same layer during the fabrication process, for example, by using the same material layer through a patterning process.

[0190] For example, the pixel defining layer 7144 can be disposed in the same layer as the fourth insulating layer 764 in the opening peripheral region 703. Therefore, the two can be formed in the same layer during the fabrication process, for example, by using the same material layer through a patterning process.

[0191] For example, the first display electrode 7141 may include a reflective layer, and the second display electrode 7143 may include a transparent layer or a translucent layer. Thus, the first display electrode 7141 can reflect light emitted from the light-emitting layer 7142, and this portion of the light is emitted into the external environment through the second display electrode 7143, thereby providing a light emissivity. When the second display electrode 7143 includes a translucent layer, some of the light reflected by the first display electrode 7141 is reflected again by the second display electrode 7143, thus forming a resonant structure between the first and second display electrodes 7141, thereby improving the light emissivity.

[0192] For example, the material of the first display electrode 7141 may include at least one transparent conductive oxide material, including inert tin oxide (ITO), inert zinc oxide (IZO), zinc oxide (ZnO), etc. Furthermore, the first display electrode 7141 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0193] For example, in the case where the display substrate 70 is an organic light-emitting diode (OLED) display substrate, the light-emitting layer 7142 may include small molecule organic materials or polymer molecule organic materials, and may be a fluorescent light-emitting material or a phosphorescent light-emitting material, emitting red light, green light, blue light, or white light, etc. Furthermore, depending on different actual needs, in different examples, the light-emitting layer 7142 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0194] In the case where the display substrate 70 is a quantum dot light-emitting diode (QLED) display substrate, the light-emitting layer 7142 may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, etc., and the particle size of the quantum dots is 2-20nm.

[0195] For example, the second display electrode 7143 may include various conductive materials. For example, the second display electrode 7143 may include metallic materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).

[0196] For example, the material of the pixel defining layer 7144 may include organic insulating materials such as polyimide, polyphthalamide, polyamide, acrylic resin, benzocyclobutene or phenolic resin, or inorganic insulating materials such as silicon oxide or silicon nitride. The embodiments disclosed herein do not limit this.

[0197] For example, such as Figure 7B and Figure 7A As shown, the display substrate 70 also includes an encapsulation layer 7160 located on the light-emitting element 7140. The encapsulation layer 7160 seals the light-emitting element 7140, thereby reducing or preventing degradation of the light-emitting element 7140 caused by moisture and / or oxygen in the environment. The encapsulation layer 7160 can be a single-layer structure or a composite layer structure, which includes a structure of stacked inorganic and organic layers. For example, the encapsulation layer 7160 may include a first inorganic encapsulation layer 7161 (i.e., the first encapsulation layer 781), a first organic encapsulation layer 7162, and a second inorganic encapsulation layer 7163 (i.e., the second encapsulation layer 782) disposed sequentially.

[0198] For example, the material of the encapsulation layer 7160 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc. The material of the first organic encapsulation layer 7162 may be a polymer material containing a desiccant or a polymer material that can block moisture, such as a polymer resin, which can planarize the surface of the display area 701 of the display substrate 70 and relieve the stress of the first inorganic encapsulation layer 7161 and the second inorganic encapsulation layer 7163. It may also include water-absorbing materials such as desiccants to absorb water, oxygen, and other substances that have penetrated into the interior.

[0199] For example, such as Figure 7B and Figure 9E As shown, the pixel driving circuit 7120 may also include a first display metal layer 7127 (e.g., Figure 7A The third conductive layer of the pixel driving circuit 7120 shown). The first display metal layer 7127 includes Figure 7B and Figure 7A The source 7125 and drain 7126 in the thin-film transistor of the pixel driving circuit 7120 shown may also include electrodes in other circuits not shown.

[0200] For example, such as Figure 7B and Figure 8 As shown, the display substrate 70 also includes a storage capacitor 7170 (e.g., Figure 9A and Figure 8 The storage capacitor Cst shown in the figure may include a first capacitor electrode 7171 (e.g., Figure 9C and Figure 8The storage capacitor Cst shown has a first capacitor electrode CE1 and a second capacitor electrode 7172 (e.g., ...). Figure 9D and Figure 9C The second capacitor electrode CE2 of the storage capacitor Cst shown. The first capacitor electrode 7171 is disposed between the gate insulating layer 7128 and the first interlayer insulating layer 7129 (e.g., located at...). Figure 9D The pixel driving circuit 7120 shown has a first conductive layer, and the second capacitor electrode 7172 is disposed between the first interlayer insulating layer 7129 and the second interlayer insulating layer 7131 (e.g., located in the first conductive layer). Figures 2A-2C The second conductive layer of the pixel driving circuit 7120 shown. The first capacitor electrode 7171 and the second capacitor electrode 7172 are stacked and at least partially overlap in a direction perpendicular to the substrate 710. The first capacitor electrode 7171 and the second capacitor electrode 7172 use the first interlayer insulating layer 7129 as the dielectric material to form the storage capacitor 7170.

[0201] For example, the second capacitor electrode 7172 can be disposed in the same layer as the first conductive pattern 730 in the peripheral region 703 of the opening. Therefore, the two can be formed in the same layer during the fabrication process, for example, by using the same material layer through a patterning process, thereby simplifying the fabrication process of the display substrate 70 and reducing the fabrication cost of the display substrate 70.

[0202] For example, in some other embodiments of this disclosure, the first capacitor electrode of the storage capacitor is still disposed on the same layer as the gate, while the second capacitor electrode of the storage capacitor is disposed on the same layer as the source and drain of the thin film transistor. Thus, the first capacitor electrode and the second capacitor electrode can use a stack of the first interlayer insulating layer and the second interlayer insulating layer as dielectric materials to form the storage capacitor.

[0203] For example, in some other embodiments of this disclosure, the first capacitor electrode of the storage capacitor is no longer disposed on the same layer as the gate, but is located between the first interlayer insulating layer and the second interlayer insulating layer, while the second capacitor electrode of the storage capacitor is disposed on the same layer as the source and drain of the thin film transistor. Thus, the first capacitor electrode and the second capacitor electrode use the second interlayer insulating layer as the dielectric material to form the storage capacitor.

[0204] It should be noted that, Figure 4 The display substrate 20 shown Figure 5A The display substrate 30 shown Figure 5B and Figure 7A The cross-sectional structure of the display area of ​​the display substrate 40 shown can also be adopted with... Figure 7B and ​ The display area 701 of the display substrate 70 shown has the same or similar structure, or other suitable structures may be used, and the embodiments disclosed herein are not limited thereto.

[0205] For example, the display substrates provided in the embodiments of this disclosure, such as display substrate 20, display substrate 30, display substrate 40, display substrate 50, and display substrate 70, can be organic light-emitting diode display substrates.

[0206] For example, the display substrate provided in the embodiments of this disclosure can also be a quantum dot light-emitting diode display substrate, an electronic paper display substrate, or other types of substrates with display functions. The embodiments of this disclosure do not limit this.

[0207] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, the method comprising: providing a substrate; forming a semiconductor pattern on the substrate; forming a first conductive pattern on the semiconductor pattern; and forming a second conductive pattern on the first conductive pattern. The display substrate includes a display area and a peripheral area surrounding the display area. The display area includes an opening, and the peripheral area includes an opening peripheral area at least partially located within the opening. The semiconductor pattern, the first conductive pattern, and the second conductive pattern are located in the opening peripheral area. The first conductive pattern is configured to transmit electrical signals for the display area. The first conductive pattern includes a plurality of first trace groups arranged side-by-side along a first direction. Each first trace group includes at least two first traces arranged side-by-side along the first direction. In a direction perpendicular to the substrate, the first traces are respectively spaced and insulated from the semiconductor pattern and the second conductive pattern to form a capacitor. The semiconductor pattern and the second conductive pattern are electrically connected through a plurality of vias disposed in the opening peripheral area, the plurality of vias being located between adjacent first trace groups in the first direction.

[0208] For example, in the method for fabricating a display substrate provided in some embodiments of this disclosure, forming a first conductive pattern on a semiconductor pattern includes: forming a first insulating layer on the semiconductor pattern, and forming the first conductive pattern on the first insulating layer. Forming a second conductive pattern on the first conductive pattern includes: forming a second insulating layer on the first conductive pattern, and forming the second conductive pattern on the second insulating layer. A plurality of vias are located at least within the first insulating layer and the second insulating layer, and at least penetrate both the first insulating layer and the second insulating layer.

[0209] For example, some embodiments of this disclosure provide a method for fabricating a display substrate that further includes forming a pixel driving circuit for pixel units on a substrate in the display area. The pixel driving circuit includes a thin-film transistor and a storage capacitor. The thin-film transistor includes a gate, an active layer, a source, and a drain. The storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode. A semiconductor pattern is disposed on the same layer as the active layer, a second conductive pattern is disposed on the same layer as the source and drain, and a first conductive pattern is disposed on the same layer as at least one of the second capacitor electrode, the gate, and the first capacitor electrode.

[0210] For example, the display substrates provided in the embodiments of this disclosure, such as the above-mentioned display substrate 20, display substrate 30, display substrate 40, display substrate 50 or display substrate 70, can be prepared by the display substrate preparation method provided in the embodiments of this disclosure.

[0211] The technical effects of the display substrate preparation method provided in this disclosure can be referred to the technical effects of the display substrate provided in the above-described embodiments, and will not be repeated here.

[0212] At least one embodiment of this disclosure also provides a display device, which includes the display substrate described in any embodiment of this disclosure, such as the display substrate 20, display substrate 30, display substrate 40, display substrate 50 or display substrate 70.

[0213] The structure, function, and technical effects of the display device provided in the embodiments of this disclosure can be referred to the corresponding description in the display substrate provided in the embodiments of this disclosure above, and will not be repeated here.

[0214] For example, the display device provided in the embodiments of this disclosure can be an organic light-emitting diode display device. Alternatively, the display device provided in the embodiments of this disclosure can also be a quantum dot light-emitting diode display device, an electronic paper display device, or other devices with display functions, or other types of devices. The embodiments of this disclosure do not limit this.

[0215] For example, the display device provided in the embodiments of this disclosure can be any product or component with display function, such as a display substrate, display panel, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc., and the embodiments of this disclosure do not limit this.

[0216] The following points need to be explained:

[0217] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0218] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements.

[0219] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0220] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising a display area and a peripheral area surrounding the display area; in, The display area includes an opening, and the surrounding area includes at least a portion of the opening periphery located within the opening; The display substrate includes a substrate and a semiconductor pattern, a first conductive pattern and a second conductive pattern located in the peripheral region of the opening. The semiconductor pattern is located on the substrate, the first conductive pattern is located on the side of the semiconductor pattern away from the substrate, and the second conductive pattern is located on the side of the first conductive pattern away from the semiconductor pattern. The first conductive pattern is configured to transmit electrical signals for the display area. The first conductive pattern includes a plurality of first trace groups arranged side-by-side along a first direction, the plurality of first trace groups including more than two first trace groups, and each first trace group including at least two first traces arranged side-by-side along the first direction. In a direction perpendicular to the substrate, the first trace is provided with insulation from the semiconductor pattern and the second conductive pattern to form a capacitor. The semiconductor pattern and the second conductive pattern are electrically connected through a plurality of vias disposed in the peripheral region of the opening, the plurality of vias being located between adjacent first trace groups in the first direction; In the plurality of first routing groups, there are areas where the vias are arranged in a substantially similar manner between adjacent first routing groups in the first direction; The spacing between adjacent first routing groups in the first direction is greater than the spacing between adjacent first routings in the first routing group in the first direction; The area surrounding the opening includes a first dam area, a second dam area, and a spacing area. The first dam area at least partially surrounds the display area, the spacing area at least partially surrounds the first dam area, and the second dam area at least partially surrounds the spacing area. The orthographic projections of the semiconductor pattern, the first conductive pattern, the second conductive pattern, and the plurality of vias on the substrate do not overlap with the first dam area, the spacing area, and the second dam area.

2. The display substrate according to claim 1, wherein, In the plurality of first routing groups, the spacing between adjacent first routing groups in the first direction is approximately the same.

3. The display substrate according to claim 1, wherein, In the plurality of first routing groups, the at least two first routing lines in each group are arranged in the same way in the first direction.

4. The display substrate according to claim 3, wherein, In each of the first routing groups, the spacing between adjacent first routings in the first direction is approximately the same.

5. The display substrate according to claim 1, wherein, The vias located on both sides of a first trace group in the first direction are arranged approximately symmetrically with respect to the first trace group along the extension direction of the first trace.

6. The display substrate according to claim 1, wherein, At least one row of vias is provided between adjacent first routing groups in the first direction, arranged along the extension direction of the first routing.

7. The display substrate according to claim 1, wherein, The semiconductor pattern includes a plurality of conductive blocks arranged side by side along a second direction, and the plurality of conductive blocks are electrically connected to the second conductive pattern through the plurality of vias. The second direction is different from the first direction.

8. The display substrate according to claim 7, wherein, The plurality of conductive blocks have approximately the same width in the second direction, and the spacing between adjacent conductive blocks in the second direction is approximately the same.

9. The display substrate according to claim 1, wherein, The second conductive pattern is continuously disposed in the area surrounding the opening.

10. The display substrate according to claim 1, further comprising a first insulating layer and a second insulating layer. in, The first insulating layer and the second insulating layer are located at least in the area surrounding the opening. The first insulating layer is located on the side of the semiconductor pattern away from the substrate, the first conductive pattern is located on the side of the first insulating layer away from the semiconductor pattern, the second insulating layer is located on the side of the first conductive pattern away from the first insulating layer, and the second conductive pattern is located on the side of the second insulating layer away from the first conductive pattern. The plurality of vias are located at least within the first insulating layer and the second insulating layer and at least penetrate the first insulating layer and the second insulating layer.

11. The display substrate according to claim 1, wherein, The display area includes a first display area and a second display area located on opposite sides of the opening. The first display area, the opening, and the second display area are arranged sequentially along the extension direction of the first trace. The first trace extends sequentially through the first display area, the area surrounding the opening, and the second display area to transmit electrical signals for the first display area and the second display area.

12. The display substrate according to claim 11, wherein, The display area also includes a third display area. The third display area is connected to one of the two opposite edges of the first display area in the first direction, and also to one of the two opposite edges of the second display area in the first direction; The display substrate includes a plurality of third traces located in the third display area. The plurality of third traces extend in the same direction as the first traces and are configured to transmit electrical signals for the third display area. The multiple third traces are arranged on the same layer as the first conductive pattern.

13. The display substrate according to claim 1, further comprising a power supply routing pattern, in, The power trace pattern is disposed on the same layer as the second conductive pattern, or is located on the side of the second conductive pattern away from the substrate. The power trace pattern is electrically connected to the second conductive pattern to provide an electrical signal.

14. The display substrate according to claim 13, wherein, The power trace pattern is located in the display area and is disposed on the same layer as the second conductive pattern. The power trace pattern is configured to provide a high-voltage signal.

15. The display substrate according to claim 1, further comprising a plurality of pixel units located in the display area. in, The pixel unit includes a pixel driving circuit located on the substrate, and the pixel driving circuit includes a thin film transistor and a storage capacitor; The thin-film transistor includes a gate, an active layer, a source, and a drain, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode. The semiconductor pattern is disposed on the same layer as the active layer, the second conductive pattern is disposed on the same layer as the source and the drain, and the first conductive pattern is disposed on the same layer as at least one of the second capacitor electrode, the gate and the first capacitor electrode.

16. The display substrate according to claim 15, wherein, The first traces in the plurality of first trace groups of the first conductive pattern are configured to transmit scan signals for the pixel driving circuit, respectively.

17. The display substrate according to claim 15, wherein, The pixel unit also includes a light-emitting element. The light-emitting element is located on the side of the pixel driving circuit away from the substrate and is electrically connected to the pixel driving circuit, which is configured to drive the light-emitting element to operate.

18. The display substrate according to claim 1, wherein, The first conductive pattern also includes at least one fourth trace. In a direction perpendicular to the substrate, the fourth trace is spaced and insulated from at least one of the semiconductor pattern and the second conductive pattern to form a capacitor.

19. A display device comprising a display substrate as claimed in any one of claims 1-18.

20. A method for preparing a display substrate, comprising: Provide substrates; A semiconductor pattern is formed on the substrate. A first conductive pattern is formed on the semiconductor pattern; as well as A second conductive pattern is formed on the first conductive pattern. The display substrate includes a display area and a peripheral area surrounding the display area. The display area includes an opening, and the surrounding area includes at least a portion of the area surrounding the opening within the opening. The semiconductor pattern, the first conductive pattern, and the second conductive pattern are located in the area surrounding the opening. The first conductive pattern is configured to transmit electrical signals for the display area. The first conductive pattern includes a plurality of first trace groups arranged side-by-side along a first direction, the plurality of first trace groups including more than two first trace groups, and each first trace group including at least two first traces arranged side-by-side along the first direction. In a direction perpendicular to the substrate, the first trace is provided with insulation from both the semiconductor pattern and the second conductive pattern to form a capacitor. The semiconductor pattern and the second conductive pattern are electrically connected through a plurality of vias disposed in the peripheral region of the opening, the plurality of vias being located between adjacent first trace groups in the first direction; In the plurality of first routing groups, there are areas where the vias are arranged in a substantially similar manner between adjacent first routing groups in the first direction; The spacing between adjacent first routing groups in the first direction is greater than the spacing between adjacent first routings in the first routing group in the first direction; The area surrounding the opening includes a first dam area, a second dam area, and a spacing area. The first dam area at least partially surrounds the display area, the spacing area at least partially surrounds the first dam area, and the second dam area at least partially surrounds the spacing area. The orthographic projections of the semiconductor pattern, the first conductive pattern, the second conductive pattern, and the plurality of vias on the substrate do not overlap with the first dam area, the spacing area, and the second dam area.

Images