Radar transceiver

Abstract

A radar transceiver having a transmitter including a phase shifter, comprising: a digital controller configured to provide a digital control signal indicative of a phase shift; a digital-to-analog converter configured to receive the digital control signal and provide an analog signal in accordance with the phase shift; the phase shifter configured to receive the analog signal and provide a phase-shifted output signal for transmission; a dummy load connected to receive the analog signal from the digital-to-analog converter and provide an analog output; a resistive network connected across the output of the dummy load; a test module configured to measure the analog output of the dummy load; and a controller module configured to control operation of the dummy load, the test module, and the digital controller during a self-test mode of operation by: enabling the dummy load; operating the digital controller to provide a series of digital control signals to the digital-to-analog converter; and operating the test module to measure the analog output of the dummy load to determine a linearity measurement of the digital-to-analog converter.

Description

Technical Field

[0001] This disclosure relates to a radar transceiver having a transmitter including a phase shifter. Background Technology

[0002] Phase rotators or phase shifters (PS) circuits are commonly used in communication systems, and more specifically, in transceivers. Particularly in radar systems, phase shifters can be placed in the transmitter path to achieve beamforming, which improves radar resolution. Summary of the Invention

[0003] According to a first aspect, a radar transceiver with a normal transmitter operation mode and a self-test operation mode is provided, the transceiver comprising:

[0004] A digital controller configured to provide digital control signals indicating phase shifts;

[0005] A digital-to-analog converter configured to receive the digital control signal and provide an analog signal according to the phase shift;

[0006] A phase shifter configured to receive the analog signal and provide a phase-shifted output signal for transmission;

[0007] A dummy load is connected to receive the analog signal from the digital-to-analog converter and provide an analog output;

[0008] A resistor network is connected across the output terminals of the dummy load.

[0009] A test module configured to measure the simulated output of the dummy load; and

[0010] The controller module is configured to control the operation of the dummy load, the test module, and the digital controller during the self-test operation mode by:

[0011] Enable the dummy load;

[0012] Operate the digital controller to provide a series of digital control signals to the digital-to-analog converter; and

[0013] The test module is operated to measure the analog output of the dummy load, thereby determining the linearity measurement of the digital-to-analog converter.

[0014] The dummy load can be a copy of the phase shifter.

[0015] The controller module can be configured to operate the test module to provide current through the resistor network and measure the resistance value of the resistor network before operating the digital controller.

[0016] The controller module can be configured to disable the dummy load during the normal transmitter operation mode.

[0017] The dummy load may include a first differential output connection and a second differential output connection, and the resistor network may include:

[0018] A first resistor is connected between the first differential output connection and the common node;

[0019] A second resistor is connected between the common node and the second differential output connection.

[0020] The test module can be configured to measure the voltage between any two of the first differential output connection and the second differential output connection and the common node.

[0021] The first resistor and the second resistor can be variable resistors.

[0022] During production self-test mode, the controller module can be configured to output and store a first digital code representing the linear measurement value of the digital-to-analog converter.

[0023] During the service self-test mode, the controller module can be configured to output a second digital code representing the linear measurement value of the digital-to-analog converter and compare the second digital code with a stored first digital code.

[0024] The transceiver can be configured to operate in the normal operating mode when the first output numeric code matches the second output numeric code.

[0025] If the first output numeric code does not match the second output numeric code, the transceiver can be configured to operate in fail-safe mode, the controller can output an error flag, and / or the controller can disable the operation of the transceiver.

[0026] If the dummy load is referred to as the first dummy load and the resistor network as the first resistor network, the transceiver may additionally include a second dummy load connected to receive the analog signal and output the baseband signal to the receiver module of the transceiver.

[0027] According to a second aspect, a method for testing a radar transceiver according to a first aspect is provided, the method comprising the controller module performing the following operations:

[0028] Enable the transceiver;

[0029] Operate the digital controller to provide digital control signals to the digital-to-analog converter;

[0030] The test module is operated to measure the output of the dummy load and provide a digital code as a linearity measurement of the digital-to-analog converter.

[0031] According to a third aspect, a computer program is provided, comprising instructions for causing a computer processor (i.e., a controller module) to execute the method according to the second aspect.

[0032] A computer program may be provided, which, when run on a computer, causes the computer to configure the computer to include any device, controller, sensor, filter, or means disclosed herein, or to perform any of the methods disclosed herein. As a non-limiting example, the computer program may be a software implementation, and the computer may be considered any suitable hardware, including digital signal processors, microcontrollers, and implementations in read-only memory (ROM), erasable programmable read-only memory (EPROM), or electrically erasable programmable read-only memory (EEPROM). The software implementation may be an assembler.

[0033] The computer program may be provided on a non-transitory computer-readable medium, which may be a physical computer-readable medium, such as an optical disc or storage device, or may be embodied as a transient signal. This transient signal may be a network download, including an Internet download.

[0034] These and other aspects of the invention will become apparent from the embodiments described below, and will be explained with reference to the embodiments described below. Attached Figure Description

[0035] The embodiments are described using the reference drawings as examples only, wherein:

[0036] Figure 1 This is a schematic block diagram of an example radar transceiver;

[0037] Figure 2 This is a schematic block diagram of an example radar transceiver with dummy load;

[0038] Figure 3 yes Figure 2 A schematic block diagram of a portion of an example radar transceiver along with associated components;

[0039] Figure 4 This is a schematic flowchart illustrating an example method for performing a self-test operation on an example transceiver; and

[0040] Figure 5 The simulation results show the linearity of the differential (top plot) and integral (bottom plot) outputs of the PSDAC with and without dummy load.

[0041] It should be noted that the figures are illustrative and not drawn to scale. For clarity and convenience in the figures, the relative dimensions and scales of the parts have been shown as enlarged or reduced in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. Detailed Implementation

[0042] Figure 1 A simplified block diagram of an example radar device 100 disclosed in US 10,418,972 B2 is shown. The radar device 100 includes a radar transceiver having a receiver module 102 and a transmitter module 104. Data output 106 can be retrieved from the receiver module 102 via a digital interface 108. The receiver module 102 may include, for example, a millimeter-wave front-end (MMW FE) 110 coupled to a receiver input RX1 and configured to provide a signal to a baseband module 112, the MMW FE 110 comprising a variable gain amplifier and a filter. The signal transmitted by the baseband module 112 can be converted from the analog domain to the digital domain via an analog-to-digital converter (ADC) 114 to provide a digital output of the receiver module 102. The digital output of the receiver module 102 can be exported from the radar device 100 via the digital interface 108. For example, the digital interface 108 may include a buffer and a data format converter.

[0043] Transmitter 104 is connected to digital controller 116. Digital controller 116 includes a direct digital synthesizer (DDS) 118. The output of DDS 118 is provided to transmitter module 104 via digital controller 116. The signal from DDS 118 can be provided at the output of digital controller 116 via Σ-Δ modulator 120.

[0044] Under the control of the DDS 118 of the digital controller 116, the phase of the signal to be transmitted is generated by the phase shifter digital-to-analog converter (PSDAC) 122 of the transmitter module 104. The PSDAC 122 drives the phase shifter 124. The phase shifter 124 also receives the oscillator signal from the phase-locked loop (PLL) circuit 126.

[0045] Phase-locked loop circuit 126 includes voltage-controlled oscillator (VCO) 128 and buffer 130. Phase shifter 124 provides phase-shift signal 131 to power amplifier (PA) 132. PA 132 also receives the output of digital-to-analog converter (DAC) 134. DAC 134 provides current-mode control of the output power of PA 132. PA 132 provides transmit signal 136 to transmitter output TX3 to be supplied to antenna.

[0046] exist Figure 1In the example shown, the phase control of transmitter module 104 and digital controller 116 can operate in either voltage or current mode. The mode of transmitter module 104 can be controlled via digital controller 116 according to the state of radar device 100. For example, in normal operating mode, the phase control of transmitter module 104 can operate in current mode. In Built-in Self-Test (BIST) operating mode, receiver module 102 can be driven in voltage mode. It has been found that voltage-operated phase shifter 124 of transmitter module 104 provides higher accuracy compared to current mode, which is suitable for testing the linearity of the receiver chain during BIST procedures, examples of which are provided below. By driving phase shifter 124 in current mode during normal operating mode, the transmitter power noise of transmitter module 104 in normal operation can be reduced compared to using a voltage-mode driven phase shifter.

[0047] In voltage operation mode, the output of DDS 118 can be provided to the input of the phase shifter DAC via Σ-Δ modulator 120. The output of phase shifter DAC 122 in voltage mode is provided to phase shifter 124 via low-pass filter 140 to remove out-of-band signals. Using a Σ-Δ (SD) modulator to drive PSDAC 122 can improve the phase accuracy of the transmitted signal by increasing the effective number of bits of PSDAC 122. In this way, the required PSDAC complexity can be reduced while still providing acceptable performance.

[0048] As part of the BIST procedure, the output of the low-pass filter 140 in voltage mode is also provided to the input of the baseband 112 of the receiver module 102 via the loopback module 142. In voltage mode, the output of the phase shifter 124 is also provided at the input of the millimeter-wave front-end 110 of the receiver module 102 via the loopback module 142. During normal operation, when the phase shifter 124 is current-driven, the output of the DDS 118 is directly provided to the input of the phase shifter DAC 122, and the output of the phase shifter DAC 122 is directly provided to the phase shifter 124 as an input. The loopback module 142 is used for the BIST procedure and is therefore not required in current operation mode.

[0049] In this way, depending on the selected mode (voltage or current), portions of the circuit are activated or deactivated to provide an optimal balance between signal phase accuracy and transmit noise power. The ability to drive the phase shifter 124 in voltage or current mode is combined within a single phase shifter architecture to provide both good signal (high SNR) for testing purposes and low transmitter noise power during normal transmitter operation.

[0050] The radar device 100 also includes a power management module 144, which can operate in a conventional manner. The radar device 100 or parts thereof can be implemented using CMOS technology.

[0051] Figure 2 A simplified block diagram of an example radar device 200 is shown. Instead... Figure 1 The device 100 in the receiver module 102 provides a low-pass filter 140, or in some cases, a dummy load 240 connected to the output of the PSDAC 122 in addition to the low-pass filter 140. The dummy load 240 can also be connected to the baseband portion of the loopback module 142. The dummy load 140 can be used for BIST sequences during operation and can also be enabled during production testing. The dummy load 240 or another dummy load 240' can also be used for loopback of the IF signal of the BIST of the baseband 112 of the receiver module 102.

[0052] Figure 3 It shows Figure 2 A more detailed view of some components of the transceiver 200. The digital controller 116 includes a DDS 118 and Δ-Σ converters 120I and 120Q for the in-phase and quadrature components of the DDS outputs I and Q. The outputs of the Δ-Σ converters 120I and 120Q are provided to a PSDAC 122 having a first path and a second path, including DACs 122I and 122Q. The differential output signal is provided to a phase shifter 124, which provides the differential outputs PS1_out+ and PS1_out- to a power amplifier 132, such as... Figure 2 As shown.

[0053] Signals from each of the inputs to phase shifter 124 are also provided to dummy load module 240. Dummy load module 240 is preferably a copy of phase shifter 124, i.e., having the same component arrangement to provide an equivalent load from the perspective of PSDAC 122. Like phase shifter 124, dummy load 240 provides differential outputs, but this dummy load 240 is connected across resistor network 331. Resistor network 331 includes a first resistor 331a connected between the first differential output connection 332 and the common node 333, and a second resistor 331b connected between the common node 333 and the second differential output connection 334 of dummy load 240.

[0054] The test module 335 is connected to the outputs 332 and 334 of the resistor network 331 and the dummy load 240, and includes an analog test bus (ATB) 336 and an analog-to-digital converter (ADC) 337 for converting the ATB outputs into digital output signals 338.

[0055] Controller module 339 is configured to control the operation of ATB 336 and dummy load 240. Controller module 339 is also configured to control the operation of digital controller 116 during self-test operation mode (during production self-test or BIST operation mode in use).

[0056] During self-test operation or in production, controller module 339 may first generate a known test signal in the form of a setting current to be provided across resistor network 331 via first test connection 340a and second test connection 340b connected to ATB 336. Under the control of controller module 339, ATB 336 allows selection of which two of the three lines A, B, and C to connect, thereby enabling the test current to be delivered through one or both resistors 331a and 331b of the resistor network. The voltage across the resistors can then be measured to determine the measured values ​​of resistors 331a and 331b. Resistors 331a and 331b may be variable to provide a series of loads to the output of dummy load 240. The values ​​of resistors 331a and 331b may be determined under the control of controller module 339, for example, by controlling the operation of the transistor switching array in the resistor network forming each of resistors 331a and 331b.

[0057] Assuming the values ​​of resistors 331a and 331b are known or determined, in self-test operation mode, controller module 339 first enables dummy load 240. Then, controller module 339 operates digital controller 116 to provide a series of digital control signals to PSDAC 122, for example, by providing signals within a range of phase shifts intended for use. The linearity of PSDAC can then be determined by measuring at each point within said range using ATB 336 and ADC 337 to provide digital output signal 338 to controller module 339.

[0058] Figure 4 The diagram illustrates an example operation during self-test mode. In the first step 401, a dummy load 240 is enabled by the controller module 339. In step 402, the controller module 339 then operates the digital controller 116 to provide a series of digital control signals to the PSDAC 122. In step 403, which can be performed concurrently with step 402, the controller module 339 operates the test module 335 to measure the output (i.e., Figure 3The signals at nodes B and C in the signal processing module are used to determine the linearity measurement of the PSDAC 122. The resulting series of digital signals can be stored as digital codes in the case of production self-test operation before the end of the method (step 406) (step 405 after step 404), or compared with previously stored digital codes in the case of BIST operation when the transceiver is in use (step 407 after step 404). If the digital code generated by the comparison in step 407 is different from the previously stored digital code, it is determined that the PSDAC is operating beyond production self-test linearity, and the controller module 339 may subsequently operate the transceiver in fail-safe mode or generate an error flag, which may cause the transceiver to be deactivated (step 409). If the comparison result in the digital codes matches the previously stored code, the controller module 339 may allow the transceiver to operate in normal mode (step 408).

[0059] Simulations show that by using a dummy load in the manner outlined herein, the I and Q outputs from PSDAC 122 to phase shifter 124 remain substantially unchanged when the dummy load path is included, and whether the dummy load is enabled (i.e., in self-test operating mode) or disabled in normal operating mode. The integral and differential linearity of the I and Q outputs are also substantially unaffected by the presence of the dummy load, regardless of whether it is enabled or disabled, thereby allowing the dummy load 240 to provide a representative load to allow for the measurement of the linearity of PSDAC 122. As an example, Figure 5 The simulation results for the differential (top) and integral (bottom) linearity of the PSDAC's I output are shown with and without a dummy load. Dashed lines indicate results with a load, while solid lines indicate results without a load. The results from the Q output (not shown) are similar. The differences between the results are small enough that a dummy load can be used to measure the PSDAC's linearity without significantly affecting the PSDAC's operation, thus enabling the determination of accurate linearity measurements during normal use.

[0060] By reading this disclosure, those skilled in the art will understand other changes and modifications. Such changes and modifications may involve equivalent and other features known in the field of memory systems that may replace or be added to the features described herein.

[0061] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalized form thereof explicitly or implicitly disclosed herein, regardless of whether it relates to the same invention as claimed in any of the present claims or whether it alleviates the same technical problem as any or all of the technical problems alleviated by this invention.

[0062] Features described in multiple embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features described in a single embodiment may also be provided individually or in any suitable sub-combination. The applicant hereby reminds that new claims may be formulated based on such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0063] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" does not exclude multiple, a single processor or other unit can perform the functions of several components recited in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. A radar transceiver (200), characterized in that, The transceiver (200) includes a normal transmitter operation mode and a self-test operation mode, comprising: A digital controller (116) is configured to provide digital control signals indicating phase shift; A digital-to-analog converter (122) is configured to receive the digital control signal and provide an analog signal according to the phase shift; A phase shifter (124) is configured to receive the analog signal and provide a phase-shifted output signal for transmission; A dummy load (240) is connected to receive the analog signal from the digital-to-analog converter (122) and provide an analog output; A resistor network (331) is connected to the output terminals of the dummy load (240); Test module (335), configured to measure the simulated output of the dummy load (240); and The controller module (339) is configured to control the operation of the dummy load (240), the test module (335), and the digital controller (116) during the self-test operation mode by: Enable the dummy load (240); Operate the digital controller (116) to provide a series of digital control signals to the digital-to-analog converter (122); and The test module (335) is operated to measure the analog output of the dummy load (240) to determine the linearity measurement of the digital-to-analog converter (122).

2. The transceiver (200) according to claim 1, characterized in that, The controller module (339) is configured to operate the test module (335) before operating the digital controller (116) to provide current through the resistor network (331) and measure the resistance value of the resistor network (331).

3. The transceiver (200) according to any one of the preceding claims, characterized in that, The dummy load (240) includes a first differential output connection and a second differential output connection (332, 334), and the resistor network (331) includes: A first resistor (331a) is connected between the first differential output connection (332) and the common node (333); A second resistor (331b) is connected between the common node (333) and the second differential output connection (334).

4. The transceiver (200) according to claim 1, characterized in that, During production self-test mode, the controller module (339) is configured to output and store a first digital code representing the linear measurement value of the digital-to-analog converter (122).

5. The transceiver (200) according to claim 4, characterized in that, During the service self-test mode, the controller module (339) is configured to output a second digital code representing the linear measurement value of the digital-to-analog converter (122) and compare the second digital code with a stored first digital code.

6. The transceiver (200) according to claim 5, characterized in that, The transceiver (200) is configured to operate in the normal operating mode when the first digit code matches the second digit code.

7. The transceiver (200) according to claim 5, characterized in that, The transceiver (200) is configured to operate in fail-safe mode if the first digital code does not match the second digital code.

8. The transceiver according to claim 1, characterized in that, The dummy load (240) is a first dummy load, and the resistor network (331) is a first resistor network. The transceiver (200) includes a second dummy load (240') of a receiver module (102) connected to receive the analog signal and output the baseband signal to the transceiver (200).

9. A method for testing a radar transceiver (200) according to any one of the preceding claims, characterized in that, The method includes the controller module (339) performing the following operations: Enable the transceiver (200); Operate the digital controller (116) to provide digital control signals to the digital-to-analog converter (122); The test module (335) is operated to measure the output of the dummy load (240) and provide a digital code as a linear measurement of the digital-to-analog converter (122).

10. A computer program product, characterized in that, Includes instructions for causing the controller module to execute the method according to claim 9.

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