Microelectronic devices and related memory devices, electronic systems, and methods

Abstract

This application relates to microelectronic devices and related memory devices, electronic systems, and methods. The microelectronic device includes: a post structure extending vertically through an insulating material; a conductive wire electrically coupled to the post structure; a contact structure between the post structure and the conductive wire; and an interconnect structure between the conductive wire and the contact structure. The conductive wire includes one or more of titanium, ruthenium, aluminum, and molybdenum. The interconnect structure includes a material composition different from that of the contact structure and one or more of the material compositions of the conductive wire.

Description

[0001] Priority requirements

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 990,518, filed on August 11, 2020, entitled “Microelectronic Devices Including Conductive Structures, and Related Memory Devices, Electronic Systems, and Methods”. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to microelectronic devices comprising conductive structures, and to related memory devices, electronic systems, and methods of forming microelectronic devices. Background Technology

[0004] A persistent goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize vertical memory array (also known as “three-dimensional (3D) memory arrays”) architectures. A conventional vertical memory array comprises vertical memory strings extending through openings in one or more conductive stack structures, which include layers of conductive and insulating structures. Each vertical memory string may contain at least one selection device series-coupled to a series combination of vertically stacked memory cells. Compared to structures with a conventional planar (e.g., two-dimensional) transistor arrangement, this configuration allows for a greater number of switching devices (e.g., transistors) to be located in cells (i.e., the length and width of the active surface consumed) of the die region by building the array upwards (e.g., vertically) on the die.

[0005] As the size and spacing of conductive features decrease, multi-level wiring structures have been used in memory devices (e.g., 3D NAND flash memory devices) to electrically connect conductive features to each other. Memory devices contain different levels of wiring structures, where the wiring structures are formed of conductive material to provide conductive paths through the memory device. As the size and spacing of conductive features continue to decrease, parasitic (e.g., stray) capacitance between adjacent conductive features within the memory device increases. Increased parasitic capacitance leads to higher power demands and memory device latency. Air gaps have been used to electrically isolate conductive features, such as conductive structures. Furthermore, as the thickness of conductive structures decreases, the resistivity of the conductive structure can increase, and the conductivity can exhibit a corresponding decrease. However, the reduced conductivity of the conductive structure can affect the performance of the memory cell string. Summary of the Invention

[0006] The embodiments described herein include microelectronic devices comprising conductive structures, and relate to related memory devices, electronic systems, and methods of forming microelectronic devices. According to one embodiment described herein, a microelectronic device includes: a post structure extending vertically through an insulating material; a conductive wire electrically coupled to the post structure, the conductive wire comprising one or more of titanium, ruthenium, aluminum, and molybdenum; a contact structure between the post structure and the conductive wire; and an interconnect structure between the conductive wire and the contact structure, the interconnect structure comprising a material composition different from that of the contact structure and one or more of the material compositions of the conductive wire.

[0007] According to an additional embodiment described herein, a memory device includes: a vertically extending string of memory cells; an access line electrically connected to and extending along a first horizontal direction of the vertically extending string of memory cells; a data line electrically connected to and extending along a second horizontal direction of the vertically extending string of memory cells, the second horizontal direction being substantially transverse to the first horizontal direction; an interconnect structure vertically inserted between and electrically connected to the data line and the vertically extending string of memory cells; and a contact structure vertically inserted between and electrically connected to the interconnect structure and the vertically extending string of memory cells, the contact structure comprising tungsten, and the data line comprising a single-phase material, including ruthenium or molybdenum.

[0008] Furthermore, according to additional embodiments described herein, a method of forming a microelectronic device includes: forming a post structure extending vertically through an insulating material; forming a contact structure above the post structure; forming an interconnect structure above the contact structure; and forming a conductive line electrically coupled to the post structure through the contact structure and the interconnect structure, the conductive line comprising one or more of titanium, ruthenium, aluminum, and molybdenum, and the interconnect structure comprising a material composition different from that of the contact structure and one or more of the material compositions of the conductive line.

[0009] According to other embodiments described herein, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device including: a string of memory cells extending vertically through a stacked structure, the stacked structure including a vertically alternating sequence of insulating and conductive structures arranged in layers; an additional conductive structure substantially free of tungsten overlying the string of memory cells; and an interconnection structure between the string of memory cells and the additional conductive structure, the interconnection structure including a beta-phase tungsten lining material substantially surrounding an alpha-phase tungsten-filled material. Attached Figure Description

[0010] Figures 1A to 1G This is a simplified partial cross-sectional view illustrating a method for forming a microelectronic device according to an embodiment of the present disclosure;

[0011] Figure 2 This is based on embodiments of the present disclosure by reference. Figures 1A to 1G A simplified cross-sectional view of a microelectronic device formed by the described method;

[0012] Figure 3 This is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0013] Figure 4 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0014] The following description provides specific details, such as material composition, shape, and size, to provide a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without employing these specific details. In fact, embodiments of this disclosure can be practiced in conjunction with conventional microelectronic device fabrication techniques used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions to form a complete microelectronic device can be performed by conventional manufacturing techniques.

[0015] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations in the shapes depicted in the drawings should be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas shown, but rather include shape deviations, for example, due to manufacturing processes. For example, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may contain some rough and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The figures are not necessarily drawn to scale. Additionally, common elements between the figures may retain the same numerical designation.

[0016] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surface of the structure that has a relatively large area compared to the other surfaces of the structure. Referring to the figures, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0017] As used herein, referring to an element as "on" or "above" another element means and includes that the element is directly on top of the other element, directly adjacent to (e.g., directly laterally adjacent to, directly vertically adjacent to) the other element, directly below the other element, or in direct contact with the other element. It also includes that the element is indirectly on top of the other element, indirectly adjacent to (e.g., indirectly laterally adjacent to, indirectly vertically adjacent to) the other element, indirectly below the other element, or nearby, and that other elements are present between them. In contrast, when an element is referred to as "directly on" or "directly adjacent to" another element, no intermediate elements are present.

[0018] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “back,” “left,” and “right” may be used herein for ease of description to describe the relationship of one element or feature to another as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material in addition to those depicted in the figures. For example, if the material in the figures is reversed, then an element described as “below,” “under,” “below,” or “on the bottom” of another element or feature will be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0019] As used herein, features described as “adjacent” to each other (e.g., areas, structures, devices) refer to and include features of a disclosed identifier (or identity) located closest to each other (e.g., closest to each other). Additional features of a disclosed identifier (or identity) that do not match “adjacent” features (e.g., additional areas, additional structures, additional devices) may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other refer to and include features of a disclosed identifier (or identity) located closest to each other (e.g., vertically closest to each other). Furthermore, features described as “horizontally adjacent” to each other refer to and include features of a disclosed identifier (or identity) located closest to each other (e.g., horizontally closest to each other).

[0020] As used in this article, the term “split” refers to the distance between identical points in two adjacent (i.e., adjacent) features.

[0021] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to include the plural forms as well.

[0022] As used in this document, “and / or” includes any and all combinations of one or more of the listed related items.

[0023] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and includes the degree to which a given parameter, characteristic, or condition conforms to variance (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, characteristic, or condition that is substantially satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0024] As used herein, the term "about" or "approximately" with respect to a particular parameter includes a value and the degree of variation of the value within acceptable tolerances for that parameter, as would be understood by one of ordinary skill in the art. For example, "about" or "approximately" with respect to a value may include additional values ​​that are within the range of 90.0% to 108.0% of the value, such as 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0025] As used herein, the term "selectively etchable" refers to and includes materials that exhibit a greater etching rate in response to exposure to a given etching chemical than another material exposed to the same etching chemical. For example, a material may exhibit an etching rate at least about three times (3x) greater than that of another material, such as about five times (5x), or about ten times (10x), twenty times (20x), or forty times (40x) greater than that of another material. Those skilled in the art can select the etching chemical and etching conditions used for selectively etching the desired material.

[0026] As used herein, “subtractive patterning” refers to one or more process actions that form a structure to be defined by removing material. For example, a “subtractive patterning process” may involve forming an etched mask structure on the area to be patterned, followed by etching, such that the material in the area masked by the mask structure is protected, while the material in the exposed area is removed by the etching removal process.

[0027] As used herein, the term "air gap" means a volume that extends into or through another region or material or between regions or materials, thereby creating a void in or between said other region or material that does not contain solid and / or liquid material. An "air gap" is not necessarily free of gaseous material (e.g., air, oxygen, nitrogen, argon, helium, or combinations thereof) and does not necessarily contain "air". An "air gap" can be, but is not necessarily, a void (e.g., an unfilled volume, a vacuum).

[0028] As used herein, the term "memory device" refers to and includes microelectronic devices that exhibit memory functions, but are not necessarily limited to memory functions. In other words, by way of example only, the term "memory device" refers to and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices with combinational logic and memory, and graphics processing units (GPUs) incorporating memory.

[0029] As used herein, “conductive material” means and includes conductive materials, such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based alloys, Fe-based alloys, etc.). Alloys based on Ni, alloys based on Fe and Ni, alloys based on Co and Ni, alloys based on Fe and Co, alloys based on Co, Ni, and Fe, alloys based on Al, alloys based on Cu, alloys based on magnesium (Mg), alloys based on Ti, steel, low-carbon steel, stainless steel), materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" refers to and includes structures formed of and containing conductive materials.

[0030] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO)x ), hafnium dioxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y And at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y This article contains chemical formulas with "x", "y", and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N y A chemical formula represents a material containing, for each atom of another element (e.g., Si, Al, Hf, Nb, Ti), an average ratio of "x" atoms of one element, "y" atoms of the other element, and "z" atoms of an additional element (if present). Because a chemical formula represents a relative atomic ratio rather than a strict chemical structure, an insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or not. As used herein, the term "non-stoichiometric compound" refers to and includes compounds composed of elements that cannot be expressed by a ratio of clearly defined natural numbers and violate the law of definite proportions. Additionally, "insulating structure" refers to and includes structures formed of and containing insulating materials.

[0031] Unless otherwise specified, the materials described herein can be formed using conventional techniques, including but not limited to spin coating, thick-layer coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the material can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by a person skilled in the art. Unless the context otherwise indicates, material removal can be achieved by any suitable technique, including but not limited to etching, planarization (e.g., chemical mechanical planarization), or other known methods.

[0032] Figures 1A to 1F A method for forming a microelectronic device structure (e.g., a memory device, such as a 3D NAND flash memory device) according to embodiments of the present disclosure is shown. References Figure 1A This illustrates a partially manufactured microelectronic device structure 100 for use in forming devices (e.g., microelectronic devices, memory devices) of this disclosure. Figure 1A The partially fabricated microelectronic device structure 100 shown in the process stages can be formed using conventional techniques not described in detail herein. The microelectronic device structure 100 includes a first insulating material 102 overlaid on a substrate material. In some embodiments, the first insulating material 102 includes a single insulating material (e.g., a dielectric material). In other embodiments, the first insulating material 102 includes an alternating stack of materials. For example, the alternating stack of materials may include alternating layers of a first dielectric material and a second dielectric material that are different from each other. At least some of the alternating dielectric material layers in the first insulating material 102 may have been replaced with a conductive material prior to the formation of the microelectronic device structure 100. Therefore, the alternating stack of materials may include alternating dielectric and conductive materials.

[0033] The first insulating material 102 (e.g., an insulating structure in an alternating material stack) may be formed of at least one dielectric material and may contain at least one dielectric material, such as one or more of the following: dielectric oxide materials (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), dielectric nitride materials (e.g., SiN) y ), dielectric oxide nitride materials (e.g., SiO2) x Ny ), and dielectric carbon oxynitride materials (e.g., SiO2). x C z N y In some embodiments, the first isolation material 102 is formed of and contains SiO2. The first isolation material 102 can be formed using one or more conventional deposition techniques, including, but not limited to, one or more of conventional CVD processes or conventional ALD processes.

[0034] like Figure 1A As shown, the guide pillar structure 104 may extend vertically through the first insulating material 102. The guide pillar structure 104 may be formed in the array region and may be configured as a memory guide pillar structure (e.g., a channel guide pillar structure). The guide pillar structure 104 may exhibit a substantially rectangular cross-sectional shape (e.g., a substantially square cross-sectional shape). However, this disclosure is not limited thereto. As a non-limiting example, in an additional embodiment, the guide pillar structure 104 exhibits a substantially circular cross-sectional shape. Additionally, the spacing between horizontally adjacent guide pillar structures 104 may range from about 50 nanometers (nm) to about 200 nm, for example, about 50 nm to about 100 nm, about 100 nm to about 150 nm, or about 150 nm to about 200 nm. In some embodiments, the critical dimensions of each guide post structure 104 in the horizontal direction are in the range of about 20 nm to about 200 nm, for example, about 20 nm to about 50 nm, about 50 nm to about 100 nm, about 100 nm to about 150 nm, or about 150 nm to about 200 nm.

[0035] Guide pillar structures 104 may be formed in openings extending vertically (e.g., along the Z direction) through the first insulating material 102. For example, guide pillar structures 104 may be formed in high aspect ratio (HAR) openings, such as openings each having an aspect ratio of at least about 20:1, at least about 40:1, at least about 50:1, at least about 60:1, at least about 80:1, or at least about 100:1. In some embodiments, the openings of guide pillar structures 104 may have an aspect ratio in the range of about 20:1 to about 40:1. Each guide pillar structure 104 includes channel material surrounding a unit membrane 104a of the filling material 104b. For example, the unit membrane 104a may include unit material formed within the opening and channel material formed adjacent to (e.g., above) the unit material. For convenience, the unit material and channel material are... Figure 1AThe diagram shows a single material (e.g., unit film 104a). However, unit film 104a should be understood to include both unit material and channel material. The unit material and channel material are formed using conventional techniques, such as CVD or ALD. For example, the unit material can be an oxide-nitride-oxide (ONO) material, such as silicon oxide-silicon nitride-silicon oxide, which is conformally formed above the sidewalls of the pillar structure 104. The unit material can be formed with a smaller thickness compared to the channel material. The channel material can be conformally formed adjacent to (e.g., above) the unit material. For example, the channel material can be polycrystalline silicon. A filler material 104b can be formed adjacent to (e.g., above) the channel material of unit film 104a, essentially filling the opening. The filler material 104b can be an insulating material, such as a high-quality silicon oxide material. For example, the filler material 104b can be highly uniform and highly conformally conformal silicon oxide (SiO₂). x The filler material 104b can be highly uniform and conformal, as during deposition, and can be formed using conventional techniques, such as ALD. In some embodiments, the filler material 104b is ALD SiO2. x The filler material 104b may be initially formed in the opening and above the exposed horizontal surface of the first insulating material 102, wherein the filler material 104b above the first insulating material 102 is subsequently removed, for example, by a planarization process (e.g., chemical mechanical planarization (CMP)). Thus, the filler material 104b is surrounded by the cell material and channel material of the cell membrane 104a. At least a portion of the post structure 104 may be operatively coupled (e.g., electrically connected) to a conductive structure (e.g., a word line structure, a source structure underlying the first insulating material 102), as described below. Figure 2 Further detailed description.

[0036] Return to reference Figure 1A A conductive plug structure 106 (e.g., a drain contact plug material) may be formed within the upper portion of the post structure 104. The conductive plug structure 106 may be formed on or above the filler material 104b and laterally adjacent to the channel material of the unit cell film 104a. The conductive plug structure 106 may be electrically coupled to the channel material of the unit cell film 104a. The conductive plug structure 106 may include a semiconductor material, such as one or more of polysilicon, silicon-germanium, and germanium. The conductive plug structure 106 may be conductively doped. The process used to form the conductive plug structure 106 may be, for example, CVD or ALD.

[0037] Contact structures 110 (e.g., contacts, bit line contacts) may be formed on or above the uppermost surface of the conductive plug structure 106. Each contact structure 110 may include an outer surface, an upper surface 110a, and a lower surface 110b adjacent to (e.g., directly vertically adjacent to) the uppermost surface of the conductive plug structure 106. Contact structures 110 may be formed using one or more conventional processes (e.g., conventional deposition processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein. For example, portions of the dielectric material (e.g., first insulating material 102) covering the conductive plug structure 106 may be removed (e.g., by conventional photolithographic patterning and etching processes) to form plug openings covering the conductive plug structure 106, conductive material may be deposited into the plug openings, and portions of the conductive material may be removed (e.g., by a CMP process) to form contact structures 110.

[0038] The contact structure 110 may be formed of and contain at least one conductive material, such as one or more of the following: metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. As a non-limiting example, the contact structure 110 may be formed of and contain one or more of the following: tungsten (W), tungsten nitride (WN). y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), Tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x Titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN) x ), iridium (Ir), iridium oxide (IrO) z ), Ruthenium (Ru), Ruthenium oxide (RuO) z ) and conductive doped silicon. In some embodiments, the contact structure 110 is formed of W and contains W.

[0039] In some embodiments, the contact structure 110 is substantially uniform. In other embodiments, the contact structure 110 is non-uniform. As used herein, the term "uniform" means that the amount of material does not change (e.g., varies) throughout different portions of another material or structure (e.g., different horizontal portions, different vertical portions). Conversely, as used herein, the term "non-uniform" means that the amount of material varies throughout different portions of another material or structure. For example, a lining material 111 (e.g., a conductive lining material) may be formed on or above the exposed surfaces of each of the first insulating material 102 and the conductive plug structure 106 of the guide post structure 104. The lining material 111 may be conformally formed on the uppermost surface of the conductive plug structure 106 and on the exposed side surfaces and upper surfaces of the first insulating material 102. In some embodiments, the lining material 111 substantially surrounds the side surfaces (e.g., sidewalls) of the first insulating material 102 within the contact opening. The lining material 111 may be formed to any desired thickness. As a non-limiting example, the lining material 111 may be formed with a thickness in the range of about 1 nm to about 10 nm, for example, in the range of about 1 nm to about 5 nm or in the range of about 5 nm to about 10 nm. In some embodiments, the lining material 111 is formed with a thickness of about 4 nm. The thickness of the lining material 111 may be substantially uniform along its length in at least one of the horizontal direction (e.g., the X direction, Y direction) and the vertical direction (e.g., the Z direction).

[0040] The lining material 111 may be formed of and contain at least one conductive material. As a non-limiting example, the lining material 111 may be a metallic material (e.g., a transition metal material) or a metal nitride material (e.g., a transition metal nitride material), such as one or more of the following: titanium nitride (TiN). y ), tungsten (W), tungsten nitride (WN) y ), Tantalum nitride (TaN) y ), cobalt (Co), molybdenum nitride (MoN) y ) or ruthenium (Ru), where y is an integer or non-integer. In some embodiments, the lining material 111 comprises TiN y For example, TiN. In other embodiments, the lining material 111 comprises molybdenum (Mo). In still other embodiments, the lining material 111 comprises ruthenium (Ru).

[0041] The lining material 111 can be formed using one or more conventional conformal deposition techniques, such as one or more of conventional ALD processes, conventional conformal CVD processes, and conventional in-situ growth processes. Because the lining material 111 is formed conformally, a portion of the contact opening within the first isolation material 102 remains substantially free of lining material 111. Therefore, the lining material 111 is formed in the contact opening without completely filling the contact opening of the first isolation material 102. In such embodiments, the lining material 111 may be formed immediately adjacent to the exposed side surface of the first isolation material 102 and may at least partially (e.g., substantially) cover the exposed side surface of the first isolation material 102, but without completely filling the remaining portion (e.g., the central portion) of the contact opening within the first isolation material 102. At least a portion of the lining material 111 can be subsequently removed using one or more conventional material removal processes. For example, the horizontal portion of the lining material 111 initially formed on the upper surface of the first isolation material 102 can be removed, while a portion of the lining material 111 remains on the exposed side surface of the first isolation material 102. The horizontal portion of the lining material 111 may or may not be removed from the uppermost surface of the conductive plug structure 106.

[0042] After the lining material 111 is formed, the filler material 112 may be formed adjacent to (e.g., on or above) the surface of the lining material 111. Figure 1A As shown, filler material 112 may at least partially (e.g., substantially) cover the upper surface of lining material 111 and extend between the side surfaces (e.g., sidewalls) of lining material 111 and above the horizontal surface of lining material 111. In other words, filler material 112 may substantially fill the remainder (e.g., unfilled portions) of the contact opening within first insulating material 102 and may also be formed above the horizontal surface of lining material 111. Filler material 112 may be formed in the central portion of the contact opening within 102. In other words, filler material 112 may substantially completely fill the central portion of the contact opening within first insulating material 102. Therefore, the central portion of the contact opening within first insulating material 102 may contain filler material 112 and may substantially not contain lining material 111. Filler material 112 may be adjacent to (e.g., in direct physical contact with) lining material 111, and lining material 111 may substantially surround (e.g., substantially continuously surround) filler material 112.

[0043] The filling material 112 of the contact structure 110 may be formed of and contain at least one conductive material, such as one or more of the following: metal, alloy, conductive metal oxide, conductive metal nitride, conductive metal silicide, and conductive doped semiconductor material. As a non-limiting example, the filling material 112 may be formed of and contain one or more of the following: W, WN.y Ni, Ta, TaN y TaSi x ,Pt, Cu, Ag, Au, Al, Mo, Ti, TiN y TiSi x TiSi x N y TiAl x N y MoN x Ir, IrO z 、Ru、RuO z And conductive doped silicon. In some embodiments, the filler material 112 is formed of W and contains W.

[0044] Contact structure 110 may be grown or deposited (e.g., by ALD, CVD, pulsed CVD, metal-organic CVD, PVD). The lining material 111 of contact structure 110 may be formed of and contain a seed material, and the filler material 112 may be formed of the seed material. For example, contact structure 110 may be formed by depositing lining material 111 (e.g., titanium nitride material) and then forming (e.g., growing, depositing) filler material 112 (e.g., tungsten) within the contact opening of first insulating material 102. In some embodiments, contact structure 110 may be formed by PVD (e.g., sputtering) targeting a material composition comprising contact structure 110. For example, contact structure 110 may be formed by exposing a target comprising the material composition of contact structure 110 to an ionized gas (e.g., argon) to form (e.g., depositing) contact structure 110 within the contact opening of first insulating material 102. In some such embodiments, contact structure 110 may include a PVD-grown conductive material, and may be referred to herein as "PVD conductive material" (e.g., PVD tungsten). In some embodiments, at least some argon gas may be present within the contact structure 110. In other embodiments, the conductive plug structure 106 serves as a seed material for growing the contact structure 110.

[0045] The outer surface (e.g., sidewall) of the contact structure 110 may exhibit a wedge-shaped profile, wherein the upper portion of each contact structure 110 has a critical dimension (e.g., width) larger than its lower portion, such as... Figure 1A As shown in the diagram. In other embodiments, the contact structure 110 has a different profile, such as a substantially rectangular profile, a disc-shaped profile, or any other three-dimensional recessed shape, such that at least a portion of the contact structure 110 (e.g., the lateral extent of the upper surface 110a) extends beyond the sidewall of the post structure 104 in at least one lateral direction (e.g., the X direction). Additional portions of the dielectric material, collectively referred to as the first insulating material 102, may be formed on or above the upper surface 110a of the contact structure 110.

[0046] Next reference Figure 1B Interconnect structures 114 (e.g., filled contact vias, filled bitline vias) may be formed on or above the upper surface 110a of the contact structure 110. Each interconnect structure 114 may include an outer surface, an upper surface 114a, and a lower surface 114b adjacent to (e.g., directly vertically adjacent to) the upper surface 110a of the contact structure 110. The interconnect structures 114 may be formed using one or more conventional processes (e.g., conventional deposition processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein. For example, a portion of the first insulating material 102 covering the contact structure 110 may be removed (e.g., by conventional photolithography patterning and etching processes) to form an opening (e.g., a via, an aperture) covering the upper surface 110a of the contact structure 110, into which conductive material may be deposited, and a portion of the conductive material may be removed (e.g., by a CMP process) to form the interconnect structure 114.

[0047] Interconnect structure 114 can be formed using a damascene process without using one or more subtractive patterning (e.g., etching) processes. In some embodiments, interconnect structure 114 is formed using a single damascene process, wherein a portion of the first insulating material 102 is selectively removed to expose a corresponding portion of the upper surface 110a of the contact structure 110 and form an opening extending through the first insulating material 102. The opening is defined by the sidewalls of the first insulating material 102 and can be formed using conventional photolithography techniques. One or more dry etching processes can be used to form the opening. The conductive material of interconnect structure 114 can be formed within the opening using, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). Alternatively or additionally, interconnect structure 114 can be formed using selective CVD deposition and conventional techniques, as described in further detail below. Subsequently, the upper portion of the conductive material above the upper surface of the first insulating material 102 can be removed (e.g., by CMP processing) to form interconnect structure 114.

[0048] In an additional embodiment, the interconnect structure 114 is formed during the formation of the contact structure 110. For example, the formation of the interconnect structure 114 may be performed substantially simultaneously with the formation of the contact structure 110 to simplify the manufacturing process. In other words, the conductive material of each of the contact structure 110 and the interconnect structure 114 may be deposited to substantially fill the extended opening in the first insulating material 102 with a single deposition action. In such embodiments, the outer surface (e.g., sidewall) of the interconnect structure 114 is initially topographically formed to exhibit a wedge-shaped profile, wherein the upper portion of each interconnect structure 114 has a critical dimension (e.g., width) larger than its lower portion and / or has a critical dimension (e.g., width) larger than that of the contact structure 110. For example, the interconnect structure 114 may be initially topographically formed to exhibit a lateral extent greater than that of the contact structure 110. A portion of the initial material of the outer surface of the interconnect structure 114 may be removed (e.g., etched) in one or more material removal processes such that the final dimension (e.g., final width) of the interconnect structure 114 is relatively smaller than the final dimension of the contact structure 110, as referenced. Figure 1F To be further detailed.

[0049] The interconnect structure 114 may be formed of and contain at least one conductive material, such as one or more of the following: metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. As a non-limiting example, the interconnect structure 114 may be formed of and contain one or more of the following: tungsten (W), tungsten nitride (WN). y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), Tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x Titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN) x ), iridium (Ir), iridium oxide (IrO) z ), Ruthenium (Ru), Ruthenium oxide (RuO) z The interconnect structure 114 is formed of and contains tungsten (W). The interconnect structure 114 may contain substantially the same material composition as the contact structure 110, or it may not contain substantially the same material composition as the contact structure 110.

[0050] In some embodiments, the interconnect structure 114 is substantially uniform. In other embodiments, the interconnect structure 114 is non-uniform. For example, a liner material 113 may optionally be formed on or above the exposed surfaces of each of the first insulating material 102 and the contact structure 110. If present, the liner material 113 may be conformally formed on the upper surface 110a of the contact structure 110 and the exposed side surfaces and upper surface of the first insulating material 102. In some embodiments, the liner material 113 substantially surrounds the side surfaces (e.g., sidewalls) of the first insulating material 102 within the opening. The liner material 113 may be formed to any desired thickness. As a non-limiting example, the liner material 113 may be formed to a thickness in the range of 1 nm to about 10 nm, for example, in the range of about 1 nm to about 5 nm or in the range of about 5 nm to about 10 nm. In some embodiments, the liner material 113 is formed to a thickness of about 4 nm. The thickness of the lining material 113 may be substantially uniform along its length in at least one of the horizontal direction (e.g., the X direction, the Y direction) and the vertical direction (e.g., the Z direction).

[0051] The lining material 113 of the interconnect structure 114 may be formed of and contain at least one conductive material. As a non-limiting example, the lining material 113 may be a metallic material (e.g., a transition metal material) or a metal nitride material (e.g., a transition metal nitride material), such as one or more of the following: TiNy, W, WNy, TaNy, Co, Mo, MoNy, or Ru, where y is an integer or non-integer. In some embodiments, the lining material 113 includes W. In other embodiments, the lining material 113 includes Mo. In still other embodiments, the lining material 113 includes Ru. The material composition of the lining material 113 of the interconnect structure 114 may be substantially the same as or different from the material composition of the lining material 111 of the contact structure 110.

[0052] The lining material 113 can be formed using one or more conventional conformal deposition techniques, such as one or more of conventional ALD processes, conventional conformal CVD processes, and conventional in-situ growth processes. Because the lining material 113 is formed conformally, a portion of the opening within the first isolation material 102 remains substantially free of the lining material 113. Therefore, the lining material 113 is formed in the opening without completely filling the opening of the first isolation material 102. In such embodiments, the lining material 113 may be formed immediately adjacent to the exposed side surface of the first isolation material 102 and may at least partially (e.g., substantially) cover the exposed side surface of the first isolation material 102, but without completely filling the remaining portion (e.g., the central portion) of the opening within the first isolation material 102. At least a portion of the lining material 113 can be subsequently removed using one or more conventional material removal processes. For example, the horizontal portion of the lining material 113 initially formed on the upper surface of the first isolation material 102 can be removed, while a portion of the lining material 113 remains on the exposed side surface of the first isolation material 102. The horizontal portion of the lining material 113 may or may not be removed from the upper surface 110a of the contact structure 110.

[0053] After the lining material 113 (if present) is formed, the filler material 115 may be formed on or above the lining material 113. Figure 1B As shown, filler material 115 may at least partially (e.g., substantially) cover the upper surface of lining material 113 and extend between the side surfaces (e.g., sidewalls) of lining material 113 and above the horizontal surface of lining material 113. In other words, filler material 115 may substantially fill the remainder of the opening within the first insulating material 102 (e.g., unfilled portion) and may also be formed above the horizontal surface of lining material 113. Filler material 115 may be formed in the central portion of the opening within 102. In other words, filler material 115 may substantially completely fill the central portion of the opening within the first insulating material 102. Therefore, the central portion of the opening within the first insulating material 102 may contain filler material 115 and may substantially not contain lining material 113. Filler material 115 may be adjacent to (e.g., in direct physical contact with) lining material 113 (if present), and lining material 113 may substantially surround (e.g., substantially continuously surround) filler material 115. In other embodiments, there is no lining material 113 in the opening, and the filler material 115 is in close proximity (e.g., in direct physical contact) to the first insulating material 102, as referenced. Figure 1G The embodiments are described in further detail.

[0054] The filling material 115 of the interconnect structure 114 may be formed of and contain at least one conductive material, such as one or more of the following: metal, alloy, conductive metal oxide, conductive metal nitride, conductive metal silicide, and conductive doped semiconductor material. As a non-limiting example, the filling material 115 may be formed of and contain one or more of the following: W, WN. y Ni, Ta, TaN y TaSi x ,Pt, Cu, Ag, Au, Al, Mo, Ti, TiN y TiSi x TiSi x N y TiAl x N y MoN x Ir, IrO z 、Ru、RuO z And conductive doped silicon. In some embodiments, the filler material 115 is formed of W and contains W. The material composition of the filler material 115 of the interconnect structure 114 may be substantially the same as or different from the material composition of the filler material 112 of the contact structure 110.

[0055] In some embodiments, the interconnect structure 114 is formed using, for example, a PVD or CVD process as described above. The lining material 113 of the interconnect structure 114 may be formed and comprised of a material configured to enhance the formation and conductivity of its filler material 115. For example, the lining material 113 may be formed and comprised of a single-phase material (e.g., a β-phase tungsten material or an α-phase tungsten material), and the filler material 115 may be formed and comprised of another single-phase material (e.g., another of a β-phase tungsten material or an α-phase tungsten material). The interconnect structure 114 may be formed (e.g., deposited, grown) adjacent to (e.g., on, directly thereon) the upper surface 110a of the contact structure 110. In some embodiments, the phase (e.g., β phase, α phase) of the interconnect structure 114 depends at least in part on the phase (e.g., β phase, α phase) of the material of the contact structure 110, which in embodiments includes, for example, the growth of a precursor material of the interconnect structure 114 directly on the contact structure 110.

[0056] In other embodiments, one or more of the contact structures 110 and interconnect structures 114 are formed using conventional ALD processes. In some such embodiments, the contact structures 110 and / or interconnect structures 114 are formed with precursors comprising tungsten hexafluoride (WF6) and silane (SiH4) to form the contact structures 110 and interconnect structures 114. Therefore, in some embodiments, the contact structures 110 and interconnect structures 114 are formed with halogen-containing precursors. In some such embodiments, the contact structures 110 and / or interconnect structures 114 may contain at least some halogens (e.g., fluorine).

[0057] For example, a precursor material (e.g., a semiconductive liner material) may be formed of and comprise at least one semiconductive material, such as one or more of the following: silicon, silicon-germanium, boron, germanium, gallium arsenide, gallium nitride, and indium phosphide. As a non-limiting example, a precursor material may be formed of and comprise at least one silicon material. As used herein, the term "silicon material" refers to and comprises a material comprising elemental silicon or a silicon compound. For example, a precursor material may be formed of and comprise one or more monocrystalline and polycrystalline silicon materials. In some embodiments, the precursor material comprises polycrystalline silicon.

[0058] The precursor material can be formed to exhibit desired dimensions (e.g., height, width) based at least in part on the desired dimensions of the contact structure 110 and the corresponding interconnect structure 114, and can be formed using one or more conventional conformal deposition processes, such as one or more of conventional conformal CVD processes and conventional ALD processes. In some embodiments, the precursor material is doped (e.g., impregnated) with one or more dopants (e.g., chemicals). The dopants in the doped precursor material can include materials that induce or promote the subsequent formation of tungsten (e.g., β-phase tungsten) from the doped precursor material, as described in further detail below. In some embodiments, the dopant includes at least one N-type dopant, such as one or more of phosphorus (P), arsenic (Ar), antimony (Sb), and bismuth (Bi). In additional embodiments, the dopant includes at least one P-type dopant, such as one or more of boron (B), aluminum (Al), and gallium (Ga). In other embodiments, the dopant includes one or more of carbon (C), fluorine (F), chlorine (Cl), bromine (Br), hydrogen (H), deuterium (… 2 H, helium (He), neon (Ne), and argon (Ar).

[0059] The precursor materials for contact structure 110 and interconnect structure 114 can be doped with at least one dopant using conventional processes (e.g., conventional implantation processes, conventional diffusion processes) to form a doped precursor material, which are not described in detail herein. As a non-limiting example, one or more phosphorus-containing substances (e.g., phosphorus atoms, phosphorus-containing molecules, phosphide ions, phosphorus-containing ions) can be implanted into the precursor material to form a doped precursor material. For example, the phosphorus-containing substance may include phosphide ions (P... 3- As another non-limiting example, one or more arsenic-containing substances (e.g., arsenic atoms, arsenic molecules, arsenic ions, arsenic-containing compounds) can be implanted into a precursor material to form a doped precursor material. For example, the arsenic-containing substance may include arsenic ions (As... 3+ In some embodiments, after dopant implantation, the amount of dopant in the doped precursor material ranges from about 0.001 atomic% to about 10 atomic%. Individual portions of the doped precursor material of contact structure 110 and / or interconnect structure 114 may individually exhibit substantially uniformly distributed dopant within their semiconducting material, or may individually exhibit non-uniformly distributed dopant within their semiconducting material.

[0060] Subsequently, the portion of the doped precursor material can be converted into contact structures 110 and / or interconnect structures 114 containing tungsten and dopants from the doped precursor material. Compared to undoped semiconducting materials, the conversion process can relatively quickly convert a portion of the doped precursor material (e.g., silicon, such as polycrystalline silicon) containing dopants dispersed therein into tungsten.

[0061] At least some of the tungsten in the contact structure 110 and / or interconnect structure 114 (e.g., collectively referred to as 'structure') may include β-phase tungsten. β-phase tungsten has a metastable A15 cubic structure. β-phase tungsten particles may exhibit an overall columnar shape. Tungsten contained within the structure may exist only in the β phase, or it may exist in both the β and alpha (α) phases. If present, α-phase tungsten has a metastable body-centered cubic structure. α-phase tungsten particles may exhibit an overall isoelastic shape. If the structure contains both β-phase and α-phase tungsten, the amount of β-phase tungsten contained in the structure may differ from or be substantially the same as the amount of α-phase tungsten contained in the structure. In some embodiments, the amount of β-phase tungsten contained in the structure is greater than the amount of α-phase tungsten contained in the structure. For example, at least a majority (e.g., greater than 50%, such as greater than or equal to about 60%, greater than or equal to about 70%, greater than or equal to about 80%, greater than or equal to about 90%, greater than or equal to about 95%, or greater than or equal to about 99%) of the tungsten contained in the structure may be in the β phase.

[0062] The dopants included in the structure may be substantially the same as those included in the doped precursor material used to form the structure. For example, the dopants used to form the structure (e.g., N-type dopants, P-type dopants, other dopants) may be present in the structure after its formation. In some embodiments, the structure comprises β-phase tungsten doped with one or more of As and P. The dopants in the structure may support (e.g., promote, enhance) the stability of the β-phase tungsten in the structure.

[0063] The structure (e.g., interconnect structure 114, contact structure 110) may exhibit a substantially uniform distribution of dopant or a non-uniform distribution of dopant. The dopant distribution within the structure may be substantially the same as or different from the dopant distribution within the doped precursor material.

[0064] The structure can be formed by treating the doped precursor material with one or more chemicals to promote the conversion of a semiconductive material (e.g., silicon) into tungsten (e.g., β-phase tungsten, α-phase tungsten). As a non-limiting example, if the doped precursor material includes doped silicon, such as doped polycrystalline silicon, then the doped precursor material can be treated with tungsten hexafluoride (WF6) to form the structure. The silicon (Si) of the doped precursor material can react with WF6 to produce tungsten (W) and silicon tetrafluoride (SiF4). The resulting SiF4 is removed as a gas. The resulting W retains the dopant from the doped precursor material to form the structure. For example, the doped precursor material can be treated with WF6 at a temperature in the range of about 200°C to about 500°C using conventional CVD equipment.

[0065] Interconnect structure 114 may be configured to be positioned above (e.g., directly vertically aligned with) contact structure 110 such that at least a portion of the outer surface of each of interconnect structure 114 and contact structure 110 is aligned with each other. In other words, the outer surface of each of interconnect structure 114 and contact structure 110 may be an elongated continuous portion of conductive material along at least one side. In an additional embodiment, interconnect structure 114 is not aligned with contact structure 110 such that the side surfaces of interconnect structure 114 and contact structure 110 are not aligned with each other along any of their sides. Figure 1B As shown, the interconnect structure 114 may be laterally offset (e.g., eccentrically or offset) to facilitate electrical connection with the contact structure 110. In other words, the vertical centerline of the interconnect structure 114 is eccentrically positioned relative to the vertical centerline of the contact structure 110.

[0066] refer to Figure 1CThe conductive material 116 may be formed on or above the upper surface of the first insulating material 102 and the upper surface 114a of the interconnect structure 114. The conductive material 116 may be formed using one or more conventional deposition processes, such as conventional ALD, conventional CVD, and conventional PVD processes. For example, the conductive material 116 may be formed as a substantially continuous flat material surface above the upper surface of the first insulating material 102 and above the upper surface 114a of the interconnect structure 114. In other words, the conductive material 116 may be formed as a substantially continuous portion of material without gaps or openings (e.g., trenches) formed in the first insulating material 102. The conductive material 116 may be substantially flat and may be present at the desired thickness of the subsequently formed conductive lines, as referenced. Figure 1D More detailed description. By initially shaping the conductive material 116 into a continuous portion of the conductive material, the conductive lines (e.g., data lines, bit lines) formed thereafter can be formed without using one or more damascene processes (e.g., single damascene or dual damascene processes).

[0067] The conductive material 116 may be formed of and contain a conductive material, such as one or more of the following: tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys, metallic materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and iridium oxide (IrO). x ), Ruthenium oxide (RuO) x The conductive material 116 may include one or more of the following materials, alloys thereof, conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium), polycrystalline silicon, and other materials exhibiting conductivity. In some embodiments, the conductive material 116 includes materials comprising one or more of the following: titanium, ruthenium, aluminum, and molybdenum, while substantially free of (e.g., substantially absent) tungsten. In some such embodiments, the conductive material 116 may contain at least some atoms of a precursor material (e.g., chlorine, carbon, oxygen) for forming the conductive material 116. The conductive material 116 may or may not contain a material composition substantially the same as that of the interconnect structure 114 and / or contact structure 110.

[0068] Return to reference Figure 1C Dielectric material 118 may be formed on or above the upper surface of conductive material 116. Dielectric material 118 may be selectively etched relative to conductive material 116 and / or subsequently formed material during common (e.g., collective, mutual) exposure to a first etchant, and conductive material 116 and / or subsequently formed material may be selectively etched relative to dielectric material 118 during common exposure to different second etchants.

[0069] In some embodiments, the dielectric material 118 also functions as a mask material (e.g., a mask, a photoresist material, an anti-reflective coating). The dielectric material 118 may also be referred to herein as a hard mask. As a non-limiting example, the dielectric material 118 may be formed from at least one of the following and may contain at least one of the following: amorphous carbon, silicon, silicon oxide, silicon nitride, silicon oxycarbide, aluminum oxide, and silicon oxynitride. In some embodiments, the dielectric material 118 is composed of at least one dielectric oxide material (e.g., SiO2 and AlO2). x It is formed of one or more of the following and includes at least one dielectric oxide material. In other embodiments, the dielectric material 118 is made of SiN. y Formed and containing SiN y The dielectric material 118 may be homogeneous (e.g., may comprise a single material) or non-homogeneous (e.g., may comprise a stack comprising at least two different materials). The dielectric material 118 may be formed using one or more conventional processes (e.g., conventional deposition processes) and conventional processing equipment, which are not described in detail herein. For example, the dielectric material 118 may be deposited (e.g., by one or more of CVD, PVD, ALD, spin coating) above the upper surface of the conductive material 116. In some embodiments, the dielectric material 118 is formed to have a dielectric structure 124 larger than that formed by the dielectric material 118. Figure 1D The initial height of the final height is determined so that the desired height of its individual parts (e.g., individual structures) can be achieved after subsequent processing actions, as described in further detail below.

[0070] Next reference Figure 1D The microelectronic device structure 100 may be patterned to form an opening 120 having an elongated portion extending in a second direction (e.g., the Y direction). The opening 120 may extend vertically (e.g., along the Z direction) through a dielectric material 118. Figure 1C ), conductive material 116 ( Figure 1C Each of the first insulating material 102 and at least a portion thereof. For example, opening 120 can be formed by transferring the pattern of the opening and features of the dielectric material 118 to a conductive material 116 overlying the first insulating material 102. The patterned dielectric material 118 can be used to selectively remove (e.g., selectively etch, selectively dry etch) the underlying material to form opening 120 by one or more etching processes (e.g., a single etching process). Opening 120 can be formed to have a desired depth, which can be selected at least in part based on the desired height of an air gap to be formed by subsequent processing of the microelectronic device structure 100, as referenced below. Figure 1E Further detailed description.

[0071] In some embodiments, dielectric material 118 ( Figure 1C ), conductive material 116 ( Figure 1C A portion of each of the conductive material 116 and the first insulating material 102 is removed, for example, by exposing the respective material to a wet etching and / or dry etching chemical reaction during one or more material removal processes. The formation of the opening 120 can be used to divide the conductive material 116 into portions to form a conductive structure 122 (e.g., a conductive line, data line, bit line) having elongated portions extending in a second direction, and to divide the dielectric material 118 into portions (e.g., segments) to form a dielectric structure 124 overlying the conductive structure 122 and having elongated portions extending in a second direction. The conductive structure 122 includes an upper surface 122a vertically adjacent to the dielectric structure 124 and a lower surface 122b vertically adjacent to the first insulating material 102. Therefore, the opening 120 can be positioned horizontally adjacent to each of the portions of the dielectric structure 124, the conductive structure 122, and the first insulating material 102. The opening 120 can also be formed by horizontally inserting (e.g., along the X direction) into segment 108 between the remaining portions of the first insulating material 102 that lie beneath the conductive structure 122. In other words, the remaining portions of the first insulating material 102 that are vertically adjacent to (e.g., beneath) the conductive structure 122 and separated on two lateral sides (e.g., in the Y direction) by the opening 120 are designated as segment 108 of the first insulating material 102, as... Figure 1D As shown in the diagram. By controlling the amount of material removed, the opening 120 can extend into a portion of the first insulating material 102, facilitating the subsequent air gap 132 (as shown). Figure 1E The formation of segment 108 adjacent to dielectric structure 124, conductive structure 122 and first insulating material 102 is described in further detail below.

[0072] In order to form the opening 120, the microelectronic device structure 100 (in a position) Figure 1D The processing stages depicted herein can be housed in conventional semiconductor tools (e.g., a single chamber of a material removal apparatus, an etching apparatus). The microelectronic device structure 100 can be exposed to one or more etchants using conventional processes (e.g., spin coating, spray coating, dip coating, vapor coating, immersion coating, combinations thereof) and conventional processing equipment, which are not described in detail herein. The total depth of the opening 120 can substantially correspond to the final height of the dielectric material 118 plus the height of the conductive material 116 plus the height of the segment 108 of the first insulating material 102. Similarly, the height of the air gap 132 can substantially correspond to the height of the dielectric structure 124 plus the height of the conductive structure 122 plus the height of the segment 108 of the first insulating material 102. Because the dielectric material 118 ( Figure 1CThe thickness of the dielectric material 118 may be reduced during the formation of the opening 120 due to the one or more material removal actions, and the dielectric material 118 may be initially formed to have an initial height (e.g., thickness) greater than the final height of the dielectric structure 124 formed by the dielectric material 118 in order to achieve the desired height of the dielectric structure 124.

[0073] Forming opening 120 included in the previous reference Figure 1C Following the described processing stages, the microelectronic device structure 100 is subtractively patterned to form a conductive structure 122 extending in a second direction (e.g., the Y direction), a dielectric structure 124 overlying the conductive structure 122, and a segment 108 underlying the conductive structure 122. For example, the opening 120 can be formed by providing an etch mask pattern comprising one or more of a resist, a hard mask, and an anti-reflective coating. For instance, the resist can be patterned using a photolithography process, and the pattern can be transferred to the underlying hard mask and / or anti-reflective layer. Alternative photolithography techniques are also possible, including processes that do not utilize hard mask layers. If one or more hard mask layers are included, the resist can be removed before the hard mask is used during etching of the underlying material. Therefore, the etch mask pattern can be provided by the resist and / or hard mask layers as the pattern is transferred to the underlying material. In some cases, the etch mask pattern blocks the area covered by the mask pattern to protect the underlying material from etching (e.g., wet or dry etching), while the etch mask pattern exposes the area not covered by the mask pattern to etch the exposed area of ​​the material to be etched.

[0074] In some embodiments, the subtractive patterning process comprises one or more (e.g., a single) material removal actions performed in a single chamber of a conventional semiconductor tool (e.g., a material removal apparatus, an etching apparatus). Because the opening 120 can be formed through the dielectric material 118, the conductive material 116, and the first insulating material 102 via a single etching action, the opening 120 extends vertically adjacent to (laterally adjacent to) the segment 108 of the dielectric structure 124, the conductive structure 122, and the first insulating material 102. By using the subtractive process, the opening 120 and the conductive structure 122 can be formed without using one or more damascene processes and without forming additional material adjacent to (e.g., beneath) the conductive structure 122 (e.g., a process required to facilitate damascene processes). Conventional device structures typically include another material, such as an etch-stopping material (e.g., a nitride material), situated between conventional conductive lines (e.g., bit lines) and conventional insulating materials (e.g., oxide materials). Such nitride materials are typically located adjacent to conventionally formed bitline vias and can be characterized as so-called "nitride etch-stop" materials, comprising a material composition different from that of the liner material 111 of the contact structure 110. According to embodiments of this disclosure, the interconnect structure 114 may be formed laterally adjacent to the first isolation material 102 (e.g., an oxide material), but not laterally adjacent to the nitride material. Therefore, forming the opening 120 and conductive structure 122 of the microelectronic device structure 100 using a subtractive patterning process provides an improvement over conventional processes (e.g., single damascene processes) by facilitating the formation of the opening 120 to the desired depth with a single process action, thereby eliminating process actions and avoiding unnecessary waste of additional isolation material (e.g., nitride material). The interconnect structure 114 may be located directly between the contact structure 110 and the conductive structure 122 and operatively coupled to them.

[0075] In some embodiments, portions of the interconnect structure 114 are removed during a subtractive patterning process. In such embodiments, the dielectric structure 124 and / or the conductive structure 122 are formed using a so-called “assisted self-alignment” process to self-align with the underlying conductive material (e.g., the interconnect structure 114). Thus, the dielectric structure 124 and the conductive structure 122 may be located above (e.g., directly vertically aligned with) the interconnect structure 114, such that one of the outer surfaces of each of the dielectric structure 124, the conductive structure 122, and the interconnect structure 114 is vertically aligned with each other. In other words, the outer surface of each of the dielectric structure 124, the conductive structure 122, and the interconnect structure 114 may be directly vertically aligned along at least one side thereof. Alternatively or additionally, at least some of the outer surfaces of the interconnect structure 114 may be adjacent to a first residual portion 126 (e.g., a remaining portion) of the first insulating material 102, which is laterally adjacent to the interconnect structure 114 and the opening 120 (e.g., between them) in a first direction (e.g., the X direction).

[0076] The opening 120 may extend vertically from the upper surface of the dielectric structure 124 to the first insulating material 102, but not to the upper vertical boundary of the contact structure 110 (e.g., the upper surface 110a). Therefore, the lower portion of the outer surface of the interconnect structure 114 may be laterally adjacent to the second residual portion 128 (e.g., the remaining portion) of the first insulating material 102, which is vertically adjacent in the vertical direction (e.g., the Z direction) to the upper surface 110a of the conductive structure 122 and the contact structure 110 (e.g., between them). In other words, the remaining portion of the first insulating material 102 (e.g., the first residual portion 126 and the second residual portion 128) may form an "L-shaped" structure of the first insulating material 102 near the upper surface 110a of the contact structure 110 and the interconnect structure 114, defining at least some openings 120 on at least two consecutive sides. The first residual portion 126 and the second residual portion 128 may protect the contact structure 110 and the interconnect structure 114 from subsequent process actions, such as material removal.

[0077] Each guide post structure 104, and its corresponding contact structure 110 and interconnect structure 114, are associated with a single (e.g., only one) conductive structure 122. For clarity and ease of understanding of the accompanying drawings and description, Figure 1D There are no additional guide post structures 104, nor the corresponding contact structures 110 and interconnect structures 114. In other words, from Figure 1DViewed from an angle (e.g., in the Y direction), each of the three (3) additional guide pillar structures 104 in each group of four (4) guide pillar structures 104 is positioned more than half a pitch deeper than the page and is associated with three (3) conductive structures 122 in each group of four (4) conductive structures 122. However, this disclosure is not limited thereto, and additional configurations of the guide pillar structures 104, contact structures 110, interconnect structures 114, and conductive structures 122 are contemplated.

[0078] Next reference Figure 1E The second insulating material 130 may be formed on or above the exposed upper surface of the dielectric structure 124 and may cover the opening 120. Figure 1D The second insulating material 130 may be formed in the opening 120, for example on the sidewalls of the dielectric structure 124, the conductive structure 122, and the segment 108. However, a large portion of the volume of the opening 120 may be substantially free of the second insulating material 130. The second insulating material 130 may be formed near the top of the opening 120 to seal unfilled spaces in the central portion therein, thereby forming one or more air gaps 132 (e.g., voids, unfilled volumes) within the central portion of the opening 120. In some embodiments, at least some of the air gaps 132 contain a gaseous material (e.g., air, oxygen, nitrogen, argon, helium, or combinations thereof). In other embodiments, the air gaps 132 contain a vacuum (e.g., a space completely free of matter). The air gaps 132 are partially defined by portions of the second insulating material 130 within and adjacent to the opening 120 (e.g., above it). The upper surface of the air gaps 132 is defined by the lower surface of the second insulating material 130 above the opening 120. The lower surface of the air gap 132 is defined by the surface of the first insulating material 102 within the opening 120, for example, the horizontal surface of the first insulating material 102 at the bottom of the opening 120. The sidewalls of the air gap 132 are defined by a second insulating material 130 within the opening 120 (e.g., on the sidewalls of the dielectric structure 124, the conductive structure 122, and the segment 108 of the first insulating material 102). Figure 1F As shown in more detail, the air gap 132 has a height H3 extending from the upper surface of the dielectric structure 124 to the surface of the first insulating material 102 at the bottom of the opening 120.

[0079] Air gap 132 is laterally adjacent to the dielectric structure 124, the conductive structure 122, and the first residual portion 126 of the first insulating material 102. For example, air gap 132 is laterally adjacent to the conductive structure 122, wherein a portion of air gap 132 extends above the plane of the upper surface 122a of the laterally adjacent conductive structure 122 (e.g., laterally adjacent to the dielectric structure 124), and a portion of air gap 132 extends below the plane of the lower surface 122b of the laterally adjacent conductive structure 122 (e.g., laterally adjacent to the interconnect structure 114 and / or the segment of the first insulating material 102). In other words, one or more (e.g., a single) air gaps 132 extend between laterally adjacent conductive structures 122, wherein the vertical extent of air gap 132 exceeds (e.g., is vertically higher and vertically lower than) the vertical extent of conductive structure 122. Because a portion of the air gap 132 extends above the midpoint of the air gap 132 and a portion of the air gap 132 extends below the midpoint of the air gap 132 of the conductive structure 122, the air gap 132 can be inserted laterally between adjacent conductive structures 122, and can exhibit a height relatively greater than the height of the conductive structure 122 in the vertical direction, as shown in the reference. Figure 1F More detailed description.

[0080] Air gap 132 can be formed at opening 120 ( Figure 1D The air gap 132 extends substantially through the height of the opening 120 after the second insulating material 130 is formed, within the central portion of the air gap 132. An elongated portion of the air gap 132 may extend in a second direction (e.g., the Y direction), wherein at least a portion of the air gap 132 is positioned adjacent to the conductive structure 122. Furthermore, the air gap 132 may be directly vertically aligned with at least a portion of the contact structure 110, such that at least a portion of the air gap 132 is located directly above (e.g., vertically aligned with) a portion of the contact structure 110. In some cases, the air gap 132 may be used as an insulating material having a dielectric constant (k) of approximately 1. The air gap 132 may limit capacitance (e.g., parasitic capacitance, stray capacitance) and increase short-circuit tolerance between laterally adjacent conductive structures 122, and may also reduce crosstalk between them.

[0081] In some embodiments, a portion of the second insulating material 130 is formed in the opening 120. Figure 1D The second insulating material 130 may be formed within and adjacent to the side surface (e.g., sidewall) of the segment 108 of the dielectric structure 124, the conductive structure 122, and / or the first insulating material 102. The second insulating material 130 may also contact the surface of the first insulating material 102 within the bottom portion of the opening 120. In other words, at least a portion of the second insulating material 130 may be formed in the opening 120 and adjacent to (e.g., laterally adjacent to) the dielectric structure 124 and the first residual portion 126, such as... Figure 1EAs shown in the diagram. Therefore, in some embodiments, at least a portion of the second insulating material 130 is laterally adjacent to the first insulating material 102. In other embodiments, at least some (e.g., each) openings 120 are substantially free of (e.g., substantially absent, substantially completely free of) the second insulating material 130, such that the lower vertical boundary of the second insulating material 130 is at or above the upper surface of the dielectric structure 124, while none of the second insulating materials 130 are located within the opening 120. The air gap 132 may be configured (e.g., sized, shaped, etc.) to reduce parasitic (e.g., stray) capacitance between adjacent conductive structures 122. In some embodiments, the air gap 132 exhibits a substantially rectangular profile in at least one horizontal direction (e.g., the X direction), for example, when the opening 120 is free of the second insulating material 130. In other embodiments, the air gap 132 exhibits a substantially disc-shaped profile, such as a "V-shaped" or "U-shaped" profile, which in embodiments includes a portion of the second insulating material 130 within the opening 120. In other embodiments, for example, the air gap 132 exhibits a substantially conical (e.g., frustum, inverted frustum, substantially Y-shaped) profile or a so-called "hourglass" (e.g., concave bow) profile.

[0082] The second insulating material 130 may be formed of at least one dielectric material and may contain at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phossilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO2). x C z N yThe second insulating material 130 is formed of and contains SiO2. In other embodiments, the second insulating material 130 is formed of and contains a low-k dielectric material. The second insulating material 130 may contain substantially the same material composition as the at least one dielectric material of the first insulating material 102 (e.g., an insulating structure in an alternating material stack), or may not contain said material composition. The second insulating material 130 may be substantially homogeneous or may be non-homogeneous. If the second insulating material 130 is non-homogeneous, then the amount of one or more elements contained in the second insulating material 130 may vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly, probabilistically). In some embodiments, the second insulating material 130 is substantially homogeneous. In other embodiments, the second insulating material 130 is non-homogeneous. For example, the second insulating material 130 may be formed of and contains a stack of at least two different dielectric materials (e.g., a laminate).

[0083] The second insulating material 130 can be formed using conventional processes (e.g., one or more of the following: conventional deposition processes such as spin coating, thick-layer coating, CVD and PVD; conventional material removal processes such as conventional CMP processes) and conventional processing equipment to obtain the air gap 132, which are not described in detail herein. For example, the second insulating material 130 can be formed on or above a portion of the exposed surface of the dielectric structure 124 using one or more conventional non-conformal deposition processes (e.g., at least one conventional non-conformal PVD process). Subsequently, the second insulating material 130 can undergo at least one conventional planarization process (e.g., at least one conventional CMP process) to promote or enhance the flatness of the upper boundary (e.g., upper surface) of the second insulating material 130. The dielectric structure 124 can be retained in the microelectronic device structure 100 after the formation of the second insulating material 130 to promote the formation of the air gap 132 adjacent to the conductive structure 122. By using the dielectric material 118 of the dielectric structure 124 during the subtractive patterning process ( Figure 1C The dielectric structure 124 serves more than one (e.g., dual) purpose by allowing the microelectronic device structure 100 to be formed adjacent to the conductive structure 122, and by allowing the microelectronic device structure 100 to be formed using fewer process actions and less material than conventional device structures.

[0084] Figure 1F yes Figure 1E An enlarged view of a portion of the microelectronic device structure 100. (See image.) Figure 1FAs shown, each air gap 132 may include an upper portion 132a, a central portion 132b (e.g., a midpoint), and a lower portion 132c. For illustrative purposes, the upper portion 132a and the lower portion 132c are separated by the central portion 132b. The central portion 132b may be laterally adjacent to the vertical midpoint 134 (e.g., the midpoint in the vertical direction) of the conductive structure 122, wherein, relative to the vertical midpoint 134 of the conductive structure 122, a portion of the air gap 132 extends above the central portion 132b of the air gap 132, and a portion of the air gap 132 extends below the central portion 132b of the air gap 132. In some embodiments, the upper portion 132a and the lower portion 132c are substantially the same height, such that the vertical height of the upper portion 132a of the air gap 132 is substantially the same as (e.g., substantially equal to) the vertical height of the lower portion 132c of the air gap 132.

[0085] Although the microelectronic device structure 100 is in Figure 1F The diagram shows a specific (e.g., symmetrical) orientation of the upper portion 132a and lower portion 132c of the air gap 132 relative to the vertical midpoint 134 of the conductive structure 122. However, such an arrangement is shown for illustrative purposes only, and any other (e.g., asymmetrical) orientation of the upper portion 132a and lower portion 132c of the microelectronic device structure 100 relative to the vertical midpoint 134 of the conductive structure 122 can be considered. For example, the upper portion 132a and lower portion 132c may extend at unequal heights above and below the central portion 132b, such that the height of the upper portion 132a of at least some air gaps 132 is different from (e.g., substantially not equal to) the height of the lower portion 132c. For example, in at least some air gaps 132, the height of the upper portion 132a may be greater than or alternatively less than the height of the lower portion 132c. The heights of the upper portion 132a and the lower portion 132c of the air gap 132 relative to the central portion 132b may be at least partially determined by the height of the dielectric structure 124 above the central portion 132b and the height of the opening 120 within the first insulating material 102. The vertical orientation of the air gap 132 may be customized (e.g., selected) to meet the design guidelines of a particular device structure.

[0086] Conductive material 116 of conductive structure 122 Figure 1C The conductive material 116 can be formed to have a desired height H1. The height H1 of the conductive material 116 can be selected at least in part based on the desired height of the conductive structure 122. As a non-limiting example, the height H1 of the conductive structure 122 can be in the range of about 5 nm to about 50 nm, for example, about 5 nm to about 10 nm, about 10 nm to about 20 nm, about 20 nm to about 30 nm, about 30 nm to about 40 nm, or about 40 nm to about 50 nm.

[0087] Dielectric material 118 of dielectric structure 124 Figure 1C It can be formed to have the desired height H2. (See above for reference.) Figure 1D As described, the dielectric material 118 may be initially configured to have a relatively large height in order to achieve the desired height H2 of the dielectric structure 124. The height H2 of the dielectric structure 124 may be at least partially based on the desired vertical offset (e.g., in the Z direction) between the conductive structure 122 and any additional structures to be formed on or above the dielectric structure 124 by subsequent processing of the microelectronic device structure 100. The height H2 of the dielectric structure 124 may be selected at least partially based on the desired height of the air gap 132 located between adjacent conductive structures 122 and extending above the central portion 132b. As a non-limiting example, the height H2 of the dielectric structure 124 may be in the range of about 5 nm to about 50 nm, for example, about 5 nm to about 10 nm, about 10 nm to about 20 nm, about 20 nm to about 30 nm, about 30 nm to about 40 nm, or about 40 nm to about 50 nm. In some embodiments, the height H2 of the dielectric structure 124 is substantially equal to the height H1 of the conductive structure 122.

[0088] As referenced above Figure 1E As described, the air gap 132 is laterally adjacent to the conductive structure 122, wherein the upper portion 132a of the air gap 132 extends above the plane of the upper surface 122a of the laterally adjacent conductive structure 122 (e.g., laterally adjacent to the dielectric structure 124), and the lower portion 132c of the air gap 132 extends below the plane of the lower surface 122b of the laterally adjacent conductive structure 122 (e.g., laterally adjacent to the segment 108 of the interconnect structure 114 and / or the first insulating material 102), but is not laterally adjacent to the contact structure 110. Therefore, the upper portion 132a of each air gap 132 extends laterally adjacent to the upper portion of the dielectric structure 124 and the conductive structure 122 (e.g., extending above its vertical midpoint 134), and the lower portion 132c extends laterally adjacent to the segment 108 of the interconnect structure 114 and / or the first insulating material 102 and laterally adjacent to the lower portion of the conductive structure 122 (e.g., extending below its vertical midpoint 134). The opening 120 may be formed to have a desired height H3. The height H3 of the opening 120 may be selected at least in part based on the desired height of the air gap 132 formed therein. In some embodiments, the height H3 of the air gap 132 corresponds to the height H3 of the opening 120. As a non-limiting example, the height H3 of the opening 120 and therefore the height H3 of the air gap 132 can be in the range of about 30 nm to about 200 nm, for example, about 30 nm to about 50 nm, about 50 nm to about 100 nm, about 100 nm to about 150 nm, or about 150 nm to about 200 nm. In some embodiments, the height H3 of the air gap 132 is in the range of about 50 nm to about 100 nm.

[0089] The height H3 of the air gap 132 can be relatively larger than the height H1 of the conductive structure 122 and the height H2 of the dielectric structure 124. The height H3 of the air gap 132 can also be relatively larger than the combined height of the conductive structure 122 (H1) and the dielectric structure 124 (H2), such as... Figure 1F As shown in the diagram. In some embodiments, the opening 120 has an aspect ratio (e.g., a high aspect ratio (HAR)) in the range of about 5:1 to about 40:1, such as between about 5:1 and about 10:1, between about 10:1 and about 20:1, or between about 20:1 and about 40:1. The height H3 of the opening 120, and therefore the height H3 of the air gap 132, may be relatively smaller than the depth D1 of the contact structure 110 within the microelectronic device structure 100. The depth D1 may correspond to the distance (e.g., in the Z direction) between the upper surface of the dielectric structure 124 and the upper surface 110a of the contact structure 110, such that at least some of the first insulating material 102 (e.g., its second residual portion 128) extends between the air gap 132 and the upper surface 110a of the contact structure 110. In other words, the second residual portion 128 separates the air gap 132 from the upper surface 110a of the contact structure 110.

[0090] Still referencing Figure 1F The interconnect structures 114 may each be formed having a width W1 (e.g., a horizontal dimension in the X direction), and the contact structures 110 may each be formed having a width W2 greater than the width W1 of the interconnect structures 114 (e.g., obtained from their upper surface 110a). As a non-limiting example, the width W1 of the interconnect structures 114 may be in the range of about 10 nm to about 100 nm, for example, about 10 nm to about 20 nm, about 20 nm to about 30 nm, about 30 nm to about 50 nm, or about 50 nm to about 100 nm, and the width W2 of the contact structures 110 may be in the range of about 20 nm to about 200 nm, for example, about 20 nm to about 50 nm, about 50 nm to about 100 nm, or about 100 nm to about 150 nm, or about 150 nm to about 200 nm. In some embodiments, the width W1 of the interconnect structure 114 is in the range of about 10 nm to about 50 nm, and the width W2 of the contact structure 110 is in the range of about 50 nm to about 150 nm.

[0091] The opening 120 and thus the air gap 132 (e.g., at its maximum horizontal extent) may each be formed having a width W3, and the conductive structure 122 may each be formed having a width W4 that is relatively smaller than the width W3 of the air gap 132. As a non-limiting example, the width W3 of the air gap 132 may be in the range of about 10 nm to about 100 nm, for example, about 10 nm to about 20 nm, about 20 nm to about 30 nm, about 30 nm to about 50 nm, or about 50 nm to about 100 nm, and the width W4 of the conductive structure 122 may be in the range of about 10 nm to about 100 nm, for example, about 10 nm to about 20 nm, about 20 nm to about 30 nm, about 30 nm to about 50 nm, or about 50 nm to about 100 nm. In some embodiments, the width W3 of the air gap 132 is in the range of about 20 nm to about 100 nm, and the width W4 of the conductive structure 122 is in the range of about 10 nm to about 60 nm. Furthermore, for example, the width W3 of the air gap 132 may be in the range of approximately 1% to approximately 500% (e.g., approximately 10% to approximately 250%, approximately 25% to approximately 125%, approximately 50% to approximately 100%) greater than the width W4 of the conductive structure 122. In other embodiments, the width W4 of the conductive structure 122 is greater than or alternatively substantially equal to the width W3 of the air gap 132.

[0092] Furthermore, the spacing 136 between horizontally adjacent conductive structures 122 can range from about 20 nm to about 200 nm, for example, about 20 nm to about 50 nm, about 50 nm to about 100 nm, or about 100 nm to about 200 nm. The spacing 136 includes a first width 136a corresponding to the width W4 of the conductive structure 122 and a second width 136b corresponding to the width W3 of the air gap 132. In some embodiments, the linewidth:space width ratio (e.g., the ratio of the width of the conductive structure 122 to the width of the air gap 132) is less than one (1). In other words, the width W4 of the conductive structure 122 is relatively smaller than the width W3 of the air gap 132. In other words, the lateral extent of the conductive structure 122 in at least one horizontal direction (e.g., in the X direction) is part of the lateral extent of the opening 120, and therefore part of the lateral extent of the air gap 132. In some embodiments, the linewidth:space width ratio (e.g., W4:W3 ratio) is substantially equal (e.g., 1:1). In other embodiments, the line-to-space ratio is greater than 1:1 (e.g., 60:40, 70:30, or 80:20). The line-to-space ratio can be customized to a desired value between the width W4 of the conductive structure 122 and the width W3 of the air gap 132, which can be selected at least in part based on the design requirements of the microelectronic device structure 100.

[0093] Continue to refer to Figure 1F as well as Figure 1EThe microelectronic device structure 100 may include a contact structure 110 on or above the conductive plug structure 106 of the post structure 104, and an interconnect structure 114 on or above the contact structure 110, as referenced above. Figure 1A and 1B As described above. The microelectronic device structure 100 may also include a conductive structure 122 on or above the interconnect structure 114, and a dielectric structure 124 on or above the conductive structure 122, as referenced above. Figure 1C and 1D As described. Contact structure 110 may contact interconnect structure 114 (e.g., direct physical contact), and interconnect structure 114 may contact conductive structure 122 (e.g., direct physical contact). Therefore, conductive structure 122 can be electrically contacted with post structure 104 via interconnect structure 114 and contact structure 110. Conductive structure 122, interconnect structure 114, and contact structure 110 may comprise one or more materials configured to reduce the resistivity of at least some of the conductive structures in order to provide increased conductivity within and between adjacent conductive structures.

[0094] exist Figure 1F In some embodiments, the conductive structure 122 may have a material composition different from that of each of the interconnect structure 114 and the contact structure 110. For example, the conductive structure 122 may include a material comprising one or more of the following: titanium, ruthenium, aluminum, and molybdenum, and at least one of the interconnect structure 114 and the contact structure 110 (e.g., each) is formed of tungsten and contains tungsten.

[0095] Furthermore, the conductive structure 122 may comprise a single-phase material (e.g., a β-phase material or an α-phase material). The conductive structure 122 (e.g., a data line, a bit line) may be formed of and comprise a conductive material, such as one or more of the following: tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys, metallic materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), comprising titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO). x ), Ruthenium oxide (RuO) xThe conductive structure 122 may contain one or more of the following materials, alloys thereof, conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium), polycrystalline silicon, and other materials exhibiting conductivity. In some embodiments, the conductive structure 122 includes materials comprising one or more of the following: titanium, ruthenium, aluminum, and molybdenum, but substantially free of (e.g., substantially absent) tungsten. In some such embodiments, the conductive structure 122 contains at least some atoms of a precursor material (e.g., chlorine, carbon, oxygen) for forming the conductive structure 122. Thus, the conductive structure 122 may substantially free of (e.g., substantially absent) halogen-containing precursors (e.g., fluorine) for forming tungsten-free materials (e.g., titanium, ruthenium, aluminum, or molybdenum), and the interconnect structure 114 and / or contact structure 110 may substantially free of (e.g., substantially absent) additional precursors (e.g., chlorine, carbon, oxygen) for forming tungsten-free materials (e.g., titanium, ruthenium, aluminum, or molybdenum).

[0096] Therefore, conductive structure 122 may have a material composition different from that of each of interconnect structure 114 and contact structure 110. Contact structure 110 and interconnect structure 114 may include tungsten, which exhibits different material properties than conductive structure 122. For example, each of contact structure 110 and interconnect structure 114 may exhibit different particle sizes, different electrical properties, and fewer impurities than conductive structure 122. In some embodiments, at least a portion of contact structure 110 and / or interconnect structure 114 includes tungsten with a particle size larger than that of the material in conductive structure 122. Because the particle size of the material may be at least partially based on the thickness (e.g., height) of the material, conductive structure 122 may exhibit a particle size in the range of about 0.1 times to about 10 times the thickness of conductive structure 122. In some embodiments, contact structure 110 and / or interconnect structure 114 exhibits a lower resistivity than conductive structure 122. Therefore, in some embodiments, interconnect structure 114 and / or contact structure 110 exhibit greater conductivity than conductive structure 122. The conductive structure 122 may be formed and comprised of a material tailored to reduce (e.g., minimize) voids that may appear during the formation of the conductive structure 122. Because the resistivity of the material may be at least partially based on the thickness (e.g., height) of the material, in some cases, such as when the thickness of the conductive structure 122 is reduced, the conductive structure 122 may exhibit a lower resistivity than the contact structure 110 and / or the interconnect structure 114.

[0097] Those skilled in the art will understand that, according to additional embodiments of this disclosure, the above description regarding... Figures 1A to 1F The described features and feature configurations can be used to meet the design needs of various microelectronic devices (e.g., various memory devices). As a non-limiting example, according to additional embodiments of this disclosure, Figure 1GA simplified partial cross-sectional view is shown of a method for forming a microelectronic device structure having a configuration different from that of microelectronic device structure 100. Throughout the remaining description and figures, features with similar functions (e.g., structures, devices) are referred to by similar reference numerals. To avoid repetition, the remaining figures (including...) Figure 1G Not all features shown in the figures are described in detail herein. Rather, unless otherwise described below, features indicated by reference numerals of previously described features (whether the previously described features were described before or after the current paragraph) should be understood to be substantially similar to the previously described features.

[0098] Figure 1G A simplified partial cross-sectional view of the microelectronic device structure 100′ is shown. Figure 1G At the processing stage depicted, the microelectronic device structure 100′ can be substantially similar to that in the process described. Figure 1E The microelectronic device structure 100 depicted in the processing stage is shown in the image. Furthermore... Figure 1G yes Figure 1E An enlarged view of a portion of the microelectronic device structure 100.

[0099] Figure 1G The microelectronic device structure 100' may be included in the guide pillar structure 104 ( Figure 1E The conductive plug structure 106 ( Figure 1E The contact structure 110 is located on or above the contact structure 110, and includes an interconnection structure 114 on or above the contact structure 110, as... Figure 1F The previous embodiment. The microelectronic device structure 100' may also include a conductive structure 122 on or above the interconnect structure 114, and a dielectric structure 124 on or above the conductive structure 122. The contact structure 110 may contact the interconnect structure 114 (e.g., direct physical contact), and the interconnect structure 114 may contact the conductive structure 122 (e.g., direct physical contact). Thus, the conductive structure 122 can be connected to the post structure 104 (through the interconnect structure 114 and the contact structure 110) Figure 1E Electrical contact. However, in Figure 1GIn some embodiments, conductive structure 122 may have a material composition substantially the same as that of interconnect structure 114. In some such embodiments, each of conductive structure 122 and interconnect structure 114 has a material composition different from that of contact structure 110. For example, conductive structure 122 and interconnect structure 114 may each include a material comprising one or more of the following: titanium, ruthenium, aluminum, and molybdenum, and contact structure 110 may include tungsten. In some embodiments, each of conductive structure 122 and interconnect structure 114 includes a material comprising one or more of the following: titanium, ruthenium, aluminum, and molybdenum, but substantially free of (e.g., substantially absent) tungsten. In some such embodiments, conductive structure 122 and interconnect structure 114 may each include at least some atoms of a precursor material (e.g., chlorine, carbon, oxygen) for forming conductive structure 122 and interconnect structure 114. Therefore, the conductive structure 122 and the interconnect structure 114 may each be substantially free of (e.g., substantially absent) halogen-containing precursors (e.g., fluorine) for forming tungsten, and the contact structure 110 may be substantially free of (e.g., substantially absent) additional precursors (e.g., chlorine, carbon, oxygen) for forming tungsten-free materials (e.g., titanium, ruthenium, aluminum, or molybdenum).

[0100] Contact structures 110 and / or interconnect structures 114 may be grown or deposited (e.g., by ALD, CVD, pulsed CVD, metal-organic CVD, PVD) within the corresponding contact openings and openings in the first insulating material 102, as... Figure 1F The previous embodiments. However, in Figure 1G In some embodiments, the interconnect structure 114 may contain substantially the same material composition as the conductive structure 122 (e.g., a single-phase material), but does not contain lining material 113 within the opening of the first insulating material 102. Figure 1F Furthermore, there may be no easily identifiable physical interface between the lower surface 122b of the conductive structure 122 and the upper surface 114a of the interconnect structure 114, such as... Figure 1G As shown in the figure. In some embodiments, the conductive structure 122 is formed during the formation of the interconnect structure 114. For example, the formation of the conductive structure 122 may be performed substantially simultaneously with the formation of the interconnect structure 114 to simplify the manufacturing process. Thus, the conductive structure 122, the interconnect structure 114, and the contact structure 110 may comprise one or more material compositions formulated to reduce the resistivity of at least some of the conductive structures in order to provide increased conductivity within and between adjacent conductive structures.

[0101] As described above, the formation Figure 1FThe microelectronic device structure 100 of the embodiment includes a conductive structure 122 formed of a first material (e.g., titanium, ruthenium, aluminum, and molybdenum) and a contact structure 110 and an interconnect structure 114 formed of a different second material (e.g., tungsten), or alternatively formed. Figure 1G The microelectronic device structure 100′ of the embodiment includes a conductive structure 122 and an interconnect structure 114 formed of a first material (e.g., titanium, ruthenium, aluminum, and molybdenum) and a contact structure 110 formed of a different second material (e.g., tungsten), which can promote performance improvements of the microelectronic device structures 100, 100′.

[0102] For example, different materials of adjacent structures (e.g., conductive structure 122 and contact structure 110 and / or interconnect structure 114) can provide a reduced resistivity (e.g., resistance level) of the conductive material. In some embodiments, the conductive material exhibits a resistance that is about 1% to about 50% or higher than the resistance of the conductive material in a conventional structure of a 3D NAND structure. For example, while a conventional conductive structure may exhibit a resistance of about 13 Ω·μm, the conductive structure of the embodiments of this disclosure may exhibit a resistance of about 5 Ω·μm. Lower resistance can be achieved without forcing an increase in the spacing or critical dimension (CD) of adjacent structures. Therefore, reduced resistivity can be achieved even as the spacing or CD of adjacent structures continues to decrease to a smaller value and as the thickness (e.g., height in the Z direction) of the conductive structure continues to decrease.

[0103] Furthermore, because the contact structures 110 and / or interconnect structures 114, having different second material compositions, are formed adjacent to the conductive structure 122 having a first material composition, at least one of the contact structures 110 and interconnect structures 114 may exhibit a lower resistivity relative to the conductive structure 122. Since the conductive structure 122 may be formed and comprised of a material composition tailored to reduce (e.g., minimize) voids, the conductive structure 122 may be selected to improve properties during the formation (e.g., deposition, growth) of such a material, and the contact structures 110 and / or interconnect structures 114 may be selected to improve properties (e.g., reduce resistivity) during the use and operation of the microelectronic device structure 100. Alternatively, because conductive structures 122 and interconnect structures 114 can be formed and comprised of a material composition tailored to reduce (e.g., minimize) voids, conductive structures 122 and interconnect structures 114 can be selected to improve properties during the formation (e.g., deposition, growth) of such materials, and contact structures 110 can be selected to improve properties (e.g., reduce resistivity) during the use and operation of microelectronic device structures 100'. Furthermore, conductive structures 122 and, in some cases, interconnect structures 114 may not contain halides, such as fluorine, which may be present in conductive structures forming halide-containing precursors. Reduced resistivity of the conductive structures can improve the performance of microelectronic device structures 100, 100'.

[0104] The microelectronic device structures formed according to the embodiments described herein can exhibit improved performance by reducing the occurrence of voids during the formation of the conductive material (e.g., conductive structure 122). Further performance improvements can be achieved by the conductive structure 122 comprising a first material composition and the contact structure 110 and / or the interconnect structure 114 comprising a different second material composition, or alternatively by the conductive structure 122 and the interconnect structure 114 comprising a first material composition and the contact structure 110 comprising a different second material composition; these configurations can exhibit improved performance compared to conventional microelectronic device structures.

[0105] Furthermore, by using a subtractive manufacturing process, the critical dimension (e.g., width) of the conductive structure 122 can be relatively smaller than the critical dimension (e.g., width) of the air gap 132 laterally inserted therebetween, thereby reducing the parasitic capacitance between adjacent conductive structures 122. Because the opening 120 is laterally adjacent to the conductive structure 122, with a portion of the opening 120 extending above the plane of the upper surface 122a of the laterally adjacent conductive structure 122 (e.g., laterally adjacent to the dielectric structure 124), and a portion of the opening 120 extending below the plane of the lower surface 122b of the laterally adjacent conductive structure 122 (e.g., laterally adjacent to the dielectric structure 124 and the first insulating material 102), the air gap 132 located within the opening 120 is laterally adjacent to the conductive structure 122, with a portion of the air gap 132 extending above the plane of the upper surface 122a of the laterally adjacent conductive structure 122, and a portion of the air gap 132 extending below the plane of the lower surface 122b of the laterally adjacent conductive structure 122, thereby further reducing the parasitic capacitance between adjacent conductive structures 122. The air gap 132 according to embodiments of this disclosure can reduce the capacitance between adjacent conductive structures 122 by up to 65%. In some cases, the reduced capacitance can, in turn, provide a reduction in programming time of about 5% to about 10%. The extension of the air gap 132 below the conductive structure 122 also allows for a reduction in parasitic capacitance between laterally adjacent interconnect structures 114. By using the air gap 132 to reduce parasitic capacitance between adjacent conductive structures 122, different material compositions (e.g., low-resistivity conductive materials) can be used within the conductive structures 122, interconnect structures 114, and / or contact structures 110. Additionally, by using subtractive processing and the resulting material, at least one critical dimension (e.g., width, height) of the conductive structure 122 can be relatively smaller than the critical dimensions of conventional conductive lines (e.g., bit lines) in conventional device structures. Therefore, the RC (resistance and capacitance product) of the conductive structure 122 can be optimized, which can be associated with increased performance of devices containing microelectronic device structures 100, 100' due to the reduction in operating speed (e.g., programming time). Furthermore, the methods of this disclosure can reduce or eliminate process actions, such as the formation of etch-stop materials used to form many conventional devices that can be used for operations similar to those of the microelectronic device structures 100, 100'. By using a single material removal action within a single chamber, the microelectronic device structures 100, 100' according to embodiments of this disclosure are formed using fewer process actions than conventional device structures. In some cases, the number of process actions can be reduced by half compared to conventional process actions.

[0106] Therefore, according to embodiments of this disclosure, a microelectronic device includes: a post structure extending vertically through an insulating material; a conductive wire electrically coupled to the post structure; a contact structure between the post structure and the conductive wire; and an interconnect structure between the conductive wire and the contact structure. The conductive wire includes one or more of titanium, ruthenium, aluminum, and molybdenum. The interconnect structure includes a material composition different from that of the contact structure and one or more of the material compositions of the conductive wire.

[0107] Furthermore, according to an additional embodiment of this disclosure, a method of forming a microelectronic device includes: forming a post structure extending vertically through an insulating material; forming a contact structure above the post structure; forming an interconnect structure above the contact structure; and forming a conductive wire electrically coupled to the post structure through the contact structure and the interconnect structure. The conductive wire includes one or more of titanium, ruthenium, aluminum, and molybdenum, and the interconnect structure includes a material composition different from that of the contact structure and one or more of the material compositions of the conductive wire.

[0108] Microelectronic device structures according to embodiments of the present disclosure (e.g., in previous references) Figures 1A to 1G The described processed microelectronic device structures 100, 100' can be included in a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). For example, Figure 2 A simplified partial cross-sectional view of a microelectronic device 201, including a microelectronic device structure 200, is shown. The microelectronic device structure 200 may be substantially similar to that in the previous reference. Figures 1A to 1G The described processed microelectronic device structures 100 and 100' are shown. (Through) Figure 2 The descriptions associated below are similar in function to those in the previous references. Figures 1A to 1G Features (e.g., structure, material, region) of one or more of the microelectronic device structures 100, 100′ described herein are referred to by reference numerals similarly prefixed with 100. To avoid duplication, Figure 2 Not all of the features shown are described in detail herein. Instead, unless otherwise described below, they are not all described in detail. Figure 2 In the middle, using the previous reference Figures 1A to 1G The addition of 100 to the reference numerals of one or more described features in the figures indicates that the features are substantially similar to those previously described and are formed in substantially the same manner as those previously described.

[0109] like Figure 2 As shown, the microelectronic device structure 200 of the microelectronic device 201 (including the previously referenced) Figures 1A to 1GOne or more of the components described herein may be operatively associated with the stacked structure 242 of the microelectronic device 201. The stacked structure 242 includes a vertically alternating (e.g., in the Z direction) sequence of additional conductive structures 244 (e.g., access lines, word lines) and insulating structures 246 arranged in layers 248. Additionally, as Figure 2 As shown, the stacked structure 242 includes a memory array region 242A and a stepped region 242B that is horizontally adjacent to the memory array region 242A (e.g., in the X direction). As described in further detail below, the microelectronic device 201 further includes additional components (e.g., features, structures, devices) within the horizontal boundaries of the different regions (e.g., memory array region 242A and stepped region 242B) of the stacked structure 242.

[0110] Each layer 248 of the stacked structure 242 of the microelectronic device 201 may each include at least one of the additional conductive structures 244 vertically adjacent to at least one of the insulating structures 246. The stacked structure 242 may include the desired number of layers 248. For example, the stacked structure 242 may include eight or more (8) layers 248, sixteen or more (16) layers 248, thirty-two or more (32) layers 248, sixty-four or more (64) layers 248, one hundred and twenty-eight (128) layers 248, or two hundred and fifty-six (256) layers 248 of the additional conductive structures 244 and insulating structures 246.

[0111] The additional conductive structure 244 of the layer 248 of the stacked structure 242 may be formed of and contain at least one conductive material, such as one or more of the following: at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co, Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, low-carbon steel, stainless steel), at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe), and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the additional conductive structure 244 is formed of and comprises a metallic material (e.g., a metal such as tungsten; an alloy). In other embodiments, the additional conductive structure 244 is formed of and comprises one or more of titanium, ruthenium, aluminum, and molybdenum, but substantially free of (e.g., substantially absent) tungsten. In an additional embodiment, the additional conductive structure 244 is formed of and comprises conductive-doped polysilicon. Each of the additional conductive structures 244 may be substantially uniform, or one or more of the additional conductive structures 244 may be substantially non-uniform. In some embodiments, each additional conductive structure 244 in the stacked structure 242 is substantially uniform. In an additional embodiment, at least one (e.g., each) of the additional conductive structures 244 in the stacked structure 242 is non-uniform. For example, each additional conductive structure 244 may be formed of and comprise a stack of at least two different conductive materials. The additional conductive structures 244 of each layer 248 in the stacked structure 242 may be substantially flat and may each exhibit a desired thickness.

[0112] The insulating structure 246 of layer 248 of stacked structure 242 may be formed of at least one dielectric material and may contain at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO xOne or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbon oxynitride material (e.g., SiO2) x C z N y In some embodiments, the insulating structure 246 is formed of and contains SiO2. Each of the insulating structures 246 may be substantially uniform, or one or more of the insulating structures 246 may be substantially non-uniform. In some embodiments, each insulating structure 246 in the stacked structure 242 is substantially uniform. In additional embodiments, at least one (e.g., each) insulating structure 246 of the stacked structure 242 is non-uniform. For example, each insulating structure 246 may be formed of and contain a stack of at least two different dielectric materials. The insulating structure 246 of each layer 248 in the stacked structure 242 may be substantially flat and may each exhibit a desired thickness.

[0113] At least one lower additional conductive structure 244 of the stacked structure 242 may serve as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of the microelectronic device 201. In some embodiments, a single (e.g., only one) additional conductive structure 244 of the vertical bottommost layer 248 of the stacked structure 242 may serve as the lower select gate (e.g., SGS) of the microelectronic device 201. In some embodiments, the upper conductive structure 244 of the stacked structure 242 may serve as the upper select gate (e.g., drain-side select gate (SGD)) of the microelectronic device 201. In some embodiments, horizontally adjacent (e.g., in the Y direction) additional conductive structures 244 in the vertical topmost layer 248 of the stacked structure 242 may serve as the upper select gate (e.g., SGD) of the microelectronic device 201. In yet another embodiment, the upper select gate of the microelectronic device 201 may be located vertically above the stacked structure 242 (e.g., within an additional stacked structure of a multi-stacked device).

[0114] Still referencing Figure 2 Within the horizontal boundaries (e.g., in the X and Y directions) of the memory array region 242A of the stacked structure 242, the microelectronic device 201 may include a guide pillar structure 204 extending vertically through the stacked structure 242. Figure 2 As shown, the guide pillar structure 204 can be formed to extend substantially vertically through the stacked structure 242. The guide pillar structure 204, comprising channel material surrounding the unit membrane 204a of the filler material 204b, can correspond to a previously referenced document. Figure 1AThe described structure includes a guide post structure 104 comprising a channel material surrounding a unit membrane 104a with a filling material 104b. For clarity and ease of understanding of the accompanying drawings and description, the conductive plug structure 206 is... Figure 2 It does not exist in [the text], and is described as a reference above. Figure 1A The described conductive plug structure 106.

[0115] The microelectronic device structure 200 can be formed as a guide pillar structure 204 containing the desired quantity (e.g., number, quantity). Although Figure 2 The microelectronic device structure 200 is depicted as comprising three (3) pillar structures 204, but the microelectronic device structure 200 may be formed to comprise more than three (3) pillar structures 204 (e.g., greater than or equal to eight (8), greater than or equal to sixteen (16), greater than or equal to thirty-two (32), greater than or equal to sixty-four (64), greater than or equal to one hundred and twenty-eight (128), greater than or equal to two hundred and fifty-six (256)). The intersection of the pillar structures 204 and the additional conductive structures 244 of the layers 248 of the stacked structure 242 may define vertically extending strings 256 of memory cells coupled in series with each other within the memory array region 242A of the stacked structure 242. In some embodiments, the memory cells 256 formed in each layer 248 of the stacked structure 242 at the intersection of the additional conductive structures 244 and the pillar structures 204 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In an additional embodiment, memory cell 256 includes a so-called "TANOS" (tantalum nitride-alumina-nitride-oxide-semiconductor) memory cell or a so-called "BETANOS" (band / barrier engineered TANOS) memory cell, each of which is a subset of MONOS memory cells. In other embodiments, memory cell 256 includes a so-called "floating gate" memory cell, incorporating a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally inserted between the pillar structures 204 of the different layers 248 of the stacked structure 242 and the central structure of the additional conductive structure 244. Microelectronic device 201 may include any desired amount and any desired distribution of pillar structures 204 within the memory array region 242A of the stacked structure 242.

[0116] The microelectronic device 201 may further include a conductive structure 222 (e.g., a digital line, data line, bit line) vertically overlying the stacked structure 242, at least one source structure 260 (e.g., a source line, source plate) vertically underlying the stacked structure 242, and at least one control device 258 vertically underlying the source structure 260. A post structure 204 may extend vertically between the conductive structure 222 and the source structure 260 (e.g., in the Z direction). The source structure 260 may extend vertically between the stacked structure 242 and the control device 258. The conductive structure 222 and the source structure 260 may each be formed of and contain at least one conductive material, such as one or more of the following: metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. As a non-limiting example, the conductive structure 222 and / or the source structure 260 may be formed from one or more of the following and include one or more of the following: W, WNy, Ni, Ta, TaNy, TaSix, Pt, Cu, Ag, Au, Al, Mo, Ti, TiNy, TiSix, TiSixNy, TiAlxNy, MoNx, Ir, IrOz, Ru, RuOz, and at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe). The microelectronic device 201 may further include a dielectric structure 224 on or above the conductive structure 222 and an air gap 232 horizontally adjacent to the adjacent conductive structure 222. The dielectric structure 224 and the air gap 232 may correspond respectively to the previously referenced materials. Figure 1D to 1G The dielectric structure 124 and air gap 132 are described.

[0117] Continue to refer to Figure 2 The control device 258 may include means and circuitry for controlling various operations of other components of the microelectronic device structure 200. As a non-limiting example, the control device 258 may include one or more of the following (e.g., each): a charge pump (e.g., V... CCP Charge pump, V NEGWL Charge pumps (e.g., DVC2 charge pumps); Delay-locked loop (DLL) circuit systems (e.g., ring oscillators); Drain supply voltage (V ddThe device includes: a regulator; means and circuitry for controlling column operations of an array (e.g., a vertical memory string array) to be formed within the microelectronic device structure 200, such as one or more of the following (e.g., each): a decoder (e.g., a column decoder), a sense amplifier (e.g., an equalization (EQ) amplifier, an isolation (ISO) amplifier, an NMOS sense amplifier (NSA), a PMOS sense amplifier (PSA)), a repair circuitry (e.g., a column repair circuitry), an I / O device (e.g., a local I / O device), a memory test device, an array multiplexer (MUX), and an error checking and correction (ECC) device; and means and circuitry for controlling row operations of an array (e.g., a vertical memory string array) within the memory region of the microelectronic device structure 200, such as one or more of the following (e.g., each): a decoder (e.g., a row decoder), a driver (e.g., a word line (WL) driver), a repair circuitry (e.g., a row repair circuitry), a memory test device, a MUX, an ECC device, and a self-refresh / wear-out equalizer. In some embodiments, the control device 258 includes a complementary metal-oxide-semiconductor (CMOS) circuit system. In such embodiments, the control device 258 may be characterized as having an "array-under CMOS" ("CuA") configuration.

[0118] Within the horizontal boundary of the stepped region 242B of the stacked structure 242, the stacked structure 242 may include at least one stepped structure 250. The stepped structure 250 includes steps 252 that are at least partially defined by the horizontal ends of the layers 248 (e.g., in the X direction). The steps 252 of the stepped structure 250 can serve as contact areas for electrically coupling additional conductive structures 244 of the layers 248 of the stacked structure 242 to other components (e.g., features, structures, devices) of the microelectronic device 201, as described in further detail below. The stepped structure 250 may include the desired amount of steps 252. Additionally, as Figure 2 As shown, in some embodiments, the steps 252 of each stepped structure 250 are arranged sequentially such that steps 252 that are directly horizontally adjacent to each other (e.g., in the X direction) correspond to layers 248 of stacked structures 242 that are directly vertically adjacent to each other (e.g., in the Z direction). In additional embodiments, the steps 252 of the stepped structures 250 are arranged randomly such that at least some steps 252 of the stepped structures 250 that are directly horizontally adjacent to each other (e.g., in the X direction) correspond to layers 248 of stacked structures 242 that are not directly vertically adjacent to each other (e.g., in the Z direction).

[0119] Still referencing Figure 2The microelectronic device 201 may further include a lower conductive structure 254 (e.g., a conductive contact structure, such as a word line contact area structure) that is physically and electrically contacted with at least some (e.g., each) of the steps 252 of the stepped structure 250 of the stacked structure 242 to provide electrical access to the additional conductive structure 244 of the stacked structure 242. The lower conductive structure 254 may be coupled to the additional conductive structure 244 of the layer 248 of the stacked structure 242 at the steps 252 of the stepped structure 250. Figure 2 As shown, the lower conductive structure 254 can physically contact the additional conductive structure 244 at the step 252 of the stepped structure 250 and extend vertically upward therefrom (e.g., in the positive Z direction) to the lower contact structure 262 of the additional structure (e.g., access device, vertical transistor) that may be on or above the lower contact structure 262.

[0120] The microelectronic device 201 may further include a first insulating material 202 on or above the stacked structure 242 and a second insulating material 230 on or above the first insulating material 202. The first insulating material 202 and the second insulating material 230 may correspond to previously referenced materials, respectively. Figures 1A to 1G The first insulating material 102 and the second insulating material 130 are described. (Example) Figure 2As shown, a first insulating material 202 may be vertically inserted (e.g., in the Z direction) between the stacked structure 242 and the second insulating material 230. The first insulating material 202 may substantially cover the stepped structure 250 within the stepped region 242B of the stacked structure 242 and may substantially surround the side surface (e.g., sidewall) of the lower conductive structure 254 on the steps 252 of the stepped structure 250. The first insulating material 202 may exhibit a substantially flat upper vertical boundary and a substantially uneven lower vertical boundary that is at least complementary to the surface morphology of the stacked structure 242 (including its stepped structure 250) below it. The second insulating material 230 may substantially cover the upper surface of the dielectric structure 224 within the memory array region 242A of the stacked structure 242. The second insulating material 230 may be formed to seal unfilled spaces between adjacent conductive structures 222 to form an air gap 232 (e.g., void, unfilled volume) therebetween. Air gap 232 is laterally adjacent to conductive structure 222, with a portion of air gap 232 extending above the plane of the upper surface of the laterally adjacent conductive structure 222 (e.g., laterally adjacent to dielectric structure 224), and a portion of air gap 232 extending below the plane of the lower surface of the laterally adjacent conductive structure 222 (e.g., laterally adjacent to a segment of interconnect structure 214 and / or first insulating material 202). In some embodiments, a portion of second insulating material 230 may be laterally adjacent to a side surface (e.g., a sidewall) of first insulating material 202. Contact structure 210 may be located on or above the uppermost surface of conductive plug structure 206 within the upper portion of post structure 204. Contact structure 210 may correspond to a previously referenced herein. Figure 1A The contact structure 110 is described.

[0121] Therefore, according to an additional embodiment of this disclosure, a memory device includes: a vertically extending string of memory cells; an access line electrically connected to the vertically extending string of memory cells and extending along a first horizontal direction; and a data line electrically connected to the vertically extending string of memory cells and extending along a second horizontal direction, the second horizontal direction being substantially transverse to the first horizontal direction. The memory device includes: an interconnect structure vertically inserted between and electrically connected to the data line and the vertically extending string of memory cells; and a contact structure vertically inserted between and electrically connected to the interconnect structure and the vertically extending string of memory cells. The contact structure comprises tungsten, and the data line comprises a single-phase material, including ruthenium or molybdenum.

[0122] According to embodiments of this disclosure, microelectronic devices including microelectronic devices (e.g., microelectronic device 201) and microelectronic device structures including the following (e.g., microelectronic device structures 100, 100', 200) can be used in embodiments of the electronic systems of this disclosure: including a conductive structure 122 composed of a first material and contact structures 110 and / or interconnect structures 114 composed of different second materials, or including a conductive structure 122 and interconnect structures 114 composed of a first material and contact structures 110 composed of different second materials. For example, Figure 3 This is a block diagram of an electronic system 303 according to an embodiment of the present disclosure. The electronic system 303 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 303 includes at least one memory device 305. Memory device 305 may include, for example, the microelectronic device structures previously described herein (e.g., microelectronic device structures 100, 100', 200) or previously referenced... Figures 1A to 1G and Figure 2 The described embodiment of the microelectronic device (e.g., microelectronic device 201) includes different material compositions of conductive structure 122, interconnect structure 114, and contact structure 110.

[0123] The electronic system 303 may further include at least one electronic signal processor device 307 (generally referred to as a “microprocessor”). The electronic signal processor device 307 may optionally include the microelectronic devices or microelectronic device structures previously described herein (e.g., previously referenced...). Figures 1A to 1G and Figure 2 The embodiments described are of the microelectronic device 201 or one or more of the microelectronic device structures 100, 100', 200. The electronic system 303 may further include one or more input devices 309 for a user to input information into the electronic system 303, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 303 may further include one or more output devices 311 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 309 and output device 311 may include a single touchscreen device that can simultaneously input information into the electronic system 303 and output visual information to the user. The input device 309 and output device 311 may be electrically connected to one or more of the memory device 305 and the electronic signal processor device 307.

[0124] refer to Figure 4 The present invention describes a processor-based system 400. The processor-based system 400 may include various microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 201 or microelectronic device structures 100, 100', 200). The processor-based system 400 may be any of various types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic device. The processor-based system 400 may include one or more processors 402, such as microprocessors, for controlling system functions and request processing in the processor-based system 400. The processor 402 and other sub-components of the processor-based system 400 may include microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 201 or microelectronic device structures 100, 100', 200).

[0125] The processor-based system 400 may include a power source 404 operatively connected to the processor 402. For example, if the processor-based system 400 is a portable system, the power source 404 may include one or more of the following: a fuel cell, a power scavenging device, a permanent battery, a replaceable battery, and a rechargeable battery. The power source 404 may also include an AC adapter; thus, the processor-based system 400 can be plugged into, for example, a wall socket. The power source 404 may also include a DC adapter, allowing the processor-based system 400 to be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0126] Depending on the functions performed by the processor-based system 400, various other devices may be coupled to the processor 402. For example, a user interface 406 may be coupled to the processor 402. The user interface 406 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 408 may also be coupled to the processor 402. The display 408 may include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projector, an audio display, or combinations thereof. Furthermore, an RF subsystem / baseband processor 410 may also be coupled to the processor 402. The RF subsystem / baseband processor 410 may include antennas coupled to an RF receiver and an RF transmitter (not shown). One or more communication ports 412 may also be coupled to the processor 402. Communication port 412 can be used to couple to one or more peripheral devices 414, such as modems, printers, computers, scanners or cameras, or to networks, such as local area networks, remote area networks, intranets or the Internet.

[0127] Processor 402 can control processor-based system 400 by implementing software programs stored in memory. The software programs may include, for example, operating systems, database software, drafting software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 402 to store various programs and facilitate their execution. For example, processor 402 may be coupled to system memory 416, which may include one or more of the following: spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), particle orbital memory, and other known memory types. System memory 416 may include volatile memory, non-volatile memory, or combinations thereof. System memory 416 is typically large enough to store dynamically loaded application programs and data. In some embodiments, system memory 416 may include semiconductor devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 201 and microelectronic device structures 100, 100', 200), or combinations thereof.

[0128] Processor 402 may also be coupled to non-volatile memory 418, which does not mean that system memory 416 must be volatile. Non-volatile memory 418 may include one or more of the following: STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory used in conjunction with system memory 416. The size of non-volatile memory 418 is typically chosen to be just large enough to store any required operating system, applications, and fixed data. In addition, non-volatile memory 418 may include mass storage, such as disk drive memory, such as a hybrid drive containing resistive memory or other types of non-volatile solid-state memory. Non-volatile memory 418 may include microelectronic devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 201 and microelectronic device structures 100, 100', 200), or combinations thereof.

[0129] Therefore, in at least some embodiments, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: a string of memory cells extending vertically through a stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; an additional conductive structure substantially tungsten-free and covering the string of memory cells; and an interconnection structure between the string of memory cells and the additional conductive structure. The interconnection structure includes a beta-phase tungsten lining material substantially surrounding an alpha-phase tungsten-filled material.

[0130] Compared to conventional structures, devices, and systems, the microelectronic device structures, devices, and systems of this disclosure advantageously facilitate one or more of the following: increased simplicity, greater package density, and increased component miniaturization. The methods and structures of this disclosure facilitate the formation of devices (e.g., apparatus, microelectronic devices, memory devices) and systems (e.g., electronic systems) having one or more of the following: improved performance, reliability, and durability; lower cost; increased yield; increased component miniaturization; improved pattern quality; and greater package density compared to conventional devices (e.g., conventional apparatus, conventional microelectronic devices, conventional memory devices) and conventional systems (e.g., conventional electronic systems).

[0131] The embodiments of this disclosure may be further characterized in the manner described below, but not limited to the manner described below.

[0132] Example 1: A microelectronic device comprising: a post structure extending vertically through an insulating material; a conductive wire electrically coupled to the post structure, the conductive wire comprising one or more of titanium, ruthenium, aluminum, and molybdenum; a contact structure between the post structure and the conductive wire; and an interconnection structure between the conductive wire and the contact structure, the interconnection structure comprising a material composition different from that of the contact structure and one or more of the material compositions of the conductive wire.

[0133] Example 2: The microelectronic device according to Example 1, wherein the conductive lines directly physically contact the interconnect structure, and the interconnect structure directly physically contacts the contact structure.

[0134] Example 3: The microelectronic device according to Example 1 or Example 2 further includes a conductive plug structure in the upper part of the guide post structure, the conductive plug structure being in direct physical contact with the contact structure.

[0135] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein one or more of the contact structure and the interconnect structure have a higher conductivity than the conductive line.

[0136] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the contact structure includes one or more of the following: phosphorus, arsenic, antimony, bismuth, boron, aluminum, gallium, carbon, fluorine, chlorine, bromine and argon.

[0137] Example 6: The microelectronic device according to any one of Examples 1 to 5 further includes a conductive liner material between the insulating material and the filler material of the contact structure.

[0138] Example 7: The microelectronic device according to Example 6, wherein the conductive liner material comprises titanium nitride, and the filler material of the contact structure comprises tungsten.

[0139] Example 8: A microelectronic device according to any one of Examples 1 to 7, further comprising: a dielectric structure on the conductive lines; and an air gap between laterally adjacent conductive lines, the air gap being laterally adjacent to the conductive lines, wherein an upper portion of the air gap extends laterally adjacent to the dielectric structure, and a lower portion of the air gap extends laterally adjacent to a segment of the insulating material.

[0140] Example 9: The microelectronic device according to Example 8, wherein a portion of the insulating material is formed in an L-shaped structure surrounding the air gap on at least two consecutive sides.

[0141] Example 10: A memory device comprising: a vertically extending string of memory cells; an access line electrically connected to the vertically extending string of memory cells and extending along a first horizontal direction; a data line electrically connected to the vertically extending string of memory cells and extending along a second horizontal direction, the second horizontal direction being substantially transverse to the first horizontal direction; an interconnect structure vertically inserted between and electrically connected to the data line and the vertically extending string of memory cells; and a contact structure vertically inserted between and electrically connected to the interconnect structure and the vertically extending string of memory cells, the contact structure comprising tungsten, and the data line comprising a single-phase material, including ruthenium or molybdenum.

[0142] Example 11: The memory device according to Example 10, wherein the interconnect structure includes an alpha phase tungsten filler material and a beta phase tungsten liner material laterally adjacent to the alpha phase tungsten filler material.

[0143] Example 12: The memory device according to Example 10 or Example 11, wherein the material composition of the interconnect structure is substantially the same as the material composition of the data line.

[0144] Example 13: A memory device according to any one of Examples 10 to 12, further comprising an air gap separating the data lines along the first horizontal direction, wherein the width of the air gap along the first horizontal direction is relatively greater than the width of the data lines along the first horizontal direction.

[0145] Example 14: The memory device according to Example 13, wherein a portion of the air gap extends vertically above the plane of the upper surface of the laterally adjacent data line, and a portion of the air gap extends vertically below the plane of the lower surface of the laterally adjacent data line.

[0146] Example 15: A method for forming a microelectronic device, the method comprising: forming a post structure extending vertically through an insulating material; forming a contact structure above the post structure; forming an interconnect structure above the contact structure; and forming a conductive wire electrically coupled to the post structure through the contact structure and the interconnect structure, the conductive wire comprising one or more of titanium, ruthenium, aluminum, and molybdenum, and the interconnect structure comprising one or more of a material composition different from that of the contact structure and the conductive wire.

[0147] Example 16: According to the method of Example 15, forming the conductive line includes forming a continuous portion of conductive material adjacent to the insulating material and removing a portion of the conductive material during a single subtractive patterning process to form the conductive line.

[0148] Example 17: The method according to Example 15 or Example 16, wherein forming the contact structure includes forming the contact structure having a first material comprising at least some fluorine, and forming the conductive wire includes forming the conductive wire having a second material comprising substantially no fluorine.

[0149] Example 18: The method according to any of Examples 15 to 17, wherein forming the contact structure includes forming a conductive liner material within a contact opening in the insulating material, and using the conductive liner material as a seed material to grow a filler material within the central portion of the contact opening.

[0150] Example 19: The method according to Example 15 or Example 16, wherein forming the contact structure includes: forming a polycrystalline silicon material overlying the post structure; and converting at least some of the polycrystalline silicon material into a conductive material including beta-phase tungsten.

[0151] Example 20: The method according to any of Examples 15 to 19, wherein forming the interconnect structure includes forming the interconnect structure operatively coupled to the conductive line and the contact structure at the very center using a single damascene process.

[0152] Example 21: The method according to any one of Examples 15 to 20, wherein forming the contact structure includes forming the contact structure with a wedge profile, wherein the upper portion of each contact structure has a critical dimension larger than its lower portion, and forming the interconnect structure includes eccentrically positioning the vertical centerline of the interconnect structure relative to the vertical centerline of the contact structure.

[0153] Example 22: The method according to any of Examples 15 to 21 further includes forming a dielectric material adjacent to the insulating material to form an air gap in an opening extending between laterally adjacent conductive lines and between laterally adjacent interconnect structures, the air gap being positioned directly vertically aligned with at least a portion of the contact structure.

[0154] Example 23: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device comprising: a string of memory cells extending vertically through a stacked structure, the stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; an additional conductive structure substantially free of tungsten overlying the string of memory cells; and an interconnection structure between the string of memory cells and the additional conductive structure, the interconnection structure comprising a beta-phase tungsten lining material substantially surrounding an alpha-phase tungsten-filled material.

[0155] Example 24: The electronic system according to Example 23, wherein the interconnect structure is laterally adjacent to the oxide material but not laterally adjacent to the nitride material.

[0156] Example 25: An electronic system according to Example 23 or Example 24, wherein the memory device includes a 3D NAND flash memory device.

[0157] Although certain illustrative embodiments have been described in conjunction with drawings, those skilled in the art will recognize and understand that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure, such as those claimed below, including legal equivalents. Furthermore, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being covered within the scope of this disclosure.

Claims

1. A microelectronic device comprising: Guide post structure, which extends vertically through the insulating material; A conductive wire, which is covered and electrically coupled to the post structure, the conductive wire comprising a single-phase material, including ruthenium or molybdenum; The contact structure between the guide post structure and the conductive wire; The interconnection structure between the conductive wire and the contact structure includes one or more material compositions that are different from the material composition of the contact structure and the material composition of the conductive wire. as well as An air gap, which is laterally adjacent to the conductive wire, wherein a portion of the air gap extends vertically above a plane of the upper surface of the laterally adjacent conductive wire, and an additional portion of the air gap extends vertically below a plane of the lower surface of the laterally adjacent conductive wire.

2. The microelectronic device of claim 1, wherein the conductive lines directly physically contact the interconnect structure, and the interconnect structure directly physically contacts the contact structure.

3. The microelectronic device according to claim 1, further comprising a conductive plug structure in the upper portion of the guide post structure, the conductive plug structure being in direct physical contact with the contact structure.

4. The microelectronic device according to any one of claims 1 to 3, wherein one or more of the contact structure and the interconnect structure have a higher conductivity than the conductive line.

5. The microelectronic device according to any one of claims 1 to 3, wherein the contact structure comprises one or more of the following: phosphorus, arsenic, antimony, bismuth, boron, aluminum, gallium, carbon, fluorine, chlorine, bromine, and argon.

6. The microelectronic device according to any one of claims 1 to 3, further comprising a conductive liner material between the insulating material and the filler material of the contact structure.

7. The microelectronic device of claim 6, wherein the conductive liner material comprises titanium nitride, and the filler material of the contact structure comprises tungsten.

8. The microelectronic device according to any one of claims 1 to 3, further comprising a dielectric structure on the conductive line, wherein the air gap laterally adjacent to the conductive line comprises an upper portion of the air gap extending laterally adjacent to the dielectric structure and a lower portion of the air gap extending laterally adjacent to a segment of the insulating material.

9. The microelectronic device of claim 8, wherein a portion of the insulating material is formed in an L-shaped structure surrounding the air gap on at least two consecutive sides.

10. A memory device comprising: A vertically extending string of memory cells; Access lines are connected in series with the vertically extending memory cells and extend along a first horizontal direction; A data line, which is overlaid on and electrically connected to the vertically extending memory cell and extends along a second horizontal direction, which is substantially transverse to the first horizontal direction; An interconnect structure is vertically inserted between and electrically connected to the data line and the vertically extending memory cell string; A contact structure is vertically inserted between and electrically connected to the interconnect structure and the vertically extending memory cell string, the contact structure comprising tungsten, and the data line comprising a single-phase material, including ruthenium or molybdenum; as well as An air gap, which is laterally adjacent to the data line, wherein a portion of the air gap extends vertically above the plane of the upper surface of the laterally adjacent data line, and an additional portion of the air gap extends vertically below the plane of the lower surface of the laterally adjacent data line.

11. The memory device of claim 10, wherein the interconnect structure comprises an alpha phase tungsten filler material and a beta phase tungsten liner material laterally adjacent to the alpha phase tungsten filler material.

12. The memory device of claim 10 or claim 11, wherein the material composition of the interconnect structure is substantially the same as the material composition of the data line.

13. The memory device of claim 10 or claim 11, wherein the width of the air gap along the first horizontal direction is relatively greater than the width of the data line along the first horizontal direction.

14. A method for forming a microelectronic device, the method comprising: Forming a guide post structure that extends vertically through the insulating material; A contact structure is formed above the guide post structure; An interconnection structure is formed above the contact structure; A conductive line is formed electrically coupled to the post structure through the contact structure and the interconnect structure, the conductive line being covered by the post structure, the conductive line comprising a single-phase material including ruthenium or molybdenum, and the interconnect structure comprising one or more material compositions different from those of the contact structure and the conductive line; A dielectric material is formed above the conductive line; An opening is formed that extends vertically through the dielectric material, the conductive line, and at least a portion of the insulating material; An air gap is formed within the opening of the laterally adjacent conductive wire, wherein a portion of the air gap extends vertically above the plane of the upper surface of the laterally adjacent conductive wire, and an additional portion of the air gap extends vertically below the plane of the lower surface of the laterally adjacent conductive wire.

15. The method of claim 14, wherein forming the conductive line comprises forming a continuous portion of conductive material adjacent to the insulating material and removing a portion of the conductive material during a single subtractive patterning process to form the conductive line.

16. The method of claim 14 or claim 15, wherein forming the contact structure comprises forming the contact structure having a first material comprising at least some fluorine, and forming the conductive wire comprises forming the conductive wire having a second material that is substantially free of fluorine.

17. The method of claim 14 or claim 15, wherein forming the contact structure comprises forming a conductive liner material within a contact opening in the insulating material, and using the conductive liner material as a seed material to grow a filler material within a central portion of the contact opening.

18. The method of claim 14 or claim 15, wherein forming the contact structure comprises: A polycrystalline silicon material is formed covering the guide pillar structure; as well as At least some of the polycrystalline silicon materials are converted into conductive materials including beta-phase tungsten.

19. The method of claim 14 or claim 15, wherein forming the interconnect structure comprises forming the interconnect structure operatively coupled thereto at the midpoint between the conductive line and the contact structure using a single damascene process.

20. The method of claim 14 or claim 15, wherein forming the contact structure comprises forming the contact structure to have a wedge profile, wherein the upper portion of each contact structure has a critical dimension larger than its lower portion, and forming the interconnect structure comprises eccentrically positioning the vertical centerline of the interconnect structure relative to the vertical centerline of the contact structure.

21. The method of claim 14 or claim 15, wherein forming the air gap within the opening comprises forming the air gap directly vertically aligned with at least a portion of the contact structure.

22. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; A memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device comprising: A string of memory cells extends vertically through a stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; An additional conductive structure is overlaid on and electrically coupled to the memory cell string, wherein the additional conductive structure comprises a single-phase material, including ruthenium or molybdenum; The interconnect structure between the memory cell string and the additional conductive structure includes a beta-phase tungsten lining material substantially surrounding an alpha-phase tungsten-filled material; and An air gap, which is laterally adjacent to the additional conductive structure, wherein a portion of the air gap extends vertically above the plane of the upper surface of the laterally adjacent additional conductive structure, and an additional portion of the air gap extends vertically below the plane of the lower surface of the laterally adjacent additional conductive structure.

23. The electronic system of claim 22, wherein the interconnect structure is laterally adjacent to the oxide material but not laterally adjacent to the nitride material.

24. The electronic system of claim 22 or claim 23, wherein the memory device comprises a 3D NAND flash memory device.

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