Method for forming a semiconductor device

Abstract

The present application relates to a method for forming a semiconductor device. The method includes forming a first member having a first portion containing a plurality of storage capacitors and a second portion surrounding the first portion; forming a second member having a concave shape having a third portion and a fourth portion surrounding the third portion, the third portion corresponding to a lower top surface of the concave shape, the third portion containing a plurality of access transistors arranged corresponding to the plurality of storage capacitors, and the fourth portion corresponding to an upper top surface of the concave shape; stacking the first member on the second member to physically connect the second portion and the fourth portion with a gap between the first portion and the third portion; cutting the first member to physically separate the first portion from the second portion; and joining the separated first and third portions to fill the gap therebetween.

Description

Technical Field

[0001] The present application relates to a semiconductor device, and in particular to a method of forming a semiconductor device. Background Art

[0002] Dynamic random access memory (DRAM) stores information in memory cells. Each memory cell includes an access transistor and a storage capacitor connected to the source or drain of the access transistor. Providing a DRAM with multiple memory cells allows for the formation of a high-capacity memory circuit. Because DRAM storage capacitors are formed into long, narrow columns, there is a risk of collapse during the manufacturing process. Summary of the Invention

[0003] According to one aspect of the present application, a method is provided. The method includes: forming a first member having a first portion containing a plurality of storage capacitors and a second portion surrounding the first portion; forming a second member having a concave shape having a third portion and a fourth portion surrounding the third portion, the third portion corresponding to a lower top surface of the concave shape, the third portion containing a plurality of access transistors arranged corresponding to the plurality of storage capacitors, and the fourth portion corresponding to an upper top surface of the concave shape; stacking the first member on the second member to physically connect the second portion and the fourth portion with a gap between the first portion and the third portion; cutting the first member to physically separate the first portion from the second portion; and joining the separated first and third portions to fill the gap therebetween.

[0004] According to another aspect of the present application, a method is provided. The method includes: forming a first member having a plurality of first cells, each of the first cells including a first portion containing a plurality of storage capacitors and a second portion surrounding the first portion; forming a second member having a plurality of second cells, each of the second cells including a third portion containing a plurality of access transistors arranged corresponding to the plurality of storage capacitors and a fourth portion surrounding the third portion, the third portion corresponding to a concave lower top surface, the third portion containing a plurality of access transistors arranged corresponding to the plurality of storage capacitors, and the fourth portion corresponding to an upper top surface of the concave shape; stacking the first member on the second member to physically connect the second portion of each of the plurality of first cells and the fourth portion of a corresponding one of the plurality of second cells, with a gap between the first portion of each of the plurality of first cells and the third portion of the corresponding one of the plurality of second cells; cutting the first member in each of the plurality of first cells to physically separate the first portion from the second portion; and joining the separated first portion of each of the plurality of first cells and the third portion of the corresponding one of the plurality of second cells to fill the gap therebetween. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1is a plan view showing one example of a schematic configuration of a layout of a semiconductor device according to the embodiment.

[0006] Figure 2 is a circuit diagram showing a schematic configuration of an equivalent circuit of a memory cell of a semiconductor device according to an embodiment.

[0007] Figure 3 is a diagram illustrating a semiconductor device and a method for manufacturing the same according to an embodiment, and is a longitudinal sectional view illustrating one example of a schematic configuration in a final process stage. Figure 3 It shows Figure 8 A longitudinal cross-sectional view of an example of a schematic configuration at a subsequent exemplary process stage.

[0008] Figure 4 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment, and is a longitudinal cross-sectional view illustrating one example of a schematic configuration in an exemplary process stage.

[0009] Figure 5 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment, and is a diagram illustrating Figure 4 A longitudinal cross-sectional view of an example of a schematic configuration at a subsequent exemplary process stage.

[0010] Figure 6 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment, and is a diagram illustrating Figure 5 A longitudinal cross-sectional view of an example of a schematic configuration at a subsequent exemplary process stage.

[0011] Figure 7 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment, and is a diagram illustrating Figure 6 A longitudinal cross-sectional view of an example of a schematic configuration at a subsequent exemplary process stage.

[0012] Figure 8 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment, and is a diagram illustrating Figure 7 A longitudinal cross-sectional view of an example of a schematic configuration at a subsequent exemplary process stage. DETAILED DESCRIPTION

[0013] Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following detailed description is made with reference to the accompanying drawings, which illustrate, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0014] Will refer to Figures 1 to 8 This embodiment is described. In the following description, DRAM is given as an example of a semiconductor device. However, the sizes and size ratios of the cells in the figures do not necessarily match the sizes and size ratios in actual semiconductor devices. In addition, in the following description, the Y direction may be referred to as the vertical direction, and the X direction may be referred to as the horizontal direction in some cases.

[0015] First, refer to Figures 1 to 3 A semiconductor device 1 according to an embodiment will be described. Figure 1 1 is a plan view showing a schematic configuration of a semiconductor device 1. Multiple memory pad sections 2 are arranged in a matrix. A memory pad edge section 4 is provided around each of the memory pad sections 2. A peripheral circuit section 5 is provided around the memory pad edge section 4. Multiple memory cells 15 are provided in the memory pad section 2. Memory cells 15 are DRAM memory elements. Note that the peripheral circuit section 5 shown in the figure is the edge of the peripheral circuit section 5, and the peripheral circuits provided in the peripheral circuit section 5 are not shown.

[0016] Figure 2 The equivalent circuit of the memory cell array forming the memory pad portion 2 of the DRAM is shown. A plurality of memory cells 15 are arranged in a matrix, and each memory cell 15 is connected to the intersection of a plurality of word lines 17 and a plurality of bit lines 18 arranged in a straight line. A single memory cell 15 includes a pair of access transistors 16 and a storage capacitor 24. The access transistor 16 includes a metal oxide semiconductor field effect transistor (MOSFET). The gate electrode 16a of the access transistor 16 (see FIG. 1 ) is connected to the gate electrode 16a of the access transistor 16. Figure 3 ) is used as a word line 17 of the DRAM. One of the source and the drain of each access transistor 16 is connected to one of the bit lines 18, and the other is connected to the storage capacitor 24. The storage capacitor 24 comprises a capacitor and stores data by accumulating charge.

[0017] When writing data to memory cell 15, a potential that turns on access transistor 16 is applied to word line 17, and a low potential or a high potential corresponding to "0" or "1" of the data to be written is applied to bit line 18. When reading data from memory cell 15, a potential that turns on access transistor 16 is applied to word line 17, and data determination is performed by causing a sense amplifier connected to bit line 18 to sense the potential drawn from storage capacitor 24 to bit line 18.

[0018] Figure 3 1 is a longitudinal sectional view showing a schematic configuration of a semiconductor device 1 according to an embodiment. A memory pad edge portion 4 and a peripheral circuit portion 5 are provided on either side of a memory pad portion 2. The semiconductor device 1 includes a first member A and a second member B. Figure 3 In the embodiment, the first member A is arranged at the upper part, and the second member B is arranged at the lower part. The first member A and the second member B exist in Figure 1 The first component A is provided with a first unit including a plurality of memory pad portions 2, a memory pad edge portion 4 and a peripheral circuit portion 5 of the semiconductor device 1. Figure 3 The second member B is provided with a second unit comprising a storage capacitor 24 in the upper portion of one of the memory pad parts 2 in FIG. Figure 3 The access transistor 16 in the lower part of one of the memory pad parts 2 in the first member A and the second member B are divided into a first unit and a second unit including the memory pad part 2, the memory pad edge part 4 and the peripheral circuit part 5, respectively.

[0019] The first component A comprises a plurality of storage capacitors 24. Figure 3 In the embodiment, the storage capacitor 24 has a cylindrical or cup shape that is long in the Y direction and narrow in the X direction. The storage capacitor 24 is formed by stacking a first conductive portion 24a, a high-K film 24b, and a second conductive portion 24c on the inner wall of each narrow cup. The first conductive portion 24a serves as an upper electrode, the high-K film 24b serves as a capacitor insulating film, and the second conductive portion 24c serves as a lower electrode.

[0020] The first conductive portion 24a and the second conductive portion 24c contain a conductive material, and for example, the first conductive portion 24a contains titanium nitride (TiN), while the second conductive portion 24c contains titanium nitride (TiN) and ruthenium (Ru). The high-K film 24b contains an insulating material having a high relative dielectric constant, and for example, contains a metal oxide material such as HfO2, ZrO2, Al2O3, or ZrO2.

[0021] A plate electrode 30 electrically connected to the first conductive portion 24a is provided above the storage capacitor 24. The plate electrode 30 is further connected to an upper electrode 34 via a contact plug 32. The plate electrode 30 and the contact plug 32 contain a conductive material such as tungsten (W). The upper electrode 34 contains a conductive material such as aluminum (Al).

[0022] The storage capacitor 24 is covered by a first insulating film 26 and a second insulating film 27. The first insulating film 26 and the second insulating film 27 contain insulating materials, and for example, the first insulating film 26 contains silicon dioxide (SiO2) and the second insulating film 27 contains silicon nitride (SiN).

[0023] The peripheral circuit section 5 includes a second insulating film 27 and a third insulating film 28. The memory pad edge section 4, the peripheral circuit section 5, and the storage capacitor 24 are covered by the third insulating film 28.

[0024] The second member B includes a semiconductor substrate 10 and a dielectric film 13. In the second member B, an isolation 12 and an active region 14 defined by the isolation 12 and a gate electrode 16a are formed in the semiconductor substrate 10. The active region 14 includes source / drain regions of an access transistor 16.

[0025] As the semiconductor substrate 10, a single crystal semiconductor substrate such as a single crystal silicon substrate is used, for example. The isolation 12 is obtained by forming a groove in the semiconductor substrate 10 and burying an insulating material in the groove. For example, silicon dioxide (SiO2) is buried in the isolation 12.

[0026] The isolation 12 serves as an isolation region for electrically isolating elements from each other. The dielectric film 13 contains an insulating material such as silicon dioxide (SiO2).

[0027] The dielectric film 13 is recessed in the peripheral circuit portion 5 to form a recessed portion 13a having a concave shape (see FIG. Figure 6 In the peripheral circuit portion 5, a step D is formed between the lower top surface portion 13d of the recess 13a and the upper top surface portion 13c of the dielectric film 13. In each memory pad edge portion 4 located between one of the memory pad portions 2 and the peripheral circuit portion 5, the top surface 13e of the dielectric film 13 has an inclined surface 4a connecting the upper top surface portion 13c and the lower top surface portion 13d. The upper top surface portion 13c is provided at the periphery of the recess 13a and serves as a shoulder at a position higher than the lower top surface portion 13d of the recess 13a in each memory pad portion 2. The upper top surface portion 13c includes the upper top surface of the recess 13a. The lower top surface portion 13d includes the lower top surface of the recess 13a.

[0028] A gate electrode 16a is formed in the active region 14. In this embodiment, the gate electrode 16a is formed as a gate electrode of the trench gate access transistor 16. The gate electrode 16a contains a conductive material and, for example, contains at least one of titanium nitride (TiN), ruthenium (Ru), tungsten nitride (WN), tungsten (W), and polysilicon (poly-Si).

[0029] Furthermore, the second member B includes bit lines 18, and each bit line 18 is connected to one side of the active region 14 through a connection portion not shown. The bit line 18 contains a conductive material and, for example, contains at least one of tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium nitride (TiN), and ruthenium (Ru).

[0030] The contact plug 20 and the contact pad 22 are connected to the other side of the active region 14, and the contact pad 22 is connected to the second conductive portion 24c of the storage capacitor 24. As described above, the semiconductor device 1 according to the present embodiment includes a single-transistor, single-capacitor type DRAM memory cell provided with the gate electrode 16a, the active region 14, the bit line 18, and the storage capacitor 24.

[0031] Next, we will refer to Figures 3 to 8 A method of manufacturing the semiconductor device 1 according to the embodiment will be described.

[0032] First, refer to Figure 4 and 5 To describe the method of forming the first member A. Figure 4 As shown, a cutting layer 42 , a plate electrode 30 , a first insulating film 26 , and a second insulating film 27 are formed on a base substrate 40 .

[0033] For example, a single crystal semiconductor substrate such as a single crystal silicon substrate is used as the base substrate 40. The cutting layer 42 contains an insulating material such as silicon nitride (SiN). The plate electrode 30 contains a conductive material such as aluminum. The first insulating film 26 contains an insulating material such as silicon oxide. The second insulating film 27 contains an insulating material such as silicon nitride (SiN).

[0034] The cutting layer 42, the first insulating film 26, and the second insulating film 27 are formed, for example, by chemical vapor deposition (hereinafter referred to as CVD). For example, the plate electrode 30 is obtained by depositing aluminum using CVD or sputtering and then patterning the deposited aluminum by performing photolithography and anisotropic dry etching.

[0035] Next, the second insulating film 27 and the first insulating film 26 are etched using photolithography and anisotropic dry etching. With this arrangement, a plurality of grooves 29 are formed that penetrate from the top surface of the second insulating film 27 to the top surface of the plate electrode 30. Each of the grooves 29 has a columnar or hole shape extending in a long and narrow shape in the Y direction of the figure.

[0036] Next, if Figure 5 As shown, a first conductive portion 24a, a high-K film 24b, and a second conductive portion 24c are formed and buried in the groove 29. The first conductive portion 24a, the high-K film 24b, and the second conductive portion 24c are formed using CVD.

[0037] Thereafter, the first conductive portion 24a, the high-k film 24b, and the second conductive portion 24c are etched back to remove excess first conductive portion 24a, high-k film 24b, and second conductive portion 24c formed on the top surface of the second insulating film 27. With this arrangement, the first conductive portion 24a, the high-k film 24b, and the second conductive portion 24c are buried within the groove 29. The first conductive portion 24a and the plate electrode 30 are in contact with each other and have electrical continuity.

[0038] The first conductive portion 24a contains a conductive material such as titanium nitride (TiN). The high-k film 24b contains an insulating material having a high relative dielectric constant, and for example, contains a metal oxide containing a metal such as zirconium (Zr) or aluminum (Al). The second conductive portion 24c contains a conductive material such as titanium nitride (TiN) and ruthenium (Ru). The upper edge surface of the second conductive portion 24c is exposed to the outside.

[0039] Next, if Figure 6 As shown, the first component A is turned vertically and placed on top of the pre-prepared second component B in an aligned state, and the two components are joined together.

[0040] The second component B is created as follows. The isolation 12, active region 14, and gate electrode 16a of the access transistor 16 are formed on a semiconductor substrate 10. The isolation 12 is formed by forming a groove in the semiconductor substrate 10 and burying an insulating material, such as silicon dioxide (SiO2), in the groove. The gate electrode 16a is formed by forming a groove in the active region 14 and then burying a conductive material in the groove. Next, after forming the bit line 18, a dielectric film 13 is formed.

[0041] The bit line 18 is formed by, for example, CVD or sputtering, and is patterned by performing photolithography and anisotropic dry etching on the deposited conductive material.

[0042] Dielectric film 13 includes an insulating material such as silicon dioxide (SiO2). A plurality of contact plugs 20 are provided within dielectric film 13 and connected to the top surface of each of active regions 14. Furthermore, contact pads 22 are provided and connected to the top surface of each of contact plugs 20. Contact plugs 20 and contact pads 22 include a conductive material such as tungsten (W). A barrier metal such as titanium nitride (TiN) may also be provided between contact plugs 20 and active region 14.

[0043] In the upper portion of the dielectric film 13, a recess 13a is formed in a region facing the memory pad portion 2. The recess 13a is formed using photolithography and dry etching. Furthermore, an inclined surface 4a connecting the upper top surface portion 13c and the lower top surface portion 13d can be formed by etching under etching conditions such that the resist formed by photolithography recedes in the horizontal direction.

[0044] The top surface of the contact pad 22 is formed to be aligned with the lower top surface portion 13d of the recess 13a. The top surface of the contact pad 22 is exposed to the outside. On the dielectric film 13, the upper top surface portion 13c in the area corresponding to the peripheral circuit portion 5 exists at a higher position than the lower top surface portion 13d of the recess 13a.

[0045] Thus, a first component A and a second component B are prepared and joined by a fusion method. In the fusion method, a treatment is first performed to attach a large number of hydroxyl groups to the surfaces of the first component A and the second component B, or in other words, a hydrophilization treatment is performed. Next, the hydrophilized surfaces of the first component A and the second component B are superimposed and joined together. The weld formed by the fusion method is formed by hydrogen bonding between the hydroxyl groups on the hydrophilized surfaces. This fusion method can be performed at room temperature.

[0046] At this time, the first member A and the second member B are superimposed, stacked, and joined while also being positioned. Positioning is performed, for example, by forming alignment marks (not shown) on the first member A and the second member B in advance and detecting the alignment marks.

[0047] A gap 13b is formed in the recess 13a between the lower surfaces of the first member A and the second member B so that the storage capacitor 24 and the contact pad 22 are not in contact. The edge surface of the contact pad 22 and the edge surface of the second conductive portion 24c are exposed. Subsequently, the base substrate 40 of the first member A is removed, for example, by using anisotropic dry etching.

[0048] Next, we will refer to Figure 7 and 8 The step of separating the memory pad portion 2 from the first member A to connect the storage capacitor 24 and the contact pad 22 will be described. Figure 7 Shown immediately after Figure 8 When etching the groove 31, the Figure 7 The status shown is Figure 8 Change of status shown.

[0049] like Figure 7As shown, the cutting layer 42 is removed by etching, and then the groove 31 is formed in the memory pad edge portion 4. For example, the groove 31 is formed using photolithography and anisotropic dry etching. Reactive ion etching (RIE) is used to etch the groove 31. In the first half of the etching of the groove 31, etching is performed under conditions such that the etching rate of silicon dioxide contained in the first insulating film 26 is high and the etching rate of silicon nitride contained in the second insulating film 27 is low. As an etching device for performing the above-mentioned etching, any of various etching devices can be used, such as a microwave electron cyclotron resonance (ECR) plasma device, a capacitively coupled plasma (CCP) device, or an inductively coupled plasma (ICP) device.

[0050] By performing etching under the above-described conditions, grooves 31 continue to be formed in memory pad edge portion 4, and the etching progress slows down when reaching the top surface of second insulating film 27. Therefore, the uniformity of the etching amount can be improved. After reaching the top surface of second insulating film 27, the etching conditions become suitable for etching silicon nitride.

[0051] At this time, the uniformity of the etching amount is improved by reducing the etching rate of silicon nitride and improving the etching controllability. During this period, the memory pad portion 2 and the peripheral circuit portion 5 of the first member A are connected by the beam 27a formed by the remaining unetched portion of the second insulating film 27. Therefore, the memory pad portion 2 and the second member B are still not in contact.

[0052] When etching further proceeds and beam 27a is removed, the connection between memory pad portion 2 of first member A and peripheral circuit portion 5 is released. At this time, a self-bias voltage is generated between the plasma generated by the RIE high-frequency discharge and the stage on which the wafer is placed, causing the plasma side to become positively charged and the stage side, i.e., the wafer side, to become negatively charged. As a result, first member A becomes more positively charged than second member B, while second member B becomes more negatively charged than first member A.

[0053] In this state, when the beam 27a connecting the peripheral circuit portion 5 and the memory pad portion 2 of the first member A is removed, the peripheral circuit portion 5 and the memory pad portion 2 are separated from each other. In this way, an attractive force caused by electrostatic force is generated between the first member A and the second member B, causing the members to attract each other. In addition, electrostatic force also acts between the conductive materials. In other words, an attractive force caused by electrostatic force is generated between the contact pad 22 and the storage capacitor 24. With this arrangement, as Figure 8 As shown, when the memory pad portion 2 and the second member B come into contact, the contact pad 22 and the storage capacitor 24 attract each other and are positioned in a self-aligned manner, thereby forming a contact state. At this time, the separated peripheral circuit portion 5 and the memory pad portion 2 are connected by filling the gap 13b therebetween. Thereafter, the contact pad 22 and the storage capacitor 24 are electrically connected by annealing. Through these steps, a Figure 8 Furthermore, during etching, the wafer is clamped to the stage with an electrostatic chuck, and the electrostatic force of the chuck also generates an electrostatic force similar to that described above.

[0054] Note that since the positioning of the memory pad portion 2 and the second member B is achieved by the electrostatic force applied between the contact pads 22 and the storage capacitors 24, in some cases, the contact pads 22 and the storage capacitors 24 may be misaligned by about one column. This is why the number of storage capacitors 24 is greater than the number of contact pads 22, and ensures that each contact pad 22 will have a corresponding storage capacitor 24 even if the contact pads 22 and the storage capacitors 24 are misaligned by one column.

[0055] Next, a third insulating film 28 is formed to cover the interior of the groove 31 and the top surface of the first member A. For example, the third insulating film 28 can be formed by CVD. Next, a contact hole is formed in the third insulating film 28, penetrating from the top surface of the third insulating film 28 to the top surface of the plate electrode 30. A conductive material is buried in the contact hole to form a contact plug 32. Thereafter, an upper electrode 34 connected to the contact plug 32 is formed on the third insulating film 28. The upper electrode 34 is deposited by CVD and patterned by photolithography and anisotropic dry etching.

[0056] Through the above steps, the semiconductor device 1 according to this embodiment is formed. Figure 3 shown.

[0057] According to the semiconductor device 1 and the manufacturing method thereof of the present embodiment, the following effects are exhibited.

[0058] Semiconductor device 1 having a single-transistor, single-capacitor structure is implemented by separately forming first member A and second member B and then bonding the two members together. This avoids unnecessary heat treatment of access transistor 16 mounted in second member B. Consequently, the performance of access transistor 16 can be improved.

[0059] Positioning when connecting the second member B and the memory pad portion 2 of the first member A is achieved by utilizing the electrostatic force generated between the contact pad 22 and the storage capacitor 24. For this reason, a step such as building in a specific structure is not required, the manufacture of the semiconductor device 1 can be simplified, and the cost of the semiconductor device 1 can be reduced.

[0060] When first member A and second member B are joined together, a gap exists between contact pad 22 and storage capacitor 24 due to recess 13a formed in second member B, and the two members are not yet bonded. Next, memory pad portion 2 is separated from first member A to allow for movement. At this point, the electrostatic force generated between contact pad 22 and storage capacitor 24 allows the two members to be positioned correctly and self-aligned. Consequently, since the connection between contact pad 22 and storage capacitor 24 is ensured, the yield of semiconductor device 1 is improved, and cost savings are achieved.

[0061] Because the number of storage capacitors 24 is greater than the number of contact pads 22, even if the contact pads 22 and storage capacitors 24 are not aligned in a row when pulled together by electrostatic force, a single transistor and single capacitor combination can be achieved. This arrangement can improve the yield of semiconductor device 1, thereby reducing the cost of semiconductor device 1.

[0062] In forming the storage capacitor 24, first, a cup-shaped groove 29 is formed, and the first conductive portion 24a, the high-K film 24b, and the second conductive portion 24c are formed on the inner wall of the groove 29. Therefore, since the formation of the pillar of the storage capacitor 24 can be avoided, the collapse of the storage capacitor 24 can be avoided, and the yield of the semiconductor device 1 can be improved.

[0063] As described above, the semiconductor devices according to various embodiments are described using DRAM as an example. However, the above description is merely an example and is not intended to be limited to DRAM. Memory devices other than DRAM, such as static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase change memory, can be used as semiconductor devices. Furthermore, devices other than memory, such as microprocessors and logic ICs of application-specific integrated circuits (ASICs), can also be used as semiconductor devices according to the aforementioned embodiments.

[0064] Although the present invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the present invention and obvious modifications and equivalents thereof. In addition, based on this disclosure, other modifications within the scope of the present invention will be apparent to those skilled in the art. It is also conceivable that various combinations or sub-combinations may be made to the specific features and aspects of the embodiments and still fall within the scope of the present invention. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with each other to form different modes of the disclosed invention. Therefore, it is intended that the scope of at least some of the present invention disclosed herein should not be limited by the specific disclosed embodiments described above.

Claims

1. A method comprising: forming a first member having a first portion containing a plurality of storage capacitors therein and a second portion surrounding the first portion; forming a second member having a concave shape having a third portion corresponding to a lower top surface of the concave shape and a fourth portion surrounding the third portion, the third portion including a plurality of access transistors disposed corresponding to the plurality of storage capacitors therein, and the fourth portion corresponding to an upper top surface of the concave shape; stacking the first member on the second member to physically connect the second portion and the fourth portion with a gap between the first portion and the third portion; cutting the first member to physically separate the first portion from the second portion; as well as The separated first and third parts are joined and the gap therebetween is filled. 2 . The method of claim 1 , wherein stacking the first member on the second member to physically connect the second portion and the fourth portion with the gap between the first portion and the third portion comprises using a welding method. 3 . The method according to claim 1 , wherein each of the storage capacitors comprises a multilayer of a first conductive film, a high-K dielectric film, and a second conductive film. 4 . The method according to claim 3 , wherein the third portion further comprises a plurality of active regions and a plurality of contact pads electrically connected to the plurality of active regions, respectively. 5 . The method of claim 4 , wherein cutting the first member to physically separate the first portion from the second portion comprises performing reactive ion etching. 6 . The method of claim 5 , wherein the first portion is attracted to the third portion by an electrostatic force during reactive ion etching, and the first portion and the third portion are joined after the first portion is separated from the second portion.

7. The method according to claim 6, wherein an electrostatic force is generated between the second conductive film of the plurality of storage capacitors of the first portion and the plurality of contact pads of the third portion so that positioning of the second conductive film and the plurality of contact pads is performed in a self-aligned manner.

8. The method of claim 1 , wherein each of the plurality of access transistors comprises a gate electrode, and the gate electrode comprises at least one of TiN, Ru, WN, W, and polysilicon, and The second portion further includes a bit line, and the bit line includes at least one of WSi, WN, W, TiN and Ru.

9. The method of claim 8, wherein the gate electrode is used as a DRAM word line.

10. The method according to claim 2, wherein the welding method includes performing a hydrophilization treatment. 11 . The method according to claim 2 , wherein the fusion bonding method includes performing a process of attaching hydroxyl groups to surfaces of the first portion and the second portion.

12. A method comprising: forming a first member having a plurality of first cells, each first cell including a first portion containing a plurality of storage capacitors therein and a second portion surrounding the first portion; forming a second member having a plurality of second units, each second unit including a third portion and a fourth portion surrounding the third portion, the third portion corresponding to a lower top surface of the concave shape, the third portion containing therein a plurality of access transistors arranged corresponding to the plurality of storage capacitors, and the fourth portion corresponding to an upper top surface of the concave shape; stacking the first member on the second member to physically connect the second portion of each of the plurality of first cells and the fourth portion of a corresponding one of the plurality of second cells with a gap between the first portion of each of the plurality of first cells and the third portion of a corresponding one of the plurality of second cells; cutting the first member in each of the plurality of first units to physically separate the first portion from the second portion; as well as The separated first portion of each of the plurality of first units and the third portion of a corresponding one of the plurality of second units are joined, and the gap therebetween is filled. 13 . The method of claim 12 , wherein stacking the first member on the second member to physically connect the second portion and the fourth portion with the gap between the first portion and the third portion comprises using a welding method. 14 . The method according to claim 12 , wherein each of the plurality of storage capacitors comprises a multilayer of a first conductive film, a high-K dielectric film, and a second conductive film. 15 . The method according to claim 14 , wherein the third portion further comprises a plurality of active regions and a plurality of contact pads electrically connected to the plurality of active regions, respectively. 16 . The method of claim 15 , wherein cutting the first member to physically separate the first portion from the second portion comprises performing reactive ion etching. 17 . The method of claim 16 , wherein the first portion is attracted to the third portion by an electrostatic force during reactive ion etching, and the first portion and the third portion are joined after the first portion is separated from the second portion.

18. The method according to claim 17, wherein an electrostatic force is generated between the second conductive film of the plurality of storage capacitors of the first portion and the plurality of contact pads of the third portion so that positioning of the second conductive film and the plurality of contact pads is performed in a self-aligned manner.

19. The method of claim 13, wherein the welding method includes performing a hydrophilization treatment.

20. The method of claim 13, wherein the fusion bonding method includes performing a process of attaching hydroxyl groups to surfaces of the first portion and the second portion.

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