Methods for fabricating memory cells, high voltage devices and logic devices on substrates by silicide on conductive blocks

Abstract

The present invention is entitled "Method for Fabricating Memory Cells, High Voltage Devices and Logic Devices on a Substrate by Silicide on a Conductive Block". The present invention discloses a method for forming a semiconductor device, the method comprising: recessing the upper surface of a first region and a second region of a semiconductor substrate relative to a third region of the substrate; forming a pair of stacked structures in the first region, each stacked structure having a control gate above a floating gate; forming a first source region in the substrate between the pair of stacked structures; forming an erase gate above the first source region; forming a dummy material block in the third region; forming a select gate adjacent to the stacked structure; forming a high voltage gate in the second region; forming a first barrier layer above at least a portion of one of the high voltage gates; forming a silicide on the top surface of the high voltage gate that is not below the first barrier layer; and replacing the dummy material block with a metal material block.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having an embedded non-volatile memory cell. Background Art

[0002] Non-volatile memory semiconductor devices formed on a silicon semiconductor substrate are well known. For example, U.S. Patents 6,747,310, 7,868,375 and 7,927,994 disclose memory cells formed on a semiconductor substrate with four gates (floating gate, control gate, select gate and erase gate), which are incorporated herein by reference for all purposes. The source region and the drain region are formed as diffusion implant regions into the substrate, thereby defining the channel region in the substrate between the source region and the drain region. The floating gate is disposed above a first portion of the channel region and controls the conductivity of the first portion, the select gate is disposed above a second portion of the channel region and controls the conductivity of the second portion, the control gate is disposed above the floating gate, and the erase gate is disposed above the source region and is laterally adjacent to the floating gate.

[0003] It is also known to form low voltage logic devices and high voltage logic devices on the same substrate as non-volatile memory cells. See, for example, U.S. Pat. No. 9,276,005, which is incorporated herein by reference for all purposes. New gate materials (such as high-K dielectric gates and metal gates) are also used to improve performance. However, the processing steps to form memory cells may adversely affect currently manufactured logic devices, and vice versa.

[0004] What is needed is an improved method of fabricating devices including memory cells, low voltage logic devices, and high voltage devices on the same substrate. Summary of the invention

[0005] The foregoing problems and needs are addressed by a method of forming a semiconductor device, the method comprising:

[0006] Providing a substrate of semiconductor material, the substrate of semiconductor material comprising a first region, a second region and a third region;

[0007] making an upper surface of the substrate in the first region and an upper surface of the substrate in the second region concave relative to an upper surface of the substrate in the third region;

[0008] forming a pair of stacked structures in the first region, wherein each of the stacked structures includes a floating gate of a conductive material disposed above and insulated from an upper surface of the substrate in the first region, and a first non-floating gate of a conductive material disposed above and insulated from the floating gate;

[0009] forming a first source region in the substrate between a pair of stacked structures in the first region;

[0010] forming a second non-floating gate disposed above and insulated from the first source region in the first region;

[0011] forming a dummy material block disposed over and insulated from the upper surface of the substrate in the third region;

[0012] forming a third non-floating gate of a conductive material, the third non-floating gate disposed above and insulated from the upper surface of the substrate in the first region and each laterally adjacent to and insulated from one of the stacked structures;

[0013] forming a fourth non-floating gate of a conductive material disposed above and insulated from the upper surface of the substrate in the second region;

[0014] forming first drain regions in the substrate in the first region, each of the first drain regions being adjacent to one of the third non-floating gates;

[0015] forming second source regions in the substrate in the second region, each second source region being adjacent to one of the fourth non-floating gates;

[0016] forming second drain regions in the substrate in the second region, each second drain region being adjacent to one of the fourth non-floating gates;

[0017] forming a third source region in the substrate in the third region, the third source region being adjacent to the dummy material block; forming a third drain region in the substrate in the third region, the third drain region being adjacent to the dummy material block;

[0018] forming a first blocking layer over at least a portion of one of the fourth non-floating gates in the second region;

[0019] forming a silicide on the first drain region, the second drain region, and the third drain region, on the second source region and the third source region, and on a top surface of a fourth non-floating gate that is not under the first barrier layer; and

[0020] Replace the pseudo material block with a metal material block.

[0021] Other objects and features of the present invention will become apparent by examining the specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1A to 14A is a cross-sectional view of a memory cell region, illustrating the steps of forming a memory cell.

[0023] Figures 1B to 14B is a cross-sectional view of a high voltage (HV) region, illustrating the steps of forming an HV device.

[0024] Figures 1C to 14Cis a cross-sectional view of a logic area, illustrating the steps of forming a logic device.

[0025] Fig.15 is a cross-sectional view of a memory cell area showing a finished memory cell.

[0026] Fig.16 is a cross-sectional view of the HV area, showing the finished HV device.

[0027] Fig.17 is a cross-sectional view of the logic area, showing the finished logic device.

[0028] FIG. 18A to FIG. 19A , FIG. 18B to FIG. 19B and FIG. 18C to FIG. 19C The cross-sectional views of the memory cell region, the HV region, and the logic region, respectively, illustrate the steps of forming the memory cell, the HV device, and the logic device, respectively, in the first alternative embodiment.

[0029] FIG. 20A to FIG. 21A , FIG. 20B to FIG. 21B and FIG. 20C to FIG. 21C are cross-sectional views of a memory cell region, an HV region, and a logic region, respectively, showing the steps of forming a memory cell, an HV device, and a logic device, respectively, in a second alternative embodiment.

[0030] FIG. 22A to FIG. 23A , FIG. 22B to FIG. 23B and FIG. 22C to FIG. 23C The cross-sectional views of the memory cell region, the HV region, and the logic region, respectively, illustrate the steps of forming the memory cell, the HV device, and the logic device, respectively, in the third alternative embodiment.

[0031] FIG. 24A to FIG. 28A , FIG. 24B to FIG. 28B and FIG. 24C to FIG. 28C The cross-sectional views of the memory cell region, the HV region, and the logic region, respectively, illustrate the steps of forming the memory cell, the HV device, and the logic device, respectively, in the fourth alternative embodiment.

[0032] FIG. 29A to FIG. 30A , FIG. 29B to FIG. 30B and FIG. 29C to FIG. 30C The cross-sectional views of the memory cell region, the HV region, and the logic region, respectively, illustrate the steps of forming the memory cell, the HV device, and the logic device in the fifth alternative embodiment.

[0033] FIG. 31A to FIG. 32A , FIG. 31B to FIG. 32B and FIG. 31C to FIG. 32C The cross-sectional views of the memory cell region, the HV region, and the logic region, respectively, illustrate the steps of forming the memory cell, the HV device, and the logic device in the sixth alternative embodiment.

[0034] FIG. 33A to FIG. 34A , FIG. 33B to FIG. 34B and FIG. 33C to FIG. 34C The cross-sectional views of the memory cell region, the HV region, and the logic region respectively illustrate the steps of forming the memory cell, the HV device, and the logic device in the seventh alternative embodiment.

[0035] Fig.33A , Fig.33B , Fig.33C and Fig.35A , Fig.35B , Fig.35C The cross-sectional views of the memory cell region, the HV region, and the logic region respectively illustrate the steps of forming the memory cell, the HV device, and the logic device in the eighth alternative embodiment.

[0036] Fig.33A , Fig.33B , Fig.33C and Fig.36A , Fig.36B , Fig.36C The cross-sectional views of the memory cell region, the HV region, and the logic region, respectively, illustrate the steps of forming the memory cell, the HV device, and the logic device in the ninth alternative embodiment. DETAILED DESCRIPTION

[0037] The present invention is a process for forming a semiconductor device by simultaneously forming a memory cell, a low voltage logic device, and a high voltage logic device on the same semiconductor substrate. The process described below involves forming a memory cell in one or more memory cell regions (also referred to as a first or MC region) 2 of a substrate 10, forming a high voltage logic device in one or more high voltage logic device regions (also referred to as a second or HV region) 4 of the substrate 10, and forming a low voltage logic device in one or more low voltage logic device regions (also referred to as a third or logic region) 6 of the substrate 10. A process is described for simultaneously forming a pair of memory cells in the MC region 2, forming a high voltage logic device in the HV region 4, and forming a lower voltage logic device in the logic region 6. However, multiple such devices are formed simultaneously in each region. The substrate 10 is a substrate of a semiconductor material (e.g., silicon).

[0038] MC Region 2 See Figures 1A to 14A , HV zone 4 see Figures 1B to 14B , and logical area 6 see Figures 1C to 14C, a cross-sectional view showing the process steps for manufacturing a semiconductor device. The process begins by recessing the upper surface 10a of the silicon substrate 10 in the MC region 2 and the HV region 4 by a recess amount R relative to the logic region 6. The recessing of the substrate upper surface 10a is preferably performed by forming a silicon dioxide (hereinafter referred to as "oxide") layer on the substrate upper surface 10a and forming a silicon nitride (hereinafter referred to as "nitride") layer on the oxide layer. A photolithography masking step is performed to cover the logic region 6 with photoresist without covering the MC region 2 and the HV region 4 (i.e., photoresist is formed on all three regions, portions of the photoresist are selectively exposed, and portions of the photoresist are selectively removed, thereby exposing portions of the underlying structure (in this case, the nitride layer in the MC region 2 and the HV region 4), while leaving other portions of the underlying structure covered by the photoresist (in this case, the nitride layer in the logic region 6). Nitride etching and oxide etching are performed to remove the silicon layer and the nitride layer from the MC region 2 and the HV region 4, thereby exposing the upper surface 10a in these regions. After removing the photoresist, thermal oxidation is then performed to form an oxide layer on the exposed portions of the upper surface 10a in the MC region 2 and the HV region 4. The thermal oxidation process consumes some silicon of the substrate, thereby effectively lowering the upper surface 10a in these regions. Then, nitride etching and oxide etching are used to remove all of the oxide layer and the nitride layer from the logic region 6, thereby obtaining Figure 1A , Figure 1B and Figure 1C The upper surface 10 a in the MC region 2 and the HV region 4 is recessed relative to the upper surface 10 a in the logic region 6 by an amount R (eg, 200 Å-700 Å).

[0039] Next, an oxide layer 12 is formed on the upper surface 10a (e.g., by deposition or by thermal growth, etc.). Thereafter, a conductive layer such as polysilicon (hereinafter referred to as "poly") 14 is formed on the oxide layer 12. The polysilicon layer 14 may alternatively be in-situ doped or undoped amorphous silicon. If undoped polysilicon or amorphous silicon is used for the layer 14, implantation and annealing are performed. Then, a photolithography masking step is performed to cover the MC region 2 and the HV region 4 with a photoresist 16, but to expose the logic region 6 (i.e., the photoresist 16 is removed from the logic region 6 as part of the masking step). Then, a polysilicon etch is used to remove the polysilicon layer 14 from the logic region 6, as shown in FIG. Figure 2A , Figure 2B and Figure 2C shown.

[0040] After removing the photoresist 16, an optional oxide layer 18 is formed over the structure, followed by a nitride layer 20 formed on the oxide layer 18. A photolithographic masking step is used to selectively cover portions of each region with photoresist. Nitride etching, oxide etching, polysilicon etching, and silicon etching are used to form trenches through the nitride 20, oxide 18, polysilicon 14, oxide 12, and into the silicon substrate 10. Preferably, these trenches are 2000A-3500A deep in the logic region 6 of the substrate 10, and 1600A-3300A deep in the MC region 2 and HV region 4 of the substrate 10. These trenches are then filled with oxide 22 by oxide deposition on the nitride layer 20 and terminated by chemical mechanical polishing (CMP), such as Figure 3A , Figure 3B and Figure 3C As shown. Oxide 22 may also be referred to as STI (shallow trench isolation) oxide 22, which is a well-known isolation technology. Oxide 22 may include a liner oxide formed by thermal oxidation prior to oxide deposition.

[0041] A series of implants may be performed to form the desired wells in the substrate 10 in each of the regions 2 / 4 / 6 (where the photoresist protects one or more of the other regions during each implant), followed by an oxide etch back to recess the STI oxide 22 below the top of the nitride layer 20. Nitride etching is then used to remove the nitride layer 20. An insulating layer 24 is then formed over the structure. Preferably, the insulating layer 24 is an ONO composite layer having oxide / nitride / oxide sublayers (formed by oxide, nitride, oxide deposition and annealing). However, the insulating layer 24 may alternatively be formed by a composite of other dielectric layers or a single dielectric material without sublayers. A conductive layer such as a polysilicon layer 26 is then formed on the structure by polysilicon deposition. The polysilicon layer 26 may alternatively be in-situ doped or undoped amorphous silicon. If undoped polysilicon or amorphous silicon is used for the layer 14, polysilicon implantation and annealing are performed. A hard mask layer 28 is then formed on the polysilicon layer 26. The hard mask layer 28 may be a nitride, SiCN, or even a composite of oxide, nitride and / or SiCN layers. Figure 4A , Figure 4B and Figure 4C Shown in.

[0042] A photolithographic masking step is used to form a photoresist 30 on the structure, wherein the photoresist is removed from the HV region 4 and selectively removed from the MC region 2 to expose the hard mask layer 28 in the HV region 4 and to expose only a portion of the hard mask layer 28 in the MC region 2. A series of etches are used to remove the exposed portions of the hard mask layer 28, the polysilicon layer 26, and the insulating layer 24, thereby leaving a spaced-apart stacked structure S1 and S2 pair of hard mask layers 28, polysilicon layers 26, and insulating layers 24 in the MC region 2, and completely removing these layers from the HV region 4. The resulting structure is Figure 5A , Figure 5B and Figure 5C Shown in.

[0043] After removing the photoresist 30, oxide deposition or thermal oxidation and etching are used to form spacers 32 along the sides of the stacks S1 and S2 in the MC region 2. Nitride deposition and etching are used to form nitride spacers 34 along the sides of the oxide spacers 32. The oxide etching and nitride etching can be combined. Polysilicon etching is performed to remove the exposed portions of the polysilicon layer 14, resulting in each spaced-apart stack structure S1 / S2 also including a block of polysilicon 14. The polysilicon layer 14 is completely removed from the HV region 4. By oxide deposition and oxide anisotropic etching, oxide spacers 36 are formed on the sides of the stack structures S1 / S2 (including along the exposed ends of the blocks of polysilicon layer 14), as shown in FIG. Fig. 6A , Figure 6B and Figure 6C shown.

[0044] A photolithography masking step is used to cover the MC region 2 and the logic region 6 with a photoresist, but to expose the HV region 4. Oxide etching is used to remove the oxide layer 12 from the HV region 4. After removing the photoresist, an insulating layer 38 is then formed on these structures on the upper surface 10a of the substrate in the HV region 4 and in the MC region 2 and the logic region 6 by thermal growth and / or deposition. The insulating layer 38 can be an oxide and / or an oxynitride, and will be used as a gate oxide of the HV device. However, it should be noted that it is optional to remove and replace the oxide 12 with the insulating layer 38, and the oxide 12 can be used as part or all of the gate oxide of the HV device alternatively. After removing the photoresist, a photoresist 40 is formed on the structure, and the photoresist is removed only from the region between the stacks S1 and S2 in the MC region 2 (referred to herein as the inner stack region). An implantation process is performed to form a source region 42 in the substrate between the stacks S1 and S2. Then, an oxide etch is used to remove the insulating layer 38, oxide spacers 36, and oxide layer 12 in the inner stack region. The resulting structure is Fig. 7A , Figure 7B and Figure 7C Shown in.

[0045] After removing the photoresist 40, a tunnel oxide 44 is formed on the structure. The tunnel oxide 44 may be an oxide and / or oxynitride formed by deposition and / or thermal growth. Due to the catalytic effect of the higher dopant level in the source region 42, the tunnel oxide 44 may have a thicker portion 44a on the source region 42. A photolithographic masking step is used to cover the HV region 4 and the logic region 6, as well as the inner stacking region in the MC region, with photoresist. The region on the other side of the stacked structures S1 and S2 (referred to herein as the outer stacking region) remains exposed. At this point, an implantation may be performed on the portion of the silicon substrate 10 in the outer stacking region (i.e., those portions of the substrate below the select gate to be formed later). Oxide etching is used to remove the exposed oxide layer 12 in the outer stacking region. After removing the photoresist, an oxide layer 46 is then formed on the structure. The oxide layer 46 may be an oxide and / or oxynitride formed by deposition and / or thermal growth or any other suitable dielectric material. The formation of the oxide layer 46 thickens or becomes part of the tunnel oxide 44 and the insulating layer 38. The resulting structure is Fig. 8A , Figure 8B and Figure 8C Shown in.

[0046] A conductive layer such as a polysilicon layer 48 is formed over the structure. The polysilicon layer 48 may be in-situ doped or undoped, and may alternatively be amorphous silicon. If undoped polysilicon or amorphous silicon is used for layer 48, doping and annealing are performed. A buffer oxide layer 50 is formed over the polysilicon layer 48. A photolithographic masking step is used to cover the buffer oxide layer 50 in the HV region 4, but to expose the buffer oxide layer 50 in the MC region 2 and the logic region 6. The exposed portions of the buffer oxide layer 50 are then removed by oxide etching in the MC region 2 and the logic region 6. After removing the photoresist, a conductive layer such as a polysilicon layer 52 (which may alternatively be amorphous silicon having the same doping as the polysilicon layer 48) is then deposited over the structure. Fig.9A , Fig. 9B and Fig. 9CAs shown. Polysilicon chemical mechanical polishing (CMP) is performed to planarize the top surface of the structure, terminating on the hard mask layer 28. A further polysilicon etch back process is used to recess the upper surface of the polysilicon layer 48 below the top of the stacks S1 and S2. This completes the formation of most of the memory cells. Oxide etching is used to remove the buffer oxide 50 in the HV region 4. A protective insulating layer 54 is formed over the structure. The protective insulating layer 54 can be an oxide, a nitride, SiCN, or a combination thereof. A photolithography masking step is used to cover the MC region 2 and the HV region 4 with photoresist while exposing the logic region 6. Etching is used to remove the protective insulating layer 54 in the logic region 6. After removing the photoresist, a series of etches are then performed to remove all material layers in the logic region 6, thereby exposing the upper surface 10a of the substrate, as shown. Fig. 10A , Fig. 10B and Fig. 10C The protective insulating layer 54 protects the MC region 2 and the HV region 4 from the series of etchings.

[0047] At this point, implantation may be performed to form doped P-wells and N-wells in the substrate 10 in the logic region 6. A dielectric layer 56 (which may be used as a gate dielectric for a logic device) is formed on the exposed upper substrate surface 10a in the logic region 6. The dielectric layer 56 may be silicon oxide, silicon oxynitride, a high-K dielectric layer, or a composite thereof. A high-K insulating material is an insulating material having a dielectric constant K greater than that of silicon dioxide. Examples of high-K insulating materials include HfO2, ZrO2, TiO2, Ta2O5, and combinations thereof. A pseudo conductive layer 58 of a pseudo material (such as polysilicon) is then formed over the structure. A hard mask layer 60 is then formed on the pseudo conductive layer 58. A photolithographic masking step is used to cover selected portions of the logic region 6 with photoresist, thereby exposing the hard mask layer 60 in the entire MC region 2 and the HV region 4 and in a portion of the logic region 6. Etching is then used to remove the exposed areas of the hard mask layer 60 in the MC region 2, the HV region 4, and the logic region 6. After removing the photoresist, etching is used to remove the exposed portions of the dummy conductive layer 58 and the dielectric layer 56 (i.e., all portions of the logic region 6 not protected by the remaining portions of the hard mask layer 60), thereby leaving the logic stack structures LS1 and LS2 in the logic region 6 (i.e., where the dummy material blocks 58 are insulated from the substrate by the dielectric layer 56). Dielectric spacers 62 are formed on the sides of the logic stack structures LS1 / LS2 by deposition and etching. At this point, implantation into the substrate 10 can be performed in the logic region 6. The resulting structure is Fig.11A , Fig. 11B and Fig. 11C Shown in.

[0048] A photolithography masking step is used to cover the logic region 6, a portion of the HV region 4, and a portion of the MC region 2 (i.e., covering the inner stacking region, the stacking structures S1 and S2, and those portions of the outer stacking region immediately adjacent to the stacking structures S1 and S2) with photoresist 64. An etch is used to remove the exposed portions of the protective insulating layer 54 and the polysilicon layer 48, as shown in FIG. Fig. 12A , Fig. 12B and Fig. 12C As shown. After removing the photoresist 64, additional selective implantation and etching (i.e., by additional photolithography masking steps and implantation) may be performed in different exposed portions of the silicon substrate 10. For example, the HV region 4 and the logic region 6 may be covered by the photoresist to expose the MC region 2, and the portion of the substrate 10 covered only by the oxide layer 46 may be implanted. The MC region 2 and the logic region 6 may be covered by the photoresist to expose the HV region 4, and the portion of the substrate 10 covered only by the oxide layer 38 may be implanted.

[0049] Oxide deposition and nitride deposition followed by spacer etching are used to form oxide spacers 66 and nitride spacers 68 on the sides of stacked structures S1 / S2 in MC region 2, on the sides of stacked structures LS 1 / LS2 in logic region 6, and on the sides of these structures in HV region 4. Implantation is performed to form drain regions 74 in the substrate adjacent to nitride spacers 68 in MC region 2, source regions 76 and drain regions 78 in HV region 4 adjacent to nitride spacers 68, and source regions 80 and drain regions 82 in logic region 6 adjacent to nitride spacers 68. Implantation into any given region may be performed by forming a photoresist to block implantation into other regions to be implanted. For example, the drain region 74 in the MC region 2, the source region 76 / drain region 78 in the HV region 4, and the source region 80 / drain region 82 of the same doping type in the logic region 6 can be formed simultaneously by the following operations: a photoresist is formed on the regions of the opposite source / drain doping type, and then a single implantation is performed in the MC region 2, the HV region 4, and the logic region 6. A barrier layer 84 (first barrier layer) is deposited over the structure. A masking step is performed to cover only those regions where the barrier layer 84 will remain with the photoresist. Then, one or more etchings are performed to remove the protective insulating layer 54 from the MC region 2 and the HV region 4, remove the exposed portion of the barrier layer 84, and remove the exposed portion of the oxide layer 46 in the MC region 2 and the oxide layer 38 in the HV region 4. After removing the photoresist, metal deposition and annealing are performed to form silicide 86 on the top surface of the exposed blocks of the polysilicon 48, the source region 76 / 80, and the drain region 74 / 78 / 82. The barrier layer 84 prevents silicide from forming in any portion where silicide is not desired. Optionally, the barrier layer 84 may be maintained in selected portions of the source / drain regions 74 / 76 / 78 / 80 / 82 and / or the polysilicon gate region 48 to block silicide formation in these selected regions. The resulting structure is Fig.13A , Fig. 13B and Fig. 13C Shown in.

[0050] Etching is used to remove the remaining portion of the hard mask layer 60 on the stacked structures LS 1 / LS2 in the logic region 6, the hard mask layer 28 on the stacked structures S 1 / S2 in the MC region 2, and any exposed nitride spacers 68 in all three regions. A layer 88 (e.g., nitride) is formed over the structure. A relatively thick layer of interlayer dielectric (ILD) insulating material 90 is then formed over layer 88. CMP is performed to planarize and recess the ILD insulating material 90, thereby exposing the pseudo conductive layer 58 in the logic region 6. A photolithographic masking step is used to cover the MC region 2 and the HV region 4 with photoresist while exposing the logic region 6. Then, polysilicon etching is used to remove the pseudo conductive layer 58 block in the logic region 6. Optionally, the dielectric layer 56 may also be removed in this step. After removing the photoresist, a dielectric layer 92 such as silicon oxide, oxynitride, a high-K dielectric layer, or a composite thereof may optionally be deposited over the structure. A metal gate material 94 layer such as Al, Ti, TiAlN, TaSiN, TaN, TiN or other suitable metal materials or their composites is formed over the dielectric layer 92. Then, CMP is performed to remove the dielectric layer 92 and the metal gate material layer 94, leaving a block of metal material 94 lined with the dielectric layer 92 in the logic region 6. The final structure is Fig.14A , Fig. 14B and Fig. 14C Shown in.

[0051] Fig.15The final memory cell structure in the MC region 2 is shown, which includes pairs of memory cells, each pair of memory cells sharing a source region 42 (first source region) spaced apart from two drain regions 74 (first drain regions), with a channel region 96 in the silicon substrate 10 extending between them. Each memory cell includes: a floating gate 14a (formed by the remaining portion of the polysilicon layer 14), which is disposed above and insulated from a first portion of the channel region 96 for controlling its conductivity; a control gate 26a (a first non-floating gate, formed by the remaining portion of the polysilicon layer 26), which is disposed above and insulated from the floating gate 14a; an erase gate 48b (a second non-floating gate, formed by a second portion of the polysilicon layer 48), which is disposed above and insulated from a source region 42 (shared by the memory cell pair); and a select gate 48a (a third non-floating gate, which may also be referred to as a word line gate, and formed by a first portion of the polysilicon layer 48), which is disposed above and insulated from a second portion of the channel region 96 for controlling its conductivity. The memory cell pairs extend in a column direction (bit line direction) and form columns of memory cells with oxide 22 between adjacent columns. A row of control gates 26a is formed as a continuous control gate line that connects the control gates 26a of an entire row of memory cells together. A row of select gates 48a is formed as a continuous select gate line (also called a word gate line) that connects the select gates 48a of an entire row of memory cells together. A row of erase gates 48b is formed as a continuous erase gate line that connects the erase gates 48b of an entire row of memory cell pairs together.

[0052] The final HV equipment in HV zone 4 is Fig.16 Each HV device includes a source region 76 and a drain region 78 (second source region and drain region) spaced apart, with a channel region 98 of the silicon substrate 10 extending therebetween. A conductive gate 48c (fourth non-floating gate) formed by a third portion of the polysilicon layer 48 is disposed above the channel region 98 and insulated therefrom for controlling its conductivity.

[0053] The final logical device in logical region 6 is Fig.17 Each logic device includes a source region 80 and a drain region 82 (third source region and drain region) spaced apart, with a channel region 100 of a silicon substrate 10 extending therebetween. A metal gate 94 is disposed above the channel region 100 and insulated from the channel region (through a dielectric layer 92) for controlling the conductivity of the channel region.

[0054] The method described above for forming memory cells, HV devices, and logic devices on the same substrate has many advantages. The formation of the memory cells and HV devices is completed before the optional high-K dielectric gates and metal gates are formed in the logic region 6, so that the optional high-K dielectric layer 92 and metal gate 94 in the logic region 6 are not adversely affected by the formation of the memory cells and HV devices. The process steps for forming the gates in the MC region 2 and the HV region 4 are separate and independent from the process steps for forming the gates in the logic region 6 (and can be customized relative to the process steps for forming the gates in the logic region). After the formation of most of the memory cells and HV devices is completed and before processing in the logic region 6 (i.e., before removing the layers left by the formation of the memory cells and HV devices in the logic region 6 and before depositing and removing the layers for forming the logic devices (including the removal of the dummy conductive layer 58), not limiting), the MC region 2 and the HV region 4 are covered by a protective insulating layer 54. The upper surface 10a of the silicon substrate 10 is recessed in the MC region 2 and the HV region 4 relative to the upper surface of the substrate in the logic region 6 to accommodate taller structures in the MC region 2 / HV region 4 (i.e., so that the top of the shorter logic device in the logic region 6 is slightly higher than the top of the taller memory cell and HV device in the MC region 2 / HV region 4, and so that it can be processed using CMP across all three regions, for example, during the CMP step of logic gate formation, the top of the select gate 48a and the HV gate 48c are intact). Layer 88 protects the silicide polysilicon block 48 from the CMP used to form the metal logic gate 94, and the control gate polysilicon 26 assists as a stop layer for this CMP. The silicide 86 improves the conductivity of the drain region 74 as well as the source region 76 / drain region 78, the source region 80 / drain region 82, the select gate 48a, the erase gate 48b, and the HV gate 48c. The memory cell select gate 48a, the memory cell erase gate 48b, and the HV device gate 48c can be formed using a single conductive material deposition (i.e., a single polysilicon layer formed by a single polysilicon deposition can be used to form all three types of gates). In addition, the same polysilicon etch can be used to define one of the edges of each select gate 48a and both edges of each HV gate 48c. The thicknesses of the various layers 46, 12, 38, and 56 under the various gates are independent of each other, and each layer is optimized for its corresponding gate operation. For example, the oxide layer 46 under the select gate 48a is preferably thinner than the oxide layer 12 under the floating gate 14a. Finally, at the same point in the process, the same etch or etch group is used to remove the protective insulating layer 54 from the MC region 2 and the HV region 4 and remove the exposed portion of the barrier layer 84, which simplifies and enhances the reliability of this portion of the formation process.

[0055] 18A to 18C and FIG. 19A to FIG. 19CA first alternative embodiment is shown, which is described above with respect to the MC region 2. Figures 1A to 12A 、HV zone 4 Figures 1B to 12B and Figures 1C to 12C Start with the same processing steps as described. Fig. 12A , Fig. 12B and Fig. 12C Starting with the structure shown, after removing the photoresist 64, oxide spacers 66 and nitride spacers 68 are formed as described above. Then, a masking step is performed to cover the logic region 6 with photoresist 102, but leaving the memory region 2 and HV region 4 exposed, as shown in FIG. Fig.18A , Fig.18B and Fig. 18C As shown. One or more etches are then used to remove the protective layer 54 from the MC region 2 and the HV region 4, which also removes the exposed oxide layer 46 in the MC region 2 and partially removes (i.e., thins) the exposed portions of the insulating layer 38 in the HV region 4. After removing the photoresist 102, the source regions 76 / 80 and the drain regions 74 / 78 / 82 are formed by implantation as described above. A barrier layer 84 is deposited over the structure. A masking step is performed to cover only those areas where the barrier layer 84 will remain with the photoresist. Then, an etch is performed to remove the exposed portions of the barrier layer 84. After removing the photoresist, metal deposition and annealing are performed to form silicide 86 on the top surfaces of the exposed blocks of polysilicon 48, source regions 76 / 80, and drain regions 74 / 78 / 82. The resulting structure is Fig.19A , Fig.19B and Fig.19C It is shown in Fig.13A , Fig. 13B and Fig. 13C The structure in is substantially the same as in the embodiment except that the barrier layer 84 is formed on the portion of the layer 38 that has been previously thinned. FIG. 14A to FIG. 14C The steps are described to complete the process.

[0056] An additional advantage of this first alternative embodiment is that the masking step using photoresist 102 can remove or thin layers 38, 46 and 54 in MC region 2 and HV region 4 before subsequent etching of barrier layer 84, and the formation of silicide layer 86 can be performed without changing the etching recipe of barrier layer 84, so that the performance of the resulting logic device is not adversely affected.

[0057] An additional advantage of this first alternative embodiment is that, due to the masking step utilizing photoresist 102, one or more etches can remove or thin layers 38, 46, and 54 in MC region 2 and HV region 4 prior to subsequent deposition and etching of barrier layer 84, and the formation of silicide layer 86 can be performed without changing the etching recipe for barrier layer 84, so that the performance of the resulting logic device is not adversely affected.

[0058] FIG. 20A to FIG. 20C and FIG. 21A to FIG. 21C A second alternative embodiment is shown, which is described above with respect to MC region 2. Figures 1A to 12A 、HV zone 4 Figures 1B to 12B and Figures 1C to 12C Start with the same processing steps as described. Fig. 12A , Fig. 12B and Fig. 12C Starting with the structure shown, after removing the photoresist 64, oxide spacers 66 and nitride spacers 68 are formed as described above. Then, a masking step is performed to cover the logic region 6 with photoresist 104, cover the spacers 66 / 68 and the exposed portion of the oxide layer 46 in the MC region 2 with photoresist 104, but leave the remaining portion of the MC region 2 and the entire HV region 4 exposed, as shown. Fig. 20A , Fig. 20B and Fig. 20C As shown. One or more etches are then used to remove the protective insulating layer 54 from the MC region 2 and the HV region 4, which also partially removes (i.e., thins) the exposed portions of the insulating layer 38 in the HV region 4. After removing the photoresist 104, the source regions 76 / 80 and the drain regions 74 / 78 / 82 are formed by implantation as described above. Then, a barrier layer 84 is deposited over the structure. A masking step is performed to cover only those areas where the barrier layer 84 will remain with the photoresist. Then, an etch is performed to remove the exposed portions of the barrier layer 84, which also removes the exposed portions of the oxide layer 46 in the MC region 2. After removing the photoresist, metal deposition and annealing are performed to form silicide 86 on the top surfaces of the exposed blocks of polysilicon 48, source regions 76 / 80, and drain regions 74 / 78 / 82. The resulting structure is Fig.21A , Fig.21B and Fig. 21C It is shown in Fig.13A , Fig. 13B and Fig. 13C The structure in is substantially the same as in the embodiment except that the barrier layer 84 is formed on the portion of the layer 38 that has been previously thinned. FIG. 14A to FIG. 14C The steps are described to complete the process.

[0059] Additional advantages of this second alternative embodiment include that the formation of silicide does not impact the baseline logic process, and the photoresist 104 covering the drain region 74 in the MC region 2 can protect the height of the STI oxide 22 for better memory cell performance control.

[0060] FIG. 22A to FIG. 22C and FIG. 23A to FIG. 23C A third alternative embodiment is shown, which is described above with respect to MC region 2. Figures 1A to 12A、HV zone 4 Figures 1B to 12B and Figures 1C to 12C Start with the same processing steps as described. Fig. 12A , Fig. 12B and Fig. 12C Starting with the structure shown, after removing the photoresist 64, oxide spacers 66 and nitride spacers 68 are formed as described above. Then, a masking step is performed to cover the logic region 6 with photoresist 106, cover the spacers 66 / 68 and the exposed portions of the oxide layer 46 in the MC region 2 with photoresist 106, and cover the portion of the protective insulating layer 54 in the MC region 2 that is vertically located above the source region 42 with photoresist 106, but leave the remaining portion of the MC region 2 and the entire HV region 4 exposed, as shown. Fig.22A , Fig. 22B and Fig. 22C As shown. One or more etches are then used to remove the exposed portions of the protective insulating layer 54 from the MC region 2 and the protective insulating layer 54 from the HV region 4, which also partially removes (i.e., thins) the exposed portions of the insulating layer 38 in the HV region 4. After removing the photoresist 106, the source regions 76 / 80 and the drain regions 74 / 78 / 82 are formed by implantation as described above. A barrier layer 84 is deposited over the structure. A masking step is performed to cover only those areas where the barrier layer 84 will remain with the photoresist. Then, an etch is performed to remove the exposed portions of the barrier layer 84, which also removes the exposed portions of the oxide layer 46 in the MC region 2. After removing the photoresist, metal deposition and annealing are performed to form silicide 86 on the top surfaces of the exposed blocks of the polysilicon layer 48, the source regions 76 / 80, and the drain regions 74 / 78 / 82. The resulting structure is Fig.23A , Fig. 23B and Fig.23C It is shown in Fig.13A , Fig. 13B and Fig. 13C The structure in is substantially the same as that in FIG. 1 , except that the barrier layer 84 is formed on a portion of the previously thinned insulating layer 38, and the silicide is not formed on the polysilicon block 48 (finally the erase gate 48 b) vertically disposed above the source region 42 in the MC region 2. Then, the above steps relative to FIG. 14A to FIG. 14C The steps are described to complete the process.

[0061] Additional advantages of this third alternative embodiment include that the formation of the silicide 86 does not affect the baseline logic process, the photoresist 106 covering the drain region 74 in the MC region 2 can protect the height of the STI oxide 22 for better memory cell performance control, and the photoresist 106 covering the erase gate 48b in the MC region 2 protects the layer 54 from etching.

[0062] FIG. 24A to FIG. 28A , FIG. 24B to FIG. 28B and FIG. 24C to FIG. 28C A fourth alternative embodiment is shown, which is described above with respect to MC region 2. Figures 1A to 12A 、HV zone 4 Figures 1B to 12B and Figures 1C to 12C Start with the same processing steps as described. Fig. 12A , Fig. 12B and Fig. 12C Starting with the structure shown, after removing the photoresist 64, a masking step is performed to cover the MC region 2 and the logic region 6 with photoresist 108, thereby exposing the HV region 4. Implantation can be performed into the HV region 4 portion of the silicon substrate 10. Then, oxide etching is used to thin the protective insulating layer 54 in the HV region 4 and the exposed portion of the insulating layer 38, as shown in FIG. Fig.24A , Fig. 24B and Fig.24C As shown. After removing the photoresist 108, oxide spacers 66 and nitride spacers 68 are formed as described above. Then, source regions 76 / 80 and drain regions 74 / 78 / 82 are formed by implantation as described above. A barrier layer 84 is deposited over the structure. A masking step is performed to cover only those areas where barrier layer 84 will remain with photoresist. Then, etching is performed to remove the exposed portions of barrier layer 84, which also removes the exposed portions of oxide layer 46 in MC region 2 and the exposed portions of thinned protective insulating layer 54 in HV region 4. After removing the photoresist, metal deposition and annealing are performed to form silicide 86 on the top surfaces of the exposed blocks of polysilicon layer 48, source regions 76 / 80, and drain regions 74 / 78 / 82 in HV region 4. The resulting structure is Fig.25A , Fig.25B and Fig.25C It is shown in Fig.13A , Fig. 13B and Fig. 13C The structure in is substantially the same, except that barrier layer 84 is formed on a portion of insulating layer 38 that has been previously thinned, and silicide is not formed on the bulk of polysilicon layer 48 in MC region 2 .

[0063] As similarly disclosed above, etching is used to remove the remaining portion of hard mask layer 60 on stacked structures LS1 / LS2 in logic region 6, hard mask layer 28 on stacked structures S1 / S2 in MC region 2, and any exposed nitride spacers 68 in all three regions. A layer 88 (e.g., nitride) is formed over the structure. A relatively thick layer of interlayer dielectric (ILD) insulating material 90 is then formed on layer 88. CMP is performed to planarize ILD insulating material 90 to expose blocks of polysilicon layer 26 and polysilicon layer 48 in MC region 2, and dummy conductive layer 58 in logic region 6. The resulting structure is Fig.26A , Fig.26B and Fig.26C Shown in.

[0064] A barrier layer 110 (second barrier layer) is formed over the structure and patterned using a masking step to expose a portion of the MC region 2 (i.e., to expose the polysilicon blocks 48 and the polysilicon blocks 26), while leaving the HV region 4 and the logic region 6 covered by the second barrier layer 110. Metal deposition and annealing are then performed to form silicide 86 on the top surfaces of the exposed blocks of the polysilicon layer 48 and the polysilicon layer 26 in the MC region 2, as shown in FIG. Fig.27A , Fig.27B and Fig.27C As shown. A masking step is used to cover the structure except the logic region 6 with photoresist. Then, the barrier layer 110 is removed from the logic region 6. As similarly disclosed above, polysilicon etching is then used to remove the blocks of pseudo conductive layer 58 in the logic region 6. Optionally, the dielectric layer 56 may also be removed in this step. After removing the photoresist, optionally, a dielectric layer 92 such as silicon oxide, oxynitride, a high-K dielectric layer, or a composite thereof may be deposited over the structure. A metal gate material 94 layer such as Al, Ti, TiAlN, TaSiN, TaN, TiN or other suitable metal materials (non-limiting) or a composite thereof is formed over the dielectric layer 92. Then, CMP is performed to remove the dielectric layer 92 and the metal gate material layer 94, leaving blocks of metal gate material 94 lined with the dielectric layer 92 in the logic region 6. The final structure is Fig.28A , Fig.28B and Fig.28C Shown in.

[0065] Advantages of the fourth alternative embodiment include that, due to the masking step of forming the photoresist 108, the oxide etch can remove or thin the layers 38 and 54 in the HV region 4 before the subsequent etching of the barrier layer 84 without changing the etching recipe of the logic process barrier layer 84, the silicide layer 86 can be formed without adversely affecting the performance of the logic device, and the memory cell performance is improved by exposing the polysilicon blocks 48 and 26 in the MC region 2 for silicide formation without affecting any other areas protected by the barrier layer 110.

[0066] FIG. 29A to FIG. 30A , FIG. 29B to FIG. 30B and FIG. 29C to FIG. 30C A fifth alternative embodiment is shown, which is derived from the description above with respect to the fourth alternative embodiment. Fig.26A , Fig.26B and Fig.26CA second barrier layer 110 is formed over the structure as described above, but the second barrier layer is patterned using a masking step to expose portions of the MC region 2 (i.e., to expose the polysilicon blocks 48, but leave the polysilicon blocks 26 covered), while leaving the HV region 4 and the logic region 6 covered by the second barrier layer 110. Metal deposition and annealing are then performed to form silicide 86 on the top surface of the exposed blocks of polysilicon 48 in the MC region 2, as shown in FIG. Fig.29A , Fig.29B and Fig.29C Then execute the above relative to FIG. 28A to FIG. 28C Describe the steps to complete the process, such as Fig. 30A , Fig. 30B and Fig. 30C shown.

[0067] Additional advantages of this fifth alternative embodiment include barrier layer 110 covering polysilicon chunks 26 to prevent silicide from forming on polysilicon chunks 26 , which may bridge to silicide 86 formed on polysilicon chunks 48 .

[0068] FIG. 31A to FIG. 32A , FIG. 31B to FIG. 32B and FIG. 31C to FIG. 32C A sixth alternative embodiment is shown, which is derived from the sixth alternative embodiment described above with respect to the fourth alternative embodiment. Fig.26A , Fig.26B and Fig.26C A second barrier layer 110 is formed over the structure as described above, but the second barrier layer is patterned using a masking step to expose portions of the MC region 2 (i.e., to expose some of the polysilicon blocks 48, but to leave the polysilicon blocks 26 and 48 over the source region 42 covered), while leaving the HV region 4 and the logic region 6 covered by the second barrier layer 110. Metal deposition and annealing are then performed to form silicide 86 on the top surfaces of the exposed polysilicon blocks 48 in the MC region 2, as shown in FIG. Fig.31A , Fig.31B and Fig.31C Then execute the above relative to FIG. 28A to FIG. 28C Describe the steps to complete the process, such as Fig.32A , Fig.32B and Fig.32C shown.

[0069] Additional advantages of this sixth alternative embodiment include that barrier layer 110 covers polysilicon blocks 26 and 48 b to prevent two closely spaced silicide layers on polysilicon blocks 26 and 48 from bridging together, and also prevents oxide layer 44 from being damaged when etching second barrier layer 110 .

[0070] FIG. 33A to FIG. 34A , FIG. 33B to FIG. 34B as well as FIG. 33C to FIG. 34CA seventh alternative embodiment is shown, which is derived from the seventh alternative embodiment described above with respect to the fourth alternative embodiment. Fig.26A , Fig.26B and Fig.26C The seventh alternative embodiment is similar to the fourth alternative embodiment, except that the metal logic gate material 94 is formed before the memory cell gate silicide is formed (using the above relative to Fig.14A , Fig. 14B , Fig. 14C The process described), such as Fig.33A , Fig.33B , Fig.33C As shown. Then, a second barrier layer 110 is formed over the structure and patterned using a masking step to expose a portion of the MC region 2 (i.e., to expose the polysilicon block 48 and the polysilicon block 26), while leaving the HV region 4 and the logic region 6 covered by the second barrier layer 110. Metal deposition and annealing are then performed to form silicide 86 on the top surfaces of the exposed blocks of polysilicon 48 and polysilicon 26 in the MC region 2, as shown. Fig.34A , Fig.34B and Fig.34C shown.

[0071] Additional advantages of this seventh alternative embodiment include better memory cell performance, exposing and forming silicide on polysilicon blocks 48 and 26 without adversely affecting any other area having barrier layer 110, and forming silicide on polysilicon blocks 48 and 26 after metal gate formation in the logic area to avoid any metal CMP polishing of silicide 86 in the event that the height of the memory cell is higher than the top surface of metal gate 94.

[0072] Fig.33A , Fig.33B , Fig.33C and Fig.35A , Fig.35B , Fig.35C An eighth alternative embodiment is shown, which is derived from the eighth alternative embodiment described above with respect to the fourth alternative embodiment. Fig.26A , Fig.26B and Fig.26C The eighth alternative embodiment is similar to the fifth alternative embodiment, except that the metal logic gate material 94 is formed before the memory cell gate silicide is formed (using the above relative to Fig.14A , Fig. 14B , Fig. 14C The process described), such as Fig.33A , Fig.33B , Fig.33CAs shown. Then, a second barrier layer 110 is formed over the structure and patterned using a masking step to expose a portion of the MC region 2 (i.e., exposing the polysilicon block 48 but leaving the polysilicon block 26 covered), while leaving the HV region 4 and the logic 6 covered by the second barrier layer 110. Metal deposition and annealing are then performed to form silicide 86 on the top surface of the exposed block of the polysilicon layer 48 in the MC region 2, as shown. Fig.35A , Fig.35B and Fig.35C shown.

[0073] Additional advantages of this eighth alternative embodiment include forming silicide 86 on polysilicon blocks 48 and 26 after metal gate formation in the logic area to avoid any metal CMP polishing of silicide 86 when the height of the memory cell is higher than the top surface of metal gate 94, and barrier layer 110 covering polysilicon block 26 to prevent silicide from forming on polysilicon block 26, which may bridge to silicide 86 formed on polysilicon block 48.

[0074] Fig.33A , Fig.33B , Fig.33C and Fig.36A , Fig.36B , Fig.36C A ninth alternative embodiment is shown, which is derived from the above description with respect to the fourth alternative embodiment. Fig.26A , Fig.26B and Fig.26C The ninth alternative embodiment is similar to the sixth alternative embodiment, except that the metal logic gate material 94 is formed before the memory cell gate silicide is formed (using the above relative to Fig.14A , Fig. 14B , Fig. 14C The process described), such as Fig.33A , Fig.33B , Fig.33C As shown. Then, a second barrier layer 110 is formed over the structure, and the second barrier layer is patterned using a masking step to expose a portion of the MC region 2 (i.e., expose some of the polysilicon blocks 48, but leave the polysilicon blocks 26 and the polysilicon blocks 48 above the source region 42 covered), while leaving the HV region 4 and the logic region 6 covered by the second barrier layer 110. Metal deposition and annealing are then performed to form silicide 86 on the top surface of the exposed polysilicon blocks 48 in the MC region 2, as shown. Fig.36A , Fig.36B and Fig.36C shown.

[0075] Additional advantages of this ninth alternative embodiment include the silicide 86 formed on the polysilicon block 48 after the metal gate is formed in the logic area to avoid any metal CMP polishing of the silicide in the case where the height of the memory cell is higher than the top surface of the metal gate 94, and the barrier layer 110 covering the polysilicon blocks 26 and 48b to avoid bridging the two closely spaced silicide layers on the polysilicon blocks 26 and 48 together, and also to avoid the oxide layer 44 from being damaged when etching the second barrier layer 110.

[0076] It should be understood that the present invention is not limited to the embodiments described above and shown herein, but covers any and all variations that fall within the scope of the appended claims. For example, the reference to the present invention herein is not intended to limit the scope of any claim or claim term, but only refers to one or more features that can be covered by one or more of these claims. The examples of materials, processes and numerical values ​​described above are merely exemplary and should not be regarded as limiting the claims. In addition, it is obvious from the claims and the specification that not all method steps need to be performed in the exact order shown or claimed, but need to be performed in any order that allows the memory cell area and logic area of ​​the present invention to be properly formed, unless otherwise specified in the claims. Finally, a single material layer can be formed into multiple such or similar material layers, and vice versa.

[0077] It should be noted that, as used herein, the terms "above" and "on" both include "directly on" (no intervening material, element or space is provided between) and "indirectly on" (intervening material, element or space is provided between). Similarly, the term "adjacent" includes "directly adjacent" (no intervening material, element or space is provided between) and "indirectly adjacent" (intervening material, element or space is provided between). For example, forming an element "above" a substrate may include directly forming the element on the substrate without intervening material / element in between, and indirectly forming the element on the substrate with one or more intervening materials / elements in between.

Claims

1. A method of forming a semiconductor device, comprising: Providing a substrate of semiconductor material, the substrate of semiconductor material comprising a first region, a second region and a third region; making an upper surface of the substrate in the first region and an upper surface of the substrate in the second region concave relative to an upper surface of the substrate in the third region; forming a pair of stacked structures in the first region, wherein each of the stacked structures includes a floating gate of a conductive material disposed above and insulated from the upper surface of the substrate in the first region, and a first non-floating gate of a conductive material disposed above and insulated from the floating gate; forming a first source region in the substrate between the pair of stacked structures in the first region; forming a second non-floating gate disposed above the first source region in the first region and insulated from the first source region; forming a dummy material block disposed above the upper surface of the substrate in the third region and insulated from the upper surface; forming third non-floating gates of a conductive material, the third non-floating gates being disposed above and insulated from the upper surface of the substrate in the first region and each laterally adjacent to and insulated from one of the stacked structures; forming a fourth non-floating gate of a conductive material disposed above and insulated from the upper surface of the substrate in the second region; forming first drain regions in the substrate in the first region, each first drain region being adjacent to one of the third non-floating gates; forming second source regions in the substrate in the second region, each second source region being adjacent to one of the fourth non-floating gates; forming second drain regions in the substrate in the second region, each second drain region being adjacent to one of the fourth non-floating gates; forming a third source region in the substrate in the third region, the third source region being adjacent to the dummy material block; forming a third drain region in the substrate in the third region, the third drain region being adjacent to the dummy material block; forming a first blocking layer over at least a portion of one of the fourth non-floating gates in the second region; forming silicide on the first drain region, the second drain region, and the third drain region, on the second source region and the third source region, and on a top surface of the fourth non-floating gate that is not under the first barrier layer, wherein the first barrier layer prevents the silicide from being formed on at least a portion of the upper surface of one of the fourth non-floating gates that is under the first barrier layer, and allows the silicide to be formed on other portions of the upper surface of the fourth non-floating gate that are not under the first barrier layer; as well as The dummy material block is replaced with a metal material block.

2. The method according to claim 1, characterized in that The forming of the second non-floating gate, the third non-floating gate, and the fourth non-floating gate includes: forming a conductive layer disposed above the upper surface in the first region and the second region and insulated from the upper surface; forming a protective insulating layer over the conductive layer in the first region and the second region; Portions of the protective insulating layer and portions of the conductive layer in the first region and the second region are etched to form the third non-floating gate from the first portion of the conductive layer and to form the fourth non-floating gate from the third portion of the conductive layer, wherein the second portion of the conductive layer between the pair of stacked structures constitutes the second non-floating gate.

3. The method according to claim 2, characterized in that The method further comprises: One or more etchings are performed to remove portions of the protective insulating layer over the second non-floating gate, the third non-floating gate, and the fourth non-floating gate, and to remove at least a portion of the first barrier layer in the second region.

4. The method according to claim 3, characterized in that: The forming of the silicide further includes forming a silicide on top surfaces of the second non-floating gate and the third non-floating gate.

5. The method according to claim 2, characterized in that: The method further comprises: forming a photoresist over the first region, the second region, and the third region; removing the photoresist from the first region and the second region; After the removing of the photoresist and before the forming of the silicide, portions of the protective insulating layer over the second non-floating gate, the third non-floating gate, and the fourth non-floating gate are removed.

6. The method according to claim 5, characterized in that The forming of the silicide further includes forming a silicide on top surfaces of the second non-floating gate and the third non-floating gate.

7. The method according to claim 2, characterized in that: Also includes: forming a photoresist over the first region, the second region, and the third region; removing the photoresist from the second region and removing a portion of the photoresist over the first non-floating gate, the second non-floating gate, and the third non-floating gate; After the removing of the photoresist and before the forming of the silicide, portions of the protective insulating layer over the second non-floating gate, the third non-floating gate, and the fourth non-floating gate are removed.

8. The method according to claim 7, characterized in that The forming of the silicide further includes forming a silicide on top surfaces of the second non-floating gate and the third non-floating gate.

9. The method according to claim 2, characterized in that: Also includes: forming a photoresist over the first region, the second region, and the third region; removing the photoresist from the second region and removing a portion of the photoresist above the third non-floating gate; After the removing of the photoresist and before the forming of the silicide, portions of the protective insulating layer over the third non-floating gate and the fourth non-floating gate are removed.

10. The method according to claim 9, characterized in that The forming of the silicide further includes forming a silicide on a top surface of the third non-floating gate.

11. The method according to claim 2, characterized in that Also includes: forming a photoresist over the first region, the second region, and the third region after the forming of the protective insulating layer and before the forming of the first barrier layer; removing the photoresist from the second region; as well as A portion of the protective insulating layer on the fourth non-floating gate is thinned.

12. The method according to claim 11, characterized in that After the formation of the silicide, the method further comprises: forming a second barrier layer over the first region, the second region, and the third region; removing a portion of the second barrier layer over the first non-floating gate, the second non-floating gate, and the third non-floating gate; Silicide is formed on top surfaces of the first non-floating gate, the second non-floating gate, and the third non-floating gate.

13. The method according to claim 11, characterized in that After the formation of the silicide, the method further comprises: forming a second barrier layer over the first region, the second region, and the third region; removing a portion of the second barrier layer above the second non-floating gate and the third non-floating gate; Silicide is formed on top surfaces of the second non-floating gate and the third non-floating gate.

14. The method according to claim 11, characterized in that After the formation of the silicide, the method further comprises: forming a second barrier layer over the first region, the second region, and the third region; removing a portion of the second barrier layer above the third non-floating gate; A silicide is formed on a top surface of the third non-floating gate.

15. The method according to claim 11, characterized in that After the formation of the silicide and after replacing the dummy material block with the metal material block, the method further includes: forming a second barrier layer over the first region, the second region, and the third region; removing a portion of the second barrier layer over the first non-floating gate, the second non-floating gate, and the third non-floating gate; Silicide is formed on top surfaces of the first non-floating gate, the second non-floating gate, and the third non-floating gate.

16. The method according to claim 11, characterized in that After the formation of the silicide and after replacing the dummy material block with the metal material block, the method further includes: forming a second barrier layer over the first region, the second region, and the third region; removing a portion of the second barrier layer above the second non-floating gate and the third non-floating gate; Silicide is formed on top surfaces of the second non-floating gate and the third non-floating gate.

17. The method according to claim 11, characterized in that After the formation of the silicide and after replacing the dummy material block with the metal material block, the method further includes: forming a second barrier layer over the first region, the second region, and the third region; removing a portion of the second barrier layer above the third non-floating gate; A silicide is formed on a top surface of the third non-floating gate.

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