Eye width measurement device and method

Abstract

The present invention discloses an eye width measurement device and a method for measuring eye width, which are used in a clock data recovery circuit. The eye width measurement device includes a delay circuit, a first multiplexer, and a correction circuit. The delay circuit includes an input terminal and an output terminal. The first multiplexer is coupled to the delay circuit and includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first multiplexer is coupled to a clock input terminal of the eye width measurement device, the second input terminal of the first multiplexer is coupled to the output terminal of the delay circuit, and the output terminal of the first multiplexer is coupled to the input terminal of the delay circuit. The correction circuit is coupled to the delay circuit and can be used to receive an oscillation clock from the delay circuit and a reference clock, so as to calibrate the oscillation clock using the reference clock.

Description

Technical Field

[0001] The present invention relates to an eye width measurement device (EWM) and a method for measuring eye width, and more particularly to an eye width measurement device that can be used in a clock and data recovery (CDR) circuit and a method for measuring the eye width of input data of the CDR circuit. Background Art

[0002] Please refer to Figure 1 , Figure 1 The schematic diagram shows the circuit structure of a high-speed data receiver 10. High-speed data receiver 10 includes an equalizer (EQ) 102 and a clock and data recovery (CDR) circuit 104. Equalizer 102 can be used to compensate for signal loss that may occur in the channel. CDR circuit 104 can be used to extract the clock signal embedded in the received data signal. High-speed data receiver 10 can be implemented in an integrated circuit (IC) included in a chip.

[0003] Generally, the eye width of the input data of the high-speed data receiver 10 can be measured through external testing. However, the eye width of the internal signal between the equalizer 102 and the clock and data recovery circuit 104 within the high-speed data receiver 10 (e.g., the input data of the clock and data recovery circuit 104) is often not measured through external testing. To obtain the eye width of the equalized data signal, the integrated circuit must include an eye width monitor (EWM) to detect the internal signals of the integrated circuit, which increases circuit cost and complexity.

[0004] A relatively simple method for measuring eye width utilizes a delay line to generate multiple clock phases. This method requires only a delay circuit and a sampling circuit to achieve eye width measurement. However, the delay line's delay is susceptible to process, voltage, and temperature (PVT) variations, resulting in errors. This makes it difficult to accurately measure the eye width of internal IC signals. Therefore, improvements are needed in this existing technology. Summary of the Invention

[0005] Therefore, the main object of the present invention is to provide a novel eye width measurement device (Eye Width Monitor, EWM) to accurately measure the eye width of a data signal included in a clock and data recovery (CDR) circuit within an integrated circuit (IC).

[0006] One embodiment of the present invention discloses an eye width measurement device for use in a clock data recovery circuit. The eye width measurement device includes a delay circuit, a first multiplexer, and a correction circuit. The delay circuit includes an input and an output. The first multiplexer is coupled to the delay circuit and includes a first input, a second input, and an output. The first input of the first multiplexer is coupled to a clock input of the eye width measurement device, the second input of the first multiplexer is coupled to the output of the delay circuit, and the output of the first multiplexer is coupled to the input of the delay circuit. The correction circuit is coupled to the delay circuit and can be used to receive an oscillation clock from the delay circuit and a reference clock, and to calibrate the oscillation clock using the reference clock.

[0007] Another embodiment of the present invention discloses a method for measuring eye width for a clock data recovery circuit. The method includes the following steps: connecting a delay circuit as an oscillator to calibrate an oscillation clock of the delay circuit using a reference clock; determining a delay setting for the delay circuit corresponding to the calibrated oscillation clock; and sampling input data of the clock data recovery circuit at the delay setting corresponding to the calibrated oscillation clock to measure the eye width of the input data of the clock data recovery circuit.

[0008] Another embodiment of the present invention discloses an eye width measurement device for use in a clock data recovery circuit. The eye width measurement device includes a delay circuit, a first multiplexer, and a frequency comparator. The delay circuit includes an input and an output. The first multiplexer is coupled to the delay circuit and includes a first input, a second input, and an output. The first input of the first multiplexer is coupled to a clock input of the eye width measurement device, the second input of the first multiplexer is coupled to the output of the delay circuit, and the output of the first multiplexer is coupled to the input of the delay circuit. The frequency comparator is coupled to the delay circuit and can be used to receive an oscillation clock from the delay circuit and a reference clock to determine the ratio of the frequency of the reference clock to the frequency of the oscillation clock.

[0009] Another embodiment of the present invention discloses a method for measuring eye width for a clock data recovery circuit. The method includes the following steps: connecting a delay circuit as an oscillator to determine the ratio of the frequency of a reference clock to the frequency of an oscillation clock from the delay circuit; sampling input data of the clock data recovery circuit using multiple sampling clocks of the delay circuit to obtain a correct number of clocks; and calculating the eye width of the input data of the clock data recovery circuit based on the ratio and the correct number of clocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of a high-speed data receiver.

[0011] Figure 2 FIG. 1 is a schematic diagram of a data receiver according to an embodiment of the present invention.

[0012] Figure 3 FIG1 is a schematic diagram of an eye width measurement device according to an embodiment of the present invention.

[0013] Figure 4 for Figure 3 Schematic diagram of the eye width measurement device operating in clock scanning mode.

[0014] Figure 5 An exemplary waveform diagram of sampling input data by a sampling clock.

[0015] Figure 6 FIG. 1 is a flow chart of an eye width measurement process according to an embodiment of the present invention.

[0016] Figure 7 FIG1 is a schematic diagram of an eye width measurement device according to another embodiment of the present invention.

[0017] Figure 8 for Figure 7 Schematic diagram of the eye width measurement device operating in clock scanning mode.

[0018] Figure 9 An exemplary waveform diagram of sampling input data by a sampling clock.

[0019] Figure 10 FIG. 1 is a flow chart of an eye width measurement process according to an embodiment of the present invention.

[0020] The description of the accompanying drawings is as follows:

[0021] 10 High-speed data receiver

[0022] 102, 202 Equalizer

[0023] 104, 204, 35, 75 clock data recovery circuit

[0024] 20 Data Receiver

[0025] 206, 30, 70 eye width measurement device

[0026] 302 Delay Circuit

[0027] 304 Correction Circuit

[0028] M1, M2 multiplexers

[0029] DAT input data

[0030] CLK_CDR Clock data recovery output clock

[0031] CLK_TRN Input training clock

[0032] CLK_OSC oscillation clock

[0033] CLK_REF reference clock

[0034] CTRL control signal

[0035] I1 Inverter

[0036] 310 N to 1 Multiplexer

[0037] 312 Data Latch

[0038] 314 Data Check Circuit

[0039] CKD[1]~CKD[N] sampling clock

[0040] 60mm and 100mm Eye Width Measurement Process

[0041] Steps 600-608, 1000-1008

[0042] 704 Frequency Comparator

[0043] F_REF Reference clock frequency

[0044] F_OSC oscillation clock frequency

[0045] 320 Computing Circuits

[0046] T_CELL Phase Shift

[0047] T_EW Eye Width

[0048] T_UI Unit Interval DETAILED DESCRIPTION

[0049] Please refer to Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a data receiver 20 according to an embodiment of the present invention. Figure 2 As shown, the data receiver 20 includes an equalizer (EQ) 202, a clock and data recovery (CDR) circuit 204, and an eye width measurement device (EWM) 206. The data receiver 20 can be a high-speed receiver capable of receiving high-speed data signals, which can be implemented in an integrated circuit (IC) and included in a chip. The implementation and operation of the equalizer 202 and the clock and data recovery circuit 204 are similar to those of Figure 1 The equalizer 102 and clock-data recovery circuit 104 are shown and will not be described in detail here. To assess the signal quality of the internal data signal between the equalizer 202 and the clock-data recovery circuit 204, an eye-width measurement device 206 may be added and coupled to a node between the equalizer 202 and the clock-data recovery circuit 204 to monitor the data signal. In other words, the eye-width measurement device 206 can detect the eye width of the input data to the clock-data recovery circuit 204.

[0050] As described above, delay circuits offer a simpler approach to eye width measurement, but are susceptible to process, voltage, and temperature (PVT) variations, leading to errors. Embodiments of the present invention offer several solutions that can eliminate or mitigate delay circuit errors, thereby improving the feasibility and reliability of eye width measurement.

[0051] Please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram of an eye width measuring device 30 according to an embodiment of the present invention. Figure 3 As shown, the eye width measurement device 30 includes a delay circuit 302, a correction circuit 304, and multiplexers (MUX) M1 and M2. The eye width measurement device 30 can be implemented in a high-speed data receiver, such as Figure 2 The eye width measurement device 206 is shown. The eye width measurement device 30 is coupled to a clock data recovery circuit 35 and is configured to measure the eye width of input data DAT to the clock data recovery circuit 35. The clock data recovery circuit 35 is configured to receive the input data DAT and output a clock data recovery output clock CLK_CDR derived from the input data DAT. Furthermore, the clock data recovery circuit 35 has a clock training mode, in which the clock data recovery circuit 35 receives an input training clock CLK_TRN instead of the input data DAT.

[0052] Specifically, the delay circuit 302 may include a delay chain consisting of multiple inverters to generate and output multiple sampling clocks with different phases. A calibration circuit 304 is coupled to the delay circuit 302 and can receive an oscillation clock CLK_OSC from the delay circuit 302 and calibrate the oscillation clock CLK_OSC using a reference clock CLK_REF from the multiplexer M2. During the calibration process, the calibration circuit 304 can also be used to control the delay of the delay circuit 302. The multiplexer M1 is coupled to the delay circuit 302. More specifically, the output of the multiplexer M1 is coupled to the input of the delay circuit 302. A first input of the multiplexer M1 is coupled to a clock input of the eye width measurement device 30 for receiving the clock data recovery output clock CLK_CDR from the clock data recovery circuit 35. A second input of the multiplexer M1 is coupled to the output of the delay circuit 302. Multiplexer M1 can receive a control signal CTRL to select whether to transmit a signal through the first input terminal or the second input terminal. Multiplexer M2 is coupled to calibration circuit 304. More specifically, the output terminal of multiplexer M2 is coupled to calibration circuit 304. A first input terminal of multiplexer M2 is coupled to the clock output terminal of clock-data recovery circuit 35 for receiving the clock-data recovery output clock CLK_CDR from clock-data recovery circuit 35. A second input terminal of multiplexer M2 is coupled to the input terminal of clock-data recovery circuit 35 for receiving the input training clock CLK_TRN in clock training mode. In this mode, either the clock-data recovery output clock CLK_CDR or the input training clock CLK_TRN can be transmitted through multiplexer M2 as reference clock CLK_REF for calibration.

[0053] Figure 3 A calibration mode is shown, in which the control signal CTRL controls the multiplexer M1 to selectively couple its second input to its output. In this case, the output of the delay circuit 302 is coupled to its input, causing the delay circuit 302 to function as an oscillator. An inverter I1 can optionally be provided between the second input of the multiplexer M1 and the output of the delay circuit 302 to cause the signal to oscillate.

[0054] In calibration mode, delay circuit 302 oscillates and outputs an oscillation clock CLK_OSC to calibration circuit 304. Calibration circuit 304 then calibrates oscillation clock CLK_OSC based on reference clock CLK_REF. In one embodiment, delay circuit 302 may be implemented as a voltage-controlled delay line or a digitally controlled delay line. Calibration circuit 304 may accordingly output a voltage signal or a digital signal to delay circuit 302 to control the delay time of delay circuit 302.

[0055] In one embodiment, the oscillation clock CLK_OSC can be calibrated to have the same frequency as the reference clock CLK_REF. Calibration of the oscillation clock CLK_OSC can be achieved through delay control of the calibration circuit 304. More specifically, the calibration circuit 304 can control the delay setting of the delay circuit 302 to adjust the frequency of the oscillation clock CLK_OSC. Therefore, after calibration, the frequency of the oscillation clock CLK_OSC is the same as the frequency of the reference clock CLK_REF, which can be the frequency of the clock data recovery output clock CLK_CDR or the frequency of the input training clock CLK_TRN of the clock data recovery circuit 204.

[0056] After the oscillation clock CLK_OSC is calibrated, the delay settings of the delay circuit 302 (e.g., the delay time of each delay unit) can be obtained. Next, the eye width measurement device 30 can switch to a clock scan mode, in which the control signal CTRL controls the multiplexer M1 to couple the first input terminal to its output terminal. In this mode, the delay circuit 302 is connected to the clock input terminal to receive the clock data recovery output clock CLK_CDR from the clock data recovery circuit 35. The delay circuit 302 functions as a delay line in the clock scan mode and as an oscillator in the calibration mode.

[0057] Please refer to Figure 4 , Figure 4 FIG. 3 is a schematic diagram of the eye width measurement device 30 operating in the clock scanning mode. Figure 4 As shown, the eye width measurement device 30 further includes an N-to-1 multiplexer 310, a data latch 312, and a data check circuit 314. The N-to-1 multiplexer 310 can receive sampling clocks CKD[1]-CKD[N] of different phases from the delay circuit 302. Under the delay setting corresponding to the calibrated oscillation clock generated in the calibration mode, the delay time (i.e., phase shift, meaning the delay time of the delay circuit 302 of each delay unit) between each sampling clock CKD[1]-CKD[N] is known. The data latch 312 can receive the input data DAT from the clock data recovery circuit 35 and sequentially receive the sampling clocks CKD[1]-CKD[N] from the N-to-1 multiplexer 310. Therefore, the sampling clocks CKD[1]-CKD[N] can sequentially sample the input data DAT, and the data check circuit 314 can thereby determine whether the sampled value obtained by each sampling clock CKD[1]-CKD[N] is correct.

[0058] Figure 5 : is an exemplary waveform diagram of sampling the input data DAT by the sampling clocks CKD[1] to CKD[N]. Figure 5As shown, the correct sampling value can be obtained from the sampling clocks between CKD[A] and CKD[B]. It should be noted that the delay setting of the delay circuit 302 is determined by the oscillation clock CLK_OSC obtained after calibration based on the reference clock CLK_REF, and the set delay time is used in the clock scan mode to sample the input data DAT. Since the delay time between each sampling clock has been calibrated, the eye width of the input data DAT of the clock data recovery circuit 35 can be accurately obtained based on the sampling results of the sampling clocks CKD[1] to CKD[N].

[0059] In conventional eye width measurement methods using delay circuits, the delay time of the delay circuit cannot be effectively controlled. Specifically, the delay time is susceptible to process, voltage, and temperature variations, resulting in significant offset or error. Consequently, accurate eye width determination is difficult using a sampling clock with an unstable delay time. In contrast, in the eye width measurement device of the present invention, the delay circuit is connected to an oscillator for calibration before sampling the input data using the sampling clock. The oscillator clock is calibrated to have the same frequency as a reference clock. This reference clock can be selected from, for example, the output clock of a clock data recovery circuit or an input training clock. This reference clock is used to determine the delay time of each delay unit in the delay circuit. The delay time is accurate and unaffected by process, voltage, and temperature variations. In other words, the calibrated delay time of the delay circuit can be adjusted to correspond to the average frequency of the input data signal from the clock data recovery circuit. The receiving circuit knows the magnitude of the average frequency and can accurately obtain the calibrated average frequency value.

[0060] The above-mentioned operation of the eye width measurement device 30 can be summarized as an eye width measurement process 60. Figure 6 The eye width measurement process 60 includes the following steps:

[0061] Step 600: Start.

[0062] Step 602 : Connect the delay circuit 302 as an oscillator to calibrate the oscillation clock CLK_OSC of the delay circuit 302 using the reference clock CLK_REF.

[0063] Step 604 : Determine a delay setting of the delay circuit 302 corresponding to the calibrated oscillation clock CLK_OSC.

[0064] Step 606 : Sample the input data DAT of the clock data recovery circuit 35 under the delay setting corresponding to the corrected oscillation clock CLK_OSC to measure the eye width of the input data DAT of the clock data recovery circuit 35 .

[0065] Step 608: End.

[0066] The detailed implementation and operation of the eye width measurement process 60 can be found in the description in the previous paragraphs and will not be repeated here.

[0067] In another embodiment, before the sampling clocks CKD[1]-CKD[N] generated by the delay circuit are used to sample the input data DAT, the frequency relationship between the oscillation clock CLK_OSC and the reference clock CLK_REF can be obtained in advance. Figure 7 , Figure 7 FIG. 7 is a schematic diagram of an eye width measuring device 70 according to another embodiment of the present invention. Figure 7 As shown, the circuit structure of the eye width measurement device 70 is similar to Figure 3 , so signals or components with similar functions are represented by the same symbols. The difference between eye width measurement device 70 and eye width measurement device 30 is that eye width measurement device 70 includes a frequency comparator 704, which replaces the calibration circuit 304 of eye width measurement device 30. Frequency comparator 704 is coupled to delay circuit 302 and receives the oscillation clock CLK_OSC from delay circuit 302 and the reference clock CLK_REF from multiplexer M2. Therefore, frequency comparator 704 compares the oscillation clock CLK_OSC with the reference clock CLK_REF to determine the ratio between the frequency of reference clock CLK_REF and the frequency of oscillation clock CLK_OSC.

[0068] Similarly, the eye width measurement device 70 is coupled to a clock data recovery circuit 75 for measuring the eye width of input data DAT to the clock data recovery circuit 75. The clock data recovery circuit 75 is configured to receive the input data DAT and, in response, output a clock data recovery output clock CLK_CDR derived from the input data DAT. Furthermore, the clock data recovery circuit 75 has a clock training mode, in which the clock data recovery circuit 75 receives an input training clock CLK_TRN instead of the input data DAT. Depending on the operation of the multiplexer M2, either the clock data recovery output clock CLK_CDR or the input training clock CLK_TRN can be selected as the reference clock CLK_REF.

[0069] Figure 7 An evaluation mode is shown, in which the control signal CTRL controls the multiplexer M1 to couple the second input terminal to its output terminal. In this case, the output terminal of the delay circuit 302 is coupled to its input terminal, so that the delay circuit 302 is connected as an oscillator. In the evaluation mode, the delay circuit 302 can oscillate and output the oscillation clock CLK_OSC to the frequency comparator 704, which compares the oscillation clock CLK_OSC with the reference clock CLK_REF.

[0070] Compared to the calibration mode where the delay time of the delay circuit 302 is adjusted by the calibration process, the evaluation mode does not control or adjust the delay time. Instead, the frequency comparator 704 is used to compare and evaluate the frequency ratio between the oscillation clock CLK_OSC and the reference clock CLK_REF.

[0071] In one embodiment, the frequency (F_REF) of the reference clock CLK_REF is M times the frequency (F_OSC) of the oscillation clock CLK_OSC, that is,

[0072] F_REF=M×F_OSC; (1)

[0073] Wherein, M is any positive number, such as an integer or a fraction. The eye width measurement device 70 can record this value for subsequent calculations.

[0074] After obtaining the frequency ratio M, the eye width measurement device 70 can further switch to a clock scan mode, in which the control signal CTRL controls the multiplexer M1 to couple the first input terminal to its output terminal. In this mode, the delay circuit 302 is connected to the clock input terminal to receive the clock data recovery output clock CLK_CDR from the clock data recovery circuit 75. The delay circuit 302 functions as a delay line in the clock scan mode and as an oscillator in the evaluation mode.

[0075] Please refer to Figure 8 , Figure 8 FIG. 7 is a schematic diagram of the eye width measurement device 70 operating in the clock scanning mode. Figure 8 As shown, the circuit structure of the eye width measurement device 70 is similar to Figure 4 The circuit structure of the eye width measurement device 30 in FIG. 1 is similar to that of the eye width measurement device 30 in FIG. Therefore, signals or components with similar functions are represented by the same symbols. The difference between the eye width measurement device 70 and the eye width measurement device 30 is that the eye width measurement device 70 further includes a calculation circuit 320. The calculation circuit 320 is coupled to the data check circuit 314 and is used to calculate the eye width of the input data DAT to the clock data recovery circuit 75.

[0076] Similarly, the N-to-1 multiplexer 310 can receive sampling clocks CKD[1]-CKD[N] of different phases from the delay circuit 302. The data latch 312 can receive the input data DAT from the clock-data recovery circuit 75 and sequentially receive the sampling clocks CKD[1]-CKD[N] from the N-to-1 multiplexer 310. Therefore, the sampling clocks CKD[1]-CKD[N] can sequentially sample the input data DAT. The data check circuit 314 can then determine whether the sampled values obtained by each sampling clock CKD[1]-CKD[N] are correct. The relevant sampling results can be further transmitted to the calculation circuit 320.

[0077] like Figure 8 As shown, the delay chain in the delay circuit 302 is composed of 2×N inverters, and the delay circuit 302 can be used to output N sampling clocks CKD[1] to CKD[N] with different phases (N is an integer greater than 1). Therefore, the phase shift T_CELL between each two consecutive sampling clocks (i.e., the delay time between CKD[i] and CKD[i+1]) is equal to:

[0078]

[0079] Wherein, T_OSC represents the oscillation period length of the oscillation clock CLK_OSC, which is the reciprocal of the frequency F_OSC of the oscillation clock CLK_OSC.

[0080] Figure 9 : is an exemplary waveform diagram of sampling the input data DAT by the sampling clocks CKD[1] to CKD[N]. Figure 9 As shown, the correct sampling value can be obtained by sampling clocks CKD[A] to CKD[B]. Therefore, the data check circuit 314 can obtain a correct clock number, which is equal to the number between sampling clocks CKD[A] to CKD[B].

[0081] In this way, the calculation circuit 320 can calculate the eye width of the input data DAT according to the ratio between the frequency of the reference clock CLK_REF and the frequency of the oscillation clock CLK_OSC and the correct number of clocks. In this example, the eye width T_EW of the input data DAT is equal to:

[0082] T_EW=(BA)×T_CELL. (3)

[0083] Combining equation (3) with equations (1) and (2) yields the eye width T_EW as follows:

[0084]

[0085] Wherein, T_UI is the unit interval of the input data DAT, which is equal to the inverse of the frequency F_REF of the reference clock CLK_REF.

[0086] As can be seen, M is the frequency ratio obtained by frequency comparator 704 in evaluation mode, and (BA) is the number of correct clocks, representing the number of sampling clocks with correct sample values. Furthermore, N is a known value based on the structure of delay circuit 302, and the value of T_UI can be easily obtained by receiving relevant information from the transmitter or detecting it through an external detector. Using this information and calculation, the eye width T_EW of the input data DAT to clock-data recovery circuit 75 can be accurately obtained.

[0087] In this example, the relationship between the oscillation frequency F_OSC of the delay circuit 302 connected as an oscillator and the reference clock frequency F_REF of the clock data recovery circuit can be obtained in evaluation mode. Subsequently, in clock scan mode, the sampling clocks CKD[1]-CKD[N] generated by the delay circuit 302 can sequentially sample the input data DAT to determine the correct number of clocks. The phase shift between each two consecutive sampling clocks is related to the oscillation frequency F_OSC of the delay circuit 302, and therefore to the reference clock frequency F_REF and the unit interval T_UI of the input data DAT. After the calculation is completed, the eye width T_EW corresponding to the unit interval T_UI can be obtained based on this information.

[0088] The above-mentioned operation of the eye width measurement device 70 can be summarized as an eye width measurement process 100. Figure 10 The eye width measurement process 100 includes the following steps:

[0089] Step 1000: Start.

[0090] Step 1002 : Connect the delay circuit 302 as an oscillator to determine the ratio of the frequency of the reference clock CLK_REF to the frequency of the oscillation clock CLK_OSC from the delay circuit 302 .

[0091] Step 1004 : Sample the input data DAT of the clock data recovery circuit 75 using the sampling clocks CKD[ 1 ]-CKD[N] of the delay circuit 302 to obtain a correct clock number.

[0092] Step 1006 : Calculate the eye width of the input data DAT of the clock data recovery circuit 75 according to the ratio and the correct number of clocks.

[0093] Step 1008: End.

[0094] The detailed implementation and operation of the eye width measurement process 100 can be found in the description in the previous paragraphs and will not be elaborated here.

[0095] It is worth noting that the purpose of the embodiment of the present invention is to provide an eye width measurement device that can accurately measure the eye width of an internal signal of an integrated circuit (such as an input data signal of a clock data recovery circuit). Those skilled in the art can make modifications or changes accordingly, but are not limited to this. For example, in the above embodiment, the delay circuit is composed of a delay chain including multiple inverters; but in another embodiment, the delay circuit can also be implemented in other ways, as long as the delay circuit can generate multiple sampling clocks with different phases. In addition, in the above sampling operation, the correct sampling value can also be determined in any way. In one embodiment, each sampling clock CKD[1]~CKD[N] can be used to sample the input data DAT to determine its correctness, and the data check circuit 314 can generate a sampling result based on this. In another embodiment, the sequence of input data DAT can be transmitted to the eye width measurement device for eye width measurement, and each sampling clock CKD[1]~CKD[N] can be used to sample the sequence of input data DAT. In this manner, the bit error rate (BER) of each sampling clock CKD[1]-CKD[N] can be obtained by sampling the input data DAT sequence. The data check circuit 314 then determines whether each sampling clock CKD[1]-CKD[N] generates a correct sample value based on the BER. For example, if the BER is less than a threshold, the sample value is considered correct. Eye width measurement using the input data DAT sequence can achieve high accuracy and reliability.

[0096] In summary, the present invention provides a novel eye width measurement device and method for measuring the eye width of signals within an integrated circuit. In an embodiment of the present invention, a delay circuit comprising a delay chain including multiple inverters can be used to generate multiple sampling clocks. In one embodiment, before the sampling clocks are used to sample input data for eye width measurement, the delay circuit can be connected to an oscillator, and the oscillator's oscillation clock can be calibrated to have the same frequency as a reference clock. This reference clock can be selected from the output clock of a clock data recovery circuit or an input training clock. The eye width measurement device can include a calibration circuit for adjusting the delay time of the delay circuit during the calibration process. This delay time information can be used to generate the sampling clock for sampling the input data. In one embodiment, before the sampling clocks are used to sample input data for eye width measurement, the delay circuit can be connected to an oscillator, and the frequency relationship between the oscillator's oscillation clock and a reference clock can be determined. This reference clock can be selected from the output clock of a clock data recovery circuit or an input training clock. The eye width measurement device can also include a frequency comparator for determining the ratio between the frequency of the reference clock and the frequency of the oscillator clock. Furthermore, the eye width measurement device may further include a calculation circuit for calculating the eye width based on the aforementioned frequency ratio and the correct number of clocks obtained through the sampling operation. In this manner, eye width information can be obtained using the corrected delay time of the delay circuit or based on the frequency relationship between the operating frequency of the clock data recovery and the oscillation clock of the delay circuit. Therefore, the eye width measurement device and eye width measurement method of the present invention can achieve accurate measurement results while being immune to the influence of process, voltage, and temperature variations.

[0097] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. An eye width measurement device for a clock data recovery circuit, the eye width measurement device comprising: a delay circuit comprising an input terminal and an output terminal; a first multiplexer coupled to the delay circuit, the first multiplexer comprising: a first input terminal coupled to a clock input terminal of the eye width measurement device; a second input terminal coupled to the output terminal of the delay circuit; and an output terminal coupled to the input terminal of the delay circuit; and a calibration circuit coupled to the delay circuit and configured to receive an oscillation clock from the delay circuit; and receiving a reference clock to calibrate the oscillation clock using the reference clock; The delay circuit is used to output a plurality of sampling clocks for eye width measurement according to the corrected oscillation clock.

2. The eye width measuring device according to claim 1, wherein: Also includes: A second multiplexer is coupled to the calibration circuit and is used for selecting an output clock of the clock-data recovery circuit or an input training clock of the clock-data recovery circuit as the reference clock.

3. The eye width measuring device according to claim 1, wherein: The correction circuit is used for controlling a delay setting of the delay circuit to correct the oscillation clock.

4. The eye width measuring device according to claim 3, wherein: Under the delay setting corresponding to the corrected oscillation clock, the delay circuit is used to output the plurality of sampling clocks, and the plurality of sampling clocks are used to sample input data of the clock data recovery circuit.

5. The eye width measuring device according to claim 1, wherein: The first multiplexer is configured to select the second input terminal in a first operation mode and to select the first input terminal in a second operation mode subsequent to the first operation mode.

6. The eye width measuring device according to claim 5, wherein: In the first operating mode, the delay circuit is connected as an oscillator.

7. The eye width measuring device according to claim 5, wherein: In the second operation mode, the delay circuit is used to receive an output clock of the clock data recovery circuit.

8. The eye width measuring device according to claim 1, wherein: The correction circuit is used for correcting the frequency of the oscillation clock so as to make it equal to the frequency of the reference clock.

9. A method for measuring eye width, for use in a clock data recovery circuit, the method comprising: Connecting a delay circuit as an oscillator to calibrate an oscillation clock of the delay circuit by a reference clock; determining a delay setting of the delay circuit corresponding to the corrected oscillation clock; as well as Under the delay setting corresponding to the corrected oscillation clock, a plurality of sampling clocks are output to sample input data of the clock data recovery circuit to measure the eye width of the input data of the clock data recovery circuit.

10. The method according to claim 9, wherein The reference clock is selected from an output clock of the clock data recovery circuit and an input training clock of the clock data recovery circuit.

11. The method according to claim 9, wherein The oscillation clock is corrected to have the same frequency as the reference clock.

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