Display device

Abstract

A display device is provided, including a substrate, a plurality of pixels disposed on the substrate, a first initialization voltage line disposed on the substrate in a first direction, and a second initialization voltage line disposed on a layer different from the first initialization voltage line, wherein the second initialization voltage line can include a horizontal portion disposed in the first direction and a vertical portion disposed in a second direction crossing the first direction, and the vertical portion can be disposed between a plurality of pixels adjacent to each other in the first direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0097931, filed with the Korean Intellectual Property Office on August 5, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device that can uniformly transmit a second initialization voltage to each region. Background Technology

[0004] Display devices are devices used to display images, and include liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays. Display devices are used in a wide variety of electronic devices such as mobile phones, navigation devices, digital cameras, e-book readers, portable game consoles, and various other terminals.

[0005] A display device may include multiple pixels arranged in both row and column directions. Various components such as transistors and capacitors, as well as various wirings capable of supplying signals to these components, may be provided in each pixel.

[0006] The display device may include a notch formed primarily at its upper end. The notch is a non-emitting area, and a camera, sensor, etc., may be disposed there. Since no pixels are disposed in the notch, the number of pixels connected to the wiring disposed on each side of the notch is very small compared to the number of pixels in other areas. Therefore, a load difference exists between the wiring disposed on each side of the notch and the wiring disposed in other areas, and thus brightness deviation may occur.

[0007] In addition, the load of the transmitted voltage may vary depending on the area of ​​the display device, which may cause brightness deviations in each area of ​​the display device.

[0008] The information disclosed in this background section is intended only to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art known to a person skilled in the art in this country. Summary of the Invention

[0009] This disclosure provides a display device capable of uniformly transmitting a second initialization voltage.

[0010] Embodiments of this disclosure provide a display device including a substrate, a plurality of pixels disposed on the substrate, a first initialization voltage line disposed on the substrate along a first direction, and a second initialization voltage line disposed on a layer different from the first initialization voltage line. The second initialization voltage line may include a horizontal portion disposed along the first direction and a vertical portion disposed along a second direction intersecting the first direction. The vertical portion may be disposed between a plurality of pixels that are adjacent to each other in the first direction.

[0011] For every four pixels set in the first direction, a vertical portion can be set.

[0012] For every two pixels set in the first direction, a vertical portion can be set.

[0013] For every eight pixels set in the first direction, a vertical portion can be set.

[0014] The display device may further include: a connection electrode disposed on the same layer as the second initialization voltage line; and a driving voltage line disposed along a second direction on the second initialization voltage line and the connection electrode, wherein the connection electrode may include a rod portion parallel to the second direction and an extension portion extending from the rod portion in a first direction.

[0015] The connecting electrodes and the driving voltage lines can be connected to each other in the extension of the connecting electrodes.

[0016] The extension portion of the connecting electrode may not be set in the pixel where the vertical portion of the second initialization voltage line is set.

[0017] In adjacent pixels in the first direction, in pixels where the vertical portion of the second initialization voltage line is not provided, the extension portion of the connecting electrode can be provided on each side of the rod portion of the connecting electrode, and each of the extension portions can be connected to the driving voltage line in two adjacent pixels in the first direction.

[0018] The display device may further include a polycrystalline semiconductor layer disposed between the substrate and the first initialization voltage line.

[0019] A portion of the polycrystalline semiconductor layer may overlap with the connection electrode and the second initialization voltage line in a third direction perpendicular to the surface of the substrate.

[0020] The display device may further include an oxide semiconductor layer disposed between the polycrystalline semiconductor layer and the second initialization voltage line.

[0021] The oxide semiconductor layer can be disposed along the second direction, and the oxide semiconductor layer may not overlap with the polycrystalline semiconductor layer in a third direction perpendicular to the surface of the substrate.

[0022] The oxide semiconductor layer may not overlap with the connection electrode and the second initialization voltage line in a third direction perpendicular to the surface of the substrate.

[0023] Another embodiment of this disclosure provides a display device, including: a substrate; a first semiconductor layer disposed on the substrate; a first initialization voltage line disposed on the first semiconductor layer along a first direction; a second semiconductor layer disposed on the first initialization voltage line and disposed along a second direction intersecting the first direction; a second initialization voltage line and a connection electrode disposed on the second semiconductor layer; and a driving voltage line disposed on the second initialization voltage line and the connection electrode along a second direction, wherein the second initialization voltage line may include a horizontal portion disposed along the first direction and a vertical portion disposed along the second direction.

[0024] The connecting electrode may include a rod portion parallel to the second direction and an extension portion extending from the rod portion in the first direction, and the connecting electrode may be connected to the drive voltage line in the extension portion.

[0025] The rod portion of the connecting electrode can be positioned between the extension portion of the connecting electrode and the vertical portion of the second initialization voltage line.

[0026] The first semiconductor layer can be a polycrystalline semiconductor layer, the second semiconductor layer can be an oxide semiconductor layer, and the first semiconductor layer and the second semiconductor layer can not overlap in a third direction perpendicular to the surface of the substrate.

[0027] The display device may further include a gate electrode, a first scan line, a light emission control line, and a bypass control line disposed on the same layer as the first initialization voltage line along a first direction, wherein a polycrystalline semiconductor layer overlapping the gate electrode in a third direction perpendicular to the surface of the substrate may form a driving transistor.

[0028] A second transistor can be formed in the region of the polycrystalline semiconductor layer that overlaps with the first scan line in a direction perpendicular to the surface of the substrate. A fifth transistor and a sixth transistor can be formed in the region of the polycrystalline semiconductor layer that overlaps with the light-emitting control line in a direction perpendicular to the surface of the substrate. A seventh transistor and an eighth transistor can be formed in the region of the polycrystalline semiconductor layer that overlaps with the bypass control line in a direction perpendicular to the surface of the substrate.

[0029] The display device may further include an initialization control line and a second scan line disposed along a first direction between the oxide semiconductor layer and the second initialization voltage line, wherein a third transistor may be formed in a region of the oxide semiconductor layer that overlaps with the second scan line in a third direction perpendicular to the surface of the substrate, and a fourth transistor may be formed in a region of the oxide semiconductor layer that overlaps with the initialization control line in a third direction perpendicular to the surface of the substrate.

[0030] According to an embodiment, a display device capable of uniformly transmitting a second initialization voltage can be provided. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure, showing only the second initialization voltage line and the pixel electrode.

[0032] Figure 2 A circuit diagram of a pixel of a display device according to an embodiment is shown.

[0033] Figure 3 A top view of a display device according to an embodiment is shown.

[0034] Figure 4 Show along Figure 3 A cross-sectional view taken from line IV-IV'.

[0035] Figure 5 Show along Figure 3 A cross-sectional view taken from line V-V'.

[0036] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 A top view showing the manufacturing sequence of the display device according to an embodiment.

[0037] Figure 13 A top view showing the area where the vertical portion of the second initialization voltage line is not located.

[0038] Figure 14 Show along Figure 13 A cross-sectional view taken from line XIV-XIV'.

[0039] Figure 15 Showing about Figure 13 The area indicated in the text and Figure 11 The layout is the same as the layout.

[0040] Figure 16 Showing with respect to another embodiment Figure 1 The same area as the region.

[0041] Figure 17 Showing with respect to another embodiment Figure 1 The same area as the region. Detailed Implementation

[0042] This disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure.

[0043] Parts irrelevant to the description will be omitted in order to clearly describe this disclosure, and throughout the specification, the same reference numerals refer to the same elements.

[0044] Furthermore, for ease of description, the dimensions and thicknesses of each element are arbitrarily shown in the accompanying drawings, and this disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thicknesses of layers, films, panels, regions, areas, etc., are enlarged for clarity. For ease of description, the thicknesses of some layers and regions are enlarged in the accompanying drawings.

[0045] It will be understood that when an element such as a layer, film, region, area, or substrate is referred to as being "on" another element, it may be directly on the other element, or an intervening element may be present. Conversely, when an element is referred to as being "directly" on another element, no intervening element is present. Furthermore, in the specification, the terms "on" or "above" refer to being positioned on or below the object portion, and do not necessarily mean being positioned on the upper side of the object portion based on the direction of gravity.

[0046] In addition, unless there is an explicit description to the contrary, the words “including” and variations such as “containing” or “comprising” will be understood to mean including the stated elements, but not excluding any other elements.

[0047] Furthermore, throughout the specification, the phrase "in plan view" or "on a plane" refers to a portion of the object viewed from above, and the phrase "in section" or "on a section" refers to a section formed by vertically cutting the portion of the object viewed from the side.

[0048] In the following, a display device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure, showing only the second initialization voltage line 128 and the pixel electrode 191. (See also...) Figure 1 The pixel electrode 191 includes a first pixel electrode 191a, a second pixel electrode 191b, and a third pixel electrode 191c. Red light can be emitted from the first pixel electrode 191a, green light can be emitted from the second pixel electrode 191b, and blue light can be emitted from the third pixel electrode 191c, but this disclosure is not limited thereto.

[0050] exist Figure 1 The image shows pixel PX, and as shown later in... Figure 2As described herein, a pixel PX includes multiple transistors T1, T2, T3, T4, T5, T6, T7, and T8 connected to several signal lines, a storage capacitor Cst, and a light-emitting diode (LED). In the following description, the area corresponding to a pixel PX refers to the area formed by... Figure 2 The area enclosed by the dashed line. (See reference) Figure 1 A pixel electrode 191 can be connected to a pixel PX.

[0051] refer to Figure 1 The second initialization voltage line 128 has a grid structure, which includes a horizontal portion 128a disposed along a first direction DR1 and a vertical portion 128b disposed along a second direction DR2 intersecting the first direction DR1. In this case, the vertical portion 128b can be disposed in the region between each pixel PX. Figure 1 The diagram shows a configuration in which a vertical portion 128b is provided for every four adjacent pixels PX in the first direction DR1. However, this is merely an example, and a vertical portion 128b of the second initialization voltage line 128 may be provided for every two adjacent pixels PX in the first direction DR1, or it may be provided for every eight adjacent pixels PX in the first direction DR1.

[0052] As described above, since the second initialization voltage line 128 is configured with a grid shape including the vertical portion 128b, a pinkish display image caused by load differences between the second initialization voltage lines 128 in each region can be prevented. That is, when the second initialization voltage line 128 only includes the horizontal portion 128a, the load applied to the notch portion or lower region of the display device may vary. However, in the display device according to this embodiment, since the second initialization voltage line 128 is configured with a grid shape including the horizontal portion 128a and the vertical portion 128b, the second initialization voltage VINT2 in each region (see [link to relevant documentation]) can be minimized. Figure 2 The difference between them.

[0053] Figure 1 Region A, which includes the vertical portion 128b of the second initialization voltage line 128, and region B, which does not include the vertical portion 128b of the second initialization voltage line 128, are shown. As described later, region A is as follows: Figure 3 The region shown, and region B is below. Figure 13 The area shown.

[0054] In the following, the specific structure of a display device according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, this is merely an example, and the structure of the present disclosure is not limited thereto.

[0055] Figure 2A circuit diagram of a pixel of a display device according to an embodiment is shown.

[0056] like Figure 2 As shown, a pixel PX of the display device according to this embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, T7 and T8 connected to a plurality of signal lines, a storage capacitor Cst and a light-emitting diode LED.

[0057] Multiple signal lines 127, 128, 151, 152, 153, 154, 155, 156, 171, 172, and 741 are connected to a pixel PX. These signal lines include a first initialization voltage line 127, a second initialization voltage line 128, a first scan line 151, a second scan line 152, an initialization control line 153, a bypass control line 154, an emission control line 155, a reference voltage line 156, a data line 171, a drive voltage line 172, and a common voltage line 741.

[0058] The first scan line 151 is connected to the gate drive section (not shown) to transmit the first scan signal GW to the second transistor T2. The second scan line 152 can be applied with a voltage of opposite polarity to the voltage applied to the first scan line 151, at the same timing as the signal applied to the first scan line 151. For example, when a high voltage is applied to the first scan line 151, a low voltage can be applied to the second scan line 152. The second scan line 152 transmits the second scan signal GC to the third transistor T3.

[0059] Initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4. Bypass control line 154 transmits the bypass signal GB to the seventh transistor T7 and the eighth transistor T8. Bypass control line 154 can be formed by the first scan line 151. Light emission control line 155 transmits the light emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0060] Data line 171 transmits data voltage DATA generated by the data driving section (not shown), and the brightness of the light-emitting diode LED changes according to the data voltage DATA applied to the pixel PX.

[0061] The driving voltage line 172 applies a driving voltage ELVDD, and the reference voltage line 156 applies a reference voltage VEH. The first initialization voltage line 127 transmits a first initialization voltage VINT1, and the second initialization voltage line 128 transmits a second initialization voltage VINT2. The first initialization voltage VINT1 and the second initialization voltage VINT2 can be different from each other. The common voltage line 741 applies a common voltage ELVSS to the cathode electrode of the light-emitting diode (LED). In this embodiment, the voltages applied to the driving voltage line 172, the reference voltage line 156, the first initialization voltage line 127, the second initialization voltage line 128, and the common voltage line 741 can all be constant voltages.

[0062] The structure and interconnections of the multiple transistors will be described in detail below.

[0063] The driving transistor T1 may have the characteristics of a p-type transistor and may comprise a polycrystalline semiconductor. The driving transistor T1 receives a data voltage DATA according to the switching operation of the second transistor T2, thereby supplying a driving current to the anode electrode of the light-emitting diode (LED). Since the brightness of the LED is adjusted according to the amount of driving current output to the anode electrode of the LED, the brightness of the LED can be adjusted according to the data voltage DATA applied to the pixel PX. For this purpose, the first electrode of the driving transistor T1 is configured to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. Additionally, the first electrode of the driving transistor T1 is also connected to the second electrode of the second transistor T2 to receive the data voltage DATA. Simultaneously, the second electrode of the driving transistor T1 is configured to output current to the LED and is connected to the anode electrode of the LED via the sixth transistor T6. Furthermore, the second electrode of the driving transistor T1 transmits the data voltage DATA applied to the first electrode to the third transistor T3. Meanwhile, the gate electrode of the driving transistor T1 is connected to one electrode of the storage capacitor Cst (hereinafter also referred to as the second storage electrode). Therefore, the voltage at the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, thereby changing the drive current output from the driving transistor T1. Additionally, the storage capacitor Cst is also used to maintain a constant voltage at the gate electrode of the driving transistor T1 during a frame.

[0064] The second transistor T2 may have the characteristics of a p-type transistor and may comprise a polycrystalline semiconductor. The second transistor T2 receives the data voltage DATA into pixel PX. The gate electrode of the second transistor T2 is connected to the first scan line 151. The first electrode of the second transistor T2 is connected to the data line 171. The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1. When the second transistor T2 is turned on by a low voltage of the first scan signal GW transmitted through the first scan line 151, the data voltage DATA transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1.

[0065] The third transistor T3 may have the characteristics of an n-type transistor and may include an oxide semiconductor. The third transistor T3 electrically connects the second electrode and the gate electrode of the driving transistor T1. Therefore, the third transistor T3 is a transistor that allows a compensation voltage, altered by the data voltage DATA passing through the driving transistor T1, to be transmitted to the second storage electrode of the storage capacitor Cst. The gate electrode of the third transistor T3 is connected to the second scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1. The second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst and the gate electrode of the driving transistor T1. The third transistor T3 is turned on by a high voltage of the second scan signal GC transmitted through the second scan line 152 to connect the gate electrode and the second electrode of the driving transistor T1, and the third transistor T3 transmits the voltage applied to the gate electrode of the driving transistor T1 to the second storage electrode of the storage capacitor Cst for storage in the storage capacitor Cst.

[0066] The fourth transistor T4 may have the characteristics of an n-type transistor and may include an oxide semiconductor. The fourth transistor T4 initializes the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the initialization control line 153, and the first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127. The second electrode of the fourth transistor T4 is connected to the second storage electrode of the storage capacitor Cst and the gate electrode of the driving transistor T1 via the second electrode of the third transistor T3. The fourth transistor T4 is turned on by a high voltage of the initialization control signal GI transmitted through the initialization control line 153, and simultaneously, the fourth transistor T4 transmits the first initialization voltage VINT1 to the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst. Therefore, the voltage at the gate electrode of the driving transistor T1 and the storage capacitor Cst are initialized.

[0067] The fifth transistor T5 may have the characteristics of a p-type transistor and may include a polycrystalline semiconductor. The fifth transistor T5 transmits the drive voltage ELVDD to the drive transistor T1. The gate electrode of the fifth transistor T5 is connected to the light-emitting control line 155, the first electrode of the fifth transistor T5 is connected to the drive voltage line 172, and the second electrode of the fifth transistor T5 is connected to the first electrode of the drive transistor T1.

[0068] The sixth transistor T6 may have the characteristics of a p-type transistor and may include a polycrystalline semiconductor. The sixth transistor T6 transmits the drive current output from the driving transistor T1 to the light-emitting diode (LED). The gate electrode of the sixth transistor T6 is connected to the light-emitting control line 155, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1, and the second electrode of the sixth transistor T6 is connected to the anode electrode of the LED.

[0069] The seventh transistor T7 may have the characteristics of a p-type transistor and may comprise a polycrystalline semiconductor. The seventh transistor T7 initializes the anode electrode of the light-emitting diode (LED). The gate electrode of the seventh transistor T7 is connected to the bypass control line 154, the first electrode of the seventh transistor T7 is connected to the anode electrode of the LED, and the second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128. When the seventh transistor T7 is turned on by the low voltage of the bypass signal GB, the second initialization voltage VINT2 is applied to the anode electrode of the LED for initialization.

[0070] The eighth transistor T8 may have the characteristics of a p-type transistor and may comprise a polycrystalline semiconductor. The gate electrode of the eighth transistor T8 is connected to the bypass control line 154, the first electrode of the eighth transistor T8 is connected to the reference voltage line 156, and the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T1. When the eighth transistor T8 is turned on by the low voltage of the bypass signal GB, the reference voltage VEH is applied to the first electrode of the driving transistor T1.

[0071] refer to Figure 2 The fourth transistor T4 and the seventh transistor T7 are not connected to the same initialization voltage line, but rather to different initialization voltage lines. That is, the fourth transistor T4 can be connected to the first initialization voltage line 127 to receive the first initialization voltage VINT1, and the seventh transistor T7 can be connected to the second initialization voltage line 128 to receive the second initialization voltage VINT2. When the fourth transistor T4 and the seventh transistor T7 are connected to the same initialization voltage line, the same initialization voltage must be applied to both transistors T4 and T7.

[0072] In some cases, the display device can be driven by changing the frequency. For example, the frequency can be changed from 120Hz to 60Hz, from 120Hz to 30Hz, or from 120Hz to 1Hz, etc. Thus, when the display device is driven by changing the frequency, the characteristics of the variable refresh rate (VRR) may deviate. In particular, a larger deviation occurs in areas displaying low grayscale. However, in this embodiment, different initialization voltages can be applied to the fourth transistor T4 and the seventh transistor T7. Therefore, by allowing the first initialization voltage VINT1 applied to the fourth transistor T4 to differ from the second initialization voltage VINT2 applied to the seventh transistor T7, the deviation of the variable refresh rate characteristics at low grayscale can be reduced.

[0073] Above, a pixel PX has been described as including eight transistors T1, T2, T3, T4, T5, T6, T7 and T8 and a storage capacitor Cst, but this disclosure is not limited thereto, and the number of transistors, the number of capacitors and their connection relationships can be varied.

[0074] In this embodiment, the driving transistor T1 may include a polycrystalline semiconductor. Additionally, the third transistor T3 and the fourth transistor T4 may include oxide semiconductors. The second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may also include polycrystalline semiconductors. However, this disclosure is not limited thereto, and at least one of the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include an oxide semiconductor. In this embodiment, by allowing the third transistor T3 and the fourth transistor T4 to include semiconductor materials different from those of the driving transistor T1, they can be driven more stably, and therefore reliability can be improved.

[0075] In the following text, reference will be made to Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 The planar structure and cross-sectional structure of the display device according to the embodiment are further described.

[0076] Figure 3 A top view of a display device according to an embodiment is shown. Figure 4 Show along Figure 3 A cross-sectional view taken from line IV-IV'. Figure 5 Show along Figure 3 The cross-sectional view taken by line V-V', and Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 A top view showing the manufacturing sequence of the display device according to an embodiment. Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This shows two adjacent pixels, and these two pixels can have symmetrical shapes. The pixel on the left will be described primarily below.

[0077] like Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 As shown, a polycrystalline semiconductor layer ACT1 can be disposed on the substrate 110. The polycrystalline semiconductor layer ACT1 may include a polycrystalline semiconductor material.

[0078] Figure 6 A polycrystalline semiconductor layer ACT1 is shown. The polycrystalline semiconductor layer ACT1 may include a channel, a first electrode, and a second electrode for each of the following transistors: a driving transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 In this configuration, each transistor is indicated, and the channel of each transistor can be set in the central region of the transistor, while the first electrode and the second electrode of each transistor can be set on both sides of the channel.

[0079] The channel of the driving transistor T1 can have a curved shape in a planar view. However, the shape of the channel of the driving transistor T1 is not limited to this and can be changed in various ways. For example, the channel of the driving transistor T1 can be bent into different shapes, or it can be formed into a rod shape.

[0080] refer to Figure 4 and Figure 5A buffer layer 111 may be disposed between the substrate 110 and the polycrystalline semiconductor layer ACT1. The buffer layer 111 may have a single-layer or multi-layer structure. The buffer layer 111 may include an organic insulating material or an inorganic insulating material. The buffer layer 111 may include silicon nitride or silicon oxide. In some embodiments, the buffer layer 111 may be omitted.

[0081] refer to Figure 4 and Figure 5 The first gate insulating film 141 can be disposed on the polycrystalline semiconductor layer ACT1. The first gate insulating film 141 may include silicon nitride or silicon oxide, etc.

[0082] The first gate conductive layer GE1 can be disposed on the first gate insulating film 141. Figure 7 The polycrystalline semiconductor layer ACT1 and the first gate conductive layer GE1 are shown together. The first gate conductive layer GE1 may include the gate electrode 1151 of the driving transistor T1, the first initialization voltage line 127, the first scan line 151, the light emission control line 155, and the bypass control line 154.

[0083] The first initialization voltage line 127, the first scan line 151, the light emission control line 155, and the bypass control line 154 can be set along the first direction DR1.

[0084] A portion of the first scan line 151 may be the gate electrode of the second transistor T2. The gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be a portion of the light emission control line 155. The gate electrodes of the seventh transistor T7 and the eighth transistor T8 may be a portion of the bypass control line 154.

[0085] After forming the first gate conductive layer GE1, which includes the gate electrode 1151 of the driving transistor T1, a doping process can be performed. The polycrystalline semiconductor layer ACT1 covered by the first gate conductive layer GE1 is undoped, and the portions of the polycrystalline semiconductor layer ACT1 not covered by the first gate conductive layer GE1 can be doped to have the same properties as a conductor. In this case, a p-type dopant can be used to perform the doping process, and the driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, which include the polycrystalline semiconductor layer ACT1, can have the characteristics of p-type transistors.

[0086] Also refer to Figure 5 The doped polycrystalline semiconductor layer ACT1, which does not overlap with the gate electrode 1151, can be conductive, and the region on the third direction DR3 perpendicular to the substrate 110 that overlaps with the gate electrode 1151 can be the channel of the driving transistor T1.

[0087] Alternatively, plasma processing can be performed instead of doping. Plasma processing can make the polycrystalline semiconductor layer ACT1 conductive.

[0088] Also refer to Figure 4 , Figure 5 and Figure 7 The second gate insulating film 142 can be disposed on the first gate conductive layer GE1, which includes the gate electrode 1151 and is located on the first gate insulating film 141. The second gate insulating film 142 may include silicon nitride or silicon oxide, etc.

[0089] The second gate conductive layer GE2 can be disposed on the second gate insulating film 142.

[0090] Figure 8 Together, the polycrystalline semiconductor layer ACT1, the first gate conductive layer GE1, and the second gate conductive layer GE2 are shown.

[0091] The second gate conductive layer GE2 may include a first storage electrode 1153, a first overlapping wiring 1154, and a second overlapping wiring 1155 of the storage capacitor Cst.

[0092] The first overlapping wiring 1154 and the second overlapping wiring 1155 can be set along the first direction DR1. (See reference) Figure 3 The first overlapping wiring 1154 overlaps with the second scan line 152 on a third direction DR3 perpendicular to the surface of the substrate 110, and the second overlapping wiring 1155 overlaps with the initialization control line 153 on the third direction DR3 perpendicular to the surface of the substrate 110.

[0093] The first storage electrode 1153 overlaps with the gate electrode 1151 of the driving transistor T1 to form a storage capacitor Cst. An opening 1152 may be formed in the first storage electrode 1153 of the storage capacitor Cst. The opening 1152 of the first storage electrode 1153 of the storage capacitor Cst may overlap with the gate electrode 1151 of the driving transistor T1. The first storage electrodes 1153 may be connected to each other along a first direction DR1.

[0094] Also refer to Figure 4 , Figure 5 and Figure 8 The first interlayer insulating film 161 can be disposed on the second gate conductive layer GE2, which includes the first storage electrode 1153. The first interlayer insulating film 161 may include silicon nitride or silicon oxide, etc.

[0095] The oxide semiconductor layer ACT2 can be disposed on the first interlayer insulating film 161. The oxide semiconductor layer ACT2 may include monometallic oxides such as indium (In) oxide, tin (Sn) oxide, or zinc (Zn) oxide; binary metal oxides such as In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, or In-Ga oxides; and oxides such as In-Ga-Zn oxides, In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, and In-Pr-Zn oxides. Ternary metal oxides such as In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, or In-Lu-Zn ​​oxides, and quaternary metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, or In-Hf-Al-Zn oxides. For example, the oxide semiconductor layer ACT2 may include indium gallium zinc oxide (IGZO) among In-Ga-Zn oxides.

[0096] Figure 9 Together, the polycrystalline semiconductor layer ACT1, the first gate conductive layer GE1, the second gate conductive layer GE2, and the oxide semiconductor layer ACT2 are shown.

[0097] The oxide semiconductor layer ACT2 may include the channel, first electrode, and second electrode of the third transistor T3, and the channel, first electrode, and second electrode of the fourth transistor T4. The oxide semiconductor layer ACT2 may not overlap with the polycrystalline semiconductor layer ACT1 on a third direction DR3 perpendicular to the surface of the substrate 110.

[0098] refer to Figure 4 and Figure 5 The third gate insulating film 143 can be disposed on the oxide semiconductor layer ACT2. The third gate insulating film 143 may include silicon nitride or silicon oxide, etc.

[0099] The third gate conductive layer GE3 can be disposed on the third gate insulating film 143.

[0100] Figure 10 Together, the polycrystalline semiconductor layer ACT1, the first gate conductive layer GE1, the second gate conductive layer GE2, the oxide semiconductor layer ACT2, and the third gate conductive layer GE3 are shown.

[0101] The third gate conductive layer GE3 may include an initialization control line 153, a second scan line 152, and a reference voltage line 156. The initialization control line 153, the second scan line 152, and the reference voltage line 156 may be arranged along a first direction DR1. Simultaneously, a reference... Figure 5 A portion of the initialization control line 153 can be the gate electrode of the fourth transistor T4. A portion of the second scan line 152 can be the gate electrode of the third transistor T3. The reference voltage line 156 can be connected to the first electrode of the eighth transistor T8.

[0102] After forming the third gate conductive layer GE3, a doping process can be performed. The portion of the oxide semiconductor layer ACT2 covered by the third gate conductive layer GE3 may be left undoped, while the portion of the oxide semiconductor layer ACT2 not covered by the third gate conductive layer GE3 may be doped to possess properties similar to those of a conductor. (See also...) Figure 5 The channel of the third transistor T3 can be disposed below its gate electrode to overlap with the second scan line 152, which serves as the gate electrode, on a third direction DR3 perpendicular to the substrate 110, and the first and second electrodes of the third transistor T3 may not overlap with its gate electrode.

[0103] Also refer to Figure 5 The channel of the fourth transistor T4 can be disposed below its gate electrode to overlap with the initialization control line 153, which serves as the gate electrode, on a third direction DR3 perpendicular to the substrate 110. The first and second electrodes of the fourth transistor T4 may not overlap with its gate electrode. The doping process of the oxide semiconductor layer ACT2 can be performed using an n-type dopant, and the third transistor T3 and the fourth transistor T4, which include the oxide semiconductor layer ACT2, can have the characteristics of n-type transistors.

[0104] Also refer to Figure 4 , Figure 5 and Figure 10 The second interlayer insulating film 162 can be disposed on the third gate conductive layer GE3.

[0105] The first data conductive layer DE1 can be disposed on the second interlayer insulating film 162. Figure 11 Together, the polycrystalline semiconductor layer ACT1, the first gate conductive layer GE1, the second gate conductive layer GE2, the oxide semiconductor layer ACT2, the third gate conductive layer GE3, and the first data conductive layer DE1 are shown.

[0106] The first data conductive layer DE1 may include a second initialization voltage line 128, a first connecting electrode CE1, a second connecting electrode CE2, a third connecting electrode CE3, a fourth connecting electrode CE4, a fifth connecting electrode CE5, a sixth connecting electrode CE6, a seventh connecting electrode CE7, and an eighth connecting electrode CE8.

[0107] The second initialization voltage line 128 includes a horizontal portion 128a disposed along the first direction DR1 and a vertical portion 128b disposed along the second direction DR2.

[0108] The second initialization voltage line 128 can be connected to the polycrystalline semiconductor layer ACT1 through the initialization voltage opening OP_128. The initialization voltage is transmitted to the polycrystalline semiconductor layer ACT1 through this opening.

[0109] The horizontal portion 128a of the second initialization voltage line 128 may alternately overlap with the reference voltage line 156 and the first initialization voltage line 127 on a third direction DR3 perpendicular to the substrate 110. The vertical portion 128b of the second initialization voltage line 128 will be described later, but it may be disposed along the second direction DR2 in a region where the eighth connection electrode CE8 is not disposed. The oxide semiconductor layer ACT2 may not overlap with the eighth connection electrode CE8 and the second initialization voltage line 128 on a third direction DR3 perpendicular to the surface of the substrate 110.

[0110] Also refer to Figure 5 The first connection electrode CE1 can be connected to the gate electrode 1151 of the driving transistor T1 through the first-1 opening OP1_1, and can be connected to the oxide semiconductor layer ACT2 through the first-2 opening OP1_2.

[0111] The second connecting electrode CE2 can be connected to the polycrystalline semiconductor layer ACT1 through the second-first opening OP2_1.

[0112] Still refer to Figure 5 The third connecting electrode CE3 can be connected to the polycrystalline semiconductor layer ACT1 through the 3-1 opening OP3_1, and can be connected to the oxide semiconductor layer ACT2 through the 3-2 opening OP3_2.

[0113] Still refer to Figure 5 The fourth connection electrode CE4 can be connected to the first initialization voltage line 127 through the 4-1 opening OP4_1, and the fourth connection electrode CE4 can be connected to the oxide semiconductor layer ACT2 through the 4-2 opening OP4_2.

[0114] The fifth connecting electrode CE5 is connected to the polycrystalline semiconductor layer ACT1 through the 5-1 opening OP5_1 and the 5-2 opening OP5_2.

[0115] The sixth connecting electrode CE6 can be connected to the polycrystalline semiconductor layer ACT1 through the opening OP6_1 of the sixth-first stage.

[0116] The seventh connection electrode CE7 can be connected to the polycrystalline semiconductor layer ACT1 through the 7-1 opening OP7_1, and can be connected to the reference voltage line 156 through the 7-2 opening OP7_2.

[0117] The eighth connection electrode CE8 can be connected to the polycrystalline semiconductor layer ACT1 through the opening OP8_1 (8-1). Additionally, the eighth connection electrode CE8 can be connected to the first storage electrode 1153 through the opening OP8_2 (8-2). Although described later, please refer to the following... Figure 3 and Figure 4 The eighth connecting electrode CE8 can receive the ELVDD voltage from the driving voltage line 172 through the driving opening OP_172. The eighth connecting electrode CE8 can transmit the ELVDD voltage transmitted in the second direction DR2 to the first direction DR1. (Reference) Figure 3 The eighth connecting electrode CE8 can be connected to the driving voltage line 172 in only one of the two adjacent pixels, and can be left unconnected to the driving voltage line 172 in the other pixel. That is, as Figure 3 and Figure 10 As shown, the eighth connection electrode CE8 can be connected only to the drive voltage line 172 on one side based on the center of the eighth connection electrode CE8.

[0118] In this case, in pixels where the driving voltage line 172 and the eighth connecting electrode CE8 are not connected, the vertical portion 128b of the second initialization voltage line 128 can be set on the second direction DR2.

[0119] refer to Figure 11 The eighth connection electrode CE8 includes a rod portion CE8_L disposed along the second direction DR2 and an extension portion CE8_W extending from the rod portion CE8_L in the first direction DR1. In the rod portion CE8_L, the eighth connection electrode CE8 can be connected to the polycrystalline semiconductor layer ACT1 through the 8-1 opening OP8_1, and can be connected to the first storage electrode 1153 through the 8-2 opening OP8_2.

[0120] Although later Figure 12 The lieutenant general described that, however, the extension portion CE8_W of the eighth connecting electrode CE8 can be connected to the driving voltage line 172 through the driving opening OP_172 to receive the ELVDD voltage.

[0121] refer to Figure 11The extension portion CE8_W of the eighth connecting electrode CE8 is only provided on one side of the rod-based portion CE8_L. The vertical portion 128b of the second initialization voltage line 128 can be provided in the area where the extension portion CE8_W of the eighth connecting electrode CE8 is not provided.

[0122] Now, at the same time, refer to Figure 4 , Figure 5 and Figure 11 The third interlayer insulating film 180 can be disposed on the first data conductive layer DE1.

[0123] The second data conductive layer DE2 can be disposed on the third interlayer insulating film 180. Figure 12 Together, we show a polycrystalline semiconductor layer ACT1, a first gate conductive layer GE1, a second gate conductive layer GE2, an oxide semiconductor layer ACT2, a third gate conductive layer GE3, a first data conductive layer DE1, and a second data conductive layer DE2.

[0124] The second data conductive layer DE2 may include data lines 171, driving voltage lines 172, and connection patterns 177. The data lines 171 and driving voltage lines 172 may be arranged along the second direction DR2.

[0125] Data line 171 can be connected to the second connection electrode CE2 through data opening OP_171. Since the second connection electrode CE2 is connected to the polycrystalline semiconductor layer ACT1 through the second-first opening OP2_1, the data voltage of data line 171 is transmitted to the polycrystalline semiconductor layer ACT1. Specifically, data line 171 can be connected to the first electrode of the second transistor T2.

[0126] The driving voltage line 172 can be arranged along the second direction DR2 and can be connected to the eighth connecting electrode CE8 in the driving opening OP_172. Specifically, the driving voltage line 172 can be connected to the extension CE8_W of the eighth connecting electrode CE8.

[0127] Also refer to Figure 4 , Figure 5 and Figure 12 Since the driving voltage line 172 is connected to the eighth connection electrode CE8 in the driving opening OP_172 and the eighth connection electrode CE8 is connected to the first storage electrode 1153 through the 8-2 opening OP8_2, the driving voltage line 172 is connected to the first storage electrode 1153.

[0128] The connection pattern 177 can be connected to the sixth connection electrode CE6 through the first connection opening OP_177_1, and can be connected to the anode electrode (not shown) through the second connection opening OP_177_2.

[0129] Although not shown, a passivation film can be disposed on a second data conductive layer DE2, including data line 171 and drive voltage line 172, and an anode electrode can be disposed on the passivation film. The anode electrode can be connected to a sixth transistor T6 and can receive the output current of drive transistor T1. A partition wall can be disposed on the anode electrode. An opening is formed in the partition wall, and the opening in the partition wall can overlap with the anode electrode. A light-emitting element layer can be disposed in the opening of the partition wall. A cathode electrode can be disposed on the light-emitting element layer and the partition wall. The anode electrode, the light-emitting element layer, and the cathode electrode can form a light-emitting diode (LED).

[0130] As described above, in the display device according to this embodiment, since the second initialization voltage line 128 is configured with a grid shape including a horizontal portion 128a and a vertical portion 128b, the problem that the load of the second initialization voltage VINT2 varies for each region can be solved.

[0131] refer to Figure 1 The vertical portion 128b of the second initialization voltage line 128 is only set in some pixels among several neighboring pixels. Figure 1 The configuration of a vertical portion 128b of a second initialization voltage line 128 is shown, wherein every four pixels PX are configured with a second initialization voltage line 128.

[0132] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This diagram shows the layout of the area in which the vertical portion 128b of the second initialization voltage line 128 is disposed. That is, Figure 3 Shown by Figure 1 The area indicated by "A" in the diagram. Figure 13 The area shown is where the vertical portion 128b of the second initialization voltage line 128 is not located, that is, Figure 13 Shown by Figure 1 The area indicated by "B" in the diagram. Figure 14 Show along Figure 13 A cross-sectional view taken from line XIV-XIV'.

[0133] Compare Figure 3 and Figure 13 ,exist Figure 13In the case of the region shown, the eighth connecting electrode CE8 includes a rod portion CE8_L and an extension portion CE8_W on each side of the rod portion CE8_L, and the eighth connecting electrode CE8 is connected to the driving voltage line 172 through the extension portion CE8_W and through two driving openings OP_172 provided on each side. Additionally, except that the vertical portion 128b of the second initialization voltage line 128 is not provided, Figure 13 and Figure 3 The same as in the above. Detailed descriptions of the same constituent elements will be omitted.

[0134] Figure 3 The eighth connection electrode CE8 includes an extension CE8_W on only one side based on the rod portion CE8_L, and is connected only to the drive voltage line 172 in one of two adjacent pixels, while... Figure 13 In this case, the eighth connecting electrode CE8 includes an extension portion CE8_W on each side of the rod portion CE8_L, and is connected to the driving voltage line 172 in both of the two adjacent pixels.

[0135] Figure 15 Showing about Figure 13 The area indicated in the text and Figure 11 The layout is the same as the previous one. Compare. Figure 11 and Figure 15 ,exist Figure 15 In the middle, the eighth connecting electrode CE8 includes a rod portion CE8_L disposed along the second direction DR2 and an extension portion CE8_W extending from each side of the rod portion CE8_L along the first direction DR1.

[0136] In other words, Figure 11 In the eighth connecting electrode CE8, the extension portion CE8_W is only provided on one side of the rod portion CE8_L, and the vertical portion 128b of the second initialization voltage line 128 is provided on the side where the extension portion CE8_W is not provided. However, in Figure 15 In this case, the extension portion CE8_W is provided on each side of the rod portion CE8_L of the eighth connecting electrode CE8. One extension portion CE8_W can be connected to the drive voltage line 172, and another extension portion CE8_W can be connected to another drive voltage line 172.

[0137] Figure 16 Showing with respect to another embodiment Figure 1 The same area as the previous area. (Reference) Figure 16 In addition to setting a vertical portion 128b of the second initialization voltage line 128 every eight neighboring pixels PX in the first direction DR1, according to Figure 16 The display device of the embodiment and Figure 1The display device is the same as that in the embodiment. Detailed descriptions of the same constituent elements will be omitted.

[0138] like Figure 16 As shown, even if a vertical portion 128b of the second initialization voltage line 128 is set for every eight adjacent pixels, it is possible to obtain the same result as... Figure 1 The same effect.

[0139] Figure 17 Showing with respect to another embodiment Figure 1 The same area as the previous area. (Reference) Figure 17 In addition to setting a vertical portion 128b of the second initialization voltage line 128 for every two adjacent pixels PX in the first direction DR1, according to Figure 17 The display device of the embodiment and Figure 1 The display device is the same as that in the embodiment. Detailed descriptions of the same constituent elements will be omitted.

[0140] like Figure 17 As shown, even if there is a vertical portion 128b of the second initialization voltage line 128 between every two adjacent pixels, it is possible to obtain the same as Figure 1 The same effect.

[0141] Figure 1 The diagram shows a configuration in which a vertical portion 128b of a second initialization voltage line 128 is set for every four adjacent pixels. Figure 16 The diagram shows a configuration in which a vertical portion 128b of a second initialization voltage line 128 is set for every eight adjacent pixels, and... Figure 17 The illustration shows a configuration in which a vertical portion 128b of a second initialization voltage line 128 is set for every two adjacent pixels, but this disclosure is not limited thereto.

[0142] In other words, in this embodiment, a vertical portion 128b of the second initialization voltage line 128 can be set every n neighboring pixels. In this case, n can be 1 to 50.

[0143] As described above, in some pixels of the display device according to the embodiment, the area of ​​the eighth connection electrode CE8 for transmitting the driving voltage ELVDD on the first direction DR1 is reduced, and the vertical portion 128b of the second initialization voltage line 128 is disposed on the second direction DR2 in the corresponding area, thus the second initialization voltage line 128 is formed in a grid shape. Therefore, for each area of ​​the display device, the same second initialization voltage VINT2 is transmitted uniformly, thereby preventing a pinkish display image due to the load difference between the second initialization voltage VINT2 of each area.

[0144] Although this disclosure has been described in conjunction with embodiments currently considered to be practical, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising: substrate; Multiple pixels are disposed on the substrate; A first initialization voltage line is disposed on the substrate along a first direction; The second initialization voltage line is set on a different layer than the first initialization voltage line; The connecting electrode is positioned on the same layer as the second initialization voltage line; as well as A driving voltage line is disposed along the second direction on the second initialization voltage line and the connecting electrode. The second initialization voltage line includes a horizontal portion arranged along the first direction and a vertical portion arranged along a second direction intersecting the first direction. The vertical portion of the second initialization voltage line is positioned between pixels adjacent to each other in the first direction, and The connecting electrode includes a rod portion parallel to the second direction and an extension portion extending from the rod portion in the first direction.

2. The display device according to claim 1, wherein For every four pixels set in the first direction, one vertical portion is set.

3. The display device according to claim 1, wherein... For every two pixels set in the first direction, one vertical portion is set.

4. The display device according to claim 1, wherein For every eight pixels set in the first direction, one vertical portion is set.

5. The display device according to claim 4, wherein... The connecting electrode is connected to the driving voltage line in the extension portion of the connecting electrode.

6. The display device according to claim 4, wherein The extension portion of the connecting electrode is not located in the pixel of the vertical portion of the second initialization voltage line.

7. The display device according to claim 4, wherein Among the pixels arranged adjacent to each other in the first direction, in the pixels where the vertical portion of the second initialization voltage line is not located, The extension portion of the connecting electrode is disposed on each side of the rod portion of the connecting electrode, and Each of the extension portions is connected to the driving voltage line in two pixels that are adjacent to each other in the first direction.

8. The display device according to claim 4, further comprising: A polycrystalline semiconductor layer disposed between the substrate and the first initialization voltage line.

9. The display device according to claim 8, wherein A portion of the polycrystalline semiconductor layer overlaps with the connection electrode and the second initialization voltage line in a third direction perpendicular to the surface of the substrate.

10. The display device according to claim 8, further comprising: An oxide semiconductor layer is disposed between the polycrystalline semiconductor layer and the second initialization voltage line.

11. The display device according to claim 10, wherein The oxide semiconductor layer is disposed along the second direction, and The oxide semiconductor layer does not overlap with the polycrystalline semiconductor layer in a third direction perpendicular to the surface of the substrate.

12. The display device according to claim 10, wherein The oxide semiconductor layer does not overlap with the connection electrode and the second initialization voltage line in a third direction perpendicular to the surface of the substrate.

13. A display device, comprising: substrate; A first semiconductor layer is disposed on the substrate; A first initialization voltage line is disposed on the first semiconductor layer along a first direction; A second semiconductor layer is disposed on the first initialization voltage line and disposed along a second direction that intersects the first direction; The second initialization voltage line and the connection electrode are disposed on the second semiconductor layer; as well as A driving voltage line is disposed along the second direction on the second initialization voltage line and the connecting electrode. The second initialization voltage line includes a horizontal portion arranged along the first direction and a vertical portion arranged along the second direction, and The connecting electrode includes a rod portion parallel to the second direction and an extension portion extending from the rod portion in the first direction.

14. The display device according to claim 13, wherein The connecting electrode is connected to the driving voltage line in the extension portion.

15. The display device according to claim 14, wherein The rod portion of the connecting electrode is disposed between the extension portion of the connecting electrode and the vertical portion of the second initialization voltage line.

16. The display device according to any one of claims 13 to 15, wherein The first semiconductor layer is a polycrystalline semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer. The first semiconductor layer and the second semiconductor layer do not overlap each other in a third direction perpendicular to the surface of the substrate.

17. The display device according to claim 16, further comprising: The gate electrode, first scan line, light emission control line, and bypass control line are disposed on the same layer as the first initialization voltage line along the first direction. A driving transistor is formed in the polycrystalline semiconductor layer that overlaps with the gate electrode on a third direction perpendicular to the surface of the substrate.

18. The display device according to claim 17, wherein The polycrystalline semiconductor layer forms a second transistor in a region that overlaps with the first scan line on a third upward direction perpendicular to the surface of the substrate. The fifth and sixth transistors are formed in the region of the polycrystalline semiconductor layer that overlaps with the light-emitting control line in a third direction perpendicular to the surface of the substrate, and The seventh and eighth transistors are formed in the region of the polycrystalline semiconductor layer that overlaps with the bypass control line in a third direction perpendicular to the surface of the substrate.

19. The display device according to claim 16, further comprising: An initialization control line and a second scan line are disposed along the first direction between the oxide semiconductor layer and the second initialization voltage line. The oxide semiconductor layer forms a third transistor in a region that overlaps with the second scan line on a third upward direction perpendicular to the surface of the substrate, and The oxide semiconductor layer forms a fourth transistor in a region that overlaps with the initialization control line in a third direction perpendicular to the surface of the substrate.

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