Display device

Abstract

A display device includes a first initialization voltage line extending in a first direction, a second initialization voltage line extending in the first direction, a first initialization connection line extending in a second direction intersecting the first direction and electrically connecting the first initialization voltage lines to each other, a second initialization connection line extending in the second direction and electrically connecting the second initialization voltage lines to each other, and a pixel connected to the first initialization voltage line, the second initialization voltage line, the first initialization connection line, and the second initialization connection line.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0106356, filed on August 24, 2020, and all the benefits accruing therefrom, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0003] One or more embodiments relate to a display apparatus, and more particularly, to a display apparatus capable of displaying high-quality images. BACKGROUND

[0004] Generally, a display apparatus includes a plurality of pixels, and each of the plurality of pixels includes a display device and a pixel circuit for controlling the display device. The pixel circuit generally includes a thin film transistor ("TFT"), a storage capacitor, and a wiring.

[0005] Recently, the number of TFTs used in a display apparatus has increased to precisely control the timing and degree of light emission. In addition, the number of pixels has also increased to display images having high resolution. SUMMARY

[0006] However, the display apparatus in the related art has a problem that it is not easy to display high-quality images.

[0007] Embodiments relate to a display apparatus capable of displaying high-quality images. According to an embodiment, a display apparatus includes a first initialization voltage line extending in a first direction, a second initialization voltage line extending in the first direction, a first initialization connection line extending in a second direction intersecting the first direction, wherein the first initialization connection line electrically connects the first initialization voltage lines to each other, a second initialization connection line extending in the second direction, wherein the second initialization connection line electrically connects the second initialization voltage lines to each other, and a pixel connected to the first initialization voltage line and the second initialization voltage line.

[0008] In an embodiment, each of the pixels can include an organic light emitting diode; a first transistor that controls an amount of current flowing from a second node electrically connected to a power voltage line to the organic light emitting diode in response to a voltage applied to a first node; a fourth transistor connected between the first node and the first initialization voltage line, wherein the fourth transistor can initialize a voltage of a first gate electrode of the first transistor in response to a voltage applied to a fourth gate electrode; and a seventh transistor connected between the second initialization voltage line and a third node located between the first transistor and the organic light emitting diode, wherein the seventh transistor can initialize a voltage of a pixel electrode of the organic light emitting diode in response to a voltage applied to a seventh gate electrode.

[0009] In an embodiment, the first initialization connection line and the second initialization voltage line can pass through each of the pixels.

[0010] In an embodiment, the first initialization connection line can be disposed in one of even columns and odd columns of the pixels, and the second initialization connection line can be disposed in the other of the even columns and the odd columns of the pixels.

[0011] In an embodiment, the first initialization connection line can be disposed in every m columns of the pixels, wherein m is a natural number greater than 1.

[0012] In an embodiment, the second initialization connection line can be disposed between the first initialization connection lines.

[0013] In an embodiment, the first initialization connection line and the second initialization connection line can be alternately disposed with each other in the first direction.

[0014] In an embodiment, a first group of the pixels through which the first initialization connection line passes can be electrically connected to the first initialization voltage line through the first initialization connection line, wherein the display apparatus further includes a first auxiliary initialization connection line positioned in a second group of the pixels through which the first initialization connection line does not pass, wherein the first auxiliary initialization connection line can be electrically connected to the first initialization voltage line.

[0015] In an embodiment, a third group of the pixels through which the second initialization connection line passes can be electrically connected to the second initialization voltage line through the second initialization connection line, wherein the display apparatus further includes a second auxiliary initialization connection line positioned in a fourth group of the pixels through which the second initialization connection line does not pass, wherein the second auxiliary initialization connection line can be electrically connected to the second initialization voltage line.

[0016] In an embodiment, the display device can further include a data line extending in the first direction, wherein the first and second initialization connection lines can be disposed in the same layer as the data line.

[0017] In an embodiment, the first and second initialization connection lines can include the same material as a material included in the data line.

[0018] In an embodiment, the first and second initialization voltage lines can be disposed under the first initialization connection line.

[0019] In an embodiment, the display device can further include a power voltage line extending in the first direction, wherein the first and second initialization connection lines are disposed in the same layer as the power voltage line.

[0020] In an embodiment, the first and second initialization connection lines can include the same material as a material included in the power voltage line.

[0021] In an embodiment, the first and second initialization voltage lines can be disposed under the first initialization connection line.

[0022] In an embodiment, the display device can further include a substrate, wherein a through-hole can be defined through a top surface and a bottom surface of the substrate, wherein the pixels can be positioned outside the through-hole of the substrate.

[0023] According to an embodiment, a display device includes a substrate, first and second initialization voltage lines disposed on the substrate and extending in a first direction, a first initialization connection line disposed on an interlayer insulation layer covering the first and second initialization voltage lines, wherein the first initialization connection line extends in a second direction intersecting the first direction and electrically connects the first initialization voltage lines to each other through contact holes defined in the interlayer insulation layer, a second initialization connection line disposed on the interlayer insulation layer, wherein the second initialization connection line extends in the second direction and electrically connects the second initialization voltage lines to each other through contact holes defined in the interlayer insulation layer, and organic light emitting diodes disposed on a planarization layer covering the first and second initialization connection lines.

[0024] In an embodiment, the first and second initialization connection lines can pass through each of the organic light emitting diodes.

[0025] In an embodiment, the first initialization connection line can be disposed in one of even-numbered columns and odd-numbered columns of the organic light emitting diodes, and the second initialization connection line can be disposed in the other of the even-numbered columns and the odd-numbered columns of the organic light emitting diodes.

[0026] In an embodiment, the first initialization connection line can be disposed in every m columns of the organic light emitting diodes, where m is a natural number greater than 1.

[0027] In an embodiment, the second initialization connection line can be disposed between the first initialization connection lines.

[0028] In an embodiment, the first initialization connection line and the second initialization connection line can be alternately disposed with each other in the first direction.

[0029] In an embodiment, a first group of the organic light emitting diodes through which the first initialization connection line passes can be electrically connected to the first initialization voltage line through the first initialization connection line, wherein the display device further includes a first auxiliary initialization connection line positioned in a second group of the organic light emitting diodes through which the first initialization connection line does not pass, wherein the first auxiliary initialization connection line can be electrically connected to the first initialization voltage line.

[0030] In an embodiment, a third group of the organic light emitting diodes through which the second initialization connection line passes can be electrically connected to the second initialization voltage line through the second initialization connection line, wherein the display device further includes a second auxiliary initialization connection line positioned in a fourth group of the organic light emitting diodes through which the second initialization connection line does not pass, wherein the second auxiliary initialization connection line can be electrically connected to the second initialization voltage line.

[0031] In an embodiment, the display device can further include a data line disposed on the interlayer insulating layer and extending in the first direction.

[0032] In an embodiment, the first initialization connection line and the second initialization connection line can include the same material as a material included in the data line.

[0033] In an embodiment, the display device can further include a power voltage line disposed on the interlayer insulating layer and extending in the first direction.

[0034] In an embodiment, the first initialization connection line and the second initialization connection line can include the same material as a material included in the power voltage line.

[0035] In an embodiment, the through hole can be defined through the top surface and the bottom surface of the substrate, and the organic light emitting diode can be positioned outside of the through hole of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0036] The above and other features of specific embodiments will be more apparent from the following description taken in conjunction with the accompanying drawings, by which:

[0037] Figure 1 is a conceptual view of a display apparatus according to an embodiment;

[0038] Figure 2 is an equivalent circuit diagram of one (sub) pixel positioned in a display area in the display apparatus of Figure 1 ;

[0039] Figure 3 is a view showing positions of a plurality of thin film transistors and a storage capacitor in the (sub) pixel of Figure 2 ;

[0040] Figure 4 is a view showing an arrangement of a semiconductor layer which is a part of the (sub) pixel of Figure 3 ;

[0041] Figure 5 is a view showing an arrangement of a first initialization connection line and a second initialization connection line of Figure 3 ;

[0042] Figure 6 is a view showing an arrangement of a first initialization voltage line, a second initialization voltage line, a first initialization connection line, and a second initialization connection line of Figure 3 ;

[0043] Figure 7 is a cross-sectional view taken along lines A-A' and B-B' of Figure 3 ;

[0044] Figure 8 is a view showing an arrangement of a first initialization voltage line, a second initialization voltage line, a first initialization connection line, and a second initialization connection line in a plurality of pixels of a display apparatus according to an embodiment;

[0045] Figure 9 is a view showing an arrangement of a first initialization voltage line, a second initialization voltage line, a first initialization connection line, a first auxiliary initialization connection line, a second initialization connection line, and a second auxiliary initialization connection line in a plurality of pixels of a display apparatus according to an alternative embodiment; and

[0046] Figure 10is a view showing an arrangement of a first initialization voltage line, a second initialization voltage line, a first initialization connection line, a first auxiliary initialization connection line, a second initialization connection line, and a second auxiliary initialization connection line in a plurality of pixels of a display device according to another alternative embodiment. DETAILED DESCRIPTION

[0047] The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0048] Since the present disclosure allows various changes and numerous embodiments, specific embodiments will be shown in the drawings and described in detail in the detailed description. The effects and features of the present disclosure will be clarified by referring to the embodiments described in detail below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various forms.

[0049] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, in which like elements are denoted by like reference numerals and repetitive description thereof is omitted.

[0050] It will be understood that when an element such as a layer, film, region, or plate is referred to as being "on" another element, it can be directly on the other element or intervening elements can be present therebetween. Also, for the purpose of convenience, the size of the elements in the drawings can be exaggerated or reduced. For example, the size and thickness of the elements in the drawings can be arbitrarily shown for the purpose of convenience, and the present disclosure is not limited thereto.

[0051] It will be understood that, although the terms "first", "second", "third", and the like can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element", "a first component", "a first region", "a first layer", or "a first portion" discussed below can be termed a second element, a second component, a second region, a second layer, or a second portion without departing from the teachings herein.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, "one," "a," or "the" are open-ended and not meant to be limiting unless otherwise indicated. For example, "an element" has the same meaning as "at least one element." "At least one" is not to be construed as limiting "one" or "a." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising," or "includes" and / or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0053] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The term "lower" can then encompass both an orientation of "lower" and "upper," according to the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The terms "below" or "beneath" can then encompass both an orientation of "below" and "above," according to the particular orientation of the figure.

[0054] In the following embodiments, the x-axis, the y-axis, and the z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments, which are idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, a region illustrated or described as flat can often have rough and / or nonlinear features. Moreover, illustrated corners can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

[0057] Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0058] Figure 1 is a conceptual view of a display device 1 according to an embodiment.

[0059] Embodiments of the display device can be implemented as an electronic device such as a smart phone, a mobile phone, a navigation device, a game console, a TV, a vehicle head unit, a notebook computer, a laptop computer, a tablet computer, a personal media player ("PMP"), or a personal digital assistant ("PDA"). In addition, the electronic device can be a flexible device.

[0060] As Figure 1 Embodiments of the display device 1 can include a display area DA and a peripheral area PA as shown in Figure 1 The shape of the substrate is not limited to a rectangular shape (in the x-y plane) as shown in

[0061] In embodiments, the substrate can include glass or metal. Alternatively, the substrate can include at least one selected from various flexible materials and bendable materials. In one embodiment, for example, the substrate can include a polymeric resin such as polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0062] The substrate can be variously modified. In one embodiment, for example, the substrate can have a multi-layer structure including two layers including a polymeric resin and a barrier layer including an inorganic material positioned between the two layers. In such an embodiment, the barrier layer can include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0063] A plurality of display devices can be positioned in the display area DA. In one embodiment, for example, each display device can be an organic light emitting diode OLED (see Figure 2 ), and can emit red light, green light, blue light, or white light. In an embodiment, one (sub) pixel positioned in the display area DA of the display device 1 of Figure 1 includes an organic light emitting diode OLED, and also includes a thin film transistor and a capacitor for controlling the degree of light emission of the organic light emitting diode OLED.

[0064] In such an embodiment, a driver, a power supply wiring, etc. can be positioned in the peripheral area PA. In addition, the peripheral area PA can include a pad area to which any one of various electronic devices such as a driving integrated circuit or a printed circuit substrate is electrically attached.

[0065] Figure 2 is an equivalent circuit diagram of one (sub) pixel SPX positioned in the display area DA of the display device 1 of Figure 1 . In an embodiment, a pixel circuit PC positioned in one (sub) pixel SPX can include a plurality of thin film transistors T1, T2, T3, T4, T5, T6, T7 (hereinafter, referred to as T1 to T7) and a storage capacitor Cst. The thin film transistors T1 to T7 and the storage capacitor Cst can be connected to a signal line, a first initialization voltage line VL1, a second initialization voltage line VL2, and a power voltage line PL.

[0066] The signal line can include a scan line SL that transmits a scan signal Sn, a previous scan line SL-1 that transmits a previous scan signal Sn-1 to the first initialization thin film transistor T4, a next scan line SL+1 that transmits the scan signal Sn to the second initialization thin film transistor T7, an emission control line EL that transmits an emission control signal En to the operation control thin film transistors T5 and T6, and a data line DL that intersects the scan line SL and transmits a data signal Dm. The power voltage line PL can transmit a driving voltage ELVDD to the driving thin film transistor T1, the first initialization voltage line VL1 can transmit a first initialization voltage Vint1 to the first initialization thin film transistor T4, and the second initialization voltage line VL2 can transmit a second initialization voltage Vint2 to the second initialization thin film transistor T7.

[0067] The driving gate electrode G1 (or first gate electrode) of the driving thin film transistor T1 (or first transistor) is connected to the lower electrode CE1 of the storage capacitor Cst, the driving source region S1 of the driving thin film transistor T1 is connected to the power voltage line PL via the operation control thin film transistor T5, and the driving drain region D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. In such an embodiment, the driving thin film transistor T1 can control the amount of current flowing from the second node N2 connected to the power voltage line PL to the organic light emitting diode OLED in response to the voltage applied to the first node N1, i.e., the voltage applied to the driving gate electrode G1. Accordingly, the driving thin film transistor T1 receives the data signal Dm and supplies the driving current I OLED The operation control thin film transistor T5 can be connected between the second node N2 and the power voltage line PL.

[0068] The switching gate electrode G2 (or second gate electrode) of the switching thin film transistor T2 (or second transistor) is connected to the scan line SL, the switching source region S2 of the switching thin film transistor T2 is connected to the data line DL, and the switching drain region D2 of the switching thin film transistor T2 is connected to the second node N2 connected to the driving source region S1 of the driving thin film transistor T1, and the driving source region S1 is connected to the power voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scan signal Sn received through the scan line SL, and performs a switching operation of transmitting the data signal Dm transmitted from the data line DL to the driving source region S1 of the driving thin film transistor T1.

[0069] The compensation thin film transistor T3 (or third transistor) can be connected between the first node N1 and the third node N3 located between the driving thin film transistor T1 and the organic light emitting diode OLED, and can diode-connect the driving thin film transistor T1 in response to the voltage applied to the compensation gate electrode G3 (or third gate electrode) of the compensation thin film transistor T3. In such an embodiment, the compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL, the compensation drain region D3 of the compensation thin film transistor T3 is connected to the driving drain region D1 of the driving thin film transistor T1 and to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6, and the compensation source region S3 of the compensation thin film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain region D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1.

[0070] The compensation thin film transistor T3 is turned on in response to a scan signal Sn received through the scan line SL, and diode-connects the drive thin film transistor T1 by electrically connecting the drive gate electrode G1 and the drive drain region D1 of the drive thin film transistor T1. In an embodiment, the compensation thin film transistor T3 has a dual gate electrode structure. In such an embodiment, the compensation gate electrode G3 of the compensation thin film transistor T3 includes a first third gate electrode G3-1 (see Figure 3 ) and a second third gate electrode G3-2 (see Figure 3 ).

[0071] The first initialization thin film transistor T4 (or fourth transistor) can be connected between the first node N1 and a first initialization voltage line VL1, and can initialize the voltage of the drive gate electrode G1 in response to a voltage applied to a first initialization gate electrode G4 (or fourth gate electrode) of the first initialization thin film transistor T4. In such an embodiment, the first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1, the first initialization source region S4 of the first initialization thin film transistor T4 is connected to the first initialization voltage line VL1, and the first initialization drain region D4 of the first initialization thin film transistor T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the compensation source region S3 of the compensation thin film transistor T3, and the drive gate electrode G1 of the drive thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to a previous scan signal Sn-1 received through the previous scan line SL-1, and performs an initialization operation of initializing the voltage of the drive gate electrode G1 of the drive thin film transistor T1 by transmitting a first initialization voltage Vint1 to the drive gate electrode G1 of the drive thin film transistor T1. In an embodiment, the first initialization thin film transistor T4 has a dual gate electrode structure. In such an embodiment, the first initialization gate electrode G4 of the first initialization thin film transistor T4 includes a first fourth gate electrode G4-1 (see Figure 3 ) and a second fourth gate electrode G4-2 (see Figure 3 ).

[0072] The operation control thin film transistor T5 (or fifth transistor) can be connected between the second node N2 and a power voltage line PL, and can be turned on in response to a voltage applied to an operation control gate electrode G5 (or fifth gate electrode) of the operation control thin film transistor T5. In such an embodiment, the operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL, the operation control source region S5 of the operation control thin film transistor T5 is connected to the power voltage line PL, and the operation control drain region D5 of the operation control thin film transistor T5 is connected to the drive source region S1 of the drive thin film transistor T1 and the switch drain region D2 of the switch thin film transistor T2.

[0073] The emission control thin-film transistor T6 (or sixth transistor) can be connected between the third node N3 and the organic light emitting diode OLED, and can be turned on in response to a voltage applied to an emission control gate electrode G6 (or sixth gate electrode) of the emission control thin-film transistor T6 from the emission control line EL. In such an embodiment, the emission control gate electrode G6 of the emission control thin-film transistor T6 is connected to the emission control line EL, the emission control source region S6 of the emission control thin-film transistor T6 is connected to the driving drain region D1 of the driving thin-film transistor T1 and the compensation drain region D3 of the compensation thin-film transistor T3, and the emission control drain region D6 of the emission control thin-film transistor T6 is electrically connected to the second initialization source region S7 of the second initialization thin-film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0074] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 are simultaneously turned on in response to an emission control signal En received through the emission control line EL, so that the driving voltage ELVDD is transmitted to the pixel electrode of the organic light emitting diode OLED and the driving current I OLED flows through the organic light emitting diode OLED.

[0075] The second initialization thin-film transistor T7 (or seventh transistor) is connected between the second initialization voltage line VL2 and the third node N3 located between the driving thin-film transistor T1 and the organic light emitting diode OLED. In an embodiment, the second initialization gate electrode G7 (or seventh gate electrode) of the second initialization thin-film transistor T7 is connected to the next scan line SL+1, the second initialization source region S7 of the second initialization thin-film transistor T7 is connected to the emission control drain region D6 of the emission control thin-film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization drain region D7 of the second initialization thin-film transistor T7 is connected to the second initialization voltage line VL2. The second initialization thin-film transistor T7 can initialize the voltage of the pixel electrode of the organic light emitting diode OLED in response to a voltage applied to the second initialization gate electrode G7 as the seventh gate electrode.

[0076] In such an embodiment, the scan line SL and the next scan line SL+1 are electrically connected to each other, so that the same scan signal Sn can be applied to the scan line SL and the next scan line SL+1. Accordingly, the second initialization thin-film transistor T7 can be turned on in response to the scan signal Sn received through the next scan line SL+1, and can perform an operation of initializing the voltage of the pixel electrode of the organic light emitting diode OLED.

[0077] The upper electrode CE2 of the storage capacitor Cst is connected to the power supply voltage line PL, and the common electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Thus, the organic light emitting diode OLED can receive a drive current I from the drive thin film transistor T1 OLED to emit light and display an image.

[0078] In an embodiment, as shown in Figure 2 , the compensation thin film transistor T3 can have a dual gate electrode structure. Alternatively, the compensation thin film transistor T3 can include a single gate electrode. In an embodiment, as shown in Figure 2 , the first initialization thin film transistor T4 can have a dual gate electrode structure. Alternatively, the first initialization thin film transistor T4 can include a single gate electrode.

[0079] Figure 3 is a view showing positions of the plurality of thin film transistors T1 to T7 and the storage capacitor Cst in the (sub)pixel SPX of Figure 2 . Figure 4 is a view showing an arrangement of the semiconductor layer 1130 as a part of the (sub)pixel SPX of Figure 3 . Figure 5 is a view showing an arrangement of the first initialization connection line 1173a and the second initialization connection line 1173b of Figure 3 . Figure 7 is a cross-sectional view taken along lines A-A' and B-B' of Figure 3 .

[0080] The drive thin film transistor T1, the switch thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 are arranged along the semiconductor layer 1130. Some portions of the semiconductor layer 1130 can constitute semiconductor layers of the drive thin film transistor T1, the switch thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. In such an embodiment, some portions of the semiconductor layer 1130 can constitute active regions, source regions, or drain regions of the thin film transistors.

[0081] The semiconductor layer 1130 can be disposed or formed on the base 101. The buffer layer 111 can be disposed or formed on the base 101, and the semiconductor layer 1130 can be formed on the buffer layer 111.

[0082] The buffer layer 111 can reduce or block penetration of foreign substances, moisture, or external air from the bottom of the base 101, and can planarize the base 101. The buffer layer 111 can include an inorganic material such as an oxide or a nitride, an organic material, or a combination of inorganic and organic materials, and can have a single-layer structure or a multi-layer structure including inorganic and organic materials. In one embodiment, for example, the buffer layer 111 can have a structure in which a first buffer layer 111a and a second buffer layer 111b are stacked, and in such an embodiment, the first buffer layer 111a and the second buffer layer 111b can include different materials from each other. In one embodiment, for example, the first buffer layer 111a can include silicon nitride, and the second buffer layer 111b can include silicon oxide.

[0083] In an embodiment, in the case where the first buffer layer 111a includes silicon nitride, hydrogen can be included when the silicon nitride is formed. Accordingly, carrier mobility of a semiconductor layer 1130 formed on the buffer layer 111 can be improved, and electrical characteristics of the thin film transistors T1 to T7 can be improved. In an embodiment, the semiconductor layer 1130 can include a silicon material, and in such an embodiment, interface adhesion properties between the semiconductor layer 1130 including silicon and the second buffer layer 111b including silicon oxide can be improved, and electrical characteristics of the thin film transistors T1 to T7 can be improved.

[0084] The semiconductor layer 1130 can include low temperature polysilicon ("LTPS"). A polysilicon material has a high electron mobility (e.g., 100 square centimeters (cm 2 / V·s) or more), and thus has low power consumption and high reliability. Alternatively, the semiconductor layer 1130 can include amorphous silicon ("a-Si") and / or an oxide semiconductor. Alternatively, some of the thin film transistors T1 to T7 can include LTPS, and others can include a-Si and / or an oxide semiconductor.

[0085] The source and drain regions of the semiconductor layer 1130 can be doped with impurities, and the impurities can include N-type impurities or P-type impurities. Each source region and each drain region can correspond to a source electrode and a drain electrode, respectively. The source and drain regions can vary from each other depending on the performance of the thin film transistor. Hereinafter, the terms "source region" and "drain region" are used instead of the terms "source electrode" and "drain electrode". In Figure 2 In an equivalent circuit diagram of FIG. 1, a specific portion of the semiconductor layer 1130 is doped with P-type impurities, and the thin film transistors T1 to T7 can be implemented as p-channel metal oxide semiconductor ("PMOS") field effect transistors ("MOSFETs"). Other portions of the semiconductor layer 1130 can also be doped with impurities, and can be used as a wiring for electrically connecting the thin film transistors T1 to T7 and / or the storage capacitor Cst.

[0086] The first gate insulating film 112 can be disposed on the semiconductor layer 1130, and the drive gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL can be disposed on the first gate insulating film 112. The first gate insulating film 112 can include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0087] The portion of the scan line SL overlapping with the second active region of the switching thin film transistor T2 and the third active region A3 of the compensation thin film transistor T3 can define the switching gate electrode G2 and the compensation gate electrode G3 including the first third gate electrode G3-1 and the second third gate electrode G3-2, respectively, the portion of the previous scan line SL-1 overlapping with the fourth active region A4 of the first initialization thin film transistor T4 can define the first initialization gate electrode G4 including the first fourth gate electrode G4-1 and the second fourth gate electrode G4-2, the portion of the next scan line SL+1 overlapping with the seventh active region of the second initialization thin film transistor T7 can define the second initialization gate electrode G7, and the portion of the emission control line EL overlapping with the operation control thin film transistor T5 and the emission control thin film transistor T6 can define the operation control gate electrode G5 and the emission control gate electrode G6, respectively. The channel of the compensation thin film transistor T3 can include the third active region A3 overlapping with the scan line SL and a region A3a between the third active region A3 and the third active region A3, and the channel of the first initialization thin film transistor T4 can include the fourth active region A4 overlapping with the previous scan line SL-1 and a region A4a between the fourth active region A4 and the fourth active region A4.

[0088] Each of the drive gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL can include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer structure or a multi-layer structure including the above-described material. In one embodiment, for example, each of the drive gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL can have a multi-layer structure including a Mo layer and an Al layer, or can have a multi-layer structure including a Mo layer, an Al layer, and a Mo layer.

[0089] The second gate insulating film 113 can be disposed or provided on the drive gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL. The second gate insulating film 113 can include silicon oxide (SiO2), silicon nitride (SiNx silicon nitride (SiN), silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0090] The electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 can be provided on the second gate insulating film 113. The electrode voltage line HL can cover at least a portion of the drive gate electrode G1, and can form a storage capacitor Cst together with the drive gate electrode G1.

[0091] The lower electrode CE1 of the storage capacitor Cst can be formed integrally with the drive gate electrode G1 of the drive thin film transistor T1 as a single integral unit. In one embodiment, for example, the drive gate electrode G1 of the drive thin film transistor T1 can be used as the lower electrode CE1 of the storage capacitor Cst. The portion of the electrode voltage line HL that overlaps the drive gate electrode G1 can be the upper electrode CE2 of the storage capacitor Cst. Thus, the second gate insulating film 113 can be used as a dielectric layer of the storage capacitor Cst.

[0092] Each of the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 can include a conductive material of molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer structure or a multi-layer structure including the above-described material. In one embodiment, for example, each of the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 can have a multi-layer structure including a Mo layer and an Al layer, or can have a multi-layer structure including a Mo layer, an Al layer, and a Mo layer.

[0093] An interlayer insulating layer 115 is provided on the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2. The interlayer insulating layer 115 can include silicon oxide (SiO2), silicon nitride (SiN x silicon nitride (SiN), silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0094] The data line DL, the power voltage line PL, the first and second initialization connection lines 1173a and 1173b, the node connection line 1174, and the connection metal 1175 can be disposed on the interlayer insulating layer 115. The data line DL, the power voltage line PL, the first and second initialization connection lines 1173a and 1173b, the node connection line 1174, and the connection metal 1175 can include a conductive material of molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer structure or a multi-layer structure including the above-described material. In an embodiment, for example, each of the data line DL, the power voltage line PL, the first and second initialization connection lines 1173a and 1173b, the node connection line 1174, and the connection metal 1175 can have a multi-layer structure including a Ti layer, an Al layer, and a Ti layer.

[0095] The data line DL can be connected to the switch source region S2 of the switch thin-film transistor T2 through the contact hole 1154. In an embodiment, a portion of the data line DL can define the switch source electrode.

[0096] The power voltage line PL can be connected to the upper electrode CE2 of the storage capacitor Cst through the contact hole 1158 defined in the interlayer insulating layer 115. Accordingly, the electrode voltage line HL and the power voltage line PL can have the same voltage level (constant voltage). In an embodiment, the power voltage line PL can be connected to the operation control drain region D5 through the contact hole 1155.

[0097] The first initialization voltage line VL1 is connected to the first initialization connection line 1173a through the contact hole 1159a, and the first initialization connection line 1173a is connected to the first initialization thin-film transistor T4 through the contact hole 1159b. The second initialization voltage line VL2 can be connected to the second initialization connection line 1173b through the contact hole 1151, and the second initialization connection line 1173b can be connected to the second initialization thin-film transistor T7 through the contact hole 1152. The first and second initialization voltage lines VL1 and VL2 can have the same constant voltage (for example, -2 volts (V)) as each other.

[0098] One end of the node connection line 1174 can be connected to the compensation source region S3 through the contact hole 1156, and the other end of the node connection line 1174 can be connected to the driving gate electrode G1 through the contact hole 1157.

[0099] The connection metal 1175 is connected to the semiconductor layer of the emission control thin-film transistor T6 through the contact hole 1153 defined through the second gate insulating film 113 and the first gate insulating film 112. The connection metal 1175 is connected to the pixel electrode 210 of the organic light-emitting diode OLED through the contact hole 1163. Thus, the emission control thin-film transistor T6 can be electrically connected to the pixel electrode 210 of the organic light-emitting diode OLED.

[0100] The planarization layer 117 can be provided on the data line DL, the power voltage line PL, the first initialization connection line 1173a and the second initialization connection line 1173b, the node connection line 1174, and the connection metal 1175, and the organic light-emitting diode OLED can be provided on the planarization layer 117.

[0101] Figure 2 An embodiment of one pixel circuit PC is shown, and Figure 3 A structure of one (sub)pixel SPX is shown. In such an embodiment, a plurality of (sub)pixels SPX having the same pixel circuit PC as Figure 2 The plurality of (sub)pixels SPX having the same pixel circuit PC as

[0102] In an embodiment, the previous scan line SL-1 can be electrically connected to the second initialization thin-film transistor T7 of another pixel circuit PC positioned in the +y-axis direction from Figure 3 the pixel circuit PC of Equation 1. Thus, the previous scan signal Sn-1 applied to the previous scan line SL-1 can be transmitted as the next scan signal to the second initialization thin-film transistor T7 of another pixel circuit PC positioned in the +y-axis direction. In such an embodiment, the next scan line SL+1 can be electrically connected to the first initialization thin-film transistor T4 of another pixel circuit PC positioned in the -y-axis direction from Figure 3 the pixel circuit PC of Equation 1, and can transmit the previous scan signal and the initialization voltage.

[0103] The planarization layer 117 disposed on the data line DL, the power voltage line PL, the first and second initialization connection lines 1173a and 1173b, the node connection line 1174, and the connection metal 1175 can have a planar top surface to planarize the pixel electrode 210. In an embodiment, the planarization layer 117 can include an organic material, and can have a single layer structure or a multi-layer structure. The planarization layer 117 can include benzocyclobutene ("BCB"), polyimide, hexamethyldisiloxane ("HMDSO"), a general-purpose polymer such as polymethyl methacrylate ("PMMA") or polystyrene ("PS"), a polymer derivative having a phenol-based group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorinated polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof. In an embodiment, the planarization layer 117 can include an inorganic material. The planarization layer 117 can include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). In an embodiment, in the case where the planarization layer 117 includes an inorganic material, chemical mechanical polishing can be performed as necessary. In an embodiment, the planarization layer 117 can include both an organic material and an inorganic material.

[0104] The organic light emitting diode OLED can include the pixel electrode 210, the common electrode 230 disposed above the pixel electrode 210, and the intermediate layer 220 disposed between the pixel electrode 210 and the common electrode 230 and including an emission layer.

[0105] The pixel electrode 210 can be connected to the connection metal 1175 through the contact hole 1163 defined in the planarization layer 117, and the connection metal 1175 can be connected to the emission control drain region D6 through the contact hole 1153 defined in the lower insulating layer. The pixel electrode 210 can be a (semi-)transmissive electrode or a reflective electrode. In an embodiment, the pixel electrode 210 can include a reflective film of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer on the reflective film. The transparent or semi-transparent electrode layer can include at least one selected from indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide ("IGO"), and aluminum zinc oxide ("AZO"). In an embodiment, the pixel electrode 210 can have a stack structure including ITO / Ag / ITO.

[0106] The pixel defining film 119 can be disposed on the planarization layer 117 and define an opening portion that exposes a central portion of the pixel electrode 210 to define an emission area of a pixel through the pixel defining film 119. In an embodiment, the pixel defining film 119 can increase a distance between an edge of the pixel electrode 210 and the common electrode 230 disposed above the pixel electrode 210 to prevent an arc or the like from being generated on the edge of the pixel electrode 210. The pixel defining film 119 can include or be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, or phenol resin by using spin coating or the like.

[0107] The intermediate layer 220 can include an organic emission layer. The organic emission layer can include an organic material including a fluorescent or phosphorescent material that emits red light, green light, blue light, or white light. The organic emission layer can include or be formed of a low molecular weight organic material or a high molecular weight organic material, and functional layers such as a hole transport layer ("HTL"), a hole injection layer ("HIL"), an electron transport layer ("ETL"), and an electron injection layer ("EIL") can be selectively disposed below and above the organic emission layer. The intermediate layer 220 can be disposed to correspond to each of the plurality of pixel electrodes 210. However, the disclosure is not limited thereto, and layers such as the HTL, the HIL, the ETL, or the EIL included in the layers of the intermediate layer 220 can be integrally formed above the plurality of pixel electrodes 210 as a single integral unit.

[0108] The common electrode 230 can be a light-transmitting electrode or a reflective electrode. In an embodiment, the common electrode 230 can be a transparent or semi-transparent electrode, and can include a metal thin film of lithium (Li), calcium (Ca), LiF / Ca, LiF / Al, aluminum (Al), silver (Ag), magnesium (Mg), or a compound thereof, having a low work function. In an embodiment, a transparent conductive oxide (TCO) film including ITO, IZO, ZnO, or In2O3 can be further disposed on the metal thin film. The common electrode 230 can be integrally formed to correspond to the plurality of pixel electrodes 210 as a single integral unit.

[0109] An encapsulation layer 300 including a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 320, and an organic encapsulation layer 330 disposed between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320 can be disposed on the common electrode 230. Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320 can include silicon oxide (SiO2), silicon nitride (SiN x) silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The organic encapsulation layer 330 can include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, sulfonic acid polyethylene, polyformaldehyde, polyarylate, hexamethyldisiloxane, an acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or a combination thereof.

[0110] In an embodiment, as described above, the first gate insulating film 112 can be provided on the semiconductor layer 1130, and the drive gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL can be provided on the first gate insulating film 112. As described above, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL include the switching gate electrode G2, the compensation gate electrode G3, the first initialization gate electrode G4, the operation control gate electrode G5, the emission control gate electrode G6, and the second initialization gate electrode G7. Thus, the first gate insulating film 112 is provided between the semiconductor layer 1130 and the drive gate electrode G1, the switching gate electrode G2, the compensation gate electrode G3, the first initialization gate electrode G4, the operation control gate electrode G5, the emission control gate electrode G6, and the second initialization gate electrode G7.

[0111] Figure 6 is a view illustrating an arrangement of the first initialization voltage line VL1, the second initialization voltage line VL2, the first initialization connection line 1173a, and the second initialization connection line 1173b in the plurality of pixels PX11 to PX42 of the display device according to an embodiment. Figure 3 is a view illustrating an arrangement of the first initialization voltage line VL1, the second initialization voltage line VL2, the first initialization connection line 1173a, and the second initialization connection line 1173b in the plurality of pixels PX11 to PX42 of the display device according to an embodiment. Figure 8 is a view illustrating an arrangement of the first initialization voltage line VL1, the second initialization voltage line VL2, the first initialization connection line 1173a, and the second initialization connection line 1173b in the plurality of pixels PX11 to PX42 of the display device according to an embodiment. Figure 9 is a view illustrating an arrangement of the first initialization voltage line VL1, the second initialization voltage line VL2, the first initialization connection line 1173a, the first auxiliary initialization connection line 1173a', the second initialization connection line 1173b, and the second auxiliary initialization connection line 1173b' in the plurality of pixels PX11 to PX42 of the display device according to an alternative embodiment. Figure 10 is a view illustrating an arrangement of the first initialization voltage line VL1, the second initialization voltage line VL2, the first initialization connection line 1173a, the first auxiliary initialization connection line 1173a', the second initialization connection line 1173b, and the second auxiliary initialization connection line 1173b' in the plurality of pixels PX11 to PX81 of the display device according to another alternative embodiment.

[0112] In an embodiment, such as Figure 6 As shown, the first initialization voltage line VL1 and the second initialization voltage line VL2 extend in a first direction (x-axis direction). The first initialization connection line 1173a extends in a second direction (y-axis direction) intersecting the first direction (x-axis direction) and is electrically connected to the first initialization voltage line VL1. The second initialization connection line 1173b extends in the second direction (y-axis direction) intersecting the first direction (x-axis direction) and is electrically connected to the second initialization voltage line VL2.

[0113] It is desirable to apply the same first initialization voltage Vint1 to the first initialization voltage line VL1. However, due to the increased size of the display device and / or the higher resolution of the display device, voltage gradation may occur in the first initialization voltage line VL1. In this case, the same first initialization voltage Vint1 may not be applied to the first initialization thin-film transistors T4 of different pixels. In an embodiment of the display device 1 according to the present invention, the first initialization connection line 1173a electrically connects the first initialization voltage lines VL1 arranged in different rows to each other, such that the potential of the first initialization voltage line VL1 can be uniformly maintained above the first initialization voltage Vint1 across the entire display area DA.

[0114] In such an embodiment, it is desirable to apply the same second initialization voltage Vint2 to the second initialization voltage line VL2. However, due to the increased size of the display device and / or the high resolution of the display device, voltage gradation may occur in the second initialization voltage line VL2. In this case, the same second initialization voltage Vint2 may not be applied to the pixel electrodes 210 of different pixels. In an embodiment of the display device 1 according to the present invention, the second initialization connection line 1173b electrically connects the second initialization voltage lines VL2 arranged in different rows to each other, such that the potential of the second initialization voltage line VL2 can be uniformly maintained above the second initialization voltage Vint2 across the entire display area DA.

[0115] In an embodiment, the display device 1 may include a substrate 101 as described above and through holes defined through the top and bottom surfaces of the substrate 101. In such an embodiment, as Figure 1 As shown, the display device 1 may be provided with a through-hole TH corresponding to the through-hole of the substrate 101. In embodiments where the display device 1 is a component of a smartphone, for example, a camera may be mounted in the through-hole TH of the display device 1, or light incident on the camera disposed in the through-hole TH may pass through the through-hole TH.

[0116] In such an embodiment, in a case where the through-hole TH passes through the top surface and the bottom surface of the substrate 101, the pixel is positioned outside the through-hole TH of the substrate 101. The thin film transistor included in the pixel and various lines electrically connected to the plurality of pixels can also be positioned outside the through-hole TH. The first initialization voltage line VL1 and the second initialization voltage line VL2 do not pass through the through-hole TH, and have end portions around the through-hole TH.

[0117] In an embodiment in which the through-hole TH is defined to pass through the substrate 101, the length of the first initialization voltage line VL1 and the second initialization voltage line VL2 in the first direction (x-axis direction) in a portion in which the through-hole TH is present is smaller than the length of the first initialization voltage line VL1 and the second initialization voltage line VL2 in the first direction (x-axis direction) in a portion in which the through-hole TH is not present. Since the length of the first initialization voltage line VL1 and the second initialization voltage line VL2 in the portion in which the through-hole TH is present and the length of the first initialization voltage line VL1 and the second initialization voltage line VL2 in the portion in which the through-hole TH is not present are different from each other, the degree of voltage drop that occurs in the first initialization voltage line VL1 and the second initialization voltage line VL2 in the portion in which the through-hole TH is present is different from the degree of voltage drop that occurs in the first initialization voltage line VL1 and the second initialization voltage line VL2 in the portion in which the through-hole TH is not present. Therefore, the first initialization voltage Vint1 and the second initialization voltage Vint2 applied to the pixels in the row having the through-hole TH are different from the first initialization voltage Vint1 and the second initialization voltage Vint2 applied to the pixels in the row not having the through-hole TH. If the first initialization voltage Vint1 and the second initialization voltage Vint2 are different from each other, the luminance of the pixels can become different from each other even when the same data signal Dm is applied to the pixels.

[0118] In an embodiment of the display device 1 according to the present application, the first initialization connection line 1173a electrically connects the first initialization voltage lines VL1 arranged in different rows to each other, and the second initialization connection line 1173b electrically connects the second initialization voltage lines VL2 arranged in different rows to each other, so that the potential of the first initialization voltage line VL1 can be uniformly maintained at the first initialization voltage Vint1 in different rows, and the potential of the second initialization voltage line VL2 can be uniformly maintained at the second initialization voltage Vint2 in rows different from each other. Therefore, the display device 1 can display a high-quality image.

[0119] In an embodiment, as Figure 8As shown, the first initialization connection line 1173a and the second initialization connection line 1173b pass through each of the pixels. In such an embodiment, one first initialization connection line 1173a and one second initialization connection line 1173b extending in the second direction (y-axis direction) pass through pixels PX11 and PX12 in the first column, another first initialization connection line 1173a and another second initialization connection line 1173b pass through pixels PX21 and PX22 in the second column, another first initialization connection line 1173a and another second initialization connection line 1173b pass through pixels PX31 and PX32 in the third column, and another first initialization connection line 1173a and another second initialization connection line 1173b pass through pixels PX41 and PX42 in the fourth column. However, this disclosure is not limited thereto.

[0120] In an alternative embodiment, for example, such as Figure 9 As shown, the first initialization connection line 1173a can be arranged in one of the even-numbered and odd-numbered columns of pixels, and the second initialization connection line 1173b can be arranged in the other of the even-numbered and odd-numbered columns of pixels. In such an embodiment, as Figure 9 As shown, a first initialization connection line 1173a passes through pixels PX11 and PX12 in the first column, and another first initialization connection line 1173a passes through pixels PX31 and PX32 in the third column. In such an embodiment, as Figure 9 As shown, a second initialization connection line 1173b passes through pixels PX21 and PX22 in the second column, and another second initialization connection line 1173b passes through pixels PX41 and PX42 in the fourth column. In such an embodiment, the first initialization connection line 1173a is arranged in the odd-numbered columns of pixels, and the second initialization connection line 1173b is arranged in the even-numbered columns of pixels.

[0121] In an embodiment, the display device 1 may further include a first auxiliary initialization connection line 1173a'. The first auxiliary initialization connection line 1173a' is located in pixels that the first initialization connection line 1173a does not pass through, i.e., pixels in even-numbered columns, and is electrically connected to the first initialization voltage line VL1. The first auxiliary initialization connection line 1173a' can be electrically connected to the first initialization thin-film transistor T4 of the corresponding pixel through a contact hole, and the first initialization thin-film transistor T4 can be electrically connected to the first initialization voltage line VL1.

[0122] In such an embodiment, the display device 1 may further include a second auxiliary initialization connection line 1173b'. The second auxiliary initialization connection line 1173b' is located in pixels that the second initialization connection line 1173b does not pass through, i.e., in pixels of an odd number of columns, and is electrically connected to the second initialization voltage line VL2. The second auxiliary initialization connection line 1173b' can be electrically connected to the second initialization thin-film transistor T7 of the corresponding pixel through a contact hole, and the second initialization thin-film transistor T7 can be electrically connected to the second initialization voltage line VL2.

[0123] In an embodiment of display device 1, the parasitic capacitance between the first initialization connection line 1173a and the second initialization connection line 1173b can be minimized. In an embodiment where the first initialization connection line 1173a and the second initialization connection line 1173b are arranged in the same column, they are close to each other, and therefore parasitic capacitance may occur between them. In an embodiment of display device 1, the first initialization connection line 1173a and the second initialization connection line 1173b are not arranged in the same column, but in different columns, so that the parasitic capacitance between them can be minimized.

[0124] However, this disclosure is not limited thereto. In an alternative embodiment, for example, the first initialization connection line 1173a may be arranged in every m columns of pixels, where m is a natural number greater than 1. In embodiments, as Figure 10 As shown, the first initialization connection line 1173a is arranged in the second column PX21. In the first direction, another first initialization connection line 1173a is arranged in the sixth column PX61, while the first initialization connection line 1173a is not arranged in the pixels PX11 of the first column, PX31 of the third column, PX41 of the fourth column, PX51 of the fifth column, PX71 of the seventh column, and PX81 of the eighth column. In such an embodiment, the first initialization connection line 1173a can be arranged in every four columns of pixels.

[0125] In such an embodiment, the second initialization connection line 1173b can be arranged between the first initialization connection lines 1173a. In such an embodiment, the second initialization connection line 1173b can also be arranged in every m columns of pixels. In an embodiment, as... Figure 10 As shown, the second initialization connection line 1173b is only arranged in the fourth column PX41 and the eighth column PX81 of the first column PX11 to the eighth column PX81.

[0126] In an embodiment, as described above, the first initialization connection line 1173a and the second initialization connection line 1173b can be alternately arranged in the first direction (x-axis direction). In such an embodiment, the first auxiliary initialization connection line 1173a' is positioned in a pixel through which the first initialization connection line 1173a does not pass, and is electrically connected to the first initialization voltage line VL1. The first auxiliary initialization connection line 1173a' can be electrically connected to the first initialization thin-film transistor T4 of the corresponding pixel through a contact hole, and can electrically connect the first initialization thin-film transistor T4 to the first initialization voltage line VL1. In such an embodiment, the second auxiliary initialization connection line 1173b' is positioned in a pixel through which the second initialization connection line 1173b does not pass, and is electrically connected to the second initialization voltage line VL2. The second auxiliary initialization connection line 1173b' can be electrically connected to the second initialization thin-film transistor T7 of the corresponding pixel through a contact hole, and can electrically connect the second initialization thin-film transistor T7 to the second initialization voltage line VL2.

[0127] In an embodiment, as described above, the first initialization voltage line VL1 and the second initialization voltage line VL2 are disposed on the second gate insulating film 113. The interlayer insulating layer 115 is disposed on the first initialization voltage line VL1 and the second initialization voltage line VL2. The first initialization connection line 1173a and the second initialization connection line 1173b can be disposed on the interlayer insulating layer 115 together with the data line DL and the power voltage line PL. Accordingly, the first initialization connection line 1173a and the second initialization connection line 1173b can include the same material as the material included in the data line DL and the power voltage line PL, and can have the same layer structure as the layer structure of the data line DL and the power voltage line PL. In one embodiment, for example, as described above, each of the data line DL, the power voltage line PL, and the first initialization connection line 1173a and the second initialization connection line 1173b can have a multilayer structure formed of Ti / Al / Ti.

[0128] As described above, according to embodiments of the application described herein, a display device capable of displaying a high-quality image can be implemented. However, the present application should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0129] While the application has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit or scope of the application as defined by the following claims.

Claims

1. A display device, wherein, The display device includes: The first initialization voltage line extends in the first direction; The second initialization voltage line extends in the first direction; A first initialization connection line extends in a second direction intersecting the first direction, wherein the first initialization connection line electrically connects the first initialization voltage lines to each other; A second initialization connection line extends in the second direction, wherein the second initialization connection line electrically connects the second initialization voltage lines to each other; and Pixels are connected to the first initialization voltage line and the second initialization voltage line. Wherein, the first group of pixels through which the first initialization connection line passes is electrically connected to the first initialization voltage line via the first initialization connection line. The display device further includes a first auxiliary initialization connection line located in a second group of pixels that the first initialization connection line does not pass through, wherein the first auxiliary initialization connection line is electrically connected to the first initialization voltage line.

2. The display device according to claim 1, wherein, Each of the pixels includes: Organic light-emitting diode; The first transistor controls the amount of current flowing from the second node, which is electrically connected to the power supply voltage line, to the organic light-emitting diode in response to a voltage applied to the first node. A fourth transistor, connected between the first node and the first initialization voltage line, wherein the fourth transistor initializes the voltage of the first gate electrode of the first transistor in response to a voltage applied to the fourth gate electrode of the fourth transistor; and A seventh transistor is connected between the second initialization voltage line and a third node between the first transistor and the organic light-emitting diode, wherein the seventh transistor initializes the voltage of the pixel electrode of the organic light-emitting diode in response to a voltage applied to the seventh gate electrode of the seventh transistor.

3. The display device according to claim 1, wherein, The first initialization connection line and the second initialization voltage line pass through each of the pixels.

4. The display device according to claim 1, wherein, The first initialization connection line is arranged in one of the even-numbered and odd-numbered columns of the pixels, and The second initialization connection line is arranged in the other of the even-numbered column and the odd-numbered column of the pixel.

5. The display device according to claim 1, wherein, The first initialization connection line is arranged in every m columns of the pixel, where m is a natural number greater than 1.

6. The display device according to claim 5, wherein, The second initialization connection line is arranged between the first initialization connection lines.

7. The display device according to claim 5, wherein, The first initialization connection line and the second initialization connection line are arranged alternately in the first direction.

8. The display device according to claim 1, in, The third group of pixels through which the second initialization connection line passes is electrically connected to the second initialization voltage line via the second initialization connection line. The display device further includes a second auxiliary initialization connection line located in a fourth group of pixels that the second initialization connection line does not pass through, wherein the second auxiliary initialization connection line is electrically connected to the second initialization voltage line.

9. The display device according to claim 1, wherein, The display device further includes: The data cable extends in the first direction. The first initialization connection line and the second initialization connection line are located in the same layer as the data line.

10. The display device according to claim 9, wherein, The first initialization connection line and the second initialization connection line comprise the same material as the material included in the data line.

11. The display device according to claim 9, wherein, The first initialization voltage line and the second initialization voltage line are positioned below the first initialization connection line.

12. The display device according to claim 1, wherein, The display device further includes: The power supply voltage line extends in the first direction. The first initialization connection line and the second initialization connection line are disposed in the same layer as the power supply voltage line.

13. The display device according to claim 12, wherein, The first initialization connection line and the second initialization connection line comprise the same material as the material included in the power supply voltage line.

14. The display device according to claim 12, wherein, The first initialization voltage line and the second initialization voltage line are positioned below the first initialization connection line.

15. The display device according to claim 1, wherein, The display device further includes: A substrate, wherein the through-hole is defined to pass through the top and bottom surfaces of the substrate. The pixel is positioned outside the through-hole of the substrate.

16. A display device, wherein, The display device includes: Base; A first initialization voltage line and a second initialization voltage line are disposed on the substrate and extend in a first direction; A first initialization connection line is disposed on an interlayer insulation layer covering the first initialization voltage line and the second initialization voltage line, wherein the first initialization connection line extends in a second direction intersecting the first direction and electrically connects the first initialization voltage lines to each other through contact holes defined in the interlayer insulation layer. A second initialization connection line is disposed on the interlayer insulation layer, wherein the second initialization connection line extends in the second direction and electrically connects the second initialization voltage lines to each other through contact holes defined in the interlayer insulation layer; and An organic light-emitting diode is disposed on a planarization layer covering the first initialization connection line and the second initialization connection line. Wherein, the first set of organic light-emitting diodes through which the first initialization connection line passes is electrically connected to the first initialization voltage line via the first initialization connection line. The display device further includes a first auxiliary initialization connection line located in a second group of organic light-emitting diodes that the first initialization connection line does not pass through, wherein the first auxiliary initialization connection line is electrically connected to the first initialization voltage line.

17. The display device according to claim 16, wherein, The first initialization connection line and the second initialization connection line pass through each of the organic light-emitting diodes.

18. The display device according to claim 16, wherein, The first initialization connection line is arranged in one of the even-numbered and odd-numbered columns of the organic light-emitting diode, and The second initialization connection line is arranged in the other of the even-numbered and odd-numbered columns of the organic light-emitting diode.

19. The display device according to claim 16, wherein, The first initialization connection line is arranged in each m column of the organic light-emitting diode, where m is a natural number greater than 1.

20. The display device according to claim 19, wherein, The second initialization connection line is arranged between the first initialization connection lines.

21. The display device according to claim 19, wherein, The first initialization connection line and the second initialization connection line are arranged alternately in the first direction.

22. The display device according to claim 16, wherein, The third group of organic light-emitting diodes, through which the second initialization connection line passes, is electrically connected to the second initialization voltage line via the second initialization connection line. The display device further includes a second auxiliary initialization connection line located in a fourth group of organic light-emitting diodes that the second initialization connection line does not pass through, wherein the second auxiliary initialization connection line is electrically connected to the second initialization voltage line.

23. The display device according to claim 16, wherein, The display device further includes: A data cable is disposed on the interlayer insulation layer and extends in the first direction.

24. The display device according to claim 23, wherein, The first initialization connection line and the second initialization connection line comprise the same material as the material included in the data line.

25. The display device according to claim 16, wherein, The display device further includes: A power supply voltage line is disposed on the interlayer insulation layer and extends in the first direction.

26. The display device according to claim 25, wherein, The first initialization connection line and the second initialization connection line comprise the same material as the material included in the power supply voltage line.

27. The display device according to claim 16, wherein, The through-hole is defined to pass through the top and bottom surfaces of the substrate, and The organic light-emitting diode is positioned outside the through-hole in the substrate.

28. The display device according to claim 1 or 16, wherein, The display device is one of a smartphone, mobile phone, navigation device, game console, television, vehicle head unit, laptop computer, tablet computer, personal media player, and personal digital assistant.

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