Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the present disclosure discloses a manufacturing method of a semiconductor device, comprising the following steps: providing a semiconductor structure, the semiconductor structure comprising a stacked structure alternately stacked by a first material layer and a second material layer, the stacked structure comprising a platform region and a step region adjacent to the platform region, the top of the platform region and the step region being the second material layer; forming a third material layer covering the upper surface of the platform region and the surface of the step region; forming a fourth material layer filling the step region and covering the platform region; removing the third material layer and the fourth material layer on the platform region, and retaining the third material layer and the fourth material layer on the edge of the platform region close to the step region; performing a first planarization, the first planarization removing the protruding fourth material layer and stopping on the second material layer and the third material layer on the upper surface of the platform region. The manufacturing method increases the connection window of the contact hole and effectively avoids over-grinding at the edge of the platform region.

Description

[0001] This disclosure is a divisional application of the patent filed on November 3, 2020, with application number 202011208819.9, entitled "Semiconductor Device and Method for Manufacturing Thereof". Technical Field

[0002] This disclosure relates to a method for fabricating a semiconductor device, which increases the connection window of the contact hole and effectively avoids over-wearing at the edge of the platform area. Background Technology

[0003] Since its inception, semiconductor integrated circuits have gone through the development stages of small-scale, medium-scale, large-scale, and ultra-large-scale integration, and have increasingly become one of the most active technological fields in modern science and technology.

[0004] Memory is a widely used semiconductor device. To overcome the limitations of traditional two-dimensional memory in terms of storage capacity, modern processes often employ stacking memory chips to achieve higher integration. For example, chips or structures with different functions can be stacked or interconnected vias using micromachining techniques to form a three-dimensional (3D) device with vertical integration and signal connectivity. Three-dimensional memory utilizes this technology to arrange memory cells three-dimensionally on a substrate, thereby improving memory performance and storage density. Summary of the Invention

[0005] The technical problem to be solved by the embodiments of this disclosure is to provide a method for manufacturing a semiconductor device, which increases the connection window of the contact hole and effectively avoids over-wearing at the edge of the platform area.

[0006] The technical problem to be solved by the embodiments of this disclosure is to provide a method for manufacturing a semiconductor device, which increases the connection window of the contact hole and effectively avoids excessive wear at the edge of the platform area.

[0007] The technical solution adopted by this disclosure to solve the above-mentioned technical problems is to provide a method for fabricating a semiconductor device, including the following steps: providing a semiconductor structure, the semiconductor structure including a stacked structure of alternating first material layers and second material layers, the stacked structure including a platform region and a step region adjacent to the platform region, the top of the platform region and the step region being the second material layer; forming a third material layer covering the upper surface of the platform region and the surface of the step region; forming a fourth material layer filling the step region and covering the platform region; removing the third material layer and the fourth material layer on the platform region, and retaining the third material layer and the fourth material layer located on the platform region near the edge of the step region; performing a first planarization, the first planarization removing the protruding fourth material layer, and retaining the second material layer and the third material layer on the upper surface of the platform region.

[0008] In one embodiment of this disclosure, the method further includes: removing a third material layer from the upper surface of the platform region; removing a second material layer from the top of the platform region to expose a first material layer; and performing a second planarization, wherein the second planarization removes a portion of the thickness of a fourth material layer on the step region and remains on the first material layer at the top of the platform region.

[0009] In one embodiment of this disclosure, the second planarization simultaneously removes a portion of the first material layer at the top of the platform region.

[0010] In one embodiment of this disclosure, a method for forming a third material layer covering the upper surface of the platform region and the surface of the step region includes: forming a third material layer covering the upper surface of the platform region, the surface of the step region, and the sidewalls; and removing the third material layer covering the sidewalls of the step region.

[0011] In one embodiment of this disclosure, the first planarization simultaneously removes a third material layer on the upper surface of the platform region away from the edge of the step region and a portion of the third material layer on the platform region near the edge of the step region.

[0012] In one embodiment of this disclosure, the first material layer includes a dielectric layer, and the second material layer includes a dummy gate layer.

[0013] In one embodiment of this disclosure, the material of the third material layer includes one or more of silicon oxynitride, aluminum oxide, and titanium nitride.

[0014] In one embodiment of this disclosure, the material of the fourth material layer includes silicon oxide.

[0015] In one embodiment of this disclosure, the first planarization is performed using chemical mechanical polishing, and the polishing selectivity of the fourth material layer relative to the third material layer is greater than 10.

[0016] In one embodiment of this disclosure, a third material layer is removed from the upper surface of the platform region using dry etching, and the etching selectivity of the third material layer relative to the first material layer and / or the second material layer is greater than 10.

[0017] Another aspect of this disclosure provides a semiconductor device comprising: a stacked structure consisting of alternating first and second material layers, the stacked structure including a plateau region and a step region adjacent to the plateau region, the top of the plateau region being the first material layer and the top of the step region being the second material layer; a third material layer covering the surface of the step region; and a fourth material layer filling the step region; wherein the upper surface of the plateau region is flush with the upper surface of the fourth material layer.

[0018] In one embodiment of this disclosure, a substrate located beneath the stacked structure is also included.

[0019] In one embodiment of this disclosure, the first material layer includes a dielectric layer, and the second material layer includes a dummy gate layer.

[0020] In one embodiment of this disclosure, the material of the third material layer includes one or more of silicon oxynitride, aluminum oxide, and titanium nitride.

[0021] In one embodiment of this disclosure, the material of the fourth material layer includes silicon oxide.

[0022] This invention discloses that, by adopting the above technical solution, it has the following significant advantages compared with the prior art:

[0023] The semiconductor device fabrication method disclosed herein increases the connection window of the contact hole by forming a third material layer covering the upper surface of the semiconductor structure platform region and the surface of the step region, effectively avoiding over-wearing at the edge of the platform region. Attached Figure Description

[0024] To make the above-mentioned objectives, features and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings, wherein:

[0025] Figure 1 and Figure 2 This is a schematic diagram illustrating a method for fabricating a semiconductor device;

[0026] Figure 3 and Figure 4 This is a schematic diagram of a semiconductor device;

[0027] Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0028] Figures 6 to 15This is a schematic diagram of the process steps of a method for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0029] Figure 16 This is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are merely some examples or embodiments of this disclosure. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0031] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure. However, this disclosure may also be implemented in other ways different from those described herein, and therefore this disclosure is not limited to the specific embodiments disclosed below.

[0032] As shown in this disclosure and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of expressly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0033] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0034] In detailing the embodiments of this disclosure, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0035] In the description of this disclosure, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings and is only for the convenience of describing this disclosure and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this disclosure; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0036] For ease of description, spatial relation terms such as “below,” “below,” “lower than,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of an element or feature shown in the accompanying drawings to other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the orientation of an element described as “below,” “below,” or “below” to other elements or features will change to “above” said other elements or features. Thus, the exemplary terms “below” and “below” can encompass both upward and downward directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0037] In the context of this disclosure, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0038] It should be understood that when a component is referred to as "on another component," "connected to another component," "coupled to another component," or "in contact with another component," it can be directly on, connected to, coupled to, or in contact with that other component, or there may be an inserting component. In contrast, when a component is referred to as "directly on another component," "directly connected to," "directly coupled to," or "directly in contact with" another component, there is no inserting component.

[0039] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this disclosure. In addition, although the terminology used in this disclosure is selected from commonly known and used terms, some terms mentioned in this disclosure may have been chosen by the applicant at his or her judgment, and their detailed meanings are explained in the relevant sections of the description herein. Furthermore, this disclosure should be understood not only by the actual terms used, but also by the meaning implied by each term.

[0040] In the fabrication of semiconductor devices (such as 3D NAND), a stepped structure is often required to ensure that the contact holes can be connected to each gate line in the core region, and an array planarization (APL) process is introduced. As the number of 3D NAND layers increases, the oxide filling the steps thickens, the polishing time for array planarization increases, and changes in the preceding layer processes lead to a series of problems such as over-polishing or under-polishing.

[0041] Figure 1 and Figure 2 This is a schematic diagram illustrating a method for fabricating a semiconductor device. (Reference) Figure 1 and Figure 2 As shown, for multilayer (e.g., 128-layer) semiconductor structures, one approach is to use a silicon nitride (SIN) hard mask as a stop layer during array planarization. However, due to differences in etch loading at locations such as the edges of the giant block region of the semiconductor structure during chemical mechanical polishing (CMP), the silicon nitride hard mask's blocking effect is poor, often causing damage to both oxide and silicon nitride. Moreover, the thickness of the silicon nitride hard mask cannot be increased indefinitely due to the limitation on the "bevel" height of the buffer oxide (BOX) layer during CMP.

[0042] Figure 3 and Figure 4 This is a schematic diagram of a semiconductor device. (Reference) Figure 3 and Figure 4 As shown, the semiconductor structure formed by this method exhibits significant over-etching at the edge of the plateau region. Furthermore, the connection windows of the contact holes in this semiconductor structure are relatively small. Consequently, during the contact hole etching step, the upper-layer steps / steps are prone to over-etching, resulting in punch-through, which fails to meet process requirements and reduces product yield.

[0043] To address the above problems, the following embodiments of this disclosure propose a method for fabricating a semiconductor device. This method increases the connection window of the contact hole and effectively avoids over-wearing at the edge of the platform area.

[0044] The method for fabricating a semiconductor device disclosed herein includes the following steps: providing a semiconductor structure, the semiconductor structure including a stacked structure of alternating first material layers and second material layers, the stacked structure including a platform region and a step region adjacent to the platform region, the top of the platform region and the step region being the second material layer; forming a third material layer covering the upper surface of the platform region and the surface of the step region; forming a fourth material layer filling the step region and covering the platform region; removing the third material layer and the fourth material layer on the platform region, and retaining the third material layer and the fourth material layer located on the platform region near the edge of the step region; performing a first planarization, the first planarization removing the protruding fourth material layer, and retaining the second material layer and the third material layer on the upper surface of the platform region.

[0045] Figure 5 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 6 to 15 This is a schematic diagram of the process steps of a semiconductor device fabrication method according to an embodiment of the present disclosure. The following is in conjunction with... Figures 5 to 15 The production method is explained.

[0046] It is understood that the following description is merely exemplary, and those skilled in the art can make various changes without departing from the spirit of this disclosure.

[0047] Step S10: Provide a semiconductor structure.

[0048] refer to Figure 7 As shown, a semiconductor structure 200 is provided. The semiconductor structure 200 includes a stacked structure consisting of alternating first material layer 110 and second material layer 120. The stacked structure includes a giant block region (GB) and a stair-step region adjacent to the giant block region. The top of the giant block region and the stair-step region is the second material layer 120. The giant block region can serve a storage function, and the stair-step region can serve an electrical connection function.

[0049] In one embodiment of this disclosure, the first material layer 110 includes a dielectric layer, and the second material layer 120 includes a dummy gate layer.

[0050] The material of the first material layer 110 can be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The material of the second material layer 120 can be, for example, silicon nitride and silicon oxynitride (SiOxNx).

[0051] The deposition methods for forming the first material layer 110 and the second material layer 120 may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, and other methods.

[0052] In one embodiment of this disclosure, after forming a multilayer stacked structure of SiOx-SiOxNx-SiOx (ONO stack), the second material layer 120 (pseudo-gate layer) can be replaced to obtain a gate layer. Replacement methods include, but are not limited to, wet etching. The replacement material can be conductive materials such as tungsten, cobalt, nickel, or titanium, or it can be polycrystalline silicon, doped silicon, or any combination thereof.

[0053] In some examples, the first material layer 110 and the second material layer 120 have different etching selectivity. For example, it can be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polycrystalline or amorphous silicon, or a combination of silicon oxide or silicon nitride and amorphous carbon, etc. For example, after forming the second material layer 120 (pseudo-gate layer) of silicon nitride or silicon oxynitride, it can be replaced with tungsten metal in subsequent process steps, but this disclosure is not limited thereto.

[0054] Continue to refer to Figure 7 As shown, in some embodiments, the semiconductor structure 200 further includes a substrate 101 located under the stacked structure.

[0055] It should be understood that the material of substrate 101 may be silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon on insulator (SOI), or germanium on insulator (GOI), etc. Substrate 101 may also include other elements or compounds, such as GaAs, InP, or SiC, etc. Substrate 101 may also be a multilayer structure, such as Si / SiGe, or include other epitaxial structures, such as silicon germanium on insulator (SGOI), etc., and this disclosure is not limited thereto.

[0056] refer to Figure 6 As shown, semiconductor structure 100 also includes a stacked structure of alternating first material layer 110 and second material layer 120, the stacked structure including a plateau region and a step region adjacent to the plateau region. Figure 7 The difference in the semiconductor structure 200 shown is that the top of the platform region and the step region of the semiconductor structure 100 is a first material layer 110.

[0057] In some embodiments, it is possible to Figure 6The semiconductor structure 100 shown is subjected to dry etching to remove the first material layer 110 at the top of its plateau region and step region, exposing the underlying second material layer 120, thereby obtaining... Figure 7 The semiconductor structure 200 shown is not limited thereto.

[0058] Step S20: A third material layer is formed covering the upper surface of the platform area and the surface of the step area.

[0059] refer to Figure 9 As shown, a third material layer 130 is formed covering the upper surface of the platform area and the surface of the step area.

[0060] For example, it is possible to Figure 7 A third material layer 130 is deposited on the upper surface of the platform region and the surface of the step region of the semiconductor structure 200 shown.

[0061] In one embodiment of this disclosure, the material of the third material layer 130 includes one or more of silicon oxynitride, aluminum oxide, and titanium nitride.

[0062] Preferably, the material of the third material layer 130 is silicon oxynitride (SiOxNy, for example, SiON).

[0063] The deposition method for forming the third material layer 130 may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, and other methods.

[0064] refer to Figure 8 and Figure 9 As shown, in one embodiment of this disclosure, the method of forming a third material layer 130 covering the upper surface of the platform region and the surface of the step region includes: forming a third material layer 130 (semiconductor structure 300) covering the upper surface of the platform region, the surface of the step region and the sidewalls, and then removing the third material layer 130 covering the sidewalls of the step region to form a semiconductor structure 400.

[0065] Preferably, a dry etching process can be used to directionally remove the third material layer 130 covering the sidewall of the step region in the semiconductor structure 300 by controlling the direction of the gas.

[0066] Step S30: A fourth material layer is formed that fills the stepped area and covers the platform area.

[0067] refer to Figure 10 As shown, a fourth material layer 140 is formed that fills the step region and covers the platform region. For example, the fourth material layer 140 can be deposited on the platform region and the step region such that the height of the fourth material layer 140 on the step region exceeds the surface of the platform region, forming a semiconductor structure 500.

[0068] In one embodiment of this disclosure, the material of the fourth material layer 140 includes silicon oxide.

[0069] For example, tetraethyl orthosilicate (TEOS) source silicon dioxide can be deposited using methods such as CVD, PECVD, or LPCVD.

[0070] Step S40: Remove the third and fourth material layers on the platform area, while retaining the third and fourth material layers located on the edge of the platform area near the step area.

[0071] refer to Figure 10 and Figure 11 As shown, the third material layer 130 and the fourth material layer 140 on the platform region of the semiconductor structure 500 are removed, while the third material layer 130 and the fourth material layer 140 located on the edge of the platform region near the step region are retained to form the semiconductor structure 600.

[0072] exist Figure 11 In one example shown, not only are the third material layer 130 and the fourth material layer 140 on the platform area near the edge of the step area retained, but also a portion of the third material layer 130 on the platform area away from the edge of the step area is retained. In other examples, only the third material layer 130 and the fourth material layer 140 on the platform area near the edge of the step area may be retained, and this disclosure is not limited thereto.

[0073] Methods for removing the third material layer 130 and the fourth material layer 140 include, but are not limited to, dry etching, which mainly utilizes reactive gases and plasma to etch the material being etched.

[0074] For example, photoresist can be coated on the upper surface of the fourth material layer 140, and then patterned using a photolithography process to form a mask pattern. Subsequently, the third material layer 130 and the fourth material layer 140 below it are etched using the mask pattern as a mask.

[0075] Step S50: Perform the first planarization. The first planarization removes the raised fourth material layer and leaves the second and third material layers on the upper surface of the platform area.

[0076] refer to Figure 12 As shown, a first planarization is performed, which removes the protruding fourth material layer 140 and leaves the second material layer 120 and the third material layer 130 on the upper surface of the platform region, forming a semiconductor structure 700.

[0077] In one embodiment of this disclosure, the first planarization simultaneously removes a portion of the third material layer 130 on the upper surface of the platform region away from the edge of the step region and a portion of the third material layer 130 on the platform region near the edge of the step region.

[0078] The first planarization is performed on the second material layer 120 and the third material layer 130 on the upper surface of the platform area, so as to retain at least a portion of the third material layer 130 on the upper surface of the platform area near the step area.

[0079] It should be understood that the primary purpose of planarization in this step is to remove the raised fourth material layer 140. During planarization, the third material layer 130 on the upper surface of the platform area away from the edge of the step area, and a portion of the second material layer 120 below it, may also be removed simultaneously. Alternatively, a portion of the third material layer 130 on the platform area near the edge of the step area may also be removed simultaneously.

[0080] In one embodiment of this disclosure, a first planarization is performed using chemical mechanical polishing, and the polishing selectivity of the fourth material layer 140 relative to the third material layer 130 is greater than 10.

[0081] Chemical mechanical polishing (CMP) is a technique that combines chemical and mechanical actions to produce a smooth surface free of scratches and contaminants.

[0082] After this step, at least a portion of the third material layer 130 near the edge of the step area on the platform area is still retained, effectively avoiding over-wearing at the edge of the platform area during the planarization process.

[0083] In one embodiment of this disclosure, after step S50, the method further includes: removing a third material layer from the upper surface of the platform area; removing a second material layer from the top of the platform area to expose a first material layer; and performing a second planarization, wherein the second planarization removes a portion of the thickness of the fourth material layer on the step area and remains on the first material layer at the top of the platform area.

[0084] refer to Figure 12 and Figure 13 As shown, the third material layer 130 on the upper surface of the platform region is removed to form a semiconductor structure 800.

[0085] In one embodiment of this disclosure, a third material layer 130 on the upper surface of the platform region can be removed by dry etching, and the etching selectivity of the third material layer 130 relative to the first material layer 110 and / or the second material layer 120 is greater than 10.

[0086] refer to Figure 13 and Figure 14As shown, the second material layer 120 at the top of the platform region is removed to expose the first material layer 110, forming a semiconductor structure 900.

[0087] For example, wet etching can be used to remove the second material layer 120 on top of the platform region to expose the first material layer 110 underneath.

[0088] After the above steps, a "bevel" with a large height difference is formed at the edge of the platform area near the step area.

[0089] refer to Figure 14 and Figure 15 As shown, a second planarization is performed, which removes part of the thickness of the fourth material layer 140 on the step region and leaves the first material layer 110 on top of the platform region to form a semiconductor structure 1000.

[0090] In one embodiment of this disclosure, the second planarization may also simultaneously remove a portion of the first material layer 110 at the top of the platform region.

[0091] When both the first material layer 110 and the fourth material layer 140 are made of silicon oxide, the polishing options for both are relatively limited. By partially over-polishing the first material layer 110 at the top of the platform region, the previously formed "bevel" can be repaired, making the upper surface of the platform region of the semiconductor structure 1000 flush with the upper surface of the fourth material layer 140 on the step region.

[0092] Figure 16 This is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure. (See reference) Figure 16 As shown, after the semiconductor structure 1000 is formed, contact holes can be connected so that the contact holes can be connected to the second material layer 120 (e.g., gate layer) of each layer of the platform region.

[0093] The semiconductor device fabrication method disclosed herein retains a third material layer 130 as a barrier layer on each step of the step region, which, together with the second material layer 120, forms a double-layer barrier effect. This effectively increases the connection window of the contact hole, avoids the phenomenon of the upper step being etched through during the contact hole etching step, and improves the product yield.

[0094] It should be noted that the phrase "used here" is incorrect. Figure 5 The flowcharts shown illustrate the steps / operations performed by the manufacturing method according to embodiments of this disclosure. It should be understood that these steps / operations are not necessarily performed precisely in sequence. Instead, various steps / operations can be processed in reverse order or simultaneously. Furthermore, other steps / operations may be added to these processes, or one or more steps / operations may be removed from these processes.

[0095] Those skilled in the art can make appropriate adjustments to the priority order of the specific operation steps of the manufacturing method according to actual needs, and this disclosure is not limited thereto.

[0096] The above embodiments of this disclosure provide a method for fabricating a semiconductor device, which increases the connection window of the contact hole and effectively avoids over-wearing at the edge of the platform area.

[0097] Another aspect of this disclosure provides a semiconductor device with high reliability.

[0098] The semiconductor device disclosed herein includes: a stacked structure consisting of alternating first and second material layers, the stacked structure including a plateau region and a step region adjacent to the plateau region, the top of the plateau region being the first material layer and the top of the step region being the second material layer; a third material layer covering the surface of the step region; and a fourth material layer filling the step region; wherein the upper surface of the plateau region is flush with the upper surface of the fourth material layer.

[0099] refer to Figure 15 As shown, the semiconductor device (e.g., semiconductor structure 1000) includes a stacked structure consisting of alternating first material layer 110 and second material layer 120. The stacked structure includes a plateau region and a step region adjacent to the plateau region. The top of the plateau region is the first material layer 110, and the top of the step region is the second material layer 120. The semiconductor device (e.g., semiconductor structure 1000) also includes a third material layer 130 covering the surface of the step region and a fourth material layer 140 filling the step region. The upper surface of the plateau region is flush with the upper surface of the fourth material layer 140.

[0100] In one embodiment of this disclosure, the semiconductor device (e.g., semiconductor structure 1000) further includes a substrate 101 located under the stacked structure.

[0101] In one embodiment of this disclosure, the first material layer 110 includes a dielectric layer, and the second material layer 120 includes a dummy gate layer.

[0102] For example, the material of the first material layer 110 may be silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The material of the second material layer 120 may be silicon nitride and silicon oxynitride (SiOxNx), for example.

[0103] In one embodiment of this disclosure, the material of the third material layer 130 includes one or more of silicon oxynitride, aluminum oxide, and titanium nitride.

[0104] In one embodiment of this disclosure, the material of the fourth material layer 140 includes silicon oxide.

[0105] In the fabrication process of the semiconductor device disclosed herein, a third material layer 130 is retained as a barrier layer on each step of the step region, which together with the second material layer 120 forms a double barrier effect. This effectively increases the connection window of the contact hole, avoids the phenomenon of the upper step being etched through during the contact hole etching step, and improves the product yield.

[0106] It should be noted that the semiconductor device of this disclosure can be used, for example... Figure 5 The semiconductor device shown is implemented using a method of fabrication, but this disclosure is not limited thereto.

[0107] Further implementation details of the semiconductor device in this embodiment can be found in [reference]. Figures 5 to 16 The described embodiments will not be elaborated upon here.

[0108] The above embodiments of this disclosure provide a semiconductor device with high reliability.

[0109] It is understood that although some inventive embodiments that are currently considered useful have been discussed in the above disclosure by way of various examples, it should be understood that such details are for illustrative purposes only, and the appended claims are not limited to the disclosed embodiments. Rather, the claims are intended to cover any combination of modifications and equivalents that conform to the substance and scope of the embodiments disclosed herein.

[0110] The basic concepts have been described above. It is clear that the above disclosure is merely illustrative and does not constitute a limitation of this disclosure. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to this disclosure by those skilled in the art. Such modifications, improvements, and corrections are suggested in this disclosure and therefore remain within the spirit and scope of the exemplary embodiments of this disclosure.

[0111] Furthermore, this disclosure uses specific terms to describe embodiments of the present disclosure. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that references to "an embodiment," "one embodiment," or "an alternative embodiment" in different locations throughout this specification do not necessarily refer to the same embodiment. Moreover, certain features, structures, or characteristics in one or more embodiments of the present disclosure can be appropriately combined.

[0112] Furthermore, unless expressly stated in the claims, the order of processing elements and sequences, the use of numbers and letters, or other names described in this disclosure are not intended to limit the order of the processes and methods of this disclosure. Although various examples have been discussed in the foregoing disclosure of some embodiments that are currently considered useful, it should be understood that such details are for illustrative purposes only, and the appended claims are not limited to the disclosed embodiments; rather, the claims are intended to cover all modifications and equivalent combinations that conform to the spirit and scope of the embodiments of this disclosure. For example, while the system components described above can be implemented by hardware devices, they can also be implemented solely by software solutions, such as installing the described system on existing servers or mobile devices.

[0113] Similarly, it should be noted that, in order to simplify the description of this disclosure and thus aid in the understanding of one or more embodiments, the foregoing description of embodiments of this disclosure sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of this disclosure requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of a single embodiment disclosed above.

[0114] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this disclosure are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0115] Although this disclosure has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are merely illustrative of this disclosure, and various equivalent changes or substitutions can be made without departing from the spirit of this disclosure. Therefore, any changes or modifications to the above embodiments within the scope of the essential spirit of this disclosure will fall within the scope of the claims of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A stacked structure, located on the substrate, is formed by alternating stacking of a first material layer and a gate layer; the stacked structure includes a plateau region and a step region. A third material layer covers the upper surface of the stepped area, and the material of the third material layer is an insulating material. The fourth material layer is located on the third material layer, covers the stepped area, and contacts the sidewall of the stepped area; At least one contact hole is located in the stepped region; the contact hole penetrates the third material layer and connects to the gate layer adjacent to the third material layer.

2. The semiconductor structure as described in claim 1, characterized in that, The contact hole also penetrates the fourth material layer.

3. The semiconductor structure as described in claim 1, characterized in that, The contact hole is filled with a conductive material; the material of the gate layer is the conductive material.

4. The semiconductor structure as described in claim 1, characterized in that, The stepped area includes: multiple steps; The multiple steps decrease sequentially from the direction closest to the platform area to the direction furthest away from the platform area.

5. The semiconductor structure as described in claim 1, characterized in that, The third material layer also covers a portion of the substrate outside the stepped region.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the third material layer is silicon oxynitride.

7. The semiconductor structure as described in claim 1, characterized in that, The third material layer is aluminum oxide.

8. The semiconductor structure as described in claim 1, characterized in that, The upper surface of the platform area is a first material layer.

9. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Provide substrate; A stacked structure is formed on the substrate, the stacked structure being formed by alternating stacking of a first material layer and a second material layer; the stacked structure includes a plateau region and a step region. A third material layer is formed covering the upper surface of the platform area, the surface of the step area, and the sidewalls of the step area; Remove the third material layer covering the sidewalls of the stepped area; A fourth material layer is formed to cover the stepped area; the fourth material layer is located on the third material layer. At least one contact hole is formed in the stepped region; the contact hole penetrates the third material layer and connects to the gate layer adjacent to the third material layer.

10. The method as described in claim 9, characterized in that, A third material layer is formed covering the upper surface of the platform area, the surface of the step area, and the sidewalls of the step area. The third material layer covering the sidewalls of the step area is then removed to form a fourth material layer covering the step area, comprising: A fourth material layer is formed that fills the stepped area and covers the platform area; At least a portion of the third material layer and at least a portion of the fourth material layer on the platform area are removed, while the third material layer and the fourth material layer located at the edge of the platform area near the step area are retained.

11. The method as described in claim 10, characterized in that, The method further includes: The first planarization is performed, thinning the fourth material layer to be flush with the third material layer retained on the surface of the platform region.

12. The method as described in claim 11, characterized in that, The method further includes: Remove the third material layer remaining on the surface of the platform area; A second planarization process is performed to remove part of the thickness of the fourth material layer on the step area, so that the surface of the fourth material layer on the step area is on the same plane as the surface of the first material layer at the top of the platform area.

13. The method as described in claim 12, characterized in that, The second planarization is also used to remove a portion of the first material layer at the top of the platform area.

14. The method as described in claim 9, characterized in that, The process of forming a contact hole in the stepped area includes: The contact hole is formed by penetrating the fourth material layer and the third material layer of the step area.

15. The method as described in claim 14, characterized in that, The method further includes: The contact hole is filled with a conductive material; wherein the conductive material is the same as the material of the gate layer.

16. The method as described in claim 9, characterized in that, The formation of the stacked structure on the substrate includes: Replace the second material layer with the gate layer.

17. The method as described in claim 16, characterized in that, The step of replacing the second material layer with the gate layer includes: Etching the second material layer; The gate layer is formed by filling the voids after the removal of the second material layer with conductive material.

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