Thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics

Abstract

A thin-film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics according to an embodiment of the present invention includes: a first substrate formed with a plurality of thin-film bulk acoustic resonators including a lower electrode, a piezoelectric layer, and an upper electrode, and a first bonding pad connected to the lower electrode or the upper electrode; and a second substrate including a plurality of vias penetrating the substrate, with a second bonding pad formed on the surface facing the first substrate at both ends of each via, and a plurality of external connection pads formed on the surface not facing the first substrate; Through the present invention, a thin-film bulk acoustic resonator chip packaging structure with improved power tolerance characteristics compared to the existing method can be provided, and at the same time, the power tolerance performance of the thin-film bulk acoustic resonator (FBAR) chip structure and packaging, as well as the requirements for packaging miniaturization, can be satisfied.

Description

Technical Field

[0001] The present invention relates to a chip packaging structure of a thin-film bulk acoustic wave resonator for improving power tolerance characteristics. In particular, it relates to a packaging of a thin-film bulk acoustic wave resonator (FBAR) with a brand-new chip structure that has more excellent power tolerance performance compared with the existing thin-film bulk acoustic wave resonator (FBAR) chip structure and packaging. Background Art

[0002] Recently, centered around small electronic devices such as smart phones, the demand for miniaturization and high-density mounting has been gradually increasing. Therefore, the surface mounting technology of electronic components such as semiconductor integrated circuits (ICs) has made great progress.

[0003] By using wafer-level packaging to replace chip-level packaging, the thickness of the packaging has been significantly reduced. In addition, a stacked substrate has been developed in printed circuit boards, and various materials, devices, and various engineering technologies have also been developed.

[0004] At the same time, along with the development of information and communication technology and the evolution of the network, the amount of information used or required by people has also shown a rapid increasing trend. Moreover, in order to implement more diverse, newer, and more advanced functions in various electronic devices, more components need to be installed inside the devices than currently. Therefore, the devices become more and more complex and the configuration of electronic components becomes more and more dense.

[0005] That is, current and future electronic devices must continuously develop and progress while satisfying two actually conflicting requirements of miniaturization and the realization of advanced functions at the same time.

[0006] The above requirements also apply to band-pass filters used in smart phones, etc. Therefore, in a gradually more complex high-frequency wireless environment such as 5G, bulk acoustic wave (BAW) filters or duplexers require higher levels of power tolerance performance and miniaturization performance.

[0007] Generally, in order to ensure the above-mentioned power tolerance performance, a structure in which a larger number of bulk acoustic wave (BAW) resonators are arranged along the length direction is adopted. In the above-mentioned case, since the size area of the resonator is enlarged, it is convenient for heat dissipation, and the overall heat resistance of the resonator can be reduced to improve the durability and reliability of power.

[0008] Figure 8 FIG. shows a type of bulk acoustic wave (BAW) element, that is, the packaging of an existing thin-film bulk acoustic wave resonator (hereinafter simply referred to as "FBAR").

[0009] Figure 8 The FBAR chip structure and package in [reference] adopt a structure in which an FBAR 20 is formed on a silicon substrate 10 and sealed using a second substrate 30 and a wafer level package (WLP).

[0010] In Figure 8 , the FBAR includes a bottom electrode, a piezoelectric layer, and a top electrode. Cavities can be formed on the lower side of the bottom electrode to more easily generate bulk acoustic waves, and a passivation layer can be formed on the upper side of the top electrode. Figure 8 The second substrate in [reference] can be a silicon substrate.

[0011] Each of the upper and lower electrodes in the above FBAR is connected to an internal electrode pad 40, and the internal electrode pad is connected to an external connection pad 60 through a via hole 50 penetrating the second substrate. The rear part of the external connection pad is connected to a signal line or a ground line. The internal electrode pad 40 may include a soldering pad for realizing wafer level package (WLP) soldering with the second substrate.

[0012] Figure 9 An existing solution for improving the power tolerance performance of a filter structure in which multiple FBARs as shown in Figure 8 are connected in series and parallel is illustrated.

[0013] Currently, in order to improve the power tolerance performance of FBARs, a method is adopted in which the number of FBARs originally connected only at one position is increased to two and configured at multiple positions as shown in Figure 9 .

[0014] However, the solution of increasing the heat dissipation area by adding FBARs as shown in Figure 9 can achieve the required power tolerance performance, but runs counter to the goal of device miniaturization.

[0015] Therefore, the present invention provides an FBAR package with a new chip structure that can meet the required power tolerance performance and the goal of composite device miniaturization.

[0016] Prior art documents

[0017] Patent documents

[0018] (Patent Document 1) Korean Patent Publication No. 10-2004-0043055 (May 22, 2004) Summary of the invention

[0019] An object of the present invention is to provide an FBAR chip structure and package with improved power tolerance performance compared to the current situation.

[0020] Another object of the present invention is to provide an FBAR chip structure and package that can simultaneously meet the requirements of power tolerance performance and package miniaturization.

[0021] Yet another object of the present invention is to provide an FBAR chip structure and package that can effectively utilize an existing thin film bulk acoustic resonator structure during the manufacturing process of a package with a new structure.

[0022] Yet another object of the present invention is to provide an FBAR chip structure and package that can directly use an existing thin film bulk acoustic resonator manufacturing process and apparatus during the manufacturing process of a package with a new structure.

[0023] The technical problems of the present invention are not limited to the technical problems mentioned above. Those of ordinary skill in the art will further clearly understand other technical problems not mentioned through the following description.

[0024] An FBAR chip structure and package with improved power tolerance performance according to an embodiment of the present invention includes: a first substrate formed with a plurality of thin film bulk acoustic resonators including a lower electrode, a piezoelectric layer, and an upper electrode, and a first bonding pad connected to the lower electrode or the upper electrode; and a second substrate including a plurality of vias penetrating the substrate, with a second bonding pad formed on the surfaces facing the first substrate at both ends of each via, and a plurality of external connection pads formed on the surface not facing the first substrate; wherein the first substrate and the second substrate are welded to each other through welding between the first bonding pad and the second bonding pad, a part of the lower electrode is connected to the first bonding pad through a piezoelectric layer via filled with a conductive material, and the plurality of vias of the second substrate include a first via connected to a signal line or a ground line through the external connection pad and a second via not connected to a signal line or a ground line.

[0025] The first via may be filled with a conductive material, and the second via may be filled with a material having a higher thermal conductivity than the first via.

[0026] The first via and the second via may be filled with the same material or different materials.

[0027] The first via may be connected to the piezoelectric layer via.

[0028] The diameters of the above-described first vias and the above-described second vias may be different from each other, and the diameter of the above-described second via may be larger than the diameter of the above-described first via.

[0029] The cross-sectional shapes of the above-described first via and the above-described second via may be different from each other.

[0030] The above-described external connection pads may be formed only on the above-described first vias.

[0031] When an external connection pad is formed on the above-described second via, the external connection pad of the above-described second via may be covered with a protective layer.

[0032] At least two or more upper electrodes of the above-described plurality of thin-film bulk acoustic resonators may be connected to each other through electrode connection portions to form a single body, and the above-described second via may be formed between the upper electrodes that are connected to each other to form a single body when viewed from a top side view.

[0033] In the above-described first substrate, a heat sink groove filled with a heat dissipation material may be formed between two or more lower electrodes that are not connected to the above-described first solder pad.

[0034] An FBAR chip structure and package with improved power tolerance performance according to another embodiment of the present invention include: a first substrate on which a plurality of thin-film bulk acoustic resonators including a lower electrode, a piezoelectric layer, and an upper electrode are formed, and a first solder pad connected to the above-described lower electrode or upper electrode; and a second substrate including a plurality of vias penetrating the substrate, second solder pads being formed on the surfaces facing the above-described first substrate at both ends of each of the above-described vias, and a plurality of external connection pads being formed on the surface not facing the above-described first substrate; wherein, the above-described first substrate and the above-described second substrate are welded to each other through welding between the above-described first solder pad and the above-described second solder pad, a part of the above-described lower electrodes is connected to the above-described first solder pad through a piezoelectric layer via filled with a conductive material, and in the above-described first substrate, a heat sink groove filled with a heat dissipation material may be formed between two or more lower electrodes that are not connected to the above-described first solder pad.

[0035] In the above-described first substrate, cavities are formed on the lower sides of the respective lower electrodes, and at least a part of the above-described heat sink groove may be formed between the cavities.

[0036] The above-described two or more lower electrodes may be connected to each other through electrode connection portions connecting between the electrodes to form a single body, and at least a part of the above-described heat sink groove may be formed on the lower side of the above-described electrode connection portion.

[0037] At least a part of the above-mentioned radiator grooves can be formed by extending further outwardly away from the above-mentioned electrode connection portion.

[0038] In the above-mentioned radiator grooves, the area of the region that separates from the electrode connection portion can be larger than the area that overlaps with the above-mentioned electrode connection portion.

[0039] The above-mentioned radiator grooves can be in a "T" shape.

[0040] The width of the head portion of the "T" shape of the above-mentioned radiator grooves can be relatively wide.

[0041] *Through the present invention, an FBAR chip structure and package with improved power tolerance performance compared to the current situation can be provided.

[0042] In addition, the present invention can simultaneously meet the power tolerance performance of the FBAR chip structure and package and the requirement for miniaturization of the package.

[0043] In addition, the present invention can effectively use the existing thin film bulk acoustic resonator structure during the manufacturing process of a package with a completely new structure.

[0044] In addition, the present invention can directly use the existing thin film bulk acoustic resonator manufacturing process and equipment during the manufacturing process of a package with a completely new structure.

[0045] The effects of the present invention are not limited to the effects mentioned above. Those of ordinary skill in the art will be able to further clearly understand other effects not mentioned through the following description. Description of the Drawings

[0046] Figure 1 An embodiment of the present invention for improving the power tolerance performance applicable to a filter structure in which multiple FBARs are connected in series and parallel is illustrated.

[0047] Figure 2 It is a scheme for improving the power tolerance performance of an FBAR chip structure and package according to the first embodiment of the present invention, showing a state in which a via hole type radiator is formed on a second substrate.

[0048] Figure 3 It is a schematic diagram illustrating the state when observing an FBAR filter package according to the first embodiment of the present invention from one side of the upper surface of the second substrate.

[0049] Figure 4 It is a scheme for improving the power tolerance performance of an FBAR chip structure and package according to the second embodiment of the present invention, showing a state in which a cavity type radiator is formed on a first substrate.

[0050] Figure 5It is a schematic diagram showing the state when observing the FBAR filter package including the cavitation type heat sink according to the second embodiment of the present invention from the side of the upper surface of the second substrate.

[0051] Figure 6 It is a top view showing the structure in the case of including two embodiments of the present invention at the same time, and a cross-sectional view when cutting along the AA' line in the above top view is shown.

[0052] Figure 7 For Figure 6 The circuit diagram corresponding to the package structure in is shown.

[0053] Figure 8 An existing film bulk acoustic resonator package is shown.

[0054] Figure 9 An existing solution for improving the power tolerance performance is shown.

[0055]

Symbol Explanation

[0056] 10, 100: The first substrate

[0057] 30, 200: The second substrate

[0058] 20, 110: Film bulk acoustic resonator (FBAR)

[0059] 40: Internal electrode pad

[0060] 50: Via hole

[0061] 60, 230: External connection pad

[0062] 111: Lower electrode

[0063] 112: Piezoelectric layer

[0064] 113: Upper electrode

[0065] 114: Cavity

[0066] 115: Electrode connection part

[0067] 120: The first welding pad

[0068] 130: Piezoelectric layer via hole

[0069] 140: Package seal dam

[0070] 150: Heat sink groove

[0071] 151: First Region

[0072] 152: Second Region

[0073] 160: Heat Dissipation Substance

[0074] 210: Via Hole

[0075] 211: First Via Hole

[0076] 212: Second Via Hole (Via Hole Type Heat Sink)

[0077] 220: Second Solder Pad

[0078] 240: Protective Layer Detailed Embodiment

[0079] Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The features, advantages, and implementation means of the present invention will be further clarified through the subsequent embodiments described in detail with reference to the drawings. However, the embodiments of the present invention described below are exemplary, and the scope of the present invention is not limited by the described embodiments. In addition, the components in each embodiment can be implemented in various different combinations within or between the embodiments without explicit mention or conflict with each other.

[0080] In addition, when it is described that a certain part "includes" a certain component, it only means that the corresponding component must be included regardless of other components, rather than indicating the impossibility of adding other components.

[0081] In addition, throughout the specification, when it is described that a certain part is "connected" to another part, it includes not only the case of "direct connection" but also the cases of "indirect connection" or "electrical connection" with other components or elements interposed therebetween.

[0082] In addition, throughout the specification, when it is described that each layer (film), region, pattern, or structure is formed "above / on the upper side" or "below / on the lower side" of a substrate, each layer (film), region, pad, or pattern, it includes the case of being formed directly or with other layers interposed therebetween. The upper side / on the upper side or the lower side / on the lower side of each layer will be described with reference to the drawings.

[0083] In addition, expressions such as "first, second" are only used to distinguish multiple components and are not used to limit the order or other characteristics between the components.

[0084] In addition, the sequence diagrams illustrated in the drawings are only exemplary sequences for obtaining the best results in the process of implementing the present invention, and other steps can be added or some steps can be deleted.

[0085] Figure 1 The power tolerance performance improvement solution of the embodiment of the present invention applicable to a filter structure in which multiple FBARs are connected in series and parallel is illustrated.

[0086] Refer to Figure 1 , for the power tolerance performance improvement solution of the FBAR filter applicable to the present invention, it is not necessary to increase the filter area by increasing the number of resonators. Instead, a heat sink can be formed between each resonator to more effectively discharge the internal heat while maintaining the resonator arrangement structure in the existing FBAR filter.

[0087] The heat sinks applicable to the present invention include two types, which will be described in sequence below.

[0088] Figure 2 It is the FBAR chip structure and package power tolerance performance improvement solution of the first embodiment of the present invention, in a state where a via-type heat sink is formed on the second substrate.

[0089] Refer to Figure 2 , the FBAR chip structure and package applicable to the present invention include a first substrate 100 and a second substrate 200. The above-mentioned first substrate and second substrate can be silicon substrates.

[0090] On the above-mentioned first substrate 100, a plurality of FBARs respectively including a lower electrode 111, a piezoelectric layer 112, and an upper electrode 113 are formed, and a first solder pad 120 for wafer-level packaging (WLP) soldering of the above-mentioned first substrate and second substrate is also formed.

[0091] At least a part of the above-mentioned plurality of upper electrodes 113 can be connected to the above-mentioned first solder pad, and at least a part of the above-mentioned plurality of lower electrodes 111 can be connected to the above-mentioned first solder pad 120 through a piezoelectric layer via hole 130 filled with a conductive substance.

[0092] Each of the above-mentioned FBARs can further include a cavity 114 formed on the lower side of the lower electrode 111.

[0093] The above-mentioned second substrate 200 can include a plurality of vias 210 formed through the substrate. The above-mentioned vias include a first via 211 connected to a signal line or a ground line, and a second via 212 not connected to a signal line or a ground line.

[0094] The above-mentioned first vias 211 and the above-mentioned second vias 212 may be through silicon vias (TSVs).

[0095] At one end of both ends of the via penetrating the second substrate facing the first substrate, a second solder pad 220 is formed.

[0096] The above-mentioned second solder pad 220 is soldered to the first solder pad 120 of the first substrate.

[0097] At the other end not facing the first substrate including the via, an external connection pad 230 for connecting to a signal line or a ground line is formed.

[0098] The above-mentioned external connection pad 230 may be formed on all vias or only on the first vias 211. Parts other than the external connection pad 230 formed in the first vias 211 may be covered with a protective layer 240, and the above-mentioned protective layer 240 may be a solder resist (SR).

[0099] An encapsulation sealing dam 140 for sealing the encapsulation on the outside may be formed between the above-mentioned first substrate 100 and the second substrate 200, and the above-mentioned encapsulation sealing dam 140 may also be soldered to the above-mentioned first solder pad 120 through the second solder pad 220.

[0100] In the structure as described above, an external radio frequency (RF) signal can be input to the electrode of the FBAR through a signal line connected to the above-mentioned external connection pad 230 to generate a bulk acoustic wave with a specific resonance frequency, and the above-mentioned bulk acoustic wave can be transmitted through multiple FBARs and output to the outside through the external connection pad 230 connected to the output side.

[0101] The above-mentioned FBAR filter package structure according to an embodiment of the present invention is different from the existing method in that a second via 212 that is not currently available is additionally formed.

[0102] The power tolerance performance improvement solution in the FBAR filter package structure according to an embodiment of the present invention is to improve the power tolerance performance of the FBAR chip structure and the package by allowing the heat generated between the resonators of the first substrate to be easily discharged to the outside through the above-mentioned second via 212.

[0103] The above-mentioned second via 212 is additionally formed in the present invention, but there is no need to add a new process for forming the second via.

[0104] That is, since it is currently necessary to form the first vias for implementing signal input / output, which is not related to the present invention, it is only necessary to form the second vias applicable to the present invention at specific positions of the package simultaneously during the process of forming the above-mentioned first vias.

[0105] The above-mentioned second vias only serve a heat dissipation function and do not participate in signal input / output.

[0106] Figure 3 It is a schematic diagram showing the state when observing the FBAR filter package of the first embodiment applicable to the present invention from the upper side of the second substrate.

[0107] Refer to Figure 3 , the second vias (via-type heat sinks) applicable to the present invention are located at the intermediate positions where the upper electrodes of multiple resonators are interconnected through the electrode connection portions 115. The above-mentioned electrode connection portions 115 can be integrally formed with the electrodes using the same material as the electrodes during the electrode formation process for interconnecting multiple electrodes, and can interconnect the upper electrodes or lower electrodes located on the same layer.

[0108] The shape of the above-mentioned second vias can be formed in various different ways according to the configuration or requirements of the resonators. In Figure 3 , the second vias 212 with a rectangular or circular cross-sectional shape are illustrated.

[0109] In addition, the above-mentioned second vias 212 can be formed to be equal to or smaller than the size of the first vias 211. However, when formed with a diameter larger than that of the first vias 211, the heat dissipation efficiency can be further improved.

[0110] The via-type heat sinks applicable to the present invention can be formed between multiple FBARs. In the structure as shown in Figure 3 , they can be formed between three mutually adjacent resonators, so that the heat generated in the three electrodes can be quickly released to the outside through the central second vias (via-type heat sinks).

[0111] In Figure 3 , the case where the via-type heat sinks applicable to the present invention are formed between three upper electrodes interconnected through the electrode connection portions 115 is illustrated. However, they can also be formed between the lower electrodes interconnected through the electrode connection portions 115 (for example, between three lower electrodes interconnected at the central portion of Figure 3 ). In the above-mentioned case, the via-type heat sinks can be connected to the lower electrodes through the piezoelectric layer vias 130 of the first substrate.

[0112] As the filling material for the second via hole described above, one of Cu (copper), Mo (molybdenum), Al (aluminum), Al_Cu (aluminum-copper alloy), Au (gold), and W (tungsten) can be used, or the second via hole can be filled with a material having better thermal conductivity than the first via hole. However, to improve the engineering efficiency, the same material as the filling material for the first via hole can be used.

[0113] Figure 4 It is a FBAR chip structure and a power tolerance performance improvement solution applicable to the second embodiment of the present invention, in a state where a cavity-type heat sink is formed on the first substrate.

[0114] Refer to Figure 4 , the heat sink applicable to the second embodiment of the present invention adopts a structure in which a heat dissipation material 160 is filled in a cavity-type heat sink groove 150.

[0115] The heat sink groove 150 can be additionally formed between a plurality of cavities 114 when forming the cavity 114 on the lower side of the lower electrode in an existing FBAR process.

[0116] Since it is formed together in the cavity 114 process and does not require an additional independent process, although it is a FBAR package with a completely new chip structure, it will not cause any problem of reduced engineering efficiency.

[0117] By filling the heat sink groove 150 with a heat dissipation material having high thermal conductivity, its heat dissipation performance can be improved.

[0118] As the heat dissipation material filled in the heat sink groove 150, one of Cu (copper), Mo (molybdenum), Al (aluminum), Al_Cu (aluminum-copper alloy), Au (gold), and W (tungsten) can be used, or the heat sink groove 150 can be filled with a material having better thermal conductivity than the lower electrode described above. However, to improve the engineering efficiency, the same material as the lower electrode described above can be used for filling.

[0119] Figure 5 It is a schematic diagram showing the state when observing a FBAR filter package including a cavity-type heat sink applicable to the second embodiment of the present invention from one side of the upper surface of the second substrate.

[0120] Refer to Figure 5 , below the electrode connection portion where three adjacent lower electrodes in the second substrate are integrally connected, a T-shaped heat sink groove 150 filled with a heat dissipation material is formed.

[0121] The above heat sink groove 150 is the lower part of a T-shape, including a first region 151 where a part of the region overlaps with the electrode connection part of the lower electrode and a second region 152 which is the head part of the T-shape.

[0122] A part of the above heat sink groove 150 overlaps with the above electrode connection part, while the remaining part of the heat sink groove 150 is formed by extending outwardly away from the above electrode connection part, and the area of the non-overlapping region extending outwardly can be larger than the area of the region overlapping with the above electrode connection part.

[0123] The size or shape of the above heat sink groove 150 can also be formed in various different ways according to the configuration of the resonator or the allowable size of the package. However, as Figure 5 shown, when the head part of the T-shape, i.e., the second region 152, is formed with a larger width, its heat dissipation efficiency can be further improved.

[0124] In addition, Figure 5 illustrates the case where the heat sink groove is formed in a "T" shape, but the above form can also be formed in a "┓" shape or a "┏" shape (hereinafter simply referred to as a semi-"T" shape) by removing one side head part of the "T".

[0125] In addition, the cavitation type heat sink applying the second embodiment of the present invention can be formed together with the via hole type heat sink applying the first embodiment described above, so as to function as a composite heat sink.

[0126] Figure 6 is a top side view illustrating the structure of the case including two embodiments of the present invention as described above, and also illustrates a cross-sectional view when cutting along the AA' line on the above top side view.

[0127] In Figure 6 the cross-sectional view illustrated on the lower side, which is the same as the case where the FBAR package is actually mounted on the main substrate, the positions of the first substrate and the second substrate are reversed up and down.

[0128] Figure 7 For Figure 6 the circuit diagram corresponding to the package structure in is illustrated.

[0129] As Figure 6 and Figure 7 shown, the package structure including two types of heat sink embodiments of the present invention can exhibit better heat dissipation performance compared with the case including only one type of heat sink.

[0130] As described above, through the FBAR chip structure and package equipped with the heat sink applicable to the present invention, various different heat sinks can be directly formed by using the existing engineering without adopting the existing method of increasing the number of FBARs, thereby improving the power tolerance performance of the FBAR chip structure and package.

[0131] Although the present invention has been described above, those with ordinary knowledge in the technical field to which the present invention pertains should understand that the present invention can be implemented in other different forms while maintaining its technical idea and essential features.

[0132] The scope of the claims of the present invention can be basically defined by the claims, but all constitutions directly derived from the matters recorded in the claims and all changes or deformation forms derived from equivalent constitutions should also be interpreted as being included in the scope of the claims of the present invention.

Claims

1. A chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics, characterized in that, it includes: a first substrate, on which a plurality of thin-film bulk acoustic resonators including a lower electrode, a piezoelectric layer, and an upper electrode are formed, and a first bonding pad connected to the lower electrode or the upper electrode; and, a second substrate, including a plurality of vias penetrating the substrate, second bonding pads are formed on the surfaces facing the first substrate at both ends of each via, and a plurality of external connection pads are formed on the surface not facing the first substrate; wherein, the first substrate and the second substrate are welded to each other by welding between the first bonding pad and the second bonding pad, at least a part of the lower electrodes are connected to the first bonding pad through via holes of the piezoelectric layer filled with a conductive material, the plurality of vias of the second substrate include a first via connected to a signal line or a ground line through the external connection pad and a second via not connected to a signal line or a ground line; in the first substrate, cavities are formed on the lower sides of the respective lower electrodes, and at least a part of heat sink grooves are formed between the cavities.

2. The chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics according to claim 1, characterized in that: the first via is filled with a conductive material, and the second via is filled with a material having a higher thermal conductivity than the first via.

3. The chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics according to claim 2, characterized in that: the first via and the second via are filled with the same material.

4. The chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics according to claim 2, characterized in that: the first via and the second via are filled with different materials.

5. The chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics according to claim 1, characterized in that: the first via is connected to the via hole of the piezoelectric layer.

6. The chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics according to claim 1, characterized in that: the diameters of the first via and the second via are different from each other.

7. The chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics according to claim 6, characterized in that: the diameter of the second via is larger than the diameter of the first via.

8. The chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics according to claim 1, characterized in that: the cross-sectional shapes of the first via and the second via are different from each other.

9. The chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics according to claim 1, characterized in that: the first via and the second via are through-silicon vias.

10. The chip packaging structure of a thin-film bulk acoustic resonator for improving power tolerance characteristics according to claim 1, characterized in that: the external connection pads are formed only on the first via.

11. The thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics according to claim 1, characterized in that: When forming an external connection pad on the second via hole, the external connection pad of the second via hole is covered by a protective layer.

12. The thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics according to claim 1, characterized in that: At least two or more upper electrodes or lower electrodes in the plurality of thin film bulk acoustic resonators are connected to each other through an electrode connection portion to form an integral body, and the second via hole can be formed between the upper electrode or the lower electrode formed as an integral body through mutual connection when viewed from a top side view.

13. The thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics according to claim 1, characterized in that: In the first substrate, a radiator groove filled with a heat dissipation material is formed between two or more lower electrodes not connected to the first welding pad.

14. A thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics, characterized in that, including: A first substrate, on which a plurality of thin film bulk acoustic resonators including a lower electrode, a piezoelectric layer, and an upper electrode are formed, and a first welding pad connected to the lower electrode or the upper electrode; and, A second substrate, including a plurality of via holes penetrating the substrate, second welding pads are formed on the surfaces facing the first substrate at both ends of each via hole, and a plurality of external connection pads are formed on the surface not facing the first substrate; wherein, the first substrate and the second substrate are welded to each other through welding between the first welding pad and the second welding pad, A part of the lower electrodes is connected to the first welding pad through a piezoelectric layer via hole filled with a conductive material, In the first substrate, a radiator groove filled with a heat dissipation material is formed between two or more lower electrodes not connected to the first welding pad; In the first substrate, air cavities are formed on the lower sides of the respective lower electrodes, and at least a part of the radiator groove is formed between the air cavities.

15. The thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics according to claim 14, characterized in that: The two or more lower electrodes can be connected to each other through an electrode connection portion connecting between the electrodes to form an integral body, and at least a part of the radiator groove is formed on the lower side of the electrode connection portion.

16. The thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics according to claim 15, characterized in that: At least a part of the radiator groove extends further outward away from the electrode connection portion.

17. The thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics according to claim 16, characterized in that: In the radiator groove, the area of the region separated from the electrode connection portion is larger than the area overlapping with the electrode connection portion.

18. The thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics according to claim 16, characterized in that: the above heat sink groove is in the shape of a "T" or a shape obtained by removing one side head of the "T" shape, that is, a semi-"T" shape.

19. The thin film bulk acoustic resonator chip packaging structure for improving power tolerance characteristics according to claim 18, characterized in that: the width of the head part of the "T" shape or semi-"T" shape of the above heat sink groove is relatively wide.

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