Semiconductor package, electronic device, and method of manufacturing semiconductor package

Abstract

A semiconductor chip (30), a heat dissipation member (20) on which the semiconductor chip (30) is mounted, and a sealing member (60) that seals the semiconductor chip (30) are provided. The sealing member (60) is made of a liquid crystal polymer.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2019-128693, filed on July 10, 2019, and Japanese Patent Application No. 2020-113132, filed on June 30, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to a semiconductor package for sealing semiconductor chips with a sealing component, an electronic device, and a method for manufacturing a semiconductor package. Background Technology

[0004] Previously, semiconductor packages in which semiconductor chips are sealed with sealing components have been proposed (see, for example, Patent Document 1). Specifically, in such semiconductor packages, the semiconductor chip is sealed with a sealing component made of glass epoxy resin or the like.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: U.S. Patent Application Publication No. 2016 / 0240471 Summary of the Invention

[0008] However, when the aforementioned semiconductor package is used in vehicles, the inventors have confirmed that cracks may be introduced into the sealing components, leading to damage. In other words, as a component for automotive applications, the aforementioned semiconductor package may have low durability.

[0009] The purpose of this invention is to provide a semiconductor package, an electronic device, and a method for manufacturing a semiconductor package that can suppress damage.

[0010] According to one technical solution of the present invention, a semiconductor package includes a semiconductor chip, a heat dissipation component carrying the semiconductor chip, and a sealing component for sealing the semiconductor chip, wherein the sealing component is made of a liquid crystal polymer.

[0011] Therefore, the sealing component is made of a liquid crystal polymer, which is a material with higher strength and greater flexibility compared to glass epoxy resin. This allows for the suppression of cracks introduced into the sealing component, thus preventing damage to the semiconductor package.

[0012] Furthermore, according to another technical solution of the present invention, the electronic device includes a semiconductor package, a cooler connected to a heat dissipation component in the semiconductor package, and a mounted component electrically connected to a pad of the semiconductor package.

[0013] This allows for the use of semiconductor packaging to construct electronic devices. Furthermore, by configuring a cooler connected to the heat dissipation components, heat dissipation can be further improved.

[0014] Furthermore, according to another technical solution of the present invention, the semiconductor packaging manufacturing method includes the following steps: preparing a substrate in which a plurality of portions constituting heat dissipation components are divided by dicing lines; preparing a semiconductor chip; placing the semiconductor chip on the portions constituting heat dissipation components of the substrate via bonding members; placing a sealing component for housing the semiconductor chip on the substrate; applying pressure and heating in the stacking direction of the substrate and the semiconductor chip, thereby making the sealing component a sealing component that seals the portions of the semiconductor chip that are different from those bonded to the bonding members and bonds to the heat dissipation components; dividing along the dicing lines; and using a component made of liquid crystal polymer as the sealing component.

[0015] This led to the creation of semiconductor packages that suppressed the introduction of cracks in the sealed components.

[0016] In addition, the parenthesized markings assigned to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent elements described in the embodiments described later. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of the semiconductor package according to the first embodiment.

[0018] Figure 2 yes Figure 1 The image shows a cross-sectional view of a semiconductor chip.

[0019] Figure 3 yes Figure 1 The diagram shows a plan view of a semiconductor chip.

[0020] Figure 4A It is Figure 1 The diagram shows a plan view of the heat dissipation component of the semiconductor package as seen from one side of the heat dissipation component.

[0021] Figure 4B It is Figure 1 The diagram shows a plan view of the semiconductor chip and side sealing components of the semiconductor package, viewed from one side of the heat dissipation component.

[0022] Figure 4C It is Figure 1 The diagram shows a plan view of the first sealing component of the semiconductor package as seen from one side of the heat dissipation component.

[0023] Figure 4D It is Figure 1The diagram shows a plan view of the first and second sealing components of the semiconductor package as viewed from one side of the heat dissipation component.

[0024] Figure 5A It means Figure 1 The diagram shows a cross-sectional view of the manufacturing process of a semiconductor package.

[0025] Figure 5B It means to continue Figure 5A A cross-sectional view of the manufacturing process of the conductor package.

[0026] Figure 5C It means to continue Figure 5B A cross-sectional view of the manufacturing process of the conductor package.

[0027] Figure 5D It means to continue Figure 5C A cross-sectional view of the manufacturing process of the conductor package.

[0028] Figure 5E It means to continue Figure 5D A cross-sectional view of the manufacturing process of the conductor package.

[0029] Figure 5F It means to continue Figure 5E A cross-sectional view of the manufacturing process of the conductor package.

[0030] Figure 5G It means to continue Figure 5F A cross-sectional view of the manufacturing process of the conductor package.

[0031] Figure 6 It is a planar diagram showing the components of the substrate.

[0032] Figure 7 This is a cross-sectional view of the semiconductor package according to the second embodiment.

[0033] Figure 8A This is a cross-sectional view showing the manufacturing process of the semiconductor package according to the second embodiment.

[0034] Figure 8B This is a cross-sectional view showing the manufacturing process of the semiconductor package according to the second embodiment.

[0035] Figure 9 This is a cross-sectional view of the semiconductor package according to the third embodiment.

[0036] Figure 10A This is a plan view of the heat dissipation component of the semiconductor package according to the fourth embodiment, viewed from one side of the heat dissipation component.

[0037] Figure 10B This is a plan view of the semiconductor chip and side sealing component of the semiconductor package according to the fourth embodiment, viewed from one side of the heat dissipation component.

[0038] Figure 10C This is a plan view of the first sealing member of the semiconductor package according to the fourth embodiment, viewed from one side of the heat dissipation member.

[0039] Figure 11 This is a schematic diagram showing the relationship between the interconnect vias and the semiconductor chip in the semiconductor package of the fourth embodiment.

[0040] Figure 12A This is a plan view of the heat dissipation component of the semiconductor package according to the fifth embodiment, viewed from one side of the heat dissipation component.

[0041] Figure 12B This is a plan view of the semiconductor chip and side sealing component of the semiconductor package according to the fifth embodiment, viewed from one side of the heat dissipation component.

[0042] Figure 12C This is a plan view of the first sealing member of the fifth embodiment as seen from one side of the heat dissipation member.

[0043] Figure 13 This is a cross-sectional view of the semiconductor package according to the sixth embodiment.

[0044] Figure 14 This is a cross-sectional view of the semiconductor package according to the seventh embodiment.

[0045] Figure 15 It means to Figure 14 The diagram shows a cross-sectional view of a semiconductor package mounted on a printed circuit board.

[0046] Figure 16 This is a cross-sectional view of the semiconductor package according to the eighth embodiment.

[0047] Figure 17 This is a cross-sectional view of the semiconductor package according to the ninth embodiment.

[0048] Figure 18 This is a cross-sectional view of the semiconductor package according to the tenth embodiment.

[0049] Figure 19 This is a cross-sectional view of the semiconductor package according to the 11th embodiment.

[0050] Figure 20 yes Figure 19 A plan view of the portion of the lower plate-shaped component located below the semiconductor package.

[0051] Figure 21 This is a cross-sectional view of the semiconductor package according to the 12th embodiment.

[0052] Figure 22 yes Figure 21A plan view of the portion of the lower plate-shaped component located below the semiconductor package.

[0053] Figure 23 This is a cross-sectional view of the semiconductor package according to the 13th embodiment.

[0054] Figure 24 This is a cross-sectional view of a semiconductor package of a modified example of the 13th embodiment.

[0055] Figure 25 This is a cross-sectional view of the semiconductor package according to the 14th embodiment.

[0056] Figure 26 This is a cross-sectional view of the semiconductor package according to the 15th embodiment.

[0057] Figure 27 This is a cross-sectional view of the semiconductor package according to the 16th embodiment.

[0058] Figure 28 This is a cross-sectional view of the semiconductor package according to the 17th embodiment.

[0059] Figure 29 This is a cross-sectional view of the semiconductor package according to the 18th embodiment.

[0060] Figure 30 This is a cross-sectional view of the semiconductor package according to the 19th embodiment.

[0061] Figure 31 This is a cross-sectional view of the semiconductor package according to the 20th embodiment.

[0062] Figure 32 This is a cross-sectional view of the semiconductor package according to the 21st embodiment.

[0063] Figure 33 This is a plan view of the semiconductor package according to the 22nd embodiment.

[0064] Figure 34 This is a plan view of the semiconductor package according to the 23rd embodiment.

[0065] Figure 35 This is a plan view of the semiconductor package according to the 24th embodiment.

[0066] Figure 36 This is a plan view of the semiconductor package according to the 24th embodiment.

[0067] Figure 37 This is a cross-sectional view of the semiconductor package according to the 25th embodiment.

[0068] Figure 38 This is a cross-sectional view of the semiconductor package according to the 26th embodiment.

[0069] Figure 39This is a cross-sectional view of the semiconductor package according to the 27th embodiment.

[0070] Figure 40A This is a cross-sectional view showing the manufacturing process of the semiconductor package according to the 27th embodiment.

[0071] Figure 40B It means to continue Figure 40A A cross-sectional view of the manufacturing process of semiconductor packaging.

[0072] Figure 41 This is a diagram used to illustrate the manufacturing method of the first embodiment.

[0073] Figure 42 This is a plan view of the substrate constituting the semiconductor package manufacturing process according to the 28th embodiment.

[0074] Figure 43 This is a cross-sectional view showing the manufacturing process of the semiconductor package according to the 29th embodiment.

[0075] Figure 44A This is a schematic diagram illustrating the manufacturing process of the plate-shaped component in the 30th embodiment.

[0076] Figure 44B It means to continue Figure 44A A schematic diagram of the manufacturing process of the plate-shaped component.

[0077] Figure 44C It means to continue Figure 44B A schematic diagram of the manufacturing process of the plate-shaped component.

[0078] Figure 45A This is a diagram showing the internal state of the LCP membrane components before heat treatment.

[0079] Figure 45B This is a diagram showing the internal state of the LCP membrane components before heat treatment.

[0080] Figure 46 This is a cross-sectional view showing the electronic device according to the 31st embodiment.

[0081] Figure 47 This is a cross-sectional view showing the electronic device according to the 32nd embodiment.

[0082] Figure 48 This is a cross-sectional view showing the electronic device according to the 33rd embodiment.

[0083] Figure 49 This is a plan view of the first sealing member of a semiconductor package in other embodiments, viewed from one side of the heat dissipation member.

[0084] Figure 50This is a cross-sectional view of a semiconductor package according to other embodiments.

[0085] Figure 51 This is a cross-sectional view of a semiconductor package according to other embodiments.

[0086] Figure 52 This is a cross-sectional view of a semiconductor package according to other embodiments.

[0087] Figure 53 This is a cross-sectional view of a semiconductor package according to other embodiments. Detailed Implementation

[0088] Hereinafter, embodiments of the present invention will be described based on the accompanying drawings. Furthermore, in each of the following embodiments, the same or equivalent parts will be given the same reference numerals for description.

[0089] (First Embodiment)

[0090] Reference Figures 1 to 4D The structure of the semiconductor package 10 according to the first embodiment will be described. Furthermore, the semiconductor package 10 of this embodiment is suitable for use in vehicles.

[0091] like Figures 1 to 4D As shown, the semiconductor package 10 includes a heat dissipation component 20, a semiconductor chip 30, a sealing component 60, etc.

[0092] The heat dissipation component 20 has an insulating substrate 21 made of silicon nitride (SiN) or aluminum nitride (ALN). Furthermore, a metal film 22 is formed on one side 21a of the insulating substrate 21, and another metal film 23 is formed on the other side 21b. In this embodiment, both the metal film 22 and the metal film 23 are made of copper and have a thickness of approximately 10 to 100 μm. Moreover, the metal film 22 and the metal film 23 have the same planar shape and are symmetrically arranged sandwiching the insulating substrate 21.

[0093] like Figure 2 and Figure 3 As shown, in this embodiment, the semiconductor chip 30 is formed using a high electron mobility transistor utilizing a two-dimensional electron gas (i.e., 2DEG). Furthermore, Figure 2 Equivalent to along Figure 3 The cross section of line II-II in the middle.

[0094] Specifically, the semiconductor chip 30 has a support substrate 31 made of silicon or silicon carbide (hereinafter referred to as SiC), and a buffer layer 32 and a semiconductor layer 33 are sequentially stacked on the support substrate 31. The semiconductor chip 30 has a generally rectangular shape. In addition, the semiconductor layer 33 is composed of epitaxial layers such as gallium nitride (GaN) layer and aluminum gallium nitride (AlGaN) layer, and a two-dimensional electron gas is generated inside it.

[0095] A drain electrode 34 and a source electrode 35 are formed on the surface of the semiconductor layer 33, separated from each other. In this embodiment, the drain electrode 34 and the source electrode 35 are each formed in a comb-like shape and the comb teeth mesh with each other. In addition, in this embodiment, the drain electrode 34 corresponds to the first electrode and the source electrode 35 corresponds to the second electrode.

[0096] Furthermore, an insulating film 36 is formed on the surface of the semiconductor layer 33 in the portion sandwiched between the drain electrode 34 and the source electrode 35. A gate wiring 37 is formed on the insulating film 36 at a location away from the drain electrode 34 and the source electrode 35. This gate wiring 37 appropriately bypasses the portion sandwiched between the source electrode 35 and the drain electrode 34 and connects to a gate electrode 38 disposed at the outer edge of the surface of the semiconductor layer 33. The drain electrode 34, the source electrode 35, and the gate electrode 38 are made of copper, for example, but are not particularly limited thereto. The gate wiring 37 is made of metals such as aluminum, platinum, or copper, or a polymer semiconductor doped with impurities, for example.

[0097] Furthermore, a protective film 39 is formed on the surface of the semiconductor layer 33 in such a way that the drain electrode 34, the source electrode 35, and the gate electrode 38 are exposed and the gate wiring 37 is covered.

[0098] Another electrode 40 is formed on the side of the support substrate 31 opposite to the semiconductor layer 33. This other electrode 40 is electrically connected to the source electrode 35, as will be described later. Thus, the source electrode 35 and the support substrate 31 are electrically connected via the other electrode 40, and current collapse is suppressed.

[0099] Such a semiconductor chip 30 controls the on / off state of the current flowing between the drain electrode 34 and the source electrode 35 via a two-dimensional electron gas by controlling the gate voltage applied to the gate wiring 37. That is, the semiconductor chip 30 of this embodiment forms a horizontal semiconductor element.

[0100] The above describes the structure of the semiconductor chip 30 according to this embodiment. By adopting the above structure, the semiconductor chip 30 is generally rectangular in shape, having one side where an active electrode 35 is formed, another side where another electrode 40 is formed, and a side connecting the two sides.

[0101] Furthermore, semiconductor chips 30 such Figure 1 As shown, the other electrode 40 is disposed on a metal film 22 formed on the heat dissipation component 20 via a bonding member 50, so that the other electrode 40 is opposite to the heat dissipation component 20. The bonding member 50 is made of a conductive material. In this embodiment, the bonding member 50 is made of a sintered body with silver-tin (AgSn) as the main component. Therefore, the other electrode 40 is electrically connected to the metal film 22 via the bonding member 50. In addition, the bonding member 50 is constructed by incorporating copper powder or the like, which has a higher thermal conductivity than silver-tin, thereby further increasing the thermal conductivity.

[0102] Furthermore, in this embodiment, in the stacking direction (hereinafter also referred to as the stacking direction) of the heat dissipation member 20 and the semiconductor chip 30, the bonding member 50 is configured to protrude beyond the semiconductor chip 30. In other words, in the stacking direction, the bonding member 50 is configured such that the semiconductor chip 30 is located within the bonding member 50. Therefore, compared to the case where the semiconductor chip 30 protrudes beyond the bonding member 50 in the stacking direction, stress concentration at the end of the bonding surface between the semiconductor chip 30 and the bonding member 50 can be suppressed. Thus, crack formation at the bonding surface between the semiconductor chip 30 and the bonding member 50 can be suppressed.

[0103] A sealing member 60 is disposed on the heat dissipation member 20 to seal a portion of the semiconductor chip 30 that differs from the portion bonded to the bonding member 50, and is bonded to the heat dissipation member 20. Specifically, the sealing member 60 is disposed on the heat dissipation member 20 to seal one side and the side surface of the semiconductor chip 30. The sealing member 60 has a side sealing member 70 that seals the side surface of the semiconductor chip 30 and a side sealing member 80 that seals one side of the semiconductor chip 30, both made of liquid crystal polymer (hereinafter also referred to as LCP). Furthermore, LCP is a material with higher strength and greater flexibility compared to glass epoxy resin. That is, LCP is a material that is less prone to cracking compared to glass epoxy resin.

[0104] In this embodiment, the side sealing component 70 is an injection-molded article formed by injection molding and is generally rectangular. Furthermore, the side sealing component 70 is disposed on the heat dissipation component 20 to seal the sides of the semiconductor chip 30 and to engage with the heat dissipation component 20. Specifically, the side sealing component 70 is as follows... Figure 1 and Figure 4B As shown, a first through-hole 71 is formed extending along the stacking direction, so that a semiconductor chip 30 and a bonding member 50 are disposed within the first through-hole 71. In addition, the first through-hole 71 is formed such that approximately the center portion of one side of the metal film 22 is exposed.

[0105] Furthermore, a second through hole 72 is formed in the side sealing member 70 such that the outer edge of one side of the metal film 22 is exposed, and a lower connecting through hole 73 connected to one side of the metal film 22 is disposed thereon. This lower connecting through hole 73 is composed of a sintered body mainly composed of silver and tin, and is also connected to the upper connecting through hole 97 described later. In addition, the lower connecting through hole 73 is formed by incorporating copper powder, which has a higher thermal conductivity than silver and tin, thereby further increasing the thermal conductivity. Furthermore, in Figure 4A In the diagram, the lower connection through-hole 73, which connects to one side of the metal film 22, is shown with a dashed line. Furthermore, in the same diagram described later, the lower connection through-hole 73, which connects to one side of the metal film 22, is also shown with a dashed line. In this embodiment, the lower connection through-hole 73 is configured as a cylinder.

[0106] One sealing component 80 such Figure 1 and Figure 4C As shown, a first sealing member 90 and a second sealing member 100, which are film-like layers, are stacked together. The first sealing member 90 is composed of an LCP film having one side 90a and the other side 90b. Furthermore, the first sealing member 90 has multiple patterns 91 to 93 made of copper foil or the like formed on one side 90a, and through holes 94 and 96 are formed so that each pattern 91 to 93 is exposed from the other side 90b. Upper connecting through holes 95 and 97 are disposed in the through holes 94 and 96. Additionally, the upper connecting through holes 95 and 97 are composed of a sintered body with silver and tin as the main components. Furthermore, the upper connecting through hole 97 is formed by incorporating copper powder or the like, which has a higher thermal conductivity than silver and tin, thereby further increasing the thermal conductivity.

[0107] Specifically, on one side 90a of the first sealing member 90, a drain pattern 91 with a shape corresponding to the drain electrode 34 is formed opposite to the drain electrode 34 of the semiconductor chip 30. On the same side 90a of the first sealing member 90, a source pattern 92 with a shape corresponding to the source electrode 35 is formed opposite to the source electrode 35 of the semiconductor chip 30. On the same side 90a of the first sealing member 90, a gate pattern 93 with a shape corresponding to the gate electrode 38 is formed opposite to the gate electrode 38 of the semiconductor chip 30. In this embodiment, the drain pattern 91 corresponds to the first pattern, and the source pattern 92 corresponds to the second pattern.

[0108] Through-holes 94 are formed between the drain pattern 91 and the drain electrode 34, between the source pattern 92 and the source electrode 35, and between the gate pattern 93 and the gate electrode 38. Furthermore, an upper connection via 95 is disposed in each through-hole 94. Thus, the source pattern 92 is electrically connected to the source electrode, the drain pattern 91 is electrically connected to the drain electrode 34, and the gate pattern 93 is electrically connected to the gate electrode 38 via the upper connection via 95.

[0109] In this embodiment, multiple upper connection vias 95 are formed to connect the drain pattern 91 to the drain electrode 34 and to connect the source pattern 92 to the source electrode 35. This allows for a reduction in inductance and enables high-speed switching operations.

[0110] Furthermore, each pattern 91 to 93 is formed, for example, from copper foil. In this case, it is preferable to set the thickness of each pattern 91 to 93 to about 18 μm or less to avoid thermal expansion of the pattern 93 in the thickness direction.

[0111] Furthermore, a through-hole 96 is formed at a position connecting the source electrode pattern 92 to the second through-hole 72 of the side sealing member 70. In this through-hole 96, an upper connection through-hole 97, electrically connected to the lower connection through-hole 73 of the side sealing member 70 and the source electrode pattern 92, is disposed. Thus, in this embodiment, the source electrode 35 of the semiconductor chip 30 is electrically connected to the other electrode 40 via the upper connection through-hole 95, the source electrode pattern 92, the upper connection through-hole 97, the lower connection through-hole 73, and one metal film 22.

[0112] In addition, Figure 4B and Figure 4C In the diagram, the upper connecting through holes 95 and 97 are indicated by dashed lines. Furthermore, in the same figures described later, the upper connecting through holes 95 and 97 are also indicated by dashed lines. In this embodiment, the upper connecting through hole 95 is formed in a cylindrical shape. Hereinafter, the lower connecting through hole 73 formed on the side sealing member 70 and the upper connecting through hole 97 connected to the lower connecting through hole 73 will also be simply referred to as the connecting through hole 61 formed on the sealing member 60. That is, in this embodiment, the connecting through hole 61 formed on the sealing member 60 is arranged in a cylindrical shape to connect the source electrode pattern 92 to a metal film 22.

[0113] Second sealing component 100 Figure 1 and Figure 4D As shown, an LCP film is disposed on the first sealing member 90. Furthermore, a contact hole 101 is formed in the second sealing member 100, exposing each of the patterns 91 to 93. Thus, the portion of the drain pattern 91 exposed from the contact hole 101 constitutes the drain pad 91a. The portion of the source pattern 92 exposed from the contact hole constitutes the source pad 92a. The portion of the gate pattern 93 exposed from the contact hole 101 constitutes the gate pad 93a. While not particularly limited, each of the patterns 91 to 93 is, for example, 18 μm or less.

[0114] Furthermore, in this embodiment, the contact holes 101 are formed at locations different from the semiconductor chip 30 in the stacking direction. That is, each pad 91a, 92a, and 93a is formed at a different location from the semiconductor chip 30 in the stacking direction. In other words, each pad 91a, 92a, and 93a is formed in a manner that does not overlap with the semiconductor chip 30 in the stacking direction. This reduces the stress applied to the semiconductor chip 30 when a printed circuit board or the like is mounted onto each pad 91a, 92a, and 93a via solder, thus suppressing damage to the semiconductor chip 30. Moreover, this structure can be appropriately applied in the embodiments described later.

[0115] Furthermore, the second sealing member 100 is pressurized and integrated with the first sealing member 90, as described later. Therefore, the second sealing member 100 is also positioned between the drain pattern 91 and the source pattern 92 formed on the first sealing member 90. Thus, the second sealing member 100 can function as a solder resist portion and also increase the insulating surface distance between the drain pattern 91 and the source pattern 92.

[0116] The above describes the structure of the sealing member 60 in this embodiment. Furthermore, the sealing member 60 is arranged within the heat dissipation member 20 in the stacking direction. That is, the heat dissipation member 20 is configured such that the sealing member 60 is located within it in the stacking direction. Specifically, the outer edge of one side 21a of the insulating substrate 21 (i.e., the heat dissipation member 20) is exposed from the sealing member 60. This suppresses stress concentration at the end of the mating surface between the sealing member 60 and the heat dissipation member 20. Therefore, it suppresses the formation of cracks at the mating surface between the sealing member 60 and the heat dissipation member 20, and prevents the sealing member 60 from peeling off from the heat dissipation member 20.

[0117] Furthermore, in this embodiment, the components are chemically bonded together by active groups to improve adhesion; specifically, this is covalent bonding (in other words, molecular bonding). In this embodiment, to improve the adhesion between the heat dissipation component 20 and the sealing component 60, the heat dissipation component 20 is subjected to ultraviolet treatment or atmospheric pressure plasma treatment after surface cleaning such as ethanol cleaning. Then, the heat dissipation component 20 forms active groups by coating it with an alkaline solution containing silicates.

[0118] Furthermore, to improve the adhesion between the peripheral portion of the semiconductor chip 30, the drain electrode 34, the source electrode 35, the gate electrode 38, and the sealing component 60, after surface cleaning such as ethanol cleaning of the drain electrode 34, oxide removal is performed by etching with dilute sulfuric acid. Then, an aqueous solution of an organic compound having silanol and amino groups is coated onto the drain electrode 34 to form active groups. The peripheral portion includes the area around the drain electrode 34, the source electrode 35, the gate electrode 38, and the sides of the substrate formed by stacking the support substrate 31, the buffer layer 32, and the semiconductor layer 33. Furthermore, since the drain electrode 34, the source electrode 35, and the gate electrode 38 are connected to the upper connection via 95 (described later), active groups may not be formed in these areas. That is, for the semiconductor chip 30, active groups can be formed only in areas different from where the drain electrode 34, the source electrode 35, and the gate electrode 38 are formed.

[0119] Furthermore, in order to improve the sealing performance between the side sealing component 70 and the first sealing component 90, and between the first sealing component 90 and the second sealing component 100, each component 70, 90, and 100 is subjected to ultraviolet treatment or atmospheric pressure plasma treatment after surface cleaning such as ethanol cleaning. Then, each component 70, 90, and 100 is coated with an aqueous solution of an organic compound having silanol and amino groups to form active groups.

[0120] The above describes the structure of the semiconductor package 10 according to this embodiment. Next, referring to... Figures 5A to 5G , Figure 6 The manufacturing method of the semiconductor package 10 described above will be explained. Furthermore, Figures 5A to 5G This diagram illustrates the process of manufacturing two adjacent semiconductor packages 10. In fact, as shown... Figure 6 As shown, more semiconductor packages 10 are manufactured in the same process. Furthermore, when preparing each component in the following processes, appropriate treatments for forming active groups are performed.

[0121] First, such as Figure 5A and Figure 6 As shown, a multi-connected substrate 210 is formed by integrating the above-mentioned insulating substrate 21 through a dicing line DL. Furthermore, in the portion of the substrate 210 that forms the insulating substrate 21, a metal film 22 and a metal film 23 are formed on one side.

[0122] Furthermore, in the substrate 210, a groove 211 is formed along the cutting line DL on the side where the other metal film 23 is formed. In this case, if the thickness of the substrate 210 is t, the groove 211 is set to a depth of about 0.1t to 0.5t. Here, we describe an example where the groove 211 is formed on the side of the substrate 210 where the other metal film 23 is formed, but the groove 211 can also be formed on the side of the substrate 210 where the metal film 22 is formed, or on both the side where the other metal film 23 is formed and the side where the metal film 22 is formed.

[0123] And, as Figure 5B As shown, a side-forming component 700 is prepared, in which the aforementioned side-sealing component 70 is integrally formed via a cutting line DL. Next, a first through-hole 71 and a second through-hole 72 are formed in the portion of the side-forming component 700 that becomes the side-sealing component 70. Then, for example, a sintered body 73a forming the lower connecting through-hole 73 is configured in the second through-hole 72 by pressing or the like. In this case, a conductive paste forming the lower connecting through-hole 73 can also be configured in the second through-hole 72 by printing or the like. Furthermore, the sintered body 73a configured by pressing or the like uses, for example, a sintered body with silver-tin as the main component. The conductive paste configured by printing uses a material in which powder with silver-tin as the main component is mixed into an organic solvent.

[0124] Similarly, as Figure 5C As shown, a first constituent component 900 is prepared to integrate the aforementioned first sealing member 90 via a cutting line DL. Furthermore, in the portion of the first constituent component 900 that forms the first sealing member 90, a drain pattern 91 and a source pattern 92 are formed. Additionally, in relation to... Figure 5C In different cross-sections, the portion of the first component 900 that serves as the first sealing member 90 is formed with a gate pattern 93. Furthermore, in the portion of the first component 900 that serves as the first sealing member 90, through-holes 94 and 96 are formed using laser technology or the like. In the through-holes 94 and 96, sintered bodies 95a and 97a, which connect to the through-holes 95 and 97 above, are formed by pressing or the like. In this case, conductive paste forming the connecting through-holes 95 and 97 above can also be formed in the through-holes 94 and 96 using a printing method or the like. Additionally, the sintered bodies 95a and 97a formed by pressing or the like are, for example, sintered bodies with silver and tin as the main components. The conductive paste formed by printing uses a material in which powder with silver and tin as the main components is mixed into an organic solvent.

[0125] In addition, such as Figure 5DAs shown, a second component 1000 is prepared to integrate the aforementioned second sealing member 100 via a cutting line DL. Furthermore, a contact hole 101 is formed in the portion of the second component 1000 that serves as the second sealing member 100.

[0126] Next, as Figure 5E As shown, a side component 700 is disposed on the substrate 210, and a semiconductor chip 30 is disposed in the first through-hole 71 via a sintered body 50a constituting a bonding member 50. In this case, conductive paste constituting the bonding member 50 can also be disposed in the first through-hole 71 by printing or the like. Furthermore, a first component 900 and a second component 1000 are sequentially stacked on the side component 700 and the semiconductor chip 30. That is, the side component 700, the first component 900, and the second component 1000 are disposed on the substrate 210 in a manner that accommodates the semiconductor chip 30. In addition, in this embodiment, the side component 700, the first component 900, and the second component 1000 correspond to sealing components. Furthermore, the sintered body 50a is, for example, a sintered body with silver and tin as the main components. The conductive paste disposed by printing uses a material in which powder with silver and tin as the main components is mixed into an organic solvent.

[0127] And, as Figure 5F As shown, while heating, pressure is applied in the stacking direction to integrate the substrate 210, side component 700, semiconductor chip 30, first component 900, and second component 1000. At this time, the sintered bodies 50a, 73a, 95a, and 97a constitute the bonding component 50, the lower connecting through-hole 73, and the upper connecting through-holes 95 and 97. Similarly, when conductive paste is provided, each conductive paste constitutes the bonding component 50, the lower connecting through-hole 73, and the upper connecting through-holes 95 and 97.

[0128] Then, as Figure 5G As shown, the substrate is divided into chip units along the cutting line DL. In this embodiment, since a groove 211 is formed on the substrate 210, cutting can be easily performed. Furthermore, the outer edge of the sealing member 60 is removed using a laser or the like, so that the outer edge of one side 21a of the insulating substrate 21 is exposed from the sealing member 60. As described above, the above-described... Figure 1 The semiconductor package 10 shown.

[0129] As explained above, in this embodiment, the sealing member 60 is made of LCP, which is a material with higher strength and greater flexibility compared to glass epoxy resin. Therefore, it is possible to suppress the introduction of cracks into the sealing member 60 and to prevent damage to the semiconductor package 10.

[0130] Furthermore, the semiconductor package 10 is bonded at the interface between the heat dissipation component 20 and the sealing component 60 by chemical bonding, where active groups are joined together. Specifically, the interface between the heat dissipation component 20 and the sealing component 60 is bonded by covalent bonds. Therefore, peeling at the interface between the heat dissipation component 20 and the sealing component 60 can be suppressed. Furthermore, the interface between the semiconductor chip 30 and the sealing component 60 is chemically bonded. Therefore, peeling at the interface between the semiconductor chip 30 and the sealing component 60 can be suppressed. Moreover, since the interface between the semiconductor chip 30 and the sealing component 60 is chemically bonded, the bonding strength between the semiconductor chip 30 and the sealing component 60 can be improved. Therefore, the area where the semiconductor chip 30 and the sealing component 60 are bonded can be reduced. In particular, when the support substrate 31 is made of SiC, the cost tends to be higher compared to when the support substrate 31 is made of silicon. Therefore, by reducing the area where the semiconductor chip 30 and the sealing component 60 are bonded, the size of the semiconductor chip 30 can be reduced, thereby reducing the cost.

[0131] Furthermore, the bonding member 50 is configured such that the semiconductor chip 30 is located within the bonding member 50 in the stacking direction. Therefore, for example, compared to the case where the semiconductor chip 30 protrudes beyond the bonding member 50 in the stacking direction, stress concentration at the end of the bonding surface between the semiconductor chip 30 and the bonding member 50 can be suppressed. Consequently, crack formation at the bonding surface between the semiconductor chip 30 and the bonding member 50 can be suppressed.

[0132] Furthermore, the heat dissipation component 20 is configured such that the sealing component 60 is located within the heat dissipation component 20 in the stacking direction. Therefore, stress concentration at the end of the mating surface between the sealing component 60 and the heat dissipation component 20 can be suppressed. Consequently, crack formation at the mating surface between the sealing component 60 and the heat dissipation component 20 can be suppressed, and peeling of the sealing component 60 from the heat dissipation component 20 can be prevented.

[0133] Furthermore, since the side sealing component 70 is made of injection molded material, it can be easily mass-produced.

[0134] Furthermore, an LCP constituting the second sealing member 100 is disposed between the drain pattern 91 and the source pattern 92. Therefore, the second sealing member 100 can function as a solder resist part while also increasing the insulating surface distance between the drain pattern 91 and the source pattern 92.

[0135] Furthermore, in this embodiment, the source electrode 35 of the semiconductor chip 30 is electrically connected to the other electrode 40. Therefore, current collapse can be reduced.

[0136] Furthermore, the heat dissipation component 20 is configured such that a metal film 22 and a metal film 23 are formed on the insulating substrate 21. Therefore, warping of the heat dissipation component 20 can be suppressed. In this embodiment, the metal film 22 and the metal film 23 are of the same shape and are symmetrically formed sandwiching the insulating substrate 21. Therefore, warping of the heat dissipation component 20 can be further suppressed.

[0137] Furthermore, during the manufacturing of the semiconductor package 10, a groove 211 is formed on the constituent substrate 210. Therefore, dicing can be easily performed. In this embodiment, an example is described where the groove 211 is formed before integrating the constituent substrate 210 with the side constituent members 700, etc., but the groove 211 can also be formed after integrating the constituent substrate 210 with the side constituent members 700, etc. That is, the groove 211 can be formed on the constituent substrate 210 before it is divided into chip units along the dicing line DL.

[0138] (Second Implementation)

[0139] The second embodiment will be described. This embodiment differs from the first embodiment described above in that the structure of the side sealing member 70 is modified. Everything else is the same as in the first embodiment, so descriptions are omitted here.

[0140] The semiconductor package 10 in this embodiment is as follows: Figure 7 As shown, the side sealing member 70 is constructed by stacking and integrally integrating plate-shaped members 74 made of multiple LCP films. The plate-shaped member 74 has an LCP film 77, a pattern 75 formed on the LCP film 77, and a connecting through-hole 76 disposed in the through-hole 76a. That is, in this embodiment, each plate-shaped member 74 constituting the side sealing member 70 and the first and second sealing members 90 and 100 have the same structure with patterns 75, 91-93 or through-holes 73, 95, 97 appropriately formed on the LCP film 77. Furthermore, the lower connecting through-hole 73 is constructed by connecting the pattern 75 formed on each plate-shaped member 74 and the connecting through-hole 76. That is, the connecting through-hole 61 is composed of the upper connecting through-hole 97 and the pattern 75 formed on each plate-shaped member 74 and the connecting through-hole 76 constituting the lower connecting through-hole 73.

[0141] Furthermore, the semiconductor chip 30 of this embodiment is configured with horizontal semiconductor elements. Also, the patterns 75 formed on each plate-shaped member 74 do not become portions through which current passes. Therefore, the patterns 75 formed on each plate-shaped member 74 can be thinner than the patterns 91-93 formed on the first sealing member 90, for example, by 12 μm or less. This allows for a reduction in the material constituting the patterns 75.

[0142] Furthermore, in this embodiment, the connecting through holes 76 of adjacent plate-shaped components 74 in the stacking direction are electrically connected via a pattern 75. Therefore, the connecting through holes 76 of each plate-shaped component 74 can be arranged to overlap in the stacking direction or to not overlap in the stacking direction.

[0143] Furthermore, in this embodiment, adjacent plate-shaped components 74 are preferably joined by chemical bonding through which active groups are bonded to each other. In this case, for example, active groups may be formed only in the pattern 75 and the via 76. Thus, compared to the case where active groups are formed throughout each plate-shaped component 74, a cost reduction can be achieved.

[0144] Furthermore, this side-sealing member 70 is manufactured by heating and pressurizing after stacking the plate-shaped members 74. That is, in this embodiment, in Figure 5B In the process, such as Figure 8A As shown, a plate-shaped component 770 is prepared to integrate the LCP film 77 via a dicing line DL. Furthermore, the plate-shaped component 770 is prepared in a number corresponding to the number of layers used to form the side sealing component 70. In this case, the number of plate-shaped component components 770 is preferably set such that the overall thickness of the plate-shaped component components 770 is greater than the thickness of the semiconductor chip 30. Therefore, in the following description... Figure 5F In subsequent heating and pressurizing processes, the quality of the formed product can be improved. Furthermore, the process of preparing the first component 900 and the second component 1000 in the first embodiment described above is the same as the process of preparing the plate-shaped component component 770 for integrating the LCP film 77 via the cutting line DL.

[0145] Furthermore, for the plate-shaped component 770, through holes 71a and 76a corresponding to the first through hole 71 are formed, and a component 76b constituting the connecting through hole 76a is disposed in the through hole 76a. The component 76b is made of conductive paste or sintered body, etc.

[0146] Furthermore, in Figure 5E In the process, such as Figure 8B As shown, plate-shaped component forming members 770 are sequentially stacked on the substrate 210, and semiconductor chip 30, first forming member 900, and second forming member 1000 are sequentially disposed thereon. Furthermore, in Figure 8B The text indicates the regions that constitute a semiconductor package 10, but in reality... Figure 5E As shown, the portions constituting multiple semiconductor packages 10 are connected by dicing lines DL. Then, by performing... Figure 5F Subsequent processes produce Figure 7 The semiconductor package 10 shown.

[0147] In this way, even if the side sealing component 70 is not made of injection molded material but is made by stacking multiple plate-shaped components 74, the same effect as the first embodiment described above can be obtained.

[0148] (Third Implementation)

[0149] The third embodiment will be described. In this embodiment, compared to the first embodiment described above, the heat dissipation component 20 does not have one metal film 22 and the other metal film 23. Everything else is the same as the first embodiment described above, so the description is omitted here.

[0150] The semiconductor package 10 in this embodiment is as follows: Figure 9 As shown, the heat dissipation component 20 does not have one metal film 22 and another metal film 23. Furthermore, the semiconductor chip 30 is disposed on the heat dissipation component 20 via the bonding component 50. In addition, the bonding component 50 of this embodiment is made of a conductive material such as a material incorporating silver particles into an organic solvent, and has a thickness of approximately 0.1 nm to 20 μm. That is, the bonding component 50 is sufficiently thin compared to the one metal film 22 described in the first embodiment above.

[0151] Furthermore, the bonding member 50 extends along the surface direction of the heat dissipation member 20 and connects to the lower connection through hole 73. That is, the bonding member 50 extends to the position where it connects to the lower connection through hole 73. Additionally, the source electrode pattern 92 connects to the bonding member 50 via the connection through hole 61 formed in the sealing member 60, thereby connecting to the other electrode 40 of the semiconductor chip 30.

[0152] Therefore, since neither one metal film 22 nor the other metal film 23 is disposed on the heat dissipation component 20, the number of components can be reduced and the same effect as in the first embodiment described above can be obtained. In addition, the bonding component 50 is formed sufficiently thin compared to the one metal film 22. Therefore, even if the bonding component 50 is not disposed on the other side 21b of the insulating substrate 21, the insulating substrate 21 becomes difficult to warp.

[0153] Furthermore, by not configuring another metal film 23 on the heat dissipation component 20, the aforementioned manufacturing process can be performed without... Figure 5G During cutting, the substrate 210 is easily fixed. Therefore, the cutting process can be simplified.

[0154] (Fourth implementation)

[0155] The fourth embodiment will be described. In this embodiment, compared to the first embodiment described above, the sealing member 60 is provided with a plurality of connecting through holes 61. Everything else is the same as in the first embodiment described above, so descriptions are omitted here.

[0156] The semiconductor package 10 in this embodiment is as follows: Figures 10A to 10C As shown, multiple connection vias 61 are formed. Specifically, one side of the metal film 22 of the heat dissipation component 20 is divided into a drain region 22a connected to the drain pattern 91, a source region 22b connected to the source pattern 92, and a gate region 22c connected to the gate pattern 93. Furthermore, the semiconductor chip 30 is disposed on the source region 22b via the bonding member 50. In this embodiment, the drain region 22a corresponds to the first region, and the source region 22b corresponds to the second region.

[0157] The side sealing member 70 has a plurality of lower connection vias 73 connected to the drain region 22a. The side sealing member 70 has a plurality of lower connection vias 73 connected to the source region 22b. The side sealing member 70 has a plurality of lower connection vias 73 connected to the gate region 22c.

[0158] Furthermore, the number of lower connection vias 73 connected to the source region 22b is greater than that in the first embodiment described above. In addition, in this embodiment, the plurality of lower connection vias 73 connected to the drain region 22a and the plurality of lower connection vias 73 connected to the source region are formed such that they are located on opposite sides, separated by the semiconductor chip 30.

[0159] In the first sealing member 90, an upper connection via 97 is formed to connect to the lower connection via 73 connected to the drain region 22a. In the first sealing member 90, an upper connection via 97 is formed to connect to the lower connection via 73 connected to the source region 22b. In the first sealing member 90, an upper connection via 97 is formed to connect to the lower connection via 73 connected to the gate region 22c.

[0160] That is, a connection via 61 is formed in the sealing member 60 to connect the drain pattern 91 and the drain region 22a. A connection via 61 is formed in the sealing member 60 to connect the source pattern 92 and the source region 22b. A connection via 61 is formed in the sealing member 60 to connect the gate pattern 93 and the gate region 22c.

[0161] Furthermore, in this embodiment, each connecting via 61 has a smaller diameter than the upper connecting via 95 that connects the source electrode 35 to the source pattern 92 and the upper connecting via 95 that connects the drain electrode 34 to the drain pattern 91. In other words, in a cross-section orthogonal to the stacking direction, the cross-sectional area of ​​each connecting via 61 is smaller than that of the upper connecting via 95 that connects the source electrode 35 to the source pattern 92 and the upper connecting via 95 that connects the drain electrode 34 to the drain pattern 91.

[0162] As explained above, in this embodiment, one side of the metal film 22 is divided into multiple regions. Furthermore, the drain pattern 91 and the gate pattern 93 are connected to the one side of the metal film 22 via connecting vias 61. Therefore, a plurality of connecting vias 61 are formed in the sealing member 60. Consequently, by means of the connecting vias 61, expansion of the sealing member 60 in the stacking direction can be suppressed, and the same effect as in the first embodiment described above can be obtained while suppressing the introduction of cracks into the connecting vias 61.

[0163] Furthermore, in this embodiment, the diameter of the connecting via 61 is smaller than that of the upper connecting via 95 connecting the drain electrode 34 to the drain pattern 91 and the upper connecting via 95 connecting the source electrode 35 to the source pattern 92. Therefore, compared to the case where the diameter of the connecting via 61 is the same as that of these upper connecting vias 95, it is easier to press-fit sintered bodies 73a and 97a into each of the through holes 72 and 96 during the manufacturing process. Thus, the manufacturing process can be simplified. In addition, the connecting via 61 suppresses the thermal expansion of the sealing member 60 and does not carry current, so even with its small diameter, the electrical characteristics of the semiconductor package 10 do not change significantly.

[0164] Furthermore, although not specifically illustrated, the more connection vias 61 formed, the better the thermal expansion of the sealing member 60 in the stacking direction can be suppressed, and therefore this is preferred. In this case, in order to suppress the thermal expansion of the sealing member 60 equally, the connection vias 61 can be formed along the outer surface of the sealing member 60. That is, in the stacking direction, the connection vias 61 can be formed surrounding the semiconductor chip 30. In other words, the connection vias 61 can be formed respectively in a manner opposite to each side of the semiconductor chip 30. For example, in Figures 10A to 10C Alternatively, connection through-holes 61 (i.e., lower connection through-hole 73 and upper connection through-hole 97) can also be formed at both ends in the left-right direction of the paper to connect the drain pattern 91 and the drain region 22a. That is, as shown Figure 11 As shown, the connecting via 61 can be formed in a manner that surrounds the semiconductor chip 30.

[0165] (Fifth Embodiment)

[0166] The fifth embodiment will be described. In this embodiment, a test pattern is provided, compared to the first embodiment described above. Everything else is the same as the first embodiment described above, so the description is omitted here.

[0167] The semiconductor package 10 in this embodiment is as follows: Figures 12A-12CAs shown, a drain pattern 91, a source pattern 92, a gate pattern 93, and a test pattern 98 are formed on one side 90a of the first sealing member 90. The test pattern 98, like the drain pattern 91, is formed from copper foil or the like.

[0168] Furthermore, an upper connection through-hole 97 connected to the test pattern 98 is formed in the first sealing member 90. Additionally, a lower connection through-hole 73 is formed in the side sealing member 70 such that the upper connection through-hole 97 connected to the test pattern 98 is connected to a metal film 22. That is, a connection through-hole 61 is formed in the sealing member 60 such that the test pattern 98 is connected to a metal film 22. Furthermore, both the source pattern 92 and the test pattern 98 are electrically connected to the metal film 22 and are at the same potential.

[0169] Therefore, by measuring the conduction resistance between the test pattern 98 and the source pattern 92, the conduction state between the source electrode 35 and the other electrode 40 of the semiconductor chip 30 can be checked, and the same effect as in the first embodiment described above can be obtained.

[0170] (Sixth Embodiment)

[0171] The sixth embodiment will be described. This embodiment differs from the first embodiment described above in that the structures of the semiconductor chip 30 and the heat dissipation component 20 are modified. Everything else is the same as in the first embodiment, so descriptions are omitted here.

[0172] The semiconductor package 10 in this embodiment is as follows: Figure 13 As shown, an insulating substrate 41, a support substrate 31, a buffer layer 32, and a semiconductor layer 33 are sequentially stacked to form a semiconductor chip 30. The insulating substrate 41 is made of silicon nitride or aluminum nitride, etc. Furthermore, in this embodiment, the support substrate 31 corresponds to the first substrate, and the semiconductor layer 33 corresponds to the second substrate.

[0173] Furthermore, the planar dimensions of the support substrate 31 and the insulating substrate 41 are larger than those of the buffer layer 32 and the semiconductor layer 33. That is, the support substrate 31 and the insulating substrate 41 have a shape in the stacking direction of the insulating substrate 41, the support substrate 31, the buffer layer 32, and the semiconductor layer 33 that protrudes beyond the semiconductor layer 33 and the buffer layer 32. Furthermore, an electrode film 42 is formed on the portion of the support substrate 31 that protrudes beyond the semiconductor layer 33 and the buffer layer 32. In this embodiment, the semiconductor chip 30 does not have an additional electrode 40.

[0174] Furthermore, the insulating substrate 41 of the semiconductor chip 30 is disposed on the heat dissipation component 20 via the bonding member 50. The bonding member 50 in this embodiment can be made of a sintered body of a material in which silver particles or metal particles of silver and tin are mixed in an organic solvent, as long as it can mechanically connect the insulating substrate 41 to the semiconductor chip 30, or it can be made of a heat dissipation adhesive or the like.

[0175] Furthermore, a connection via 61 is formed in the sealing member 60 to electrically connect the source electrode pattern 92 to the electrode film 42. That is, in this embodiment, the source electrode 35 is electrically connected to the support substrate 31 via the upper connection via 95, the source electrode pattern 92, the connection via 61, and the electrode film 42. In this way, even when the source electrode 35 is electrically connected to the support substrate 31, current collapse can be reduced.

[0176] Furthermore, in this embodiment, since the source electrode 35 is electrically connected to the support substrate 31 as described above, the heat dissipation component 20 is constructed from a metal plate 24 such as copper. Therefore, compared to the case where the heat dissipation component 20 is constructed from silicon nitride or aluminum nitride, the heat dissipation performance of the heat dissipation component 20 can be improved.

[0177] As explained above, in this embodiment, since the heat dissipation component 20 is constructed of a metal plate 24, the heat dissipation performance of the heat dissipation component 20 can be improved and the same effect as in the first embodiment described above can be obtained.

[0178] (Seventh Embodiment)

[0179] The seventh embodiment will be described. In this embodiment, compared to the first embodiment described above, a plurality of semiconductor chips 30 are integrally sealed with a sealing member 60. Everything else is the same as in the first embodiment described above, so descriptions are omitted here.

[0180] The semiconductor package 10 of this embodiment is configured as a so-called 2-in-1 package, in which two semiconductor chips 30 are integrally sealed by a sealing member 60. Furthermore, the two semiconductor chips 30 have the same structure. Hereinafter, one semiconductor chip 30 will be designated as the first semiconductor chip 30a, and the other semiconductor chip 30 will be designated as the second semiconductor chip 30b. Additionally, in... Figure 14 In the diagram, the first semiconductor chip 30a is shown on the right side of the paper, and the second semiconductor chip 30b is shown on the right side of the paper.

[0181] Specifically, in the heat dissipation component 20, two one-sided metal films 22 are formed separately from each other. Furthermore, a first semiconductor chip 30a and a second semiconductor chip 30b are respectively disposed on each one-sided metal film 22 via a bonding member 50.

[0182] The sealing member 60 is configured to integrally seal the first and second semiconductor chips 30a and 30b. Specifically, the side sealing member 70 is configured to seal the sides of the first and second semiconductor chips 30a and 30b. Furthermore, the one-side sealing member 80 is configured to seal one side of the first and second semiconductor chips 30a and 30b.

[0183] The first sealing member 90 has a drain pattern 91 connected to the drain electrode 34 of the first semiconductor chip 30a and a source pattern 92 connected to the source electrode 35 of the second semiconductor chip 30b. Furthermore, the first sealing member 90 has a connection pattern 99 electrically connected to the source electrode 35 of the first semiconductor chip 30a and the drain electrode 34 of the second semiconductor chip 30b. Moreover, the first sealing member 90 has a connection pattern 99 electrically connected to the source electrode 35 of the first semiconductor chip 30a and the drain electrode 34 of the second semiconductor chip 30b. Figure 14 In different cross sections, gate patterns 93 connected to the gate electrode 38 of the first semiconductor chip 30a and gate patterns 93 connected to the gate electrode 38 of the second semiconductor chip 30b are respectively formed.

[0184] Furthermore, an upper connection via 95 is formed in the first sealing member 90 to connect the drain electrode 34 of the first semiconductor chip 30a to the drain pattern 91. An upper connection via 95 is also formed in the first sealing member 90 to connect the source electrode 35 of the second semiconductor chip 30b to the source pattern 92. Additionally, an upper connection via 95 is formed in the first sealing member 90 to connect the source electrode 35 of the first semiconductor chip 30a to the connection pattern 99, and also to connect the drain electrode 34 of the second semiconductor chip 30b to the connection pattern 99. In other words, the first and second semiconductor chips 30a and 30b are electrically connected to each other.

[0185] Furthermore, in the first sealing component 90, in conjunction with Figure 14 In different cross sections, an upper connection via 95 is formed such that the gate electrode 38 of the first semiconductor chip 30a is connected to the gate using pattern 93. In the first sealing member 90, an upper connection via 95 is formed such that the gate electrode 38 of the second semiconductor chip 30b is connected to the gate using pattern 93.

[0186] Furthermore, a connection via 61 is formed in the sealing member 60 to connect the connection pattern 99 to a metal film 22 on which the first semiconductor chip 30a is disposed. A connection via 61 is also formed in the sealing member 60 to connect the source electrode pattern 92 to a metal film 22 on which the second semiconductor chip 30b is disposed. Thus, the first and second semiconductor chips 30a and 30b electrically connect the source electrode 35 and the other electrode 40, respectively.

[0187] The second sealing member 100 has a contact hole 101 that exposes a portion of the drain pattern 91, the source pattern 92, and the connection pattern 99. Furthermore, the portions of the drain pattern 91, the source pattern 92, and the connection pattern 99 exposed from the contact hole 101 become the drain pad 91a, the source pad 92a, and the connection pad 99a, respectively.

[0188] In addition, in relation to Figure 14 In different cross-sections, the second sealing member 100 is formed with a contact hole 101 that exposes a portion of the gate pattern 93. Furthermore, as described above... Figure 4D As explained in the diagram, the portion of the gate pattern 93 exposed from the contact hole 101 becomes the gate pad 93a.

[0189] Such a semiconductor package 10 is used, for example, in a DC / DC converter circuit or an inverter circuit, with a first semiconductor chip 30a forming the upper arm and a second semiconductor chip 30b forming the lower arm. In this case, the drain pad 91a becomes the high-voltage side pad, the source pad 92a becomes the low-voltage side pad, and the connection pad 99a becomes the output pad. Furthermore, the aforementioned semiconductor package 10... Figure 15 As shown, it is used together with the printed circuit board 110 and the cooler 140, which are the mounted components, to form an electronic device 1.

[0190] The printed circuit board 110 has one side 110a and another side 110b opposite to the first side 110a. A wiring pattern 111 is formed on one side 110a and a wiring pattern 112 is formed on the other side 110b. Through-hole electrodes 113 are formed to electrically connect the wiring pattern 111 and the wiring pattern 112. Furthermore, on the printed circuit board 110, electronic components such as ceramic capacitors are disposed on one side wiring pattern 111 via solder 115 or the like as connecting members.

[0191] Furthermore, in the semiconductor package 10, the drain pad 91a, the source pad 92a, and the connection pad 99a are respectively connected to the wiring pattern 112 on the other side of the printed circuit board 110 via solder 120, which serves as a connection component. Additionally, in relation to... Figure 15In different cross-sections, the gate pad 93a of the semiconductor package 10 is connected to the wiring pattern 112 on the other side of the printed circuit board 110 via solder 120. Furthermore, it is preferable that the solder 120 is not in a paste form but rather consists of solder bumps, so that reliability can be improved by ensuring sufficient height.

[0192] Furthermore, between the printed circuit board 110 and the semiconductor package 10, an underfill 130 is provided to ensure the reliability of the solder 120 and the insulation between the drain pad 91a, the source pad 92a, the gate pad 93a, and the connection pad 99a.

[0193] Furthermore, on the other side of the semiconductor package 10, a cooler 140 made of metal or the like is disposed via a connecting component 141 such as a heat dissipation lubricant on the metal film 23.

[0194] As explained above, the semiconductor package 10, which integrally seals multiple semiconductor chips 30 with a sealing component 60, can also achieve the same effect as the first embodiment described above.

[0195] (A variation of the seventh embodiment)

[0196] A variation of the seventh embodiment will be described. In the seventh embodiment, a semiconductor package 10 in which two semiconductor chips 30 are sealed by a sealing member 60 was described, but the semiconductor package 10 can also be made as follows: For example, the semiconductor package 10 can be a so-called 4-in-1 package in which four semiconductor chips 30 are sealed by the sealing member 60. Furthermore, the semiconductor package 10 can also be a so-called 6-in-1 package in which six semiconductor chips 30 are sealed by the sealing member 60.

[0197] (Eighth Embodiment)

[0198] The eighth embodiment will be described. In this embodiment, compared to the first embodiment described above, a vertically shaped semiconductor element is formed in the semiconductor chip 30. Everything else is the same as in the first embodiment described above, so descriptions are omitted here.

[0199] The semiconductor package 10 in this embodiment is as follows: Figure 16 As shown, the semiconductor chip 30 is configured by forming vertically oriented semiconductor elements. For example, the semiconductor chip 30 of this embodiment has a semiconductor substrate 43 made of silicon or SiC, etc. Although the detailed structure of the semiconductor chip 30 is not shown, a drain electrode 34 is formed on the side of the heat dissipation member 20, and an active electrode 35 is formed on the side opposite to the heat dissipation member 20. Furthermore, in relation to... Figure 16In different cross-sections, the semiconductor chip 30 has gate wiring 37, gate electrode 38, etc., formed on the side opposite to the heat dissipation component 20. Furthermore, the drain electrode 34 of the semiconductor chip 30 is connected to a metal film 22 via a conductive bonding member 50. In this embodiment, the drain electrode 34 corresponds to both the first electrode and the other electrode.

[0200] In the first sealing member 90, an active electrode pattern 92 and a drain electrode pattern 91 are formed. Furthermore, in the first sealing member 90, in conjunction with... Figure 16 In different cross sections, gate patterns 93 are formed.

[0201] Furthermore, in the first sealing member 90, a solid pattern 95b is disposed within the through hole 94 to connect the source electrode pattern 92 to the source electrode 35. In this embodiment, the solid pattern 95b is disposed to reduce resistance, but the source electrode pattern 92 and the source electrode 35 can also be connected via the upper connection through hole 95 in the same manner as in the first embodiment. Furthermore, in relation to... Figure 16 In different cross sections, an upper connection via 95 is provided in such a way that the gate is connected to the gate electrode 38 by pattern 93.

[0202] Furthermore, in the sealing member 60, a connection via 61 is formed in such a way that the drain pattern 91 is electrically connected to a metal film 22. Thus, the drain pattern 91 is connected to the drain electrode 34 via the connection via 61 and the metal film 22. In addition, it is preferable that multiple connection vias 61 are formed to facilitate the flow of current in order to reduce inductance.

[0203] As explained above, even if a vertical semiconductor element is formed in the semiconductor chip 30, the same effect as in the first embodiment described above can be obtained.

[0204] (9th embodiment)

[0205] The ninth embodiment will be described. In this embodiment, compared to the second embodiment described above, a plate-shaped member 74 is also disposed between the semiconductor chip 30 and the heat dissipation member 20. Everything else is the same as in the second embodiment described above, so descriptions are omitted here.

[0206] The semiconductor package 10 in this embodiment is as follows: Figure 17As shown, a plate-shaped component 74 is also disposed between the other electrode 40 of the semiconductor chip 30 and the heat dissipation component 20. In this embodiment, the plate-shaped component 74 disposed between the other electrode 40 of the semiconductor chip 30 and the heat dissipation component 20 is also referred to as the lower plate-shaped component 740, and the plate-shaped component 74 disposed on the lower plate-shaped component 740 is also referred to as the middle plate-shaped component 840. Furthermore, the lower plate-shaped component 740 has a lower layer connection via 760 appropriately formed in the LCP film 77, and is disposed in such a way that it covers one side of the metal film 22. The middle plate-shaped component 840 is made with the same structure as the middle layer pattern 850 and the middle layer connection via 860 appropriately formed in the LCP film, and is disposed on the lower plate-shaped component 740.

[0207] Furthermore, the other electrode 40 of the semiconductor chip 30 is connected to a metal film 22 via a lower layer connection via 760 formed in the lower plate-shaped member 740. In this embodiment, the metal film 22 extends below the middle layer connection via 860 formed in the middle plate-shaped member 840. The middle layer connection via 860 is connected to the metal film 22 via the lower layer connection via 760. Thus, in this embodiment, the other electrode 40 of the semiconductor chip 30 is electrically connected to the source electrode 35. Additionally, in this embodiment, the thickness of the metal film 22 is thinner than that of the metal film 22 in the first embodiment, so that the lower plate-shaped member 740 can cover the metal film 22. Furthermore, the other side 21b of the insulating substrate 21 does not have another metal film 23. However, it is also possible to have a structure where the other side 21b of the insulating substrate 21 has another metal film 23.

[0208] Furthermore, in this embodiment, the outer edge of one side 21a of the heat dissipation component 20 is also sealed by the sealing component 60. That is, the sealing component 60 is arranged such that its outer edge end coincides with the outer edge end of the heat dissipation component 20 in the stacking direction. Additionally, such a semiconductor package 10, as described above... Figure 5G In the process of dividing the chip into chip units along the cutting line DL, the outer edge of the sealing member 60 can be left unremoved. Furthermore, in the above embodiments and the embodiments described below, corresponding to the configuration of each embodiment, the outer edge of one side 21a of the heat dissipation member 20 can be sealed by the sealing member 60, or the outer edge of one side 21a of the heat dissipation member 20 can be exposed from the sealing member 60.

[0209] As explained above, alternatively, a lower plate-shaped component 740 may be configured, and the other electrode 40 of the semiconductor chip 30 may be connected to the source electrode 35 via a lower connection via 760 formed in the lower plate-shaped component 740.

[0210] (10th Embodiment)

[0211] The tenth embodiment will be described. This embodiment, compared to the ninth embodiment described above, specifies the placement of the lower layer connecting through-hole 760. Everything else is the same as the ninth embodiment described above, so the description is omitted here.

[0212] like Figure 18 As shown, in this embodiment, the semiconductor package 10 is configured such that the lower layer connection via 760 is connected to the inner edge portion of the semiconductor chip 30, and is not configured to connect the lower layer connection via 760 to the outer edge portion of the semiconductor chip 30. In this embodiment, the lower layer connection via 760 is located at a position a distance L from the outer edge of the semiconductor chip 30, which is a distance equal to the thickness of the semiconductor chip 30.

[0213] In such a semiconductor package 10, damage to the underlying interconnect via 760 can be suppressed, thereby improving reliability. Specifically, the outermost portion of the semiconductor chip 30 is more prone to bending and generating greater stress. Therefore, by positioning the underlying interconnect via 760 in a portion of the semiconductor chip 30 different from the stress-prone area, damage to the underlying interconnect via 760 can be suppressed.

[0214] (11th Embodiment)

[0215] The 11th embodiment will be described. This embodiment differs from the 9th embodiment described above in that the structure of the lower plate-shaped member 740 is modified. Everything else is the same as the 9th embodiment described above, so descriptions are omitted here.

[0216] The semiconductor package 10 in this embodiment is as follows: Figure 19 and Figure 20 As shown, the diameter of the lower-layer connection via 760 formed in the lower-layer plate-like component 740 varies depending on its placement. Specifically, the diameter of the portion of the lower-layer connection via 760 that connects to the inner edge of the semiconductor chip 30 is larger than the diameter of the portion that connects to the outer edge of the semiconductor chip 30. In other words, the connection area of ​​the portion of the lower-layer connection via 760 that connects to the inner edge of the semiconductor chip 30 is larger than the connection area of ​​the portion that connects to the outer edge of the semiconductor chip 30. More specifically, the diameter of the lower-layer connection via 760 gradually decreases from the portion connected to the inner edge of the semiconductor chip 30 toward the portion connected to the outer edge.

[0217] In this semiconductor package 10, the inner edge of the semiconductor chip 30 is more prone to high temperatures compared to the outer edge. Therefore, by configuring a lower layer connection via 760 with a larger diameter in the high-temperature portion of the semiconductor chip 30, heat dissipation can be improved. Furthermore, as described in the 10th embodiment above, the outer edge of the semiconductor chip 30 is more prone to bending and generating greater stress. Therefore, by configuring a lower layer connection via 760 with a smaller diameter in the portion of the semiconductor chip 30 where stress is more likely to occur, damage to the lower layer connection via 760 can be suppressed. In other words, the semiconductor package 10 according to this embodiment can improve heat dissipation while suppressing damage to the lower layer connection via 760.

[0218] (12th implementation)

[0219] The 12th embodiment will be described. This embodiment differs from the 9th embodiment described above in that the structure of the lower plate-shaped member 740 is modified. Everything else is the same as the 9th embodiment described above, so descriptions are omitted here.

[0220] In this embodiment, such as Figure 21 As shown, a lower plate-shaped component 740 is formed by sequentially stacking a first lower plate-shaped component 741 and a second lower plate-shaped component 742 from the heat dissipation component 20 side. Furthermore, a first lower layer connection through-hole 761, serving as a lower layer connection through-hole 760, is formed in the first lower plate-shaped component 741. A lower layer pattern 752 and a second lower layer connection through-hole 762, also serving as a lower layer connection through-hole 760, are formed in the second lower plate-shaped component 742.

[0221] Specifically, a plurality of second lower layer connection vias 762 are formed in the second lower layer plate-shaped member 742 to connect to the other electrode 40 of the semiconductor chip 30, and the second lower layer connection vias 762 are formed to connect to the middle layer connection vias 860 formed in the middle layer plate-shaped member 840. Furthermore, a lower layer pattern 752 is formed in the second lower layer plate-shaped member 742 to connect the second lower layer connection vias 762 to each other. That is, the lower layer pattern 752 extends from the portion located below the semiconductor chip 30 to the portion located below the middle layer connection vias 860.

[0222] In the first lower plate-shaped member 741, a plurality of first lower layer connection vias 761 are formed to connect the lower layer pattern 752 formed on the second lower plate-shaped member 742 to a metal film 22. Furthermore, in this embodiment, the metal film 22 is approximately the same size as the lower layer pattern 752 and is formed opposite to the lower layer pattern 752. That is, the metal film 22, like the lower layer pattern 752, extends from the portion located below the semiconductor chip 30 to the portion located below the middle layer connection via 860. Moreover, the portion of the first lower layer connection via 761 that is on the outer side of the semiconductor chip 30 in the stacking direction is also connected to the lower layer pattern 752.

[0223] Furthermore, in this embodiment, such as Figure 21 and Figure 22 As shown, the first lower layer connecting through hole 761 formed in the first lower plate-shaped member 741 has a larger diameter than the second lower layer connecting through hole 762 formed in the second lower plate-shaped member 742. Furthermore, the first lower layer connecting through hole 761 formed in the first lower plate-shaped member 741 and the second lower layer connecting through hole 762 formed in the second lower plate-shaped member 742 are formed at different positions in the stacking direction. In other words, the first lower layer connecting through hole 761 formed in the first lower plate-shaped member 741 and the second lower layer connecting through hole 762 formed in the second lower plate-shaped member 742 are arranged so as not to overlap in the stacking direction. In this embodiment, the first lower layer connecting through hole 761 formed in the first lower plate-shaped member 741 and the second lower layer connecting through hole 762 formed in the second lower plate-shaped member 742 are formed to be staggered and offset from each other when viewed from the stacking direction. Additionally, in Figure 22 In the image, for ease of understanding, the first lower layer connecting via 761 is shaded.

[0224] As explained above, the first lower plate-shaped component 741 and the second lower plate-shaped component 742 can be stacked to form the lower plate-shaped component 740. Furthermore, in such a semiconductor package 10, the second lower plate-shaped component 742 is more prone to high temperatures compared to the first lower plate-shaped component 741. Therefore, by making the second lower layer connection via 762 formed in the second lower plate-shaped component 742 smaller than the first lower layer connection via 761 formed in the first lower plate-shaped component 741, damage to the second lower layer connection via 762 can be suppressed, thereby improving reliability.

[0225] Furthermore, a metal film 22 and a lower layer pattern 752 formed on the second lower layer plate-like member 742 extend to the outer side of the semiconductor chip 30 in the stacking direction. Also, a first lower layer connection via 761 formed on the first lower layer plate-like member 741 is connected to the lower layer pattern 752 formed on the second lower layer plate-like member 742 on the outer side of the semiconductor chip 30 in the stacking direction. Therefore, when heat generated in the semiconductor chip 30 is transferred from the second lower layer connection via 762 to the lower layer pattern 752, the heat diffuses in the planar direction within the lower layer pattern 752 and is transferred to the insulating substrate 21 via the first lower layer connection via 761 and a metal film 22. Therefore, compared to the case where the first lower layer connection via 761 formed on the first lower layer plate-like member 741 in the stacking direction is only connected to the lower layer pattern 752 formed on the second lower layer plate-like member 742 on the inner side of the semiconductor chip 30, heat dissipation is improved. In this case, although not specifically illustrated, by making the number of first lower layer connection through holes 761 greater than the number of second lower layer connection through holes 762, it is easier to dissipate heat to the heat dissipation component 20.

[0226] Furthermore, the first lower layer connecting through-hole 761 and the second lower layer connecting through-hole 762 are formed at different positions in the stacking direction. Therefore, compared with the case where the first lower layer connecting through-hole 761 and the second lower layer connecting through-hole 762 overlap in the stacking direction, the stress that may be generated in the first lower layer connecting through-hole 761 and the second lower layer connecting through-hole 762 can be reduced, and the reliability can be further improved.

[0227] (13th implementation)

[0228] The 13th embodiment will be described. In this embodiment, compared to the 9th embodiment described above, a roughened portion is formed on the insulating substrate 21. Everything else is the same as in the 9th embodiment described above, so the description is omitted here.

[0229] The semiconductor package 10 in this embodiment is as follows: Figure 23 As shown, a roughened portion 25 is formed on the insulating substrate 21 at the portion that engages with the sealing member 60. In this embodiment, the roughened portion 25 is formed in the shape of a frame surrounding the portion of the insulating substrate 21 where a metal film 22 is formed. Such a roughened portion 25 is formed, for example, by laser processing or sandblasting of the insulating substrate 21.

[0230] Therefore, a roughened portion 25 is formed on the insulating substrate 21, which improves the adhesion between the lower plate-shaped member 740 and the insulating substrate 21. This helps to prevent the lower plate-shaped member 740 from peeling off from the insulating substrate 21.

[0231] (A variation of the 13th embodiment)

[0232] A variation of the 13th embodiment will be described. In the 13th embodiment described above, on the insulating substrate 21, as... Figure 24 As shown, the groove 26 can be formed instead of the roughened portion 25. Therefore, in the portion where the groove 26 is formed, the adhesion between the LCP film 77 constituting the lower plate-shaped member 740 and the insulating substrate 21 can be improved, thus achieving the same effect as in the 12th embodiment described above. Furthermore, by forming the groove 26, assuming that peeling develops from the interface between the lower plate-shaped member 740 and the insulating substrate 21, the direction of peeling development changes due to the groove 26. Therefore, peeling development can also be suppressed.

[0233] (14th embodiment)

[0234] The 14th embodiment will be described. In this embodiment, compared to the first embodiment described above, a recess is formed in the insulating substrate 21. Everything else is the same as in the first embodiment described above, so descriptions are omitted here.

[0235] The semiconductor package 10 in this embodiment is as follows: Figure 25 As shown, a recess 27 is formed on one side 21a of the insulating substrate 21. The bottom surface of the recess 27 is larger than the plane of the semiconductor chip 30, and the depth of the recess 27 is shallower than the thickness of the semiconductor chip 30.

[0236] A metal film 22 extends from the bottom surface of the recess 27 to the periphery of the portion where the recess 27 is formed. Furthermore, the metal film 22 is connected to the lower connecting through hole 73 at a portion different from the portion where the recess 27 is formed.

[0237] The semiconductor chip 30 is configured such that the other electrode 40 side is housed in the recess 27. However, the semiconductor chip 30 is housed in the recess 27 such that a portion of the drain electrode 34 and the source electrode 35 side protrudes from the recess 27.

[0238] In such a semiconductor package 10, since the semiconductor chip 30 is disposed within the recess 27 formed in the insulating substrate 21, the amount of resin in the sealing member 60 that seals the semiconductor chip 30 can be reduced. Therefore, the amount of LCP, which is more expensive than the insulating substrate 21, can be reduced, thereby achieving cost reduction.

[0239] (15th implementation)

[0240] The 15th embodiment will be described. In this embodiment, compared to the 9th embodiment described above, the middle layer pattern 850 is removed from the middle layer plate-like member 840. Everything else is the same as the 9th embodiment described above, so descriptions are omitted here.

[0241] The semiconductor package 10 in this embodiment is as follows: Figure 26As shown, no intermediate layer pattern 850 is formed in the intermediate layer plate-shaped component 840. Furthermore, the intermediate layer connecting through holes 860 of each intermediate layer plate-shaped component 840 are directly connected to each other.

[0242] Such a semiconductor package 10 is manufactured, for example, as follows. That is, in the embodiment described above... Figure 8A When the plate-shaped component 770 is formed, no through-hole 76a is formed in the plate-shaped component 770 constituting the middle plate-shaped component 840, and no component 76b is disposed there. Furthermore, the plate-shaped component 770 constituting the middle plate-shaped component 840 and the plate-shaped component 770 constituting the lower plate-shaped component 740 are stacked and pre-integrated by temporary pressure or the like. Next, through-hole 76a is formed together in the plate-shaped component 770 constituting the middle plate-shaped component 840 and the plate-shaped component 770 constituting the lower plate-shaped component 740 using laser cutting, drilling, punching, or the like. Then, a component 76b, such as conductive paste, is disposed in the through-hole 76a. Therefore, even if the middle layer pattern 850 is not formed in the middle plate-shaped component 840, it is easy to connect the middle layer connecting through-holes 860 formed in each middle plate-shaped component 840.

[0243] Therefore, the middle layer pattern 850 of the middle layer plate-shaped component 840 can be reduced, thus enabling component reduction.

[0244] Furthermore, this embodiment can be applied to the embodiments described above and those described later. Also, for example, when this embodiment is applied to the 12th embodiment, the lower layer pattern 752 disposed between the second lower layer connection via 762 formed in the second lower layer plate-like member 742 and the first lower layer connection via 761 formed in the first lower layer plate-like member 741 can be removed. In this case, the lower layer pattern 752 can be configured to have only the portion located below the semiconductor chip 30. That is, in this embodiment, a semiconductor package 10 in which the pattern 75 is appropriately removed in adjacent plate-like members 74 in the stacking direction can be obtained.

[0245] (Sixteenth Embodiment)

[0246] The 16th embodiment will be described. In this embodiment, compared to the 9th embodiment described above, a vertically shaped semiconductor element is formed in the semiconductor chip 30. That is, the 8th embodiment is combined with the 9th embodiment described above. Everything else is the same as the 9th embodiment described above, so descriptions are omitted here.

[0247] The semiconductor package 10 in this embodiment is as follows: Figure 27As shown, the semiconductor chip 30 is formed with a vertically oriented semiconductor element similar to that in the eighth embodiment. Specifically, the semiconductor chip 30 has a drain electrode 34 formed on the side of the heat sink 20 and an active electrode 35 formed on the side opposite to the heat sink 20. Furthermore, in relation to... Figure 27 In different cross sections, the semiconductor chip 30 has gate wiring 37, gate electrode 38, etc. formed on the side opposite to the heat dissipation component 20.

[0248] Furthermore, the drain electrode 34 of the semiconductor chip 30 is connected to a metal film 22 via a lower-layer connection via 760. In this embodiment, the drain electrode 34 corresponds to both the first electrode and the other electrode.

[0249] In this way, the sealing component 60 can be constructed using multiple plate-shaped components 74, and a vertical semiconductor element can be formed in the semiconductor chip 30.

[0250] (17th embodiment)

[0251] The 17th embodiment will be described. In this embodiment, compared to the 16th embodiment described above, a capacitor is further disposed in the sealing member 60. Everything else is the same as in the 16th embodiment described above, so descriptions are omitted here.

[0252] In this embodiment, such as Figure 28 As shown, a capacitor 150 having a pair of electrodes 150a and 150b is also disposed in the sealing member 60. Specifically, the capacitor 150 is disposed near and to the side of the semiconductor chip 30. Furthermore, the capacitor 150 is disposed such that one electrode 150a is located on the side of the first sealing member 90 and the other electrode 150b is located on the side of the lower plate member 740. In addition, the capacitor 150 of this embodiment is made of silicon or the like and has a thickness approximately equal to that of the semiconductor chip 30.

[0253] A source electrode pattern 92 formed on the first sealing member 90 extends to the portion opposite to the capacitor 150. A metal film 22 formed on one side of the insulating substrate 21 extends to the portion opposite to the capacitor 150.

[0254] Furthermore, the electrode 150a of the capacitor 150 is connected to the source pattern 92 via the upper connection via 95, and is connected to one side of the metal film 22 of the drain electrode 34 of the semiconductor chip 30 via the lower connection via 760.

[0255] In this embodiment, the source pattern 92, the upper connecting via 95, the metal film 22, and the lower connecting via 760 correspond to wiring layers. Furthermore, this semiconductor package 10, like the semiconductor chip 30, is manufactured by placing the capacitor 150 within the plate-shaped component 770.

[0256] In this embodiment, the semiconductor package 10, by placing the capacitor 150 within the sealing member 60, allows the semiconductor chip 30 and the capacitor 150 to be positioned close together, thus shortening the wiring layer connecting the semiconductor chip 30 and the capacitor 150. Consequently, parasitic inductance can be reduced.

[0257] Furthermore, the semiconductor package 10 of this embodiment is constructed by similarly arranging the capacitor 150 and the semiconductor chip 30 within the sealing member 60. Therefore, compared to the case where the capacitor 150 is arranged in another location and connected to the semiconductor chip 30, the structure can be simplified, and the manufacturing process can be simplified.

[0258] Furthermore, in the above description, an example of capacitor 150 having the same thickness as semiconductor chip 30 was given, but capacitor 150 may also be formed to be thinner than semiconductor chip 30. In this case, for example, by appropriately forming an intermediate layer pattern 850 and an intermediate layer connection via 860 in an intermediate layer plate-like member 840 disposed between the electrode 150a of capacitor 150 and the source pattern 92, the electrode 150a of capacitor 150 can be connected to the source pattern 92.

[0259] (Embodiment 18)

[0260] The 18th embodiment will be described. In this embodiment, compared to the 9th embodiment, a heat dissipation component is added to the second sealing member 100 of the semiconductor package 10. Everything else is the same as in the 9th embodiment described above, so the description is omitted here.

[0261] The semiconductor package 10 in this embodiment is as follows: Figure 29 As shown, a heat dissipation component 160 is also disposed on the second sealing component 100. In this embodiment, the heat dissipation component 160 is opposite to the semiconductor chip 30 and is disposed in a portion of the second sealing component 100 that is different from the portion forming the contact hole 101.

[0262] Furthermore, in the second sealing member 100, an upper connection through hole 103 is formed in the through hole 102 that passes through the second sealing member 100, so as to connect the heat dissipation member 160 and the source electrode pattern 92. As a result, the heat dissipation member 160 and the source electrode pattern 92 are thermally connected.

[0263] Therefore, the heat generated by the semiconductor chip 30 can be dissipated from the heat dissipation component 160, thus further improving the heat dissipation performance.

[0264] (19th embodiment)

[0265] The 19th embodiment will be described. In this embodiment, compared to the 9th embodiment, a high-heat-dissipation component is added to the heat dissipation component 20 side of the semiconductor package 10. Everything else is the same as in the 9th embodiment described above, so the description is omitted here.

[0266] The semiconductor package 10 in this embodiment is as follows: Figure 30 As shown, on the other side 21b of the insulating substrate 21 constituting the heat dissipation component 20, a high heat dissipation component 170 made of a material with a higher thermal conductivity than the insulating substrate 21 is disposed. Furthermore, in this embodiment, the planar dimension of the high heat dissipation component 170 is larger than that of the heat dissipation component 20. Additionally, such a high heat dissipation component 170 is made of, for example, a metallic material such as copper or aluminum.

[0267] Furthermore, the insulating substrate 21 and the high heat dissipation component 170 are connected by a bonding component 171, such as a sintered body with silver and tin as the main components. Alternatively, the insulating substrate 21 and the high heat dissipation component 170 can also be connected by covalent bonds that bond the active groups together.

[0268] Therefore, heat can be dissipated from the heat dissipation component 20 via the high heat dissipation component 170, thus further improving heat dissipation performance. Furthermore, in this embodiment, since the planar dimension of the high heat dissipation component 170 is larger than that of the insulating substrate 21, heat dissipation performance can be further improved compared to cases where the planar dimension of the high heat dissipation component 170 is smaller than or equal to that of the insulating substrate 21. Moreover, when the semiconductor package 10 of this embodiment is mounted on the cooler 140 as described in the seventh embodiment above, the high heat dissipation component 170 is mounted on the cooler 140 via a connecting member 141 such as a thermal grease. Therefore, by increasing the planar dimension of the high heat dissipation component 170, the contact area between the high heat dissipation component 170 and the connecting member 141 can be increased, further improving heat dissipation performance.

[0269] (A variation of the 19th embodiment)

[0270] A variation of the 19th embodiment described above will be described. In the 19th embodiment, instead of using the insulating substrate 21, the high heat dissipation component 170 can be directly disposed on the other side of the electrode 40 of the semiconductor chip 30 as the heat dissipation component 20. In this case, the high heat dissipation component 170 is conductive when it is made of metal. Therefore, when the heat dissipation component 20 is constructed with the high heat dissipation component 170, an LCP film or the like can be disposed between the high heat dissipation component 170 and the metal film 22.

[0271] Furthermore, in the 19th embodiment described above, as in the 1st embodiment described above, another metal film 23 can be disposed on the other side 21b of the insulating substrate 21 and the thickness of the other metal film 23 can be increased, thereby enabling the other metal film 23 to function as a high heat dissipation component 170.

[0272] Furthermore, in the 19th embodiment described above, the size of the high heat dissipation component 170 in the planar direction may also be smaller than that of the insulating substrate 21.

[0273] (20th embodiment)

[0274] The 20th embodiment will be described. This embodiment, compared to the 16th embodiment described above, includes two semiconductor chips 30 on which vertically shaped semiconductor elements are formed. Everything else is the same as the 16th embodiment described above, so descriptions are omitted here.

[0275] The semiconductor package 10 in this embodiment is as follows: Figure 31 As shown, similar to the seventh embodiment described above, it is a so-called 2-in-1 package in which two semiconductor chips 30 are integrally sealed with a sealing member 60. Furthermore, the two semiconductor chips 30 have the same structure as in the sixth embodiment described above. That is, each semiconductor chip 30 is configured with a drain electrode 34 formed on one side and a source electrode 35 and a gate electrode 38 formed on one side. Hereinafter, one semiconductor chip 30 will be referred to as the first semiconductor chip 30a, and the other semiconductor chip 30 as the second semiconductor chip 30b. Furthermore, in Figure 31 In the diagram, the first semiconductor chip 30a is shown on the right side of the paper, and the second semiconductor chip 30b is shown on the right side of the paper. Furthermore, the first semiconductor chip 30a and the second semiconductor chip 30b are configured such that the drain electrode 34 is located on the side opposite to the heat sink 20, and the source electrode 35 and the gate electrode 38 are located on the side of the heat sink 20. Additionally, the gate electrode 38 is formed on the side opposite to the heat sink 20. Figure 31 In different cross sections.

[0276] The first sealing member 90 and the second sealing member 100 have the same structure as in the seventh embodiment described above. Specifically, the first sealing member 90 has a drain pattern 91 formed to connect with the drain electrode 34 of the first semiconductor chip 30a. The first sealing member 90 also has a connection pattern 99 forming to connect the source electrode 35 of the first semiconductor chip 30a to the drain electrode 34 of the second semiconductor chip 30b. Finally, the first sealing member 90 has a source pattern 92 formed to connect with the source electrode 35 of the second semiconductor chip 30b.

[0277] Furthermore, in the first sealing member 90, upper connecting through holes 95 are formed, which are connected to the drain pattern 91, the source pattern 92, and the connecting pattern 99, respectively. In the first sealing member 90, in relation to... Figure 31 In different cross-sections, a gate pattern 93 connected to the gate electrode 38 of the first semiconductor chip 30a and an upper connection via 95 connected to the gate pattern 93 are formed. In the first sealing member 90, in relation to... Figure 31 In different cross sections, a gate pattern 93 connected to the gate electrode 38 of the second semiconductor chip 30b and an upper connection via 95 connected to the gate pattern 93 are formed.

[0278] The second sealing member 100 has a contact hole 101 that exposes a portion of the drain pattern 91, the source pattern 92, and the connection pattern 99. Furthermore, the portions of the drain pattern 91, the source pattern 92, and the connection pattern 99 exposed from the contact hole 101 become drain pads 91a, source pads 92a, and connection pads 99a, respectively. Additionally, the second sealing member 100... Figure 31 Contact holes 101 are formed in different cross sections, exposing a portion of the gate pattern 93. Furthermore, the portion of the gate pattern 93 exposed from the contact holes 101 becomes the gate pad 93a.

[0279] A metal film 22 is formed on the portion opposite to the first semiconductor chip 30a and the portion opposite to the second semiconductor chip 30b. Furthermore, the portions of the metal film 22 opposite to the first semiconductor chip 30a and the second semiconductor chip 30b are formed separately. Additionally, the metal film 22 opposite to the first semiconductor chip 30a has a portion opposite to the source electrode 35 and a portion opposite to the gate electrode 38, which are formed separately. The metal film 22 opposite to the second semiconductor chip 30b has a portion opposite to the source electrode 35 and a portion opposite to the gate electrode 38, which are formed separately.

[0280] Furthermore, the source electrode 35 of the first semiconductor chip 30a is connected to a metal film 22 opposite to the source electrode 35 via a lower layer connection via 760. The source electrode 35 of the second semiconductor chip 30b is also connected to a metal film 22 opposite to the source electrode 35 via a lower layer connection via 760. Additionally, the gate electrode 38 of the first semiconductor chip 30a is connected to... Figure 31 In different cross-sections, the metal film 22 opposite to the gate electrode 38 is connected via a lower connecting via 760. The gate electrode 38 of the second semiconductor chip 30b is connected to... Figure 31 In different cross sections, they are connected to a metal film 22 opposite to the gate electrode 38 via a lower connecting via 760.

[0281] Furthermore, a metal film 220 opposite to the first semiconductor chip 30a extends in the stacking direction to the outer side of the first semiconductor chip 30a. Similarly, a metal film 22 opposite to the second semiconductor chip 30b extends in the stacking direction to the outer side of the second semiconductor chip 30b.

[0282] Furthermore, a connection through-hole 61 is formed in the sealing member 60 to connect the connection pattern 99 to a metal film 22 connected to the source electrode 35 of the first semiconductor chip 30a. A connection through-hole 61 is also formed in the sealing member 60 to connect the source electrode pattern 92 to a metal film 22 connected to the source electrode 35 of the second semiconductor chip 30b. Furthermore, in the sealing member 60, in relation to… Figure 31 In different cross-sections, a connection via 61 is formed to connect a metal film 22, which is connected to the gate electrode 38 of the first semiconductor chip 30a, to the gate pad 93a. Furthermore, in the sealing member 60, in relation to... Figure 31 In different cross sections, a connecting via 61 is formed to connect a metal film 22 connected to the gate electrode 38 of the second semiconductor chip 30b to the gate pad 93a.

[0283] Such a semiconductor package 10 is used, for example, in DC / DC converter circuits and inverter circuits, with a first semiconductor chip 30a forming the upper arm and a second semiconductor chip 30b forming the lower arm. In this case, the drain pad 91a becomes the high-voltage side pad, the source pad 92a becomes the low-voltage side pad, and the connection pad 99a becomes the output pad.

[0284] As explained above, a semiconductor package 10 can also be manufactured in which two semiconductor chips 30, on which vertically shaped semiconductor elements are formed, are integrally sealed by a sealing member 60. Furthermore, in this semiconductor package 10, since the first semiconductor chip 30a and the second semiconductor chip 30b can be arranged close to each other, the wiring layer connecting the first semiconductor chip 30a and the second semiconductor chip 30b can be shortened. Therefore, parasitic inductance can be reduced.

[0285] Furthermore, in this embodiment, an example is described where the first semiconductor chip 30a and the second semiconductor chip 30b are arranged with the drain electrode 34 located on the side opposite to the heat sink 20, and the source electrode 35 and the gate electrode 38 located on the side of the heat sink 20. However, the first semiconductor chip 30a and the second semiconductor chip 30b can also be arranged such that the source electrode 35 and the gate electrode 38 are located on the side opposite to the heat sink 20, and the drain electrode 34 is located on the side of the heat sink 20. Furthermore, in such a configuration, the connection relationship of the metal film 22, the lower layer connection via 760, and the connection via 61 formed in the sealing member 60 can be appropriately adjusted so that the connection relationship between each pad 91a, 92a, 93a, 99a and the first semiconductor chip 30a and the second semiconductor chip 30b is as described above.

[0286] (21st embodiment)

[0287] The 21st embodiment will be described. This embodiment differs from the 20th embodiment described above in that the arrangement of the first semiconductor chip 30a and the second semiconductor chip 30b is changed. Everything else is the same as the 20th embodiment described above, so the description is omitted here.

[0288] In the semiconductor package 10 of this embodiment, as Figure 32 As shown, the first semiconductor chip 30a is configured such that the drain electrode 34 is located on the side opposite to the heat sink 20, while the source electrode 35 and gate electrode 38 are located on the side of the heat sink 20. On the other hand, the second semiconductor chip 30b is configured such that the drain electrode 34 is located on the side of the heat sink 20, while the source electrode 35 and gate electrode 38 are located on the side opposite to the heat sink 20. That is, the first semiconductor chip 30a and the second semiconductor chip 30b are configured in reverse order.

[0289] Furthermore, a metal film 22 formed on the insulating substrate 21 has a portion opposite to the source electrode 35 of the first semiconductor chip 30a and a portion opposite to the drain electrode 34 of the second semiconductor chip 30b, which are connected together. The source electrode 35 of the first semiconductor chip 30a and the drain electrode 34 of the second semiconductor chip 30b are respectively connected to the common metal film 22 via a lower layer connection via 760.

[0290] The drain electrode 34 of the first semiconductor chip 30a is connected to the drain pattern 91 formed on the first sealing member 90 via the upper connection via 95. The source electrode 35 of the second semiconductor chip 30b is connected to the source pattern 92 formed on the first sealing member 90 via the upper connection via 95. The gate electrode 38 of the second semiconductor chip 30b is connected to... Figure 32 In different cross sections, the gate is connected to the gate formed in the first sealing member 90 via the upper connecting through hole 95 using pattern 93.

[0291] Furthermore, a connection through hole 61 is formed in the sealing member 60, which connects the connection pattern 99 to a metal film 22 connected to the source electrode 35 of the first semiconductor chip 30a and the drain electrode 34 of the second semiconductor chip 30b.

[0292] As explained above, the first semiconductor chip 30a and the second semiconductor chip 30b can be configured in reverse. Furthermore, in such a semiconductor package 10, the source electrode 35 of the first semiconductor chip 30a and the drain electrode 34 of the second semiconductor chip 30b are connected only through a metal film 22 and a lower-layer connection via 760, thus simplifying the structure.

[0293] (22nd Embodiment)

[0294] The 22nd embodiment will be described. In this embodiment, the arrangement of the pads 91a, 92a, and 93a of the semiconductor package 10 is changed compared to the 9th embodiment. Everything else is the same as in the 9th embodiment described above, so the description is omitted here.

[0295] The semiconductor package 10 of this embodiment, when viewed from the stacking direction, is a generally planar rectangular shape having two sets of opposing first to fourth sides 10a to 10d. Furthermore, the semiconductor package 10 has a first gate pad 931a and a second gate pad 932a serving as gate pads 93a, which are disposed on the outer edge of the semiconductor package 10.

[0296] Specifically, the first gate pad 931a is disposed near the corner connecting the second side 10b and the third side 10c, and the second gate pad 932a is disposed near the corner connecting the third side 10c and the fourth side 10d. That is, the first gate pad 931a and the second gate pad 932a are disposed in opposite portions of the outer edge. More specifically, the source pad 92a is disposed all the way to the vicinity of the third side 10c, and the first gate pad 931a and the second gate pad 932a are disposed in a manner that sandwiches the source pad 92a. Furthermore, the gate electrode 38 of the semiconductor chip 30 is connected to the first gate pad 931a and the second gate pad 932a.

[0297] In this semiconductor package 10, the first gate pad 931a and the second gate pad 932a are respectively disposed in opposite portions of the outer edge. Therefore, when connecting the semiconductor package 10 to the printed circuit board 110, only one of the gate pads 931a and 932a needs to be connected to the printed circuit board 110, thus improving the wiring freedom on the printed circuit board 110 side. In this case, for example, when the first gate pad 931a is connected to the printed circuit board 110, by shortening the length of the wiring layer connecting the first gate pad 931a to the drive circuit that applies a predetermined voltage to the first gate pad 931a, the deviation of the drive voltage can be reduced. Furthermore, when connecting the semiconductor package 10 to the printed circuit board 110, the gate of one side can be connected to the printed circuit board 110 using pads 931a and 932a. Therefore, the winding of the wiring on the printed circuit board 110 side becomes easier, for example, it is possible to make a structure that does not require the wiring of the printed circuit board 110 to be wound in multiple layers. As a result, the effect of generating excess magnetic flux can be suppressed.

[0298] (23rd implementation)

[0299] The 23rd embodiment will be described. This embodiment combines the 20th embodiment with the 22nd embodiment, but changes the arrangement of the pads 91a, 92a, 93a, and 99a of the semiconductor package 10. Everything else is the same as the 22nd embodiment described above, so the description is omitted here.

[0300] The semiconductor package 10 in this embodiment is similar to that in the 22nd embodiment, having a first semiconductor chip 30a and a second semiconductor chip 30b. Furthermore, the semiconductor package 10 as... Figure 34 As shown, when viewed from the stacking direction, each pad 911a, 931a, 991a, 933a, 921a, 912a, 932a, 992a, 934a, and 922a is arranged along the outer edge.

[0301] Specifically, the semiconductor package 10 has a first drain pad 911a, a first gate pad 931a, a first connection pad 991a, a second gate pad 932a, and a first source pad 921a arranged sequentially along the second side 10b. Furthermore, a second drain pad 912a, a third gate pad 933a, a second connection pad 992a, a fourth gate pad 934a, and a second source pad 922a are arranged along the fourth side 10d. That is, each pad 911a, 931a, 991a, 932a, 921a, 912a, 933a, 992a, 934a, and 922a is located in a corresponding portion of the outer edge of the semiconductor package 10.

[0302] Additionally, although not specifically illustrated, the drain electrode 34 of the first semiconductor chip 30a is connected to the first drain pad 911a and the second drain pad 912a. The source electrode 35 of the second semiconductor chip 30b is connected to the first source pad 921a and the second source pad 922a. The source electrode 35 of the first semiconductor chip 30a and the drain electrode 34 of the second semiconductor chip 30b are connected to the first connection pad 991a and the second connection pad 992a. The gate electrode 38 of the first semiconductor chip 30a is connected to the first gate pad 931a and the third gate pad 933a. The gate electrode 38 of the second semiconductor chip 30b is connected to the second gate pad 932a and the fourth gate pad 934a.

[0303] According to the embodiment described above, the pads 911a, 931a, 991a, 932a, 921a, 912a, 933a, 992a, 934a, and 922a of the semiconductor package 10 are respectively disposed in opposite portions of the outer edge portion. Furthermore, the electrodes 34, 35, and 38 of the first semiconductor chip 30a are electrically connected to the pads 911a, 931a, and 991a arranged along the second side 10b, and electrically connected to the pads 912a, 933a, and 992a arranged along the fourth side 10d. Similarly, the electrodes 34, 35, and 38 of the second semiconductor chip 30b are electrically connected to the pads 991a, 932a, and 921a arranged along the second side 10b, and electrically connected to the pads 992a, 934a, and 922a arranged along the fourth side 10d.

[0304] Therefore, the semiconductor package 10 of this embodiment can be configured as a DC / DC converter circuit or an inverter circuit by connecting one of the pads 911a, 931a, 991a, 932a, 921a arranged along the second side 10b or the pads 912a, 933a, 992a, 934a, 922a arranged along the fourth side 10d to the printed circuit board 110. Thus, the wiring freedom on the printed circuit board 110 side can be increased, achieving the same effect as in the 22nd embodiment.

[0305] In addition, such a semiconductor package 10 can also be used, for example, in the construction of a 4-in-1 package or a 6-in-1 package.

[0306] (24th implementation)

[0307] The 24th embodiment will be described. In this embodiment, the configuration of the gate pad 93a is changed compared to the 22nd embodiment described above. Everything else is the same as the 22nd embodiment described above, so the description is omitted here.

[0308] The semiconductor package 10 in this embodiment is as follows: Figure 35 As shown, when viewed from the stacking direction, the semiconductor chip 30 is disposed approximately in the center. Furthermore, the semiconductor package 10 has drain pads 91a and source pads 92a symmetrically arranged with respect to an imaginary line K extending in one direction through the center of the semiconductor chip 30. Figure 35 In this embodiment, the drain pad 91a is arranged along the fourth side 10d, and the source pad 92a is arranged along the second side 10b. Furthermore, the gate pad 93a is arranged on the third side 10c, intersecting the imaginary line K. That is, in the semiconductor package 10 of this embodiment, there is one gate pad 93a.

[0309] According to the embodiment described above, when an electronic device 1 is constructed together with a printed circuit board 110 as in the seventh embodiment described above, the wiring freedom on the printed circuit board 110 side can be improved. That is, when constructing the electronic device 1, the wiring freedom on the printed circuit board 110 side can be improved. Figure 35 The semiconductor packaging 10 together, and also prepared Figure 36 Semiconductor package 10 as shown. Figure 36 Semiconductor package 10 relative to Figure 35 In the semiconductor package 10, the drain pad 91a and the source pad 92a are arranged in reverse order. That is, the drain pad 91a is arranged along the second side 10b, and the source pad 92a is arranged along the fourth side 10d. However, in Figure 36 In the semiconductor package 10, there is also one gate pad 93a.

[0310] Furthermore, in the case of constituting electronic device 1, it is used according to the constraints of the printed circuit board 110 side. Figure 35 Semiconductor package 10 or Figure 36 This is one side of the semiconductor package 10. Therefore, the wiring freedom on the printed circuit board 110 side can be improved. In other words, the versatility of the semiconductor package 10 can be improved. Furthermore, even with only one gate pad 93a in the semiconductor package 10 in this embodiment, the wiring freedom on the printed circuit board 110 side can still be improved. Therefore, compared with the case where two gate pads 93a are arranged in the semiconductor package 10, the semiconductor package 10 can also be miniaturized, and the wiring freedom on the printed circuit board 110 side can be improved.

[0311] Furthermore, although not specifically illustrated, in the case of forming a vertically oriented semiconductor element, the portion where the source electrode 35 can be disposed can be increased by setting only one gate electrode 38. Therefore, in such a semiconductor chip 30, it is easy to expand the effective area through which current can flow, and low on-resistance can be achieved. In other words, in the case of a semiconductor chip 30 with the same on-resistance, miniaturization of the semiconductor chip 30 can be achieved.

[0312] (25th embodiment)

[0313] The 25th embodiment will be described. This embodiment, compared to the 20th embodiment described above, includes two capacitors. Everything else is the same as the 20th embodiment described above, so the description is omitted here.

[0314] In this embodiment, such as Figure 37 As shown, together with the first semiconductor chip 30a and the second semiconductor chip 30b, a first capacitor 151 having a pair of electrodes 151a and 151b and a second capacitor 152 having a pair of electrodes 152a and 152b are disposed within the sealing member 60. Furthermore, Figure 37 This is consistent with the description in the 20th embodiment above. Figure 32 Different cross-sections, the first semiconductor chip 30a and the second semiconductor chip 30b are arranged in relation to... Figure 37 In different cross sections. Furthermore, in this embodiment, the first capacitor 151 and the second capacitor 152 are made of silicon or the like, and have a thickness approximately equal to that of the semiconductor chip 30.

[0315] The first capacitor 151 and the second capacitor 152 are disposed on the lower plate member 740 in the same manner as the first semiconductor chip 30a and the second semiconductor chip 30b. Specifically, the first capacitor 151 and the second capacitor 152 are disposed on the lower plate member 740 with one electrode 151b, 152b located on the side of the lower plate member 740 and the other electrode 151a, 152a located on the side of the first sealing member 90.

[0316] Furthermore, the electrode 151a of the first capacitor 151 is connected to the drain pattern 91 formed on the first sealing member 90 via the upper connection via 95. The electrode 152a of the second capacitor 152 is connected to the source pattern 92 formed on the first sealing member 90 via the upper connection via 95. Additionally, the electrodes 151b of the first capacitor 151 and 152b of the second capacitor 152 are connected to a metal film 22 via a lower connection via 760. That is, in this embodiment, the series structure of the first semiconductor chip 30a and the second semiconductor chip 30b is connected in parallel to the series structure of the first capacitor 151 and the second capacitor 152. Furthermore, in this embodiment, the drain pattern 91, the source pattern 92, the upper connection via 95, the metal film 22, and the lower connection via 760 correspond to wiring layers.

[0317] Therefore, the first capacitor 151 and the second capacitor 152 are disposed together with the first semiconductor chip 30a and the second semiconductor chip 30b. Thus, by arranging the first semiconductor chip 30a and the second semiconductor chip 30b, and the first capacitor 151 and the second capacitor 152 close together, the wiring layers connecting them can be shortened. Therefore, parasitic inductance can be reduced. Furthermore, compared to the 25th embodiment described later, the enlargement of the semiconductor package 10 in the thickness direction can be suppressed.

[0318] Furthermore, the above description illustrates an example of the series connection of the first capacitor 151 and the second capacitor 152 relative to the series connection of the first semiconductor chip 30a and the second semiconductor chip 30b. However, the first capacitor 151 and the second capacitor 152 may also be connected in parallel relative to the series connection of the first semiconductor chip 30a and the second semiconductor chip 30b, respectively.

[0319] Furthermore, the first capacitor 151 and the second capacitor 152 may also be formed thinner than the first semiconductor chip 30a and the second semiconductor chip 30b, similar to the 17th embodiment described above.

[0320] (26th embodiment)

[0321] The 26th embodiment will be described. This embodiment differs from the 25th embodiment described above in that the arrangement of the first capacitor 151 and the second capacitor 152 is changed. Everything else is the same as the 25th embodiment described above, so the description is omitted here.

[0322] In this embodiment, such as Figure 38 As shown, a first capacitor 151 is disposed on a first semiconductor chip 30a, and a second capacitor 152 is disposed on a second semiconductor chip 30b. In this embodiment, the first capacitor 151 and the second capacitor 152 are configured such that a pair of electrodes 151a, 151b, 152a, and 152b are located on the second sealing member 100 along the planar direction of the semiconductor package 10.

[0323] The sealing member 60 is configured to seal both the first capacitor 151 and the second capacitor 152. In this embodiment, the sealing member 60 includes an upper sealing member 180 disposed on the second sealing member 100. Furthermore, the upper sealing member 180 is constructed by stacking an upper plate-shaped member 940 with the same structure as the middle plate-shaped member 840, and appropriately forms an upper pattern 950 and an upper connecting through-hole 960.

[0324] Furthermore, the upper sealing member 180 has a contact hole 181 formed on the portion located most opposite to the insulating substrate 21, exposing the upper pattern 950 that is connected to the drain pattern 91, the source pattern 92, and the connection pattern 99. The portion of the upper pattern 950 exposed from the contact hole 181 becomes the drain pad 91a, the source pad 92a, and the connection pad 99a. Additionally, in relation to... Figure 38 In different cross sections, the upper pattern 950 also constitutes the gate pad 93a.

[0325] Furthermore, the drain electrode 34 of the first semiconductor chip 30a is connected to the drain pad 91a via the upper connection via 97, the drain pattern 91, and the upper connection via 960. The source electrode 35 of the second semiconductor chip 30b is connected to the source pad 92a via the upper connection via 97, the source pattern 92, and the upper connection via 960. The connection pattern 99 is connected to the connection pad 99a via the upper connection via 97 and the upper connection via 960. The gate electrode 38 of the first semiconductor chip 30a and the gate electrode 38 of the second semiconductor chip 30b are connected to... Figure 38 In different cross sections, the gate is connected to the gate pad 93a via the upper connection via 95, the gate pattern 93, the upper connection via 960, etc.

[0326] One electrode 151a of the first capacitor 151 is connected to the upper pattern 950 constituting the drain pad 91a via an upper connection via 960 formed in the upper sealing member 180. The other electrode 151b of the second capacitor 152 is connected to the upper pattern 950 constituting the source pad 92a via an upper connection via 960 formed in the upper sealing member 180. The other electrode 151b of the first capacitor 151 and the electrode 152a of the second capacitor 152 are connected to... Figure 38 Different cross sections are connected via an upper pattern 950 and an upper connecting through hole 960 formed on the upper sealing member 180.

[0327] Thus, even if the first capacitor 151 and the second capacitor 152 are stacked relative to the first semiconductor chip 30a and the second semiconductor chip 30b, the same effect as in the 24th embodiment described above can be obtained. Furthermore, in such a semiconductor package 10, compared to the 24th embodiment described above, the increase in size in the planar direction can be suppressed.

[0328] (27th implementation)

[0329] The 27th embodiment will be described. In this embodiment, compared to the first embodiment described above, the semiconductor package 10 is provided with connection bumps. Everything else is the same as in the first embodiment described above, so descriptions are omitted here.

[0330] In the semiconductor package 10 of this embodiment, as Figure 39 As shown, connection bumps 190 are disposed on the drain pad 91a and the source pad 92a. Additionally, in relation to... Figure 39 In different cross sections, connection bumps 190 are also provided on the gate pad 93a. The connection bumps 190 are, for example, made of a sintered body with silver and tin as the main components.

[0331] The above describes the structure of the semiconductor package 10 according to this embodiment. Next, referring to... Figure 40A , Figure 40B The manufacturing method of the semiconductor package 10 described above will be explained.

[0332] First, such as Figure 40A As shown, a bump construct 1900 is prepared, having an LCP film 191 and a release member 192 made of a Teflon (registered trademark) film disposed on the LCP film 191. Next, a through-hole 193 is formed in the bump construct 1900, and a bump construct member 190a constituting the bump is disposed in the through-hole 193. The through-hole 193 is formed at a position and size corresponding to the contact hole 101. The bump construct member 190a is constructed by applying conductive paste using a printing method or the like. The conductive paste, for example, uses a material in which powder with silver-tin as the main component is mixed into an organic solvent. In this case, temporary sintering or the like is performed as needed to evaporate the organic solvent to prevent the conductive paste from overflowing from the through-hole 193.

[0333] Furthermore, the planar dimension of the protrusion component 1900 is the same as that of the first component 900, etc. And, in Figure 40A , Figure 40B The figure shows a method for manufacturing one semiconductor package 10, but in practice, multiple semiconductor packages 10 are manufactured together as described in the first embodiment above.

[0334] Next, as Figure 40B As shown, for those that have progressed to the equivalent of Figure 5F The process involves arranging a bump component 1900 such that the bump component 190a is positioned on the contact hole 101. While heating, pressure is applied in the lamination direction to form a connecting bump 190 from the bump component 1900, and the connecting bump 190 is connected to each of the pads 91a, 92a, and 99a. Then, the connecting bump 190 is left on each of the pads 91a, 92a, and 99a, and the bump component 1900 is removed from the second component 1000 using a stripping member 192. Thus, the connecting bump 190 is positioned on each of the pads 91a, 92a, and 99a.

[0335] Then, although not specifically illustrated, the process involves dividing the chip into chip units along the cutting line DL, and then manufacturing... Figure 39 The semiconductor package 10 shown.

[0336] Therefore, when the semiconductor package 10 is mounted to the printed circuit board 110 via solder 120 as described in the seventh embodiment above, it is easy to ensure the spacing between the semiconductor package 10 and the printed circuit board 110, and it is easy to ensure the thickness of the solder 120. Thus, height deviation of the solder 120 can be suppressed. Furthermore, since the spacing between the semiconductor package 10 and the printed circuit board 110 is easily ensured, the injectability of the underfill 130 can also be improved.

[0337] (28th embodiment)

[0338] The 28th embodiment will be described. This embodiment differs from the first embodiment described above in that the method for manufacturing the semiconductor package 10 is changed. Everything else is the same as the first embodiment described above, so the description is omitted here.

[0339] First, in the first embodiment described above, a semiconductor package 10 is manufactured by preparing a constituent substrate 210, which serves as a multi-layer substrate. In this case, for example, Figure 41 As shown, the inner edge portion of the substrate 210 is used as the constituting region 210a and the outer edge portion of the substrate 210 is used as the auxiliary region 210b. While forming positioning holes and the like in the auxiliary region 210b, the semiconductor package 10 is manufactured from the constituting region 210a.

[0340] In addition, Figure 41 In this substrate 210, the area where a metal film 22 is disposed is the constitutive region 210a. Furthermore, the auxiliary region 210b is disposed to surround the constitutive region 210a. In such a constitutive substrate 210, the auxiliary region 210b is prone to becoming a wasted area.

[0341] Therefore, in this embodiment, as Figure 42 As shown, the outer edge portion of the substrate 210 is also used as the constitutive region 210a for constituting the semiconductor package 10. Furthermore, a portion of the outer edge portion of the substrate 210 is used as an auxiliary region 210b. That is, the outer edge portion of the substrate 210 is in a state where the constitutive region 210a and the auxiliary region 210b coexist.

[0342] In this embodiment, when the substrate 210 is made into a planar rectangular shape, the corner portions are designated as auxiliary regions 210b. Furthermore, in Figure 42 In this case, the area where no metal film 22 is formed is called auxiliary region 210b. Auxiliary region 210b is as follows: Figure 42 As shown, it is preferable to arrange the substrate 210 in an asymmetrical manner relative to the center of the substrate 210. This makes it easy to determine the positional relationship of the substrate 210 and facilitates positioning.

[0343] Therefore, it is not necessary to arrange the auxiliary region 210b in the entire outer edge of the substrate 210, so the substrate 210 can be utilized effectively. Furthermore, the manufacturing method of the first embodiment described above has been used as an example, but the same applies when manufacturing the semiconductor package 10 of the second and ninth embodiments described above.

[0344] (29th embodiment)

[0345] The 29th embodiment will be described. In this embodiment, compared to the first embodiment described above, grooves are formed in the side component 700, the first component 900, and the second component 1000. Everything else is the same as in the first embodiment described above, so descriptions are omitted here.

[0346] In this embodiment, such as Figure 43 As shown, in Figure 5E In the process, the parts that form the cutting line DL in the side component 700, the first component 900 and the second component 1000 are respectively stacked to form the groove portion 701, 901 and 1001.

[0347] In addition, grooves 701, 901, and 1001 pass through Figures 5B to 5D The side component 700, the first component 900, and the second component 1000 are formed respectively during the process of preparing them. Furthermore, the grooves 701, 901, and 1001 are formed, for example, by laser processing. In this embodiment, the grooves 211 are not formed in the substrate 210, but they can also be formed in the substrate 210. Then, by processes such as... Figure 5F That way, they are heated and pressurized simultaneously, integrating them into one unit.

[0348] In this way, even if grooves 701, 901, and 1001 are formed in the side component 700, the first component 900, and the second component 1000, cutting can be easily performed. Furthermore, by forming grooves 701, 901, and 1001 in the side component 700, the first component 900, and the second component 1000, cutting can be easily performed. Figure 5F After integration in the process, the thermal shrinkage of the LCP film that makes up each component 700, 900, and 1000 can be reduced through the grooves 701, 901, and 1001.

[0349] In addition, in this embodiment, an example is described in which the grooves 701, 901, and 1001 are formed before the side component 700, the first component 900, and the second component 1000 are integrated. However, for example, the groove 1001 may be formed in the second component 1000 after the side component 700, the first component 900, and the second component 1000 are integrated.

[0350] (30th embodiment)

[0351] The 30th embodiment will be described. This embodiment, compared to the 9th embodiment described above, specifies a method for manufacturing the plate-shaped member 74. Everything else is the same as in the 9th embodiment described above, so the description is omitted here.

[0352] In this embodiment, the plate-shaped member 74 constituting the sealing member 60 is manufactured as follows. That is, firstly, as... Figure 44A As shown, LCP membrane component 7400 is prepared. At this time, LCP membrane component 7400 is as follows... Figure 45A As shown, the internal state becomes an amorphous state.

[0353] Next, the LCP membrane component 7400 is subjected to heat treatment, such as... Figure 45B The material is crystallized as shown. Furthermore, the heat treatment is performed at a temperature lower than the melting point of the LCP film component 7400, approximately 300°C, for several tens of minutes to several hours. In this case, it is preferable to gradually increase the temperature from approximately 270°C to approximately 300°C. This helps to suppress the melting of the LCP film component 7400.

[0354] In addition, in relation to Figure 44A In different processes, such as Figure 44B As shown, component 7500 is prepared from metal sheets such as copper. Then, as... Figure 44C As shown, a plate-shaped component 770 is formed by laminating an LCP film component 7400 and a metal sheet component 7500 together. The lamination process is performed while heating and pressurizing. However, the heating time during the lamination of the LCP film component 7400 and the metal sheet component 7500 is very short compared to the process of heating the LCP film component 7400 to crystallize it. Therefore, the LCP film component 7400 will not crystallize solely through heating during this lamination process.

[0355] Then, although not specifically illustrated, after appropriate cutting or other processes as needed, the pattern 75 is etched or otherwise formed into the desired shape, and a sintered body or conductive paste constituting the connecting through-hole 76 is configured to form a plate-shaped component 74.

[0356] In addition, the plate-shaped component 770 is described here as an example, but the first component 900 and the second component 1000 are also formed in the same way.

[0357] As a result, the LCP film component 7400 crystallizes, so when the plate-shaped component components 770 (i.e., plate-shaped components 74) and the semiconductor chip 30 are integrated while heating and pressurizing, the misalignment of the pattern 75 and the connecting vias 76 can be suppressed. Therefore, it is possible to suppress the situation where electrical connections between adjacent plate-shaped components 74 in the stacking direction are not achieved.

[0358] (31st embodiment)

[0359] The 31st embodiment will be described. In this embodiment, compared to the 9th embodiment described above, a semiconductor package 10 is mounted on a printed circuit board 110 to form an electronic device 1. Everything else is the same as in the 9th embodiment described above, so descriptions are omitted here.

[0360] In this embodiment, such as Figure 46 As shown, an electronic device 1 is constructed having a semiconductor package 10, a printed circuit board 110, a cooler 140, and a pressing component 300.

[0361] The printed circuit board 110 has a through hole 116 extending in the thickness direction. Furthermore, a plurality of terminal portions 117 are formed on the printed circuit board 110, exposing themselves from the through hole 116. Additionally, in... Figure 46 In the diagram, the structure of the printed circuit board 110 is simplified, but the printed circuit board 110 and... Figure 15 Similarly, the printed circuit board 110 is appropriately formed with a wiring pattern 111, through-hole electrodes 113, etc.

[0362] Furthermore, the semiconductor package 10 is connected to the printed circuit board 110 by connecting the drain pad 91a and the source pad 92a to the terminal portion 117 via solder 120. Figure 46 In different cross sections, the semiconductor package 10 is connected to the printed circuit board 110 by connecting the gate pad 93a to the terminal portion 117 via solder 120.

[0363] Furthermore, the heat dissipation component 20 of the semiconductor package 10 is connected to the cooler 140 via a connecting component 141 such as grease.

[0364] The pressing member 300 is constructed of a housing or the like and has a pressing portion 301 protruding in one direction. The pressing portion 301 is made of an elastomer such as rubber and has the same number of terminal portions 117 as the number of terminals connected to the semiconductor package 10. In this embodiment, the terminal portions 117 are connected to the drain pad 91a, the source pad 92a, and the gate pad 93a, so it has three pressing portions 301.

[0365] Furthermore, the pushing member 300 is configured such that the portion of the terminal portion 117 of the printed circuit board 110 that is connected to each of the pads 91a, 92a, and 93a is pushed toward the semiconductor package 10 by the pushing member 301.

[0366] In this way, the electronic device 1 can be constructed using the semiconductor package 10. Furthermore, in the electronic device 1 of this embodiment, since the portions of the terminal portion 117 connected to each of the pads 91a, 92a, and 93a are pushed, the spacing deviation between the semiconductor package 10 and the cooler 140 can be suppressed, and heat dissipation can be improved by making it easy to narrow the spacing.

[0367] (32nd embodiment)

[0368] The 32nd embodiment will be described. This embodiment differs from the 30th embodiment described above in that the structure of the electronic device 1 is modified. Everything else is the same as the 30th embodiment described above, so the description is omitted here.

[0369] The printed circuit board 110 of the electronic device 1 in this embodiment is as follows: Figure 47 As shown, no holes 116 are formed in the printed circuit board 110, which is the same structure as in the seventh embodiment. Furthermore, the printed circuit board 110 is fixed to the cooler 140 by fastening components 118 such as screws. Additionally, in Figure 47 The structure of the printed circuit board 110 is simplified and shown in the figure, but the printed circuit board 110 and Figure 15 Similarly, the printed circuit board 110 has a wiring pattern 111, through-hole electrodes 113, etc.

[0370] The drain pad 91a and source pad 92a of the semiconductor package 10 are respectively connected to the wiring pattern 112 on the other side of the printed circuit board 110 via solder 120. Furthermore, in conjunction with... Figure 13 In different cross sections, the gate pad 93a of the semiconductor package 10 is connected to the wiring pattern 112 on the other side of the printed circuit board 110 via solder 120. Furthermore, an underfill 130 is disposed between the printed circuit board 110 and the semiconductor package 10.

[0371] The pushing part 301 of the pushing member 300 can push the printed substrate 110 as a whole toward the cooler 140. Furthermore, the pushing member 300 pushes the semiconductor package 10 toward the cooler 140 by pushing the printed substrate 110 toward the cooler 140.

[0372] Even so, by pressing the semiconductor package 10 through the printed circuit board 110, the same effect as in the 30th embodiment described above can be obtained. Furthermore, by directly pressing the printed circuit board 110, the warping of the printed circuit board 110 to the opposite side of the semiconductor package 10 and the thickness deviation of the printed circuit board 110 can be easily absorbed by the pressing part 301.

[0373] (33rd implementation)

[0374] The 33rd embodiment will be described. This embodiment, compared to the 9th embodiment described above, constitutes an electronic device 1. Everything else is the same as the 9th embodiment described above, so the description is omitted here.

[0375] The electronic device 1 in this embodiment is as follows: Figure 48 As shown, a recess 142 is formed on the cooler 140. Furthermore, the semiconductor package 10 is disposed via a sealing member 143, such as an O-ring, to block the opening end of the recess 142. The recess 142 is connected to a cooling pipe (not shown), through which the cooling medium flows. That is, the recess 142 is formed to constitute a cooling passage 142a for the flow of the cooling medium. The cooling medium may be, for example, water or a common antifreeze.

[0376] Furthermore, in this embodiment, the other side 21b of the insulating substrate 21 has a textured structure 21c. Additionally, in Figure 48 Although omitted, in the same manner as in the 31st embodiment described above, each of the pads 91a, 92a, and 93a of the semiconductor package 10 is electrically connected to the printed circuit board 110.

[0377] In this electronic device 1, the cooling medium flows within the recess 142, thereby further improving heat dissipation. Furthermore, in the electronic device of this embodiment, a textured structure 21c is formed on the other side 21b of the insulating substrate 21, increasing the contact area between the heat dissipation component 20 and the cooling medium. Therefore, heat dissipation can be further improved.

[0378] (Other implementation methods)

[0379] The present invention has been described according to embodiments, but it should be understood that the invention is not limited to these embodiments and constructions. The invention also includes various modifications and equivalent variations. In addition, various combinations and forms, and even combinations and forms that include only one element or more thereof, also fall within the scope and spirit of the invention.

[0380] In the above embodiments, the bonding of the components may be improved by mechanical bonding rather than chemical bonding. For example, in the first embodiment described above, the heat dissipation component 20 and the sealing component 60 may be roughened by plasma irradiation or the like, thereby improving the bonding through the anchoring effect.

[0381] Furthermore, in the first embodiment described above, the other metal film 23 may not be formed symmetrically with the other metal film 22, or it may not be configured at all. Additionally, the bonding member 50 may be configured within the semiconductor chip 30 in the stacking direction. Furthermore, the heat dissipation member 20 may be configured within the sealing member 60 in the stacking direction. Even with such a structure, by using LCP to construct the sealing member 60, the same effects as in the first embodiment described above can be obtained. Furthermore, in the other embodiments described above, these structures can be appropriately modified to include both the other metal film 22 and the other metal film 23.

[0382] Furthermore, in the first embodiment described above, for example, instead of sintering the body 73a in the second through hole 72 of the side component 700, a metal film (i.e., the lower connecting through hole 73) may be disposed in the second through hole 72 by a CVD method or the like. Such a structure is also applicable to the first component 900. Moreover, these structures can be appropriately applied in other embodiments.

[0383] Furthermore, in the above embodiments, the semiconductor chip 30 may also be formed with a superjunction MOSFET or an IGBT. In addition, the semiconductor chip 30 may be formed using a support substrate 31 made of gallium oxide, gallium nitride, or the like, instead of a support substrate 31 made of silicon or SiC.

[0384] Furthermore, in the first embodiment described above, during the manufacture of the semiconductor package 10, in Figure 5E and Figure 5F The process can also be like this: That is, in... Figure 5EIn the process, after the side component 700 is disposed on the substrate 210 and the semiconductor chip 30 is disposed in the first through hole 71 via the sintered body 50a, they can be temporarily bonded at a low temperature. Then, the first component 900 and the second component 1000 can be sequentially stacked on the side component 700 and the semiconductor chip 30, and the process can be performed. Figure 5F The process can be integrated. Similarly, in the second embodiment described above, the first component 900 and the second component 1000 can be integrated by stacking after the plate-shaped component 770 constituting the side sealing component 70 is temporarily bonded to the semiconductor chip 30, etc. Furthermore, these manufacturing methods can be appropriately applied in the above embodiments.

[0385] Furthermore, in the above embodiments, such as Figure 49 As shown, slits 91b to 93b can also be formed in each of the patterns 91 to 93 formed in the first sealing member 90. Specifically, in each pattern 91 to 93, slits 91b to 93b are formed where the portion different from the portion connected to the upper connecting through holes 95 and 97 has been removed. As a result, stress can be released by the slits 91b to 93b, thus mitigating the stress applied to the upper connecting through holes 95 and 97 from each pattern 91 to 93. In this case, for example, as with the upper connecting through hole 97 connected to the source pattern 92, by forming slits 92b in the stacking direction in a manner that substantially surrounds the upper connecting through hole 97, the stress applied to the upper connecting through hole 97 can be further mitigated. Alternatively, slits 91b to 93b may not be formed in each of the patterns 91 to 93, but rather in one or two patterns.

[0386] Furthermore, in the ninth embodiment described above, the lower layer connecting through hole 760 can also be... Figure 50 It is made into a cylindrical shape as shown. Furthermore, this lower-layer connection through-hole 760 can be applied to various embodiments having a lower-layer connection through-hole 760.

[0387] Furthermore, in the ninth embodiment described above, each pad 91a, 92a, and 93a can also be as follows: Figure 51 As shown, the pads 91a, 92a, and 93a are formed in a different position in the stacking direction than the via 61. In other words, each pad 91a, 92a, and 93a can also be formed in a position in the stacking direction that does not overlap with the via 61. Therefore, when the printed circuit board 110 is mounted to each pad 91a, 92a, and 93a via solder 120, the stress applied to the via 61 can be reduced, and damage to the via 61 can be suppressed. In this case, the source pad 92a can be formed in a position in the stacking direction as shown. Figure 51 It can also be configured as shown between the connecting via 61 and the semiconductor chip 30, or as shown in the diagram. Figure 52As shown, it is positioned on the opposite side of the semiconductor chip 30, separated by a connecting via 61.

[0388] Furthermore, such as Figure 53 As shown, alternatively, multiple vias 61 can be arranged circumferentially around each pad 91a, 92a, 93a at positions different from each pad 91a, 92a, 93a in the stacking direction. In this case, the multiple vias 61 are preferably arranged at equal intervals in the circumferential direction. Therefore, when the printed circuit board 110 is mounted to each pad 91a, 92a, 93a via solder 120, stress is easily distributed across each via 61, suppressing the application of excessive stress to the semiconductor chip 30. Furthermore, these... Figures 51-53 Such a structure can also be appropriately applied to the above-described embodiments.

[0389] Furthermore, the above embodiments can be appropriately combined. For example, the second embodiment can be appropriately combined with other embodiments to form the side sealing member 70 using multiple plate-shaped members 74. Furthermore, the third embodiment can be appropriately combined with other embodiments to form the joining member 50 joined to the connecting through-hole 61 without having one metal film 22 and the other metal film 23. Furthermore, the fourth embodiment can be appropriately combined with other embodiments to form a connecting through-hole 61 that connects the drain pattern 91 to the drain region 22a, thus having multiple connecting through-holes 61. Furthermore, the fifth embodiment can be appropriately combined with other embodiments to include a test pattern 98. Furthermore, the sixth embodiment can be appropriately combined with other embodiments to form a semiconductor chip 30 with an insulating substrate 41, and the heat dissipation member 20 is composed of a metal plate 24. Furthermore, the seventh embodiment can be appropriately combined with other embodiments to integrally seal multiple semiconductor chips 30 with the sealing member 60. Furthermore, the eighth to 32 embodiments can also be appropriately applied respectively. Furthermore, the forms that combine the above-described embodiments can be further combined with each other.

Claims

1. A semiconductor package, comprising sealing a semiconductor chip on which semiconductor elements are formed with a sealing component, characterized in that, have: The aforementioned semiconductor chips; Heat dissipation components, equipped with the aforementioned semiconductor chips; and The aforementioned sealing component seals the aforementioned semiconductor chip; The aforementioned sealing component has a portion made of a liquid crystal polymer film; At least one of the interfaces of the different components, including the interface between the aforementioned heat dissipation component and the aforementioned sealing component, is joined by chemical bonding; The above chemical bonding is a covalent bond bonding.

2. The semiconductor package as described in claim 1, characterized in that, In the stacking direction of the heat dissipation component and the semiconductor chip, the heat dissipation component is sized such that the sealing component is located inside the heat dissipation component.

3. The semiconductor package as described in claim 1 or 2, characterized in that, The sealing member described above has a surface sealing member that seals the portion of the semiconductor chip opposite to the heat dissipation member, and a side sealing member that seals the portion of the semiconductor chip that is different from the portion sealed by the surface sealing member. The semiconductor chip is formed as a semiconductor element having a first electrode and a second electrode and through which current flows; In the aforementioned sealing component, a first pattern electrically connected to the first electrode and a second pattern electrically connected to the second electrode are formed.

4. The semiconductor package as described in claim 3, characterized in that, The aforementioned semiconductor element is a horizontal element through which current flows in the surface direction of the aforementioned semiconductor chip.

5. The semiconductor package as described in claim 3, characterized in that, The aforementioned semiconductor element is a vertical element through which current flows in the thickness direction of the aforementioned semiconductor chip.

6. The semiconductor package as described in claim 3, characterized in that, The aforementioned semiconductor chip has a shape with opposing sides and a gate electrode for controlling the current flowing between the first electrode and the second electrode. In the aforementioned sealing member, a gate pattern electrically connected to the gate electrode is formed, and a contact hole is formed to expose the gate pattern and form a gate pad. The gate pad is provided in two parts, one of which is located on one side of the opposite side and the other is located on the other side of the opposite side.

7. The semiconductor package as described in claim 3, characterized in that, The portion of the semiconductor chip that differs from the portions forming the first electrode and the second electrode is covalently bonded to the sealing component.

8. The semiconductor package as described in claim 3, characterized in that, A liquid crystal polymer constituting the sealing member is disposed between the first pattern and the second pattern.

9. The semiconductor package as described in claim 3, characterized in that, In the aforementioned sealing component, an upper connecting through hole is formed to connect the first electrode to the first pattern and an upper connecting through hole to connect the second electrode to the second pattern; In at least one of the first pattern and the second pattern described above, a slit is formed after removing a portion that is different from the portion connecting the upper connecting through hole.

10. The semiconductor package as described in claim 3, characterized in that, In the aforementioned sealing component, a contact hole is formed to expose the first pattern and form a pad, and a contact hole is formed to expose the second pattern and form a pad. The aforementioned pads are provided with connection bumps.

11. The semiconductor package as described in claim 3, characterized in that, The aforementioned semiconductor chip is mounted on the aforementioned heat dissipation component via a bonding component.

12. The semiconductor package as claimed in claim 11, characterized in that, In the stacking direction of the heat dissipation component and the semiconductor chip, the bonding component is sized such that the semiconductor chip is located within the bonding component.

13. The semiconductor package as claimed in claim 11, characterized in that, The aforementioned heat dissipation component has an insulating substrate and a metal film formed on one side of the insulating substrate; The aforementioned joining components are made of a conductive material; The semiconductor chip has an electrode formed on the side opposite to the heat dissipation component. The electrode is electrically and mechanically connected to the metal film via the bonding component when the other electrode is opposite to the metal film. In the aforementioned sealing component, a connecting through hole is formed to electrically connect the first pattern or the second pattern to one side of the metal film.

14. The semiconductor package as claimed in claim 13, characterized in that, The aforementioned heat dissipation component has a metal film formed on the opposite side of the aforementioned insulating substrate.

15. The semiconductor package as described in claim 14, characterized in that, The aforementioned metal film on one side and the aforementioned metal film on the other side are of the same shape and are symmetrically formed sandwiching the aforementioned insulating substrate.

16. The semiconductor package as claimed in claim 13, characterized in that, The aforementioned metal film is divided into multiple regions, including a first region and a second region; In the sealing member described above, a connecting through hole is formed to connect the first pattern to the first region, and a connecting through hole is formed to connect the second pattern to the second region. The semiconductor chip is disposed on the second region of the metal film via the bonding member.

17. The semiconductor package as claimed in claim 13, characterized in that, The aforementioned side sealing component is made of injection-molded material.

18. The semiconductor package as claimed in claim 3, characterized in that, The aforementioned heat dissipation component has an insulating substrate and a metal film formed on one side of the insulating substrate; The aforementioned side sealing component is stacked with a plurality of plate-shaped components having a liquid crystal polymer film and a connecting through hole disposed on the liquid crystal polymer film and penetrating the liquid crystal polymer film in the thickness direction, and having a lower plate-shaped component disposed between the semiconductor chip and the heat dissipation component and a middle plate-shaped component disposed on the lower plate-shaped component; The aforementioned middle-layer plate-shaped component has a middle-layer connecting via formed in the aforementioned liquid crystal polymer film as the aforementioned connecting via; The lower plate-shaped component is formed with a lower connecting via that connects the semiconductor chip to the metal film on one side, and a lower connecting via that connects the middle connecting via formed in the middle plate-shaped component to the metal film on one side.

19. The semiconductor package as claimed in claim 18, characterized in that, The lower layer connection vias that connect the semiconductor chip to the metal film are provided in a plurality of manner.

20. The semiconductor package as claimed in claim 19, characterized in that, The lower-layer connection via that connects the semiconductor chip to the metal film is only connected to the inner edge of the semiconductor chip.

21. The semiconductor package as claimed in claim 19, characterized in that, The connection area of ​​the portion of the lower layer connecting via that connects the semiconductor chip to the metal film is greater than the connection area of ​​the portion that connects to the outer edge of the semiconductor chip.

22. The semiconductor package as claimed in claim 19, characterized in that, The aforementioned lower plate-shaped component is formed by sequentially stacking the first lower plate-shaped component and the second lower plate-shaped component from the heat dissipation component side; As a lower layer connection via connecting the semiconductor chip to the metal film, a first lower layer connection via is formed in the first lower layer plate-shaped component, and a second lower layer connection via is formed in the second lower layer plate-shaped component. The first lower layer connection via and the second lower layer connection via are formed at different positions in the stacking direction of the heat dissipation component and the semiconductor chip, and the diameter of the first lower layer connection via is larger than the diameter of the second lower layer connection via.

23. The semiconductor package as described in claim 18, characterized in that, Multiple of the aforementioned middle-layer plate-shaped components are stacked on top of the aforementioned lower-layer plate-shaped components; The intermediate layer connecting through holes of adjacent intermediate layer plate-shaped components in the stacking direction of the aforementioned intermediate layer plate-shaped components are directly connected.

24. The semiconductor package as claimed in claim 11, characterized in that, The aforementioned heat dissipation components have an insulating substrate; The aforementioned joining components are made of a conductive material; The semiconductor chip has an electrode formed on the side opposite to the heat dissipation component, and the electrode is electrically and mechanically connected to the bonding component. In the aforementioned sealing member, a connecting through hole is formed to electrically connect the aforementioned first pattern or the aforementioned second pattern to the aforementioned joining member.

25. The semiconductor package as described in claim 13, characterized in that, In the aforementioned sealing component, a test pattern is formed that is separated from the aforementioned first pattern and the aforementioned second pattern; In the aforementioned sealing component, a connecting through hole is formed to connect the aforementioned test pattern with the portion connecting the aforementioned second pattern.

26. The semiconductor package as claimed in claim 13, characterized in that, The aforementioned insulating substrate is made of silicon nitride.

27. The semiconductor package as claimed in claim 11, characterized in that, The aforementioned joining components are made of sintered bodies.

28. The semiconductor package as claimed in claim 27, characterized in that, The aforementioned joining components are composed of a sintered body with silver and tin as the main components.

29. The semiconductor package as described in claim 3, characterized in that, The aforementioned semiconductor chip is constructed by sequentially stacking a semiconductor chip insulating substrate, a first substrate, and a second substrate; The first substrate protrudes from the second substrate in the stacking direction of the insulating substrate for the semiconductor chip, the first substrate, and the second substrate, and an electrode film is formed on the protruding portion. In the aforementioned sealing component, a connecting through hole is formed to electrically connect the first pattern or the second pattern to the electrode film.

30. The semiconductor package as claimed in claim 29, characterized in that, The aforementioned heat dissipation components are made of metal plates.

31. The semiconductor package as described in claim 1 or 2, characterized in that, In the aforementioned sealing component, a capacitor is disposed together with the aforementioned semiconductor chip; The capacitor and the semiconductor chip are electrically connected via a wiring layer formed on the sealing component.

32. The semiconductor package as described in claim 1 or 2, characterized in that, The heat dissipation component has a roughened portion at the part where it engages with the sealing component.

33. The semiconductor package as described in claim 1 or 2, characterized in that, The aforementioned heat dissipation component has a recess; The semiconductor chip is disposed in the recess with the portion protruding from the recess on the opposite side of the heat dissipation component.

34. The semiconductor package as described in claim 1 or 2, characterized in that, Another heat dissipation component is disposed on the side opposite to the aforementioned heat dissipation component, separated from the aforementioned sealing component.

35. The semiconductor package as described in claim 1 or 2, characterized in that, It has a high heat dissipation component, which is disposed on the side opposite to the sealing component and separated from the heat dissipation component, and is made of a material with a higher thermal conductivity than the heat dissipation component.

36. The semiconductor package as described in claim 1 or 2, characterized in that, The sealing component exposes pads that are electrically connected to the semiconductor chip on the side opposite to the heat dissipation component.

37. An electronic device comprising a semiconductor package in which a semiconductor chip having semiconductor elements formed thereon is sealed by a sealing member, characterized in that, have: The semiconductor package of claim 36; A cooler, connected to the heat dissipation component in the aforementioned semiconductor package; and The mounted component is electrically connected to the pads of the aforementioned semiconductor package.

38. The electronic device as claimed in claim 37, characterized in that, The aforementioned mounted component has a through hole in the thickness direction and a plurality of terminal portions exposed from the through hole; The pads of the aforementioned semiconductor package are connected to the aforementioned terminal portion; It has a pressing member that presses the portion of the terminal section that is connected to the solder pad.

39. The electronic device as claimed in claim 37, characterized in that, The aforementioned installed components are fixed to the aforementioned cooler via fastening components; It has a pushing member that pushes the semiconductor package toward the cooler side by pushing the mounted component toward the cooler side.

40. The electronic device as claimed in claim 37, characterized in that, The aforementioned cooler has a recess through which the cooling medium flows; The semiconductor package is configured such that the heat dissipation component blocks the recess.

41. A method for manufacturing a semiconductor package, comprising sealing a semiconductor chip on which semiconductor elements are formed with a sealing component, characterized in that, Perform the following procedures: A substrate is prepared by dividing multiple parts that constitute heat dissipation components using cutting lines. Prepare the aforementioned semiconductor chips; The semiconductor chip is disposed on the portion of the substrate that constitutes a heat dissipation component via a bonding component; On the aforementioned substrate, a sealing component for housing the aforementioned semiconductor chip is disposed; While applying pressure and heating in the stacking direction of the above-mentioned substrate and the above-mentioned semiconductor chip, the sealing component is formed to seal the portion of the semiconductor chip that is different from the portion that is joined to the joining component and to join to the above-mentioned substrate. Divide along the aforementioned cutting lines; As the aforementioned sealing component, a component made of liquid crystal polymer is prepared; In the process of forming the sealing component, at least one of the interfaces of different components, including the interface between the heat dissipation component and the sealing component, is joined by covalent bonds as a chemical bond.

42. The method for manufacturing a semiconductor package as described in claim 41, characterized in that, Before forming the aforementioned sealing component, the following steps are performed: The above-mentioned heat dissipation components are coated with an alkaline solution containing silicates to form active groups; An active group is formed by coating the aforementioned sealing components with an aqueous solution of an organic compound containing silanol and amino groups.

43. The method for manufacturing a semiconductor package as described in claim 41 or 42, characterized in that, In the process of preparing the above-mentioned substrate, a substrate having a groove is prepared, the groove being formed on the side of the substrate opposite to the side where the semiconductor chip is disposed, which is the portion that forms the cutting line.

44. The method for manufacturing a semiconductor package as described in claim 43, characterized in that, In the process of preparing the above-mentioned constituent substrate, a constituent substrate with a groove portion having a depth of 0.1t to 0.5t is prepared when the thickness of the above-mentioned constituent substrate is set to t.

45. The method for manufacturing a semiconductor package as described in claim 41 or 42, characterized in that, In the process of preparing a substrate with a groove as the aforementioned substrate, the groove is formed after the sealing member is formed.

46. ​​The method for manufacturing a semiconductor package as described in claim 41 or 42, characterized in that, In the process of configuring the sealing component described above, the sealing component described above is configured, which includes a side sealing component formed by injection molding that seals the side of the semiconductor chip and is joined to the heat dissipation component. Before configuring the aforementioned side sealing component, a through hole is formed in the aforementioned side sealing component, and a conductive material is disposed in the aforementioned through hole; In the process of forming the sealing component, the conductive material is connected to a designated location.

47. The method for manufacturing a semiconductor package as described in claim 41 or 42, characterized in that, In the process of arranging the above-mentioned sealing components, plate-shaped components are prepared and arranged by stacking the plate-shaped components. In the process of preparing the plate-shaped component, a film component made of liquid crystal polymer and in an amorphous state is prepared, and the film component is heated to crystallize it.

Images