System and method for capacitance extraction and computer readable storage medium

Abstract

A method for capacitance extraction includes performing a first capacitance extraction on one or more first regions of a semiconductor layout, performing a second capacitance extraction on one or more second regions of the semiconductor layout, the second capacitance extraction having a resolution less than a resolution of the first capacitance extraction, constructing a netlist for the semiconductor layout based on results of the first and second capacitance extractions, and modifying the semiconductor layout based on the netlist. The modified semiconductor layout is used to manufacture an integrated circuit. Embodiments of the invention also relate to systems for capacitance extraction and non-transitory computer-readable storage media.

Description

Technical Field

[0001] Embodiments of the present invention relate to systems and methods for capacitance extraction, as well as computer-readable storage media. Background Technology

[0002] Different design methodologies and electronic design automation (“EDA”) tools are employed to design integrated circuits (“ICs”) of varying complexity. IC design engineers design ICs by translating circuit specifications into geometric descriptions of physical components that combine to form basic electronic components. Generally, these geometric descriptions are polygons of various sizes representing conductive parts located on different processing layers. The geometric description of the physical components is commonly referred to as the IC layout. After creating an initial IC layout, a set of steps is typically used to test and optimize the layout to verify that the IC conforms to design specifications for parasitic capacitances and resistances within the IC. The IC layout can be modified through one or more design optimization cycles until simulation results meet the design specifications.

[0003] Parasitic capacitance and resistance can cause various adverse effects and undesirable performance in designed ICs, such as unwanted long signal delays on various interconnects. Therefore, it is essential to accurately predict the impact of parasitic capacitance and resistance on the performance of designed ICs so that design engineers can compensate for these adverse effects through appropriate design optimization steps. Summary of the Invention

[0004] According to one aspect of the present invention, a method for capacitance extraction is provided, comprising: performing a first capacitance extraction on one or more first regions of a semiconductor layout; performing a second capacitance extraction on one or more second regions of the semiconductor layout, the resolution of the second capacitance extraction being less than the resolution of the first capacitance extraction; constructing a netlist for the semiconductor layout based on the results of the first and second capacitance extractions; and modifying the semiconductor layout based on the netlist, the modified semiconductor layout being used for manufacturing an integrated circuit.

[0005] According to another aspect of the present invention, a system for capacitance extraction is provided, comprising: a processing unit; and one or more memory units storing instructions for one or more programs. The one or more programs can be executed by the processing unit to perform operations including: receiving a semiconductor layout; identifying multiple regions within the semiconductor layout; performing capacitance extraction based on different precisions on the multiple regions; constructing a netlist for the semiconductor layout based on the results of the capacitance extraction; and modifying the semiconductor layout based on the netlist, the modified semiconductor layout being used for manufacturing an integrated circuit.

[0006] According to another aspect of the present invention, a non-transitory computer-readable storage medium is provided for storing an instruction set executable by one or more processors of a device to cause the device to perform a method comprising: performing a first capacitance extraction having a first precision on one or more first regions of a semiconductor layout; performing a second capacitance extraction having a second precision different from the first precision on one or more second regions other than the one or more first regions; constructing a netlist for the semiconductor layout based on the results of the first capacitance extraction and the second capacitance extraction; and modifying the semiconductor layout based on the netlist, the modified semiconductor layout being used for manufacturing an integrated circuit. Attached Figure Description

[0007] When with attachment Figure 1 When reading this invention, the various aspects will be best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a schematic diagram of a design system according to some embodiments of the present invention.

[0009] Figure 2 This is a flowchart illustrating a simplified IC design process according to an exemplary embodiment of the present invention.

[0010] Figure 3 This is a schematic diagram of a semiconductor layout according to an exemplary embodiment of the present invention.

[0011] Figure 4 This is a schematic diagram of a semiconductor layout divided into regions according to an exemplary embodiment of the present invention.

[0012] Figure 5A and Figure 5B This is a schematic diagram illustrating the process of determining 3D capacitance using different time length parameters according to an exemplary embodiment of the present invention.

[0013] Figure 6 This is a schematic diagram of a semiconductor layout divided into regions according to an exemplary embodiment of the present invention.

[0014] Figure 7 This is a schematic diagram of a semiconductor layout divided into regions according to an exemplary embodiment of the present invention.

[0015] Figure 8 This is a schematic diagram of a semiconductor layout according to an exemplary embodiment of the present invention.

[0016] Figure 9 This is a flowchart illustrating a method for capacitance extraction according to an exemplary embodiment of the present invention.

[0017] Figure 10 This is an exemplary netlist constructed after capacitance extraction according to an exemplary embodiment of the present invention. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] The terms used in this specification have their common meanings in the art and in the specific text in which each term is used. Examples used in this specification, including instances of any term discussed herein, are illustrative only and are in no way intended to limit the scope and meaning of the invention or any of the illustrative terms. Similarly, the invention is not limited to the various embodiments given in this specification.

[0020] While the terms “first,” “second,” etc., may be used herein to describe multiple elements, these elements are not to be limited by these terms. These terms are used to distinguish different elements. For example, a first element may also be referred to as a second element, and similarly, a second element may also be referred to as a first element, without departing from the scope of this embodiment. The term “and / or” as used herein includes any and all combinations of one or more of the listed associated items.

[0021] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used therein may be interpreted accordingly.

[0022] In this document, the term “coupling” may also be referred to as “electrical coupling”, and the term “connection” may be referred to as “electrical connection”. “Coupling” and “connection” may also be used to indicate that two or more elements cooperate with each other or interact with each other.

[0023] Figure 1This is a schematic diagram of a design system 100 according to some embodiments of the present invention. Figure 1 As shown, the design system 100 includes a processing unit 110, one or more memory units 120, an input / output (I / O) interface 130, and a bus 140. In some embodiments, the processing unit 110 is communicatively coupled to the memory units 120 and the I / O interface 130 via the bus 140. In various embodiments, the processing unit 110 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a multiprocessor, a distributed processing system, or a suitable processor. Various circuits or units implementing the processing unit 110 are within the scope of this invention.

[0024] Memory cell 120 stores one or more program codes for assisting integrated circuit design. For example, memory cell 120 may store instructions for one or more programs that can be executed by the processing unit to perform operations. For example, memory cell 120 stores program code encoded with an instruction set for performing capacitance extraction of an integrated circuit layout or layout pattern. In some embodiments, the capacitance extraction operation may be performed automatically when the processing unit 110 executes the program code. Therefore, through the processing unit 110 and the program code stored in memory cell 120, electronic design automation (EDA) tools can run on design system 100 to assist IC designers at various steps in the IC design process.

[0025] In some embodiments, memory unit 120 may be a non-transitory computer-readable storage medium, for example, storing a set of executable instruction codes for performing capacitance extraction. In some embodiments, the computer-readable storage medium is an electronic, magnetic, fiber-optic, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, computer-readable storage media include semiconductor or solid-state memory, magnetic tape, mobile optical disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), digital video disc (DVD), flash memory, and / or other media now known or developed hereafter capable of storing code or data. The hardware modules or devices described in this invention include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors, and / or hardware modules or devices now known or developed hereafter.

[0026] I / O interface 130 is configured to receive input or commands from various control devices, such as those operated by circuit designers and / or layout designers. Therefore, design system 100 can be controlled using the input or commands received by I / O interface 130. In some embodiments, I / O interface 130 may be communicatively coupled to one or more peripheral devices 142, 144, 146, which may be storage devices, servers, displays configured to display the state of program code execution (e.g., cathode ray tube (CRT), liquid crystal display (LCD), touchscreen, etc.), or input devices for conveying information and commands to processing unit 110 (e.g., keyboard, keypad, mouse, trackball, touchpad, touchscreen, cursor arrow keys, or combinations thereof). Design system 100 may also transmit data to or communicate with peripheral devices or other terminal devices via network 148 (such as a local network, an internet service provider, the internet, or any combination thereof).

[0027] Figure 2 This is a flowchart illustrating a simplified IC design process 200 according to certain embodiments of the present invention. Figure 2 As shown, in the Register Transfer Level (RTL) design phase 210, system specifications such as desired functionality, communication, and other requirements are translated into an RTL design. An RTL design can be a design abstraction that models synchronous digital circuitry based on the flow of digital signals (data) between hardware registers and the logical operations performed on those signals. RTL designs can be provided in programming languages ​​such as VHDL or Verilog and typically describe the behavior of digital circuitry and its interconnections with inputs and outputs. RTL designs can be provided for System-on-Chip (SoC), blocks, cells, and / or elements of an SoC, or one or more sub-blocks, cells, or elements in a hierarchical design.

[0028] In the logic design phase 220, the RTL design is transformed into a logic design that generates a netlist of interconnected logic circuits. The logic design may employ typical logic elements, such as AND, OR, XOR, NAND, and NOR elements, as well as cells demonstrating the desired functionality from one or more libraries. In some instances, one or more intellectual property (IP) cores may be utilized and embedded into the SoC. Thus, a netlist describing the connectivity of various electronic components involved in the circuitry of the design is generated. For example, the netlist may include a list of electronic components in the circuitry and a list of nodes to which they are connected. In some embodiments, design constraints and the RTL design are sent to a synthesizer for logic synthesis to generate a pre-layout gate-level netlist. The pre-layout gate-level netlist can then be integrated into a verification environment for system gate-level simulation. After simulation and verification, the logic design is complete.

[0029] In the placement design phase 230, the gate-level netlist is converted into a physical geometry representation. For example, the placement design phase 230 may include placement planning, which is the process of placing various blocks, cells, and / or components, as well as input / output pads, across regions based on design constraints. Such resources may be placed on one or more layers of the device. Placement barriers may arise during the planarization phase, resulting in routing barriers serving as guidelines for standard cell placement. As an example, a SoC design may be divided into one or more functional blocks or partitions. Placement and routing (P&R) tools then perform the placement of physical components within each block and the integration of emulated blocks or external IP cores, and run routing to connect the components together. Thus, an initial integrated circuit layout is created.

[0030] In the post-design testing and optimization phase 240, steps 242, 244, 246, and 248 are performed. Specifically, a Design Rule Check (DRC) and Layout to Schematic (LVS) step 242 can be performed to check whether the created layout conforms to design rules and verify that the created layout is equivalent to the desired design schematic. Then, a Resistance and Capacitor Extraction (RC Extraction) step 244 can be performed to “extract” the electrical characteristics of the layout. Common electrical characteristics extracted from integrated circuit layouts include capacitances and resistances in electronic devices and various interconnects (often referred to as “networks”) that electrically connect the aforementioned devices. This step can also be called “parasitic extraction” because these capacitance and resistance values ​​are often underlying device physical characteristics used in the device configuration and materials used to manufacture the IC, rather than being placed in place by the IC designer.

[0031] Then, a layout-back gate-level simulation step 246 can be performed on the designed IC to ensure that the design conforms to the specifications of parasitic capacitances and resistors in the IC. If parasitic capacitances and resistors cause poor performance (No in step 248), the integrated circuit layout can be changed through one or more design optimization cycles by repeating logic design phase 220, layout design phase 230, and post-design testing and optimization phase 240 until the simulation results meet the design specifications (Yes in step 248).

[0032] Figure 3 This is a schematic diagram of semiconductor layout 300, used to explain an exemplary parasitic capacitance extraction process according to certain embodiments of the present invention. Figure 3As shown, in some embodiments, semiconductor layout 300 includes signal pads 310, 320, 330, and 340 and a mesh network 350. For example, signal pad 310 may include a VDD network coupled to a first power supply configured to provide a first power supply voltage that is typically a positive supply voltage (e.g., VDD). Signal pad 320 may include a VSS network coupled to a second power supply configured to provide a second power supply voltage that is typically a negative supply voltage or ground (e.g., VSS). Signal pad 330 may include an enable network for an EN signal, and signal pad 340 may be an output network for output signals. In some embodiments, mesh network 350 may be a power distribution network (PDN) mesh network, wherein dummy devices and one or more circuits are coupled between signal pads 310, 320, 330, and 340. For example, mesh network 350 may include target circuitry (e.g., functional circuitry 360), such as a 101-stage ring oscillator, an SRAM bit cell (BC) array, etc.

[0033] When performing RC extraction on semiconductor layout 300, design system 100 may run programs to identify one or more patterns (e.g., “original patterns”) of one or more electrical components in semiconductor layout 300 and extract parasitic parameters from the identified patterns. Among these parasitic parameters, parasitic capacitance affects time delay, power consumption, and signal integrity. EDA tools running on design system 100 can provide various capacitance extraction tools to predict power, performance, and area (PPA) estimates based on parasitic parameters, enabling foundries to refine designs at advanced nodes to meet foundry- and customer-defined PPA targets. For example, capacitance extraction tools may include applying 2D RC extraction methods, 2.5D RC extraction methods, 3D RC extraction methods, or any other suitable RC extraction method.

[0034] Generally, the 2.5-DRC extraction method is more accurate than the 2D RC extraction method, but less accurate than the 3DRC extraction method. On the other hand, due to the complexity of estimation and computation, the 2.5-DRC extraction method requires more extraction time compared to the 2DRC extraction method, but less extraction time compared to the 3DRC extraction method.

[0035] In some embodiments of the present invention, EDA tools can apply different levels of precision to the capacitance extraction in different regions of the semiconductor layout 300. (See reference) Figure 4 , Figure 4This is a schematic diagram of a semiconductor layout 300 divided into regions 410 and 420, used to explain the parasitic capacitance extraction process according to some embodiments of the present invention. In some embodiments, at least one of regions 410 and 420 may be a 3D region having a Z-boundary in the thickness direction (Z direction) of the semiconductor layout 300. Regions 410 and 420 also have boundaries in the XY plane, such as an X-boundary in the X direction and a Y-boundary in the Y direction. The boundaries may be specified by the user and / or automatically generated by the design system 100. In some embodiments, region 410 is not necessarily as shown in the diagram. Figure 4 The rectangle shown.

[0036] In some embodiments, the user specifies the X and Y boundaries in the semiconductor layout 300. The user may also specify the Z boundary by identifying the number of layers to be included in region 410. In some embodiments, the Z boundary includes all layers of the semiconductor layout 300, while in some other embodiments, the Z boundary includes some, but not all, layers of the semiconductor layout 300.

[0037] More accurate RC extraction results can reduce the gap between simulation and silicon measurements and help IC designers optimize semiconductor placement, but it requires more computational resources and is time-consuming. Under real-world time and / or computational resource constraints, design system 100 will struggle to achieve high accuracy and efficiency for all components during RC extraction. The user or design system 100 must prioritize components based on several factors, such as circuit complexity, to optimize overall RC extraction accuracy and efficiency. In some embodiments, design system 100 may execute a program to automatically identify region 410 as having RC extraction accuracy that prioritizes efficiency and automatically identify the boundaries of region 410. For example, the LVS extraction tool can be used to identify various circuit or electrical components, such as transistors, conductors, etc., in semiconductor placement 300. In some embodiments, design system 100 may assign higher accuracy settings to transistors with complex 3D structures and lower accuracy settings to conductors. Therefore, the LVS extraction tool automatically identifies the locations of these electrical components. The RC extraction tool can then automatically generate the boundaries of region 410 from predefined rules based on the location information of the electrical components. In some embodiments, the type of electronic components or circuits of the semiconductor layout 300 subjected to higher precision settings is preset in the RC extraction tool.

[0038] In some embodiments, region 410 may be partially defined by user-defined settings and partially identified by design system 100. For example, the user may identify the Z boundary, and design system 100 may automatically identify the X and Y boundaries of region 410. In another instance, the user may specify a region (in any one or more of the X, Y, and Z directions) where RC extraction accuracy is prioritized over efficiency, and design system 100 may automatically identify one or more regions 410 from the user-specified region.

[0039] like Figure 4 As shown, region 420 may be an area including signal pads 310, 320, 330, and 340, while region 410 may be an area including one or more functional circuits 360 (e.g., a 101-stage ring oscillator, an SRAMBC array, etc.). In some embodiments, functional circuit 360 may be critical circuitry preferably with higher RC extraction accuracy. To provide optimal overall extraction accuracy for regions 410 and 420 given computational resources or time constraints, design system 100 may automatically select a running program to apply different configurations in regions 410 and 420 to provide different capacitance extraction accuracies without consuming significant machine resources or large capacitance extraction turnaround times. For example, in some embodiments, design system 100 may perform a first capacitance extraction on region 410 at a first resolution (e.g., with an accuracy tolerance of about 0.3%) and a second capacitance extraction on region 420 at a second resolution lower than the first resolution (e.g., with an accuracy tolerance of about 3%). Therefore, relatively high precision settings with high time and resource requirements can be applied to critical functional circuits (e.g., circuit 360) of the semiconductor layout 300, while relatively low precision settings with low time and resource requirements can be applied to extract parasitic parameters outside the extraction area 420, where speed and efficiency outweigh precision to reduce the total time and computational resources used for capacitance extraction. Thus, in some embodiments, capacitance extraction for overall layout design can be completed without the stitching process desired in mesh and parallel simulation methods, avoiding problems or risks arising from the stitching process. Therefore, fast and accurate parasitic parameter extraction results can be obtained.

[0040] For example, in some embodiments, when applying the 3D capacitance determination process, the design system 100 may apply different step size parameters to regions 410 and 420. In other words, the design system 100 may apply the 3D capacitance determination process based on a first step size parameter to generate a first netlist including one or more capacitance results associated with region 420, while applying the 3D capacitance determination process based on a second step size parameter greater than the first step size parameter to generate a second netlist including one or more capacitance results associated with one or more second regions.

[0041] In some embodiments, a first step length parameter or a second step length parameter associated with different precision settings may be preset and pre-stored in a database in the design system 100. In some embodiments, the IC designer may also manually configure one or more step length parameters for the first capacitor extraction or the second capacitor extraction via the I / O interface 130 of the design system 100. In some embodiments, the design system 100 may also run a program to determine one or more step length parameters for the first capacitor extraction or the second capacitor extraction using an artificial intelligence (AI) or machine learning (ML) model.

[0042] Figure 5A and Figure 5B This is a schematic diagram illustrating the process of determining 3D capacitance using different phase length parameters according to some embodiments of the present invention. Figure 5A and Figure 5B As shown, layouts 500A and 500B both include structures A and B, which are divided into parts A1 and A2 and B1 and B2, respectively.

[0043] The 3D Field Solver (3DFS) is a 3DRC extraction tool used to perform 3D field solving simulations. The simulation uses Maxwell's equations to calculate electromagnetic fields and uses these fields to calculate corresponding electrical parameters such as parasitic capacitance, resistance, and / or inductance. In some embodiments, random walk techniques can be applied to the 3D Field Solver to solve equations in 3D and can be used to calculate capacitance between any interconnect pairs in the layout with high accuracy. By applying the random walk method to extract layout parasitic capacitance, the 3D Field Solver allows users to specify accuracy limits and calculate results with user-specified precision. For example, different accuracy settings may be associated with different step size parameters (e.g., the maximum step size of the random walk).

[0044] For example, Figure 5A and Figure 5B The capacitance value C between parts A1 and B2 shown is... A1B2 The following equation can be used to calculate and obtain:

[0045] C A1B2 =Q A / V B

[0046] Q A =∫∫εE(r k )dS k

[0047] E(r k )=∫∫G E (r k -r k-1 )V(r k )dS k

[0048] V(r k )=∫∫G V (r k+1 -r k V k+1 dS k+1 ,

[0049] Among them, V B Let Q represent the given boundary conditions. A Let r represent the charge to be calculated in a random walk consisting of a series of random steps. kLet S represent the k-th step size of the random walk. k The area of ​​the associated rectangle (e.g., the Gaussian integral surface) is represented by the k-th random step size of the random walk, G. E and G V Let represent the Green's function, and ε represent the dielectric parameter between parts A1 and B2.

[0050] like Figure 5A As shown, when based on a relatively small step size parameter (e.g., in...), Figure 4 In area 410, when performing the 3D capacitance determination process, the number of random walks is larger, resulting in higher resolution. On the other hand, as... Figure 5B As shown, when based on a relatively large step size parameter (e.g., in...), Figure 4 In the 3D capacitance determination process (in zone 420), the random selection of the step size in the random walk is "expanded", for example, expanded to a range with a larger possible value, resulting in fewer steps and lower resolution, thus speeding up the extraction.

[0051] refer to Figure 6 , Figure 6 This is a schematic diagram of a semiconductor layout 600 divided into regions 610 and 620, used to explain an exemplary parasitic capacitance extraction process according to some embodiments of the present invention. Figure 6 As shown, the semiconductor layout 600 includes structures A, B, D, E and F, wherein structures A and B are respectively divided into portions A1 and A2 and B1 and B2.

[0052] like Figure 6 As shown, in some embodiments, design system 100 can apply different types of capacitance determination processes to regions 610 and 620 to quickly obtain accurate parasitic parameter extraction results. In other words, design system 100 can perform a “hybrid” extraction combining two or more different capacitance extraction tools or processes. For example, design system 100 can apply a 3D capacitance determination process based on a selected step size parameter to generate a first netlist including one or more capacitance results associated with region 610, while simultaneously applying a 2.5-D capacitance determination process to generate a second netlist including one or more capacitance results associated with region 620. As another example, design system 100 can select any two of the 3D, 2.5-D, 2D, or 1D capacitance determination processes to apply to regions 610 and 620, respectively. Other combinations and permutations of different types of capacitance determination processes can be used.

[0053] In some embodiments, in areas outside zone 610, a 2.5-D capacitance determination process can be performed using a rule-based capacitance extractor to quickly and efficiently calculate the capacitance value. For example, the capacitance value C BD C DE C EFThe capacitance can be calculated based on the corresponding unit capacitance value and the length values ​​of structures D, E, and F. The unit capacitance value can depend on different metal width values ​​and spatial combinations, and is obtained by the 2.5-D capacitance extractor based on predefined rules. For example, the capacitance value C between structures B and D... BD ,like Figure 6 As shown, the following equation can be used to calculate and obtain:

[0054] C BD =UnitCap1×L1,

[0055] Where UnitCap1 represents the unit capacitance value obtained based on the metal width W1 of structure D and the spatial combination S1 between structures B and D, and L1 represents the length of structure D. Similarly, the capacitance values ​​C located between structure D and structure E, and between structure E and F, respectively. DE and C EF Similar equations can be used to calculate and obtain:

[0056] C DE＝ UnitCap2×L2

[0057] C EF =UnitCap3×L3,

[0058] UnitCap2 calculates and obtains the corresponding unit capacitance value based on the metal width W2 of structure E and the spatial combination S2 between structure D and F. UnitCap3 represents the corresponding unit capacitance value based on the metal width W3 of structure F and the spatial combination S3 between structure E and F. L2 represents the length of structure E, and L3 represents the length of structure F.

[0059] On the other hand, within the region of zone 610, the 3D capacitance determination process described herein can be performed based on a selected step size parameter.

[0060] refer to Figure 7 , Figure 7 This is a schematic diagram of a semiconductor layout 700 divided into regions 710 and 720, used to explain an exemplary parasitic capacitance extraction process according to some embodiments of the present invention. Figure 7 As shown, in some embodiments, the network may span a zone 710 with a high-precision setting and a zone 720 with a low-precision setting. In other words, one or more electrical components (e.g., structures A and B) may be partially located within zone 710 (e.g., portion A1 of structure A and portion B1 of structure B) and partially located outside zone 710, and within zone 720 (e.g., portion A2 of structure A and portion B2 of structure B). Figure 7 As shown, the X and Y boundaries of region 710 can be determined by the minimum X coordinate X. min Minimum Y coordinatemin Maximum X coordinate max and the maximum Y coordinate max limited.

[0061] In some embodiments, the design system 100 may apply a first precision setting (e.g., a high precision setting) to the parasitic capacitance between portions A1 and B1, both located within region 710, and a second precision setting (e.g., a low precision setting) to the parasitic capacitance between portions A1 and B2, between portions A2 and B1, and between portions A2 and B2, at least one of which is located within region 720.

[0062] For example, if a 3D capacitance extractor is applied to zones 710 and 720, then the system 100 is designed to run a program based on the first step long parameter C. A1B1 The system 100 is designed to calculate the first capacitance parameter associated with portions A1 and B1 within region 710. Furthermore, the system 100 can run a program to calculate the second capacitance parameter C associated with portions A2 and B2 within region 720 based on a second step size different from the first step size. A2B2 The third capacitance parameter C associated with part A1 and part B2 A1B2 And the fourth capacitance parameter C associated with part A2 and part B1 A2B1 .

[0063] Then, the 3D capacitance extractor can be based on the first capacitance parameter C. A1B1 Second capacitor parameter C A2B2 Third capacitor parameter C A1B2 and the fourth capacitor parameter C A2B1 The total capacitance C associated with structures A and B can be calculated using the following equation. AB :

[0064] C AB =C A1B1 +C A1B2 +C A2B1 +C A2B2

[0065] refer to Figure 8 , Figure 8 This is a schematic diagram of a semiconductor layout 800, used to explain an exemplary parasitic capacitance extraction process according to some embodiments of the present invention. Similar to... Figure 3 Semiconductor layout 300, Figure 8 The semiconductor layout 800 also includes signal pads 310, 320, 330, and 340, as well as a mesh network 350. For example... Figure 8 As shown, the signal pad 310, including the VDD network, is configured to receive the voltage signal S. V1 S V2 To SVN And the signal pad 330, including the enable network, is configured to receive the enable signal S. E1 S E2 To S EN In some embodiments, different precision settings may be applied to different areas or regions corresponding to different signals identified or selected by the user or by the design system 100. For example, the user may predefine specific signals of the semiconductor layout 800. Thus, when performing capacitance extraction, the design system 100 may determine the corresponding precision configuration associated with one or more signals of the semiconductor layout 800, and then apply a capacitance determination process based on the precision configuration to calculate the capacitance value between at least two components associated with the signal.

[0066] The above methods can be used to obtain capacitance extraction results with different precision settings. It should be noted that, although in Figure 4 , Figure 6 or Figure 7 In exemplary embodiments, a target region (e.g., region 410, 610, or 710) is identified as associated with a high-precision configuration, but the invention is not limited thereto. In some embodiments, the design system 100 may identify two or more target regions in the layout and apply the same high-precision settings to these target regions when performing capacitance extraction. In some other embodiments, the design system 100 may apply different high-precision settings to different target regions when performing capacitance extraction. Regions outside the target regions in the layout may be identified as peripheral regions corresponding to settings that have relatively low precision but high capacitance extraction efficiency compared to the high-precision settings applied in the target regions.

[0067] In some embodiments, when performing capacitance extraction, the design system 100 may combine the above-mentioned... Figures 4 to 8 The different methods described herein. For example, design system 100 may apply a 3D capacitance determination process in some identification areas with different precision settings and a 2.5-D capacitance determination process in the remaining areas of the layout. In some embodiments, design system 100 may apply precision settings corresponding to one or more rectangular areas identified by the user, and also apply precision settings corresponding to elements or structures corresponding to one or more identified or selected signals. In some embodiments, design system 100 may apply a 3D capacitance determination process having precision settings corresponding to elements or structures corresponding to one or more identified or selected signals, and apply a 2.5-D capacitance determination process to the remaining elements or structures in the layout. These are Figures 4 to 8 Examples of possible combinations of the methods described herein are provided, and the invention is not limited thereto.

[0068] After capacitance extraction, the design system 100 can construct a netlist for semiconductor layout based on the results of the capacitance extraction (e.g., a first capacitance extraction within the target region and a second capacitance extraction outside the target region). Specifically, in some embodiments, the design system 100 can record multiple capacitance components (e.g., Figure 6 The capacitance value C in AB C BD C DE and C EF And the corresponding accuracy parameters associated with the capacitance components in the netlist. For example, the capacitance value C between structures A and B. AB This can be associated with a relevant high resolution (e.g., with an accuracy of approximately 0.3% tolerance), while the capacitance value C located between structures B and D, between structures D and E, and between structures E and F is... BD C DE and C EF This can be associated with a lower resolution (e.g., with an accuracy tolerance of approximately 3%). Furthermore, in some embodiments, the design system 100 may further record the coordinates of specified X, Y, and / or Z boundaries to identify high-resolution areas (e.g., respectively) in the header of the constructed netlist. Figure 4 , Figure 6 and Figure 7 (Regions 410, 610, and 710 in the header). For example, the coordinates recorded in the header may include the minimum X coordinate X. min Minimum Y coordinate min Maximum X coordinate max and the maximum Y coordinate max These are the coordinates that define the X and Y boundaries of the high-resolution region.

[0069] Based on the constructed netlist, the design system 100 can perform post-layout gate-level simulation and check whether the design meets the expected specifications for parasitic capacitance and resistance in the IC. The above process can be repeated until the design specifications are met.

[0070] refer to Figure 9 . Figure 9 This is a flowchart illustrating a method 900 for capacitance extraction according to some embodiments of the present invention. For a better understanding of the invention, method 900 is combined with… Figure 1 The design system 100 shown and Figures 2 to 8 The examples shown are used for discussion, but are not limited thereto. In some embodiments, by... Figure 1 The method 900 is described by various circuit simulation tools and / or electronic design automation (EDA) tools running on the design system 100. For example... Figure 9 As shown, in some embodiments, method 900 includes operations 910, 920, 930, 940, 950, and 960.

[0071] At operation 910, design system 100 receives semiconductor layout (e.g., Figure 4 (Semiconductor layout 300 in the semiconductor layout). At operation 920, design system 100 identifies multiple regions within the semiconductor layout (e.g., semiconductor layout 300). Figure 4 (Regions 410 and 420 in the design system). In some embodiments, the regions are identified in response to user input. In some other embodiments, the regions may be determined partially or entirely automatically by the design system 100.

[0072] At operation 930, the design system 100 performs capacitance extraction using one or more capacitor extractors based on different levels of precision in different zones. For example, one or more capacitor extractors may perform a first capacitance extraction on one or more first zones and a second capacitance extraction on one or more second zones, wherein the resolution of the second capacitance extraction is less than the resolution of the first capacitance extraction.

[0073] At operation 940, design system 100 constructs a netlist for semiconductor layout based on the results of capacitance extraction. Figure 10 This is an exemplary netlist 1000 constructed after capacitance extraction according to some embodiments of the present invention. Figure 10 As shown, the design system 100 can record data related to capacitor elements (e.g., in the netlist 1000) in the netlist 1000. Figure 10 The corresponding precision parameters associated with regions 1012 and 1022 in the data (e.g., in...) Figure 10 In regions 1010 and 1020). The design system 100 can also record coordinates (e.g., in...). Figure 10 In region 1030 of the netlist 1000, regions with high or low resolution are identified in the header portion 1040 of the netlist 1000. Figure 10 The netlist 1000 shown is a simplified example to help understand the present invention and is not intended to limit the invention.

[0074] At operation 950, system 100 is designed based on a constructed netlist (e.g., Figure 10 The design system 100 uses a netlist 1000 to modify the semiconductor layout. In some embodiments, the design system 100 can repeat operations 910 to 950 and perform verification processes. As described above... Figure 2 As explained, the design system 100 can perform back-to-gate simulation to ensure that the modified semiconductor layout design meets the specifications of parasitic capacitance and resistance in the IC, until the simulation results meet the design specifications and optimized semiconductor layout obtained for IC manufacturing.

[0075] At operation 960, after the design layout is completed, integrated circuits can be fabricated based on the modified semiconductor layout. For example, in IC manufacturing processes, electron beam lithography can be used to transfer an IC pattern including semiconductor layout elements to an electron beam-sensitive resist layer coated on a semiconductor substrate. In some embodiments, a tape-out of the modified IC pattern for mask fabrication or electron beam writing can be generated. Tape-out refers to an IC pattern that can be used in a mask fabrication or electron beam writing format. The tape-out can be formed based on the modified semiconductor layout generated at operation 950.

[0076] In some embodiments, IC manufacturing processes may involve fabricating masks or mask sets based on wafer fabrication. Masks are used in photolithography processes to transfer components onto a semiconductor substrate. For example, based on a modified semiconductor layout, a mechanism using electron beams or multiple electron beams can be used to form patterns on the mask (photomask or intermediate mask). Various suitable techniques can be used to form the mask. For example, the mask can be a transmission mask or a reflection mask, such as an extreme ultraviolet (EUV) mask, but the invention is not limited thereto.

[0077] The above illustrations include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be added, substituted, rearranged, and / or eliminated as appropriate without departing from the spirit and scope of the invention.

[0078] By applying different extraction accuracies to different areas of the layout for capacitance extraction, EDA tools running on the design system can achieve an ideal balance between the required accuracy, processing time, and computational resources for capacitance extraction, thereby improving capacity and performance. EDA tools can handle complex designs, such as IC layouts with 101-level ring oscillators and SRAM bit cell arrays.

[0079] In some embodiments, a method for capacitance extraction is disclosed, comprising: performing a first capacitance extraction on one or more first regions of a semiconductor layout; performing a second capacitance extraction on one or more second regions of the semiconductor layout, the resolution of the second capacitance extraction being less than the resolution of the first capacitance extraction; constructing a netlist for the semiconductor layout based on the results of the first and second capacitance extractions; and modifying the semiconductor layout based on the netlist, the modified semiconductor layout being used for manufacturing an integrated circuit.

[0080] In the above method, performing the first capacitance extraction includes: applying a three-dimensional (3D) capacitance determination process based on the first step long parameter to generate a first netlist including one or more capacitance results associated with one or more first regions.

[0081] In the above method, performing the second capacitance extraction includes: applying a 3D capacitance determination process based on a second step length parameter that is greater than the first step length parameter to generate a second netlist that includes one or more capacitance results associated with one or more second regions.

[0082] In the above method, performing the second capacitance extraction includes applying a 2.5-dimensional (2.5-D) capacitance determination process to generate a second netlist that includes one or more capacitance results associated with one or more second regions.

[0083] The above method also includes: identifying regions including functional circuits in the semiconductor layout as one or more first regions.

[0084] The above method also includes: determining one or more step size parameters for first capacitance extraction or second capacitance extraction using an artificial intelligence or machine learning model.

[0085] The method further includes: calculating a first capacitance parameter associated with a first part of a first structure and a first part of a second structure based on a first step length parameter, wherein the first part of the first structure and the first part of the second structure are located in one or more first regions; and calculating a second capacitance parameter associated with a second part of a first structure and a second part of a second structure based on a second step length parameter different from the first step length parameter, wherein the second part of the first structure and the second part of the second structure are located in one or more second regions.

[0086] The method further includes: calculating a third capacitance parameter associated with the first part of the first structure and the second part of the second structure based on a second step size parameter; calculating a fourth capacitance parameter associated with the second part of the first structure and the first part of the second structure based on the second step size parameter; and calculating the capacitance value associated with the first structure and the second structure based on the first capacitance parameter, the second capacitance parameter, the third capacitance parameter and the fourth capacitance parameter.

[0087] The above method also includes recording the corresponding precision parameters associated with multiple capacitor elements in the semiconductor layout in the netlist.

[0088] The above method also includes recording the coordinates that identify one or more first zones in the header of the netlist.

[0089] The method described above also includes: determining a precision configuration associated with a signal in the semiconductor layout; and applying a capacitance determination process based on the precision configuration to calculate the capacitance value between at least two elements associated with the signal.

[0090] In some embodiments, a system is also disclosed, including: a processing unit; and one or more memory units storing instructions for one or more programs, which can be executed by the processing unit to perform operations. The operations include: receiving a semiconductor layout; identifying multiple regions within the semiconductor layout; performing capacitance extraction based on different precisions on the multiple regions; constructing a netlist for the semiconductor layout based on the results of the capacitance extraction; and modifying the semiconductor layout based on the netlist, the modified semiconductor layout being used to manufacture an integrated circuit.

[0091] In the above system, the operation also includes: applying a three-dimensional capacitance determination process based on the first step long parameter to calculate the capacitance value between at least two elements in one or more first zones of a plurality of zones.

[0092] In the above system, the operation further includes: applying a three-dimensional capacitance determination process based on a second step length parameter that is greater than the first step length parameter, to calculate the capacitance value between at least two elements in one or more second regions that are different from one or more first regions.

[0093] In the aforementioned system, the operation further includes: applying a 2.5-dimensional capacitance determination process to calculate the capacitance value between at least two elements in one or more second regions that are different from one or more first regions.

[0094] In the aforementioned system, the operation further includes: determining a precision configuration associated with the signal; and applying a capacitance determination process based on the precision configuration to calculate the capacitance value between at least two elements associated with the signal.

[0095] In some embodiments, a non-transitory computer-readable storage medium is also disclosed. The non-transitory computer-readable storage medium stores an instruction set executable by one or more processors of the device to cause the device to perform a method. The method includes: performing a first capacitance extraction with a first precision on one or more first regions of a semiconductor layout; performing a second capacitance extraction with a second precision different from the first precision on one or more second regions other than the one or more first regions; constructing a netlist for the semiconductor layout based on the results of the first and second capacitance extractions; and modifying the semiconductor layout based on the netlist, the modified semiconductor layout being used to manufacture an integrated circuit.

[0096] In the aforementioned non-transitory computer-readable storage medium, performing the first capacitance extraction includes: applying a three-dimensional capacitance determination process based on a first step long parameter to calculate the capacitance value between at least two elements within one or more first regions.

[0097] In the aforementioned non-transitory computer-readable storage medium, performing the second capacitance extraction includes: applying a 2.5-dimensional capacitance determination process to calculate the capacitance value between at least two elements within one or more second regions.

[0098] In the aforementioned non-transitory computer-readable storage medium, the method further includes: determining a precision configuration associated with the signal; and applying a capacitance determination process based on the precision configuration to calculate the capacitance value between at least two elements associated with the signal.

[0099] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the invention.

Claims

1. A method for capacitance extraction, comprising: Performing a first capacitance extraction on one or more first regions of a semiconductor layout using a first resolution, the first capacitance extraction comprising: calculating a first capacitance parameter associated with a first portion of a first structure and a first portion of a second structure within the same first region based on a first step length parameter selected for a random walk method; Performing a second capacitance extraction on one or more second regions of the semiconductor layout using a second resolution smaller than the first resolution, the second capacitance extraction includes: calculating a second capacitance parameter associated with a second portion of the first structure and a second portion of the second structure within the same second region, and an additional capacitance parameter associated with a first portion of the first structure and a first portion of the second structure in the first region and a corresponding second portion of the second structure and a second portion of the first structure in the second region; Calculate the total capacitance value, which is associated with the first structure and the second structure. Calculating the total capacitance value includes calculating the sum of the first capacitance parameter, the second capacitance parameter, and the additional capacitance parameter. A netlist is constructed for the semiconductor layout based on the results of the first and second capacitance extractions; and The semiconductor layout is modified based on the netlist, and the modified semiconductor layout is used to manufacture integrated circuits.

2. The method according to claim 1, wherein, The execution of the first capacitance extraction includes: The three-dimensional capacitance determination process is applied based on the first step long parameter to generate a first netlist that includes one or more capacitance results associated with the one or more first regions.

3. The method according to claim 2, wherein, Performing the second capacitor extraction includes: The three-dimensional capacitance determination process is applied based on a second step length parameter that is greater than the first step length parameter to generate a second netlist that includes one or more capacitance results associated with the one or more second regions.

4. The method according to claim 1, wherein, Performing the second capacitor extraction includes: A 2.5D capacitance determination process is applied to generate a second netlist that includes one or more capacitance results associated with the one or more second regions.

5. The method according to claim 1, further comprising: The regions that include the functional circuitry in the semiconductor layout are identified as the one or more first regions.

6. The method according to claim 1, further comprising: One or more step size parameters are determined using an artificial intelligence or machine learning model for the extraction of the first or second capacitor.

7. The method according to claim 1, wherein, The one or more first regions include the functional circuitry of the semiconductor layout, and the one or more second regions include a plurality of signal pads of the semiconductor layout.

8. The method according to claim 1, wherein calculating the additional capacitance parameter comprises: The third capacitance parameter associated with the first part of the first structure and the second part of the second structure is calculated based on the second step size parameter. The fourth capacitance parameter associated with the second part of the first structure and the first part of the second structure is calculated based on the second step size parameter. as well as The total capacitance value associated with the first structure and the second structure is calculated based on the first capacitance parameter, the second capacitance parameter, the third capacitance parameter, and the fourth capacitance parameter.

9. The method according to claim 1, further comprising: The netlist records the corresponding accuracy parameters associated with the multiple capacitor elements in the semiconductor layout.

10. The method according to claim 1, further comprising: The coordinates identifying the one or more first regions are recorded in the header of the netlist.

11. The method of claim 1, further comprising: Determine the precision configuration associated with the signals of the semiconductor layout; as well as The capacitance determination process is applied based on the accuracy configuration to calculate the capacitance value between at least two elements associated with the signal.

12. A system for capacitance extraction, comprising: Processing unit; as well as One or more memory units store instructions for one or more programs, which can be executed by the processing unit to perform operations including: Receive semiconductor layout; Identify a plurality of regions within the semiconductor layout, the plurality of regions comprising one or more first regions and one or more second regions; Performing a first capacitance extraction on one or more first regions of the semiconductor layout using a first resolution, the first capacitance extraction comprising: calculating a first capacitance parameter associated with a first portion of a first structure and a first portion of a second structure within the same first region based on a first step length parameter selected for a random walk method; Performing a second capacitance extraction on one or more second regions of the semiconductor layout using a second resolution smaller than the first resolution, the second capacitance extraction includes: calculating a second capacitance parameter associated with a second portion of the first structure and a second portion of the second structure within the same second region, and an additional capacitance parameter associated with a first portion of the first structure and a first portion of the second structure in the first region and a corresponding second portion of the second structure and a second portion of the first structure in the second region; Calculate the total capacitance value, which is associated with the first structure and the second structure. Calculating the total capacitance value includes calculating the sum of the first capacitance parameter, the second capacitance parameter, and the additional capacitance parameter. Based on the results of the capacitance extraction, a netlist is constructed for the semiconductor layout; and The semiconductor layout is modified based on the netlist, and the modified semiconductor layout is used to manufacture integrated circuits.

13. The system according to claim 12, wherein, The operation also includes: The three-dimensional capacitance determination process is applied based on the first step long parameter to calculate the first capacitance parameter in one or more of the plurality of regions.

14. The system according to claim 13, wherein, The operation also includes: The three-dimensional capacitance determination process is applied based on the second step size parameter to calculate the second capacitance parameter.

15. The system according to claim 13, wherein, The operation also includes: A 2.5D capacitance determination process is applied to calculate the second capacitance parameters.

16. The system according to claim 12, wherein, The operation also includes: Determine the precision configuration associated with the signal; and The capacitance determination process is applied based on the accuracy configuration to calculate the capacitance value between at least two elements associated with the signal.

17. A non-transitory computer-readable storage medium storing an instruction set, the instruction set being executable by one or more processors of a device to cause the device to perform a method, the method comprising: Performing a first capacitance extraction on one or more first regions of a semiconductor layout using a first resolution, the first capacitance extraction comprising: calculating a first capacitance parameter associated with a first portion of a first structure and a first portion of a second structure within the same first region based on a first step length parameter selected for a random walk method; Performing a second capacitance extraction on one or more second regions of the semiconductor layout using a second resolution smaller than the first resolution, the second capacitance extraction includes: calculating a second capacitance parameter associated with a second portion of the first structure and a second portion of the second structure within the same second region, and an additional capacitance parameter associated with a first portion of the first structure and a first portion of the second structure in the first region and a corresponding second portion of the second structure and a second portion of the first structure in the second region; Calculate the total capacitance value, which is associated with the first structure and the second structure. Calculating the total capacitance value includes calculating the sum of the first capacitance parameter, the second capacitance parameter, and the additional capacitance parameter. A netlist is constructed for the semiconductor layout based on the results of the first and second capacitance extractions; and The semiconductor layout is modified based on the netlist, and the modified semiconductor layout is used to manufacture integrated circuits.

18. The non-transitory computer-readable storage medium according to claim 17, wherein, The execution of the first capacitance extraction includes: The three-dimensional capacitance determination process is applied based on the first step long parameter to calculate the first capacitance parameter.

19. The non-transitory computer-readable storage medium according to claim 17, wherein, The execution of the second capacitance extraction includes: A 2.5D capacitance determination process is applied to calculate the second capacitance parameters.

20. The non-transitory computer-readable storage medium according to claim 17, wherein, The method further includes: Determine the precision configuration associated with the signal; and The capacitance determination process is applied based on the accuracy configuration to calculate the capacitance value between at least two elements associated with the signal.

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