Display device

Abstract

A display device is provided. The display device includes a pixel, an emission driver, a scan driver, a data driver, and a timing controller. The pixel includes a first transistor connected between a first node and a second node. The emission driver supplies an emission control signal at a first frequency to an emission control line. The scan driver supplies first to fourth scan signals to the first to fourth scan lines, respectively. The data driver supplies a data signal to the data line. The first scan signal controls the timing at which a voltage from a first power supply is supplied to the first node or the second node, and the second scan signal controls the timing at which a first electrode of the first transistor and a gate electrode of the first transistor are connected to each other. The scan driver controls the bias state of the first transistor by supplying the first scan signal and the second scan signal multiple times during a non-emission period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from and all benefits derived from Korean Patent Application No. 10-2020-0064183, filed on May 28, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present invention generally relate to display devices, and more particularly to display devices applicable to various frame frequencies. Background Art

[0004] The display device displays an image by a control signal applied from the outside.

[0005] The display device includes a plurality of pixels. Each pixel includes a plurality of transistors, a light-emitting device electrically coupled to the plurality of transistors, and a capacitor. The plurality of transistors generates a drive current based on a signal provided via a signal line, and the light-emitting device emits light based on the drive current.

[0006] A low-power display device is desired to improve the driving efficiency of the display device. For example, when displaying a still image, the power consumption of the display device can be reduced by lowering the driving frequency (or data writing frequency). In addition, the display device can display images at various frame frequencies (or driving frequencies) to achieve image display under various conditions. Summary of the Invention

[0007] A driving current may leak in the pixel due to the low driving frequency, and flickering of the image may be recognized. In addition, image distortion may be viewed due to changes in frame frequency, changes in frame response speed, etc.

[0008] Embodiments provide a display device capable of improving image quality with respect to various frame frequencies by controlling a bias state of a driving transistor of a pixel.

[0009] Embodiments also provide a driving method of a display device.

[0010] According to an embodiment of the present invention, a display device is provided, including a pixel, an emission driver, a scan driver, a data driver, and a timing controller. The pixel includes a first transistor coupled between a first node and a second node to generate a driving current. The pixel is connected to a first scan line, a second scan line, a third scan line, a fourth scan line, an emission control line, and a data line. The emission driver supplies an emission control signal at a first frequency to the emission control line. The scan driver supplies a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the first scan line, the second scan line, the third scan line, and the fourth scan line, respectively, during a period in which the emission control signal is supplied. The data driver supplies a data signal to the data line. The timing controller controls driving of the scan driver, the emission driver, and the data driver. The first scan signal controls timing at which a voltage of a first power source is supplied to the first node or the second node, and the second scan signal controls timing at which a first electrode of the first transistor and a gate electrode of the first transistor are coupled to each other. The scan driver controls a bias state of the first transistor by supplying the first scan signal and the second scan signal a plurality of times during a non-emission period in which the emission control signal is supplied.

[0011] In an embodiment, the pixel may further include a light-emitting device, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, the second transistor being connected between the data line and the first node, the second transistor being turned on in response to a fourth scan signal supplied to the fourth scan line, the third transistor being connected between the second node and a third node connected to the gate electrode of the first transistor, the third transistor being turned on in response to the second scan signal, the fourth transistor being turned on in response to the first scan signal supplied to the first scan line to apply the voltage of the first power supply to the first transistor, the fifth transistor being connected between the driving power supply and the first node, the fifth transistor being turned off in response to the emission control signal supplied to the emission control line, the sixth transistor being connected between the second node and the first electrode of the light-emitting device, and the sixth transistor being turned off in response to the emission control signal supplied to the emission control line.

[0012] In an embodiment, the scan driver may supply the second scan signal to the second scan line and the first scan signal to the first scan line in a first period in the non-emission period.

[0013] In an embodiment, in the first period, the fourth transistor may be turned on after the third transistor is turned on.

[0014] In an embodiment, during the first period, a time length during which the third transistor is turned on may be longer than a time length during which the fourth transistor is turned on.

[0015] In an embodiment, the pixel may further include a seventh transistor coupled between the third node and the second power source, the seventh transistor being turned on in response to a third scan signal supplied to the third scan line.

[0016] In an embodiment, the scan driver may supply the third scan signal to the third scan line in the second period in the non-emission period, and supply the second scan signal to the second scan line in the third period in the non-emission period.

[0017] In an embodiment, the second time period may begin between the first time period and the third time period.

[0018] In an embodiment, in the third period, the scan driver may supply the fourth scan signal to the fourth scan line while overlapping a portion of the second scan signal.

[0019] In an embodiment, the scan driver may supply the first scan signal to the first scan line again in a fourth period after the third period.

[0020] In an embodiment, during a remaining period after the fourth period in the non-emission period, supply of the first to fourth scan signals may be suspended, and a time length of the remaining period may be greater than a pulse width of the first scan signal.

[0021] In an embodiment, the remaining period may have a time length equal to or greater than approximately 10 microseconds (μs).

[0022] In an embodiment, the pixel may further include an eighth transistor coupled between the first electrode of the light emitting device and the third power source, the eighth transistor being turned on in response to the first scan signal.

[0023] In an embodiment, one electrode of the fourth transistor may be coupled to the first node.

[0024] In an embodiment, one electrode of the fourth transistor may be coupled to the second node.

[0025] In an embodiment, the scan driver may include: a first scan driver that supplies multiple first scan signals to the first scan line during a non-emission period, a second scan driver that supplies multiple second scan signals to the second scan line during the non-emission period, a third scan driver that supplies a third scan signal to the third scan line between the times when the second scan signals are supplied, and a fourth scan driver that supplies a fourth scan signal to the fourth scan line while overlapping with a portion of the multiple second scan signals.

[0026] In an embodiment, the scan driver may supply the third scan signal and the fourth scan signal at a second frequency corresponding to the frame frequency. The second frequency may be lower than the first frequency.

[0027] In an embodiment, a frame period may include a plurality of non-emission periods. The scan driver may supply the first scan signal in the plurality of non-emission periods. The scan driver may supply the second scan signal, the third scan signal, and the fourth scan signal only in the first non-emission period among the plurality of non-emission periods.

[0028] In the display device according to the present invention, during the display scanning period of variable frequency driving and low frequency driving, before writing a data signal, the fourth transistor is turned on while the third transistor is turned on. Therefore, brightness uniformity can be improved and the occurrence of flicker can be minimized.

[0029] In addition, during a time period equal to or greater than 10 μs between the fourth period in which the voltage of the first power supply is supplied to the pixel and the start of the emission period, all transistors of the pixel are turned off (i.e., no scanning signal is supplied), so that the on-bias state of the first transistor can be reset before light emission. Therefore, an unexpected increase in brightness caused by initialization of the gate voltage of the first transistor (i.e., during the second period) can be suppressed or prevented.

[0030] Therefore, the image quality of the display device to which the variable frame frequency driving including a plurality of emission periods and a plurality of non-emission periods in one frame period is applied can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings.

[0032] Figure 1 1 is a diagram showing an embodiment of a display device according to the present invention.

[0033] Figure 2 It is shown that the Figure 1 FIG. 1 is a diagram of an embodiment of a scan driver in a display device shown in FIG.

[0034] Figure 3 It is shown that the Figure 1 is a circuit diagram of an embodiment of a pixel in a display device shown in .

[0035] Figure 4 is shown to be supplied to Figure 3 1 is a timing diagram of an embodiment of signals for a pixel shown in FIG.

[0036] Figure 5 is shown as supplied to the Figure 3 1 is a timing diagram of an embodiment of signals for a pixel shown in FIG.

[0037] Figure 6A and Figure 6B It shows that according to Figure 3FIG. 1 is a diagram showing an embodiment of a change in the driving current of the first transistor according to the bias state of the first transistor of the pixel.

[0038] Figure 7 is shown to be supplied to Figure 3 1 is a timing diagram of another embodiment of pixel signals shown in FIG.

[0039] Figure 8 is shown to be supplied to Figure 3 1 is a timing diagram of another embodiment of the pixel signals shown in .

[0040] Figure 9 It is shown that the Figure 1 0 is a circuit diagram of another embodiment of a pixel in a display device shown in . DETAILED DESCRIPTION

[0041] Hereinafter, the embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Throughout the accompanying drawings, the same reference numerals are given to the same elements, and their repeated description will be omitted.

[0042] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0043] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0044] The wording used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. Unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are intended to include the plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It will also be understood that the terms "comprise" and / or "comprising" or "include" and / or "including" when used in this specification indicate the presence of stated features, regions, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, parts and / or groups thereof.

[0045] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the figures. In an embodiment, when the device in a figure is turned over, the element described as being on the "lower" side of the other elements will subsequently be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the figure, the exemplary term "lower" may include both "lower" and "upper" orientations. Similarly, when the device in a figure is turned over, the element described as being "below" or "beneath" the other elements will subsequently be oriented to be "above" the other elements. Therefore, the exemplary term "lower" or "under" may include both "upper" and "lower" orientations.

[0046] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0047] Inventive features may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0048] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, this element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals throughout the text indicate the same elements.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their context in the relevant art and the present invention, and will not be interpreted in an ideal or overly rigid sense unless expressly defined as such herein.

[0050] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. In embodiments, regions shown or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0051] Figure 1 1 is a diagram showing an embodiment of a display device according to the present invention.

[0052] Reference Figure 1 , the display device 1000 may include a pixel unit 100 , a scan driver 200 , an emission driver 300 , a data driver 400 , and a timing controller 500 .

[0053] The display device 1000 can display images at various frame frequencies (e.g., refresh rate, drive frequency, or screen refresh rate) depending on driving conditions. The frame frequency is the frequency at which a data voltage is substantially written to the drive transistor of a pixel PX within one second. For example, the frame frequency is referred to as a screen scan rate or a screen refresh rate and represents, for example, the frequency at which a display screen is refreshed within one second.

[0054] In an embodiment, the output frequency of the fourth scan signal supplied to the fourth scan line S4i to supply the data signal from the data driver 400 may be changed corresponding to the frame frequency. In an embodiment, for example, the frame frequency for displaying a moving image may be equal to or higher than about 60 Hz. In this embodiment, for example, the frame frequency may be about 120 Hz. The fourth scan signal may be supplied to each horizontal line (pixel row) 60 times within 1 second (s).

[0055] In an embodiment, the display device 1000 may control the output frequency of the scan driver 200 and the emission driver 300, and the corresponding output frequency of the data driver 400. In an embodiment, for example, the display device 1000 may display images corresponding to various frame frequencies ranging from approximately 1 Hz to approximately 120 Hz. However, this is merely illustrative, and for example, the display device 1000 may display images at a frame frequency equal to or higher than approximately 120 Hz. In this embodiment, for example, the display device 1000 may display images at a frame frequency of approximately 240 Hz or approximately 480 Hz.

[0056] The pixel unit 100 may include scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n, emission control lines E1 to En, and data lines D1 to Dm (m and n are integers greater than 1). In addition, the pixel unit 100 may include pixels PX coupled to the scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n, the emission control lines E1 to En, and the data lines D1 to Dm. Each of the pixels PX may include a driving transistor and a plurality of switching transistors.

[0057] In an embodiment, for example, input image data IRGB and control signals Sync and DE may be supplied from a host system (not shown) such as an application processor (“AP”) to the timing controller 500 through a predetermined interface.

[0058] The timing controller 500 may generate a first control signal SCS, a second control signal ECS, and a third control signal DCS based on the input image data IRGB, a synchronization signal (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), an internal data enable signal, a clock signal, etc. The first control signal SCS may be supplied to the scan driver 200, the second control signal ECS may be supplied to the emission driver 300, and the third control signal DCS may be supplied to the data driver 400. The timing controller 500 may rearrange the input image data IRGB and supply the rearranged data to the data driver 400.

[0059] The scan driver 200 may receive a first control signal SCS from the timing controller 500 and supply first, second, third, and fourth scan signals to the first, second, third, and fourth scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n, respectively.

[0060] The first to fourth scan signals may be set to a gate-on voltage (e.g., a low voltage) corresponding to the type of transistor to which the corresponding scan signal is supplied. The transistor receiving the scan signal may be set to an on state when the scan signal is supplied. In an embodiment, for example, the gate-on voltage of the scan signal supplied to a p-channel metal oxide semiconductor ("PMOS") transistor may have a logic low level, and the gate-on voltage of the scan signal supplied to an n-channel metal oxide semiconductor ("NMOS") transistor may have a logic high level. Hereinafter, the expression "supplying a scan signal" may mean supplying the scan signal at a logic level that turns on the transistor controlled by the scan signal.

[0061] In an embodiment, the scan driver 200 may supply some of the first to fourth scan signals a plurality of times within the non-emission period, thereby controlling a bias state of a driving transistor included in the pixel PX.

[0062] The emission driver 300 may supply emission control signals to the emission control lines E1 to En based on the second control signal ECS. In an embodiment, for example, the emission control signals may be sequentially supplied to the emission control lines E1 to En.

[0063] The emission control signal may be set to a gate-off voltage (e.g., a high voltage). A transistor receiving the emission control signal may be turned off when the emission control signal is supplied, and may be turned on otherwise. Hereinafter, the expression "supplying an emission control signal" may mean supplying the emission control signal at a logic level that causes the transistor controlled by the emission control signal to be turned off.

[0064] For ease of description, Figure 1 , each of the scan driver 200 and the emission driver 300 is shown as a single component, but the present invention is not limited thereto. Depending on the design, the scan driver 200 may include multiple scan drivers, each of which supplies at least one of the first to fourth scan signals. Furthermore, at least portions of the scan driver 200 and the emission driver 300 may be integrated into a single drive circuit, a single module, or the like.

[0065] The data driver 400 may receive a third control signal DCS and image data RGB from the timing controller 500. The data driver 400 may convert the digital image data RGB into analog data signals (data voltages). The data driver 400 may supply data signals to the data lines D1 to Dm in response to the third control signal DCS. The data signals supplied to the data lines D1 to Dm may be supplied synchronously with the fourth scan signals supplied to the fourth scan lines S41 to S4n.

[0066] In an embodiment, the display device 1000 may further include a power supply. The power supply may supply the pixel unit 100 with a voltage of a first driving power supply VDD, a voltage of a second driving power supply VSS, a voltage of a first power supply VEH (or a bias power supply), and a voltage of a second power supply Vint (or an initialization power supply) for driving the pixel PX. The second power supply Vint may include an initialization power supply output at different voltage levels (e.g., Figure 3 Vint1 and Vint2 shown in ).

[0067] The display device 1000 can operate at various frame frequencies. When driven at low frequencies, image defects such as flickering may be observed due to current leakage in the pixels. In addition, due to changes in the bias state of the drive transistor when the display device is driven at various frame frequencies, changes in response speed due to threshold voltage shifts caused by changes in hysteresis characteristics, and the like, afterimages such as image attraction may be observed.

[0068] In order to improve the image quality, one frame period of the pixel PX may include one display scanning period and one bias scanning period according to the frame frequency. Figure 4 and Figure 5 The operations of the display scanning period and the bias scanning period are described in detail.

[0069] Figure 2 It is shown that the Figure 1 FIG. 1 is a diagram of an embodiment of a scan driver in a display device shown in FIG.

[0070] Reference Figure 1 and Figure 2 , the scan driver 200 may include a first scan driver 220 , a second scan driver 240 , a third scan driver 260 , and a fourth scan driver 280 .

[0071] The first control signal SCS may include first to fourth scan start signals FLM1 to FLM4 , which may be supplied to the first to fourth scan drivers 220 , 240 , 260 , and 280 , respectively.

[0072] The pulse width, supply timing, etc. of the first to fourth scan start signals FLM1 to FLM4 can be determined according to the driving conditions and frame frequency of the pixel PX. The first to fourth scan signals can be output based on the first to fourth scan start signals FLM1 to FLM4, respectively. In an embodiment, for example, the pulse width of at least one scan signal among the first to fourth scan signals can be different from the pulse widths of the other scan signals.

[0073] The first scan driver 220 may sequentially supply a first scan signal to the first scan lines S11 to S1n in response to a first scan start signal FLM1. The second scan driver 240 may sequentially supply a second scan signal to the second scan lines S21 to S2n in response to a second scan start signal FLM2. The third scan driver 260 may sequentially supply a third scan signal to the third scan lines S31 to S3n in response to a third scan start signal FLM3. The fourth scan driver 280 may sequentially supply a fourth scan signal to the fourth scan lines S41 to S4n in response to a fourth scan start signal FLM4.

[0074] Figure 3 It is shown that the Figure 1 is a circuit diagram of an embodiment of a pixel in a display device shown in .

[0075] For ease of description, we will Figure 3 Pixels 10 arranged on an i-th horizontal line (or i-th pixel row) and coupled to a j-th data line Dj are shown in FIG.

[0076] Reference Figure 1 and Figure 3 , the pixel 10 may include a light emitting device LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.

[0077] A first electrode (e.g., an anode or a cathode) of the light emitting device LD may be coupled to the sixth transistor M6, and a second electrode (e.g., a cathode or an anode) of the light emitting device LD may be coupled to the second driving power source VSS. The light emitting device LD may generate light having a predetermined brightness corresponding to the amount of current supplied from the first transistor M1.

[0078] In an embodiment, the light-emitting device LD may be an organic light-emitting diode including an organic emission layer. In another embodiment, the light-emitting device LD may be an inorganic light-emitting device including an inorganic material. In another embodiment, the light-emitting device LD may be a light-emitting device configured from a composite of an inorganic material and an organic material. In an alternative embodiment, the light-emitting device LD may include a plurality of inorganic light-emitting devices connected in parallel and / or in series between the second driving power source VSS and the sixth transistor M6.

[0079] A first electrode of the first transistor M1 (or driving transistor) may be coupled to a first node N1, and a second electrode of the first transistor M1 may be coupled to a second node N2. A gate electrode of the first transistor M1 may be coupled to a third node N3. The first transistor M1 may control the amount of current flowing from the first driving power source VDD to the second driving power source VSS via the light-emitting device LD in accordance with the voltage of the third node N3. To this end, the first driving power source VDD may be set to a voltage higher than that of the second driving power source VSS.

[0080] The second transistor M2 may be coupled between the j-th data line Dj (hereinafter also referred to as the data line) and the first node N1. A gate electrode of the second transistor M2 may be coupled to the i-th fourth scan line S4i (hereinafter also referred to as the fourth scan line). When the fourth scan signal is supplied to the fourth scan line S4i, the second transistor M2 may be turned on to allow the data line Dj and the first node N1 to be electrically coupled to each other.

[0081] The third transistor M3 may be coupled between the second electrode (i.e., the second node N2) and the third node N3 of the first transistor M1. The gate electrode of the third transistor M3 may be coupled to the i-th second scan line S2i (hereinafter also referred to as the second scan line). When the second scan signal is supplied to the second scan line S2i, the third transistor M3 may be turned on to allow the second electrode of the first transistor M1 and the third node N3 to be electrically coupled to each other. In other words, the timing at which the second electrode (e.g., the drain electrode) of the first transistor M1 and the gate electrode of the first transistor M1 are coupled to each other may be controlled by the second scan signal. When the third transistor M3 is turned on, it may be coupled to the first transistor M1 in the form of a diode.

[0082] The fourth transistor M4 may be turned on when a first scan signal is supplied to the i-th first scan line S1i (hereinafter also referred to as the first scan line) to supply the voltage of the first power supply VEH to the first transistor M1. In an embodiment, the fourth transistor M4 may be coupled between the first node N1 and the first power supply VEH. The timing at which the voltage of the first power supply VEH is supplied to the first node N1 may be controlled by the first scan signal.

[0083] The gate electrode of the fourth transistor M4 may be coupled to the first scan line S1i. When the fourth transistor M4 is turned on, the voltage of the first power source VEH may be supplied to the first node N1. In an embodiment, the voltage of the first power source VEH may have a level similar to that of the data voltage of the black grayscale. In an embodiment, for example, the voltage of the first power source VEH may have a level of approximately 5 volts (V) to approximately 7 volts.

[0084] Therefore, when the fourth transistor M4 is turned on, a predetermined high voltage may be applied to the source electrode of the first transistor M1. When the third transistor M3 is in the off state, the first transistor M1 may have an on-bias state (i.e., a state in which the first transistor M1 may be turned on). In other words, the first transistor M1 may be on-biased.

[0085] The fifth transistor M5 may be coupled between the first driving power source VDD and the first node N1. A gate electrode of the fifth transistor M5 may be coupled to an i-th emission control line Ei (hereinafter also referred to as an emission control line). The fifth transistor M5 is turned off when an emission control signal is supplied to the emission control line Ei, and is turned on otherwise.

[0086] The sixth transistor M6 may be coupled between the second electrode (i.e., the second node N2) of the first transistor M1 and the first electrode (i.e., the fourth node N4) of the light emitting device LD. A gate electrode of the sixth transistor M6 may be coupled to the emission control line Ei. The sixth transistor M6 may be controlled in substantially the same manner as the fifth transistor M5.

[0087] The seventh transistor M7 may be coupled between the third node N3 and the second power supply Vint1 (hereinafter also referred to as the first initialization power supply). A gate electrode of the seventh transistor M7 may be coupled to the i-th third scan line S3i (hereinafter also referred to as the third scan line). When the third scan signal is supplied to the third scan line S3i, the seventh transistor M7 may be turned on to supply the voltage of the first initialization power supply Vint1 to the third node N3. The voltage of the first initialization power supply Vint1 is set to a voltage lower than the voltage of the data signal supplied to the data line Dj.

[0088] Therefore, when the seventh transistor M7 is turned on, the gate voltage of the first transistor M1 may be initialized to the voltage of the first initialization power source Vint1 .

[0089] The eighth transistor M8 may be coupled between the first electrode of the light-emitting device LD (i.e., the fourth node N4) and the third power source Vint2 (hereinafter also referred to as the second initialization power source). In an embodiment, the gate electrode of the eighth transistor M8 may be coupled to the first scan line S1i. When the first scan signal is supplied to the first scan line S1i, the eighth transistor M8 may be turned on to supply the voltage of the second initialization power source Vint2 to the first electrode of the light-emitting device LD.

[0090] When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting device LD, the parasitic capacitor of the light-emitting device LD can be discharged. Since the residual voltage charged in the parasitic capacitor is discharged (removed), unexpected micro-emissions can be prevented. Therefore, the black rendering capability of the pixel 10 can be improved.

[0091] The first initialization power source Vint1 and the second initialization power source Vint2 may generate voltages different from each other. That is, the voltage for initializing the third node N3 and the voltage for initializing the fourth node N4 may be set to be different from each other.

[0092] In low-frequency driving, where the length of a frame period is extended, when the voltage of the first initialization power supply Vint1 supplied to the third node N3 is too low, a strong conduction bias is applied to the first transistor M1, and thus the threshold voltage of the first transistor M1 is shifted during the corresponding frame period. This hysteresis characteristic may cause a flicker phenomenon in low-frequency driving. Therefore, in low-frequency driving, a higher voltage of the first initialization power supply Vint1 than the voltage of the second drive power supply VSS may be desirable in the display device.

[0093] However, when the voltage of the second initialization power supply Vint2 supplied to the fourth node N4 is higher than the predetermined reference voltage, the voltage of the parasitic capacitor of the light emitting device LD is not discharged, but the parasitic capacitor can be charged. Therefore, the voltage of the second initialization power supply Vint2 will be lower than the voltage of the second driving power supply VSS.

[0094] However, this is merely illustrative, and the voltage of the first initialization power source Vint1 and the voltage of the second initialization power source Vint2 may be substantially the same.

[0095] The storage capacitor Cst is coupled between the first driving power source VDD and the third node N3 and may store a voltage applied to the third node N3.

[0096] The first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may be implemented using polycrystalline silicon semiconductor transistors. In an embodiment, for example, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may include a polycrystalline silicon semiconductor layer configured as an active channel using a low-temperature polycrystalline silicon ("LTPS") process. In addition, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may be implemented using p-type transistors (e.g., PMOS transistors). Therefore, the gate-on voltage of the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 when they are turned on may have a logic low level.

[0097] Since the polysilicon semiconductor transistor has a fast response speed, the polysilicon semiconductor transistor can be applied to a switching element in which fast switching is desired.

[0098] The third transistor M3 and the seventh transistor M7 may be implemented using oxide semiconductor transistors. In an embodiment, for example, the third transistor M3 and the seventh transistor M7 may be implemented using n-type oxide semiconductor transistors (e.g., NMOS transistors) and include an oxide semiconductor layer as an active layer. Therefore, the gate-on voltage when the third transistor M3 and the seventh transistor M7 are turned on may have a logic high level.

[0099] Oxide semiconductor transistors can be provided by a low-temperature process and have a charge mobility lower than that of polysilicon semiconductor transistors. That is, oxide semiconductor transistors have excellent off-current characteristics. Therefore, when the third transistor M3 and the seventh transistor M7 are implemented using oxide semiconductor transistors, leakage current from the second node N2 due to low-frequency driving can be minimized, and display quality can be improved accordingly.

[0100] Figure 4 is shown to be supplied to Figure 3 1 is a timing diagram of an embodiment of signals for a pixel shown in FIG. Figure 5 is shown as supplied to the Figure 3 1 is a timing diagram of an embodiment of signals for a pixel shown in FIG.

[0101] Reference Figure 4 and Figure 5 , in the variable frequency driving for controlling the frame frequency, one frame period FP may include a display scanning period DSP and at least one bias scanning period BSP.

[0102] The display scan period DSP may include a first non-emission period NEP1 and a first emission period EP1. The bias scan period BSP may include a second non-emission period NEP2 and a second emission period EP2. Figure 4 The non-emission period NEP and the transmission period EP shown in FIG can be respectively Figure 5 The first non-emission period NEP1 and the first emission period EP1 are shown in FIG.

[0103] The display scanning period DSP includes a period in which a data signal actually corresponding to an output image is written. In an embodiment, for example, when a still image is displayed by low-frequency driving, a data signal may be written within each display scanning period DSP.

[0104] like Figure 5 As shown in , the emission control signal may be supplied to the emission control line Ei at a first frequency higher than the frame frequency. The third scan signal and the fourth scan signal may be supplied at a second frequency lower than the first frequency. In an embodiment, for example, the first frequency may be approximately 240 Hz, and the second frequency may be approximately 60 Hz. The frequencies of the third scan signal and the fourth scan signal may be substantially equal to the frame frequency.

[0105] However, this is merely illustrative, and the second frequency may be approximately 60 Hz or lower. As the second frequency becomes lower or as the difference between the first frequency and the second frequency becomes larger, the number of times the bias scan period BSP is repeated in the frame period FP (i.e., the number of bias scan periods BSP) may increase. In an embodiment, for example, the frame period FP may include one display scan period DSP and a plurality of consecutive bias scan periods BSP according to the frame frequency.

[0106] In an embodiment, the second scan signal may be supplied only in the first non-emission period NEP1. The second scan signal may be supplied to the second scan line S2i a plurality of times during the first non-emission period NEP1.

[0107] In an embodiment, a first scan signal may be supplied during the first non-emission period NEP1 and the second non-emission period NEP2. The first scan signal may be supplied to the first scan line S1i multiple times during the first non-emission period NEP1. Furthermore, the first scan signal may be supplied to the first scan line S1i multiple times during the second non-emission period NEP2. The first scan signal may be a signal for controlling the first transistor M1 to be in an on-bias state. In an embodiment, for example, when the fourth transistor M4 is turned on by the first scan signal, the voltage of the first power supply VEH may be supplied to the first node N1.

[0108] The display device in the embodiment of the present invention can periodically apply the voltage of the first power supply VEH to the source electrode of the first transistor M1 via the fourth transistor M4. When the voltage of the first power supply VEH is supplied to the source electrode of the first transistor M1, the first transistor M1 can be in an on-bias state, and the threshold voltage characteristics of the first transistor M1 can be changed. Therefore, the characteristics of the first transistor M1 are fixed to a predetermined state during low-frequency driving, thereby preventing degradation of the first transistor M1.

[0109] Although already Figure 5 FIG1 shows a case where the first scan signal is supplied in all the first non-emission period NEP1 and the second non-emission period NEP2, but the present invention is not limited thereto. The first scan signal may be supplied in part of the second non-emission period NEP2. In an embodiment, for example, the first scan signal may be supplied only in Figure 5 A display scanning period DSP and a bias scanning period BSP shown in FIG are supplied to the first scanning line S1i.

[0110] The period in which the emission control signal has a logic low level may correspond to the emission period EP, the first emission period EP1, and the second emission period EP2, and the period other than the emission period EP, the first emission period EP1, and the second emission period EP2 may correspond to the non-emission period NEP, the first non-emission period NEP1, and the second non-emission period NEP2.

[0111] The gate-on voltages of the second scan signal and the third scan signal supplied to the third transistor M3 and the seventh transistor M7, respectively, which are implemented as n-type transistors, have a logic high level. The gate-on voltage of the fourth scan signal supplied to the second transistor M2, which is implemented as a p-type transistor, and the gate-on voltage of the first scan signal supplied to each of the fourth transistor M4 and the eighth transistor M8, which are implemented as p-type transistors, have a logic low level.

[0112] like Figure 5 As shown in FIG, in the second non-emission period NEP2, which is a non-emission period of the bias scan period BSP, the first scan signal can be supplied to the first scan line S1i. Therefore, the voltage of the first power supply VEH can be supplied to the source electrode of the first transistor M1 in the second non-emission period NEP2. That is, a conduction bias can be periodically applied to the first transistor M1 regardless of the frame frequency. In addition, the first scan signal can be supplied to the first scan line S1i multiple times in the second non-emission period NEP2 to maintain a stable conduction bias state. Therefore, the brightness change of the first transistor M1 during the frame period FP in low-frequency driving can be minimized. Even in the display scan period DSP, the first scan signal can be supplied to the first scan line S1i multiple times to drive the scan driver 200 and simplify the configuration of the display device 1000.

[0113] In the following, reference will be made to Figure 4 The scanning signal supplied in the display scanning period DSP and the operation of the pixel 10 are described in detail.

[0114] The emission control signal may be supplied to the emission control line Ei during the non-emission period NEP. Therefore, the fifth transistor M5 and the sixth transistor M6 may be turned off during the non-emission period NEP. The non-emission period NEP may include a first period P1 to a fifth period P5.

[0115] During the first period P1, the scan driver 200 may supply the second scan signal to the second scan line S2i and the first scan signal to the first scan line S1i. In an embodiment, the first scan signal may be supplied after the second scan signal is supplied. Therefore, during the first period P1, the fourth transistor M4 may be turned on after the third transistor M3 is turned on.

[0116] When only the fourth transistor M4 is turned on without supplying the second scan signal, the voltage of the first power supply VEH may be supplied to the first node N1 (i.e., the source electrode of the first transistor M1). Since the voltage of the first power supply VEH is approximately 5V or higher, the first transistor M1 may have an on-bias state. In an embodiment, for example, the first transistor M1 may have a source voltage of approximately 5V or higher and a drain voltage of approximately 5V or higher, and the absolute value of the gate-source voltage of the first transistor M1 may increase.

[0117] In this state, when the data signal is supplied by supplying the fourth scan signal, the driving current may be unexpectedly changed due to the influence of the bias state of the first transistor M1, and the image brightness may fluctuate (eg, the brightness increases).

[0118] To address this issue, the scan driver 200 may supply the second scan signal earlier than the first scan signal during the first period P1. Therefore, the third transistor M3 may be turned on earlier than the fourth transistor M4. When the third transistor M3 is turned on, the second node N2 and the third node N3 may be coupled to each other. Subsequently, when the fourth transistor M4 is turned on, the voltage of the first power supply VEH may be transferred to the third node N3 via the first node N1. In an embodiment, for example, the voltage difference between the first node N1 and the third node N3 may be reduced to the threshold voltage level of the first transistor M1. Therefore, the gate-source voltage of the first transistor M1 may be significantly reduced during the first period P1. In an embodiment, for example, the first transistor M1 may be set to an off-bias state.

[0119] As described above, in order to prevent an unexpected increase in brightness caused by the supply of the voltage of the first power source VEH before writing the data signal in the first period P1, the supply of the first scan signal and the second scan signal can be controlled so that the fourth transistor M4 is turned on in a state where the third transistor M3 is turned on.

[0120] In an embodiment, in the first period P1, the pulse width W1 of the second scan signal may be greater than the pulse width W2 of the first scan signal. In an embodiment, for example, in the first period P1, the third transistor M3 may be turned on earlier than the fourth transistor M4 and turned off after the fourth transistor M4 is turned off.

[0121] However, this is merely illustrative, and the third transistor M3 may be turned off earlier than the fourth transistor M4 .

[0122] The eighth transistor M8 may be turned on in response to the first scan signal, and the voltage of the second initialization power source Vint2 may be supplied to the first electrode (ie, the fourth node N4 ) of the light emitting device LD.

[0123] Subsequently, during the second period P2, the scan driver 200 may supply a third scan signal to the third scan line S3i. The seventh transistor M7 may be turned on by the third scan signal. When the seventh transistor M7 is turned on, the voltage of the first initialization power supply Vint1 may be supplied to the gate electrode of the first transistor M1. That is, during the second period P2, the gate voltage of the first transistor M1 may be initialized based on the voltage of the first initialization power supply Vint1. Therefore, a strong on-bias may be applied to the first transistor M1, and the hysteresis characteristic may be changed (i.e., the threshold voltage may be shifted).

[0124] Subsequently, in a third period P3, the scan driver 200 may supply the second scan signal to the second scan line S2i. The third transistor M3 may be turned on again in response to the second scan signal. In the third period P3, the scan driver 200 may supply the fourth scan signal to the fourth scan line S4i while overlapping with a portion of the second scan signal. The second transistor M2 may be turned on by the fourth scan signal, and the data signal may be supplied to the first node N1.

[0125] The first transistor M1 can be coupled in the form of a diode through the turned-on third transistor M3, and data signal writing and threshold voltage compensation can be performed. Since the supply of the second scan signal is maintained even after the supply of the fourth scan signal is suspended, the threshold voltage of the first transistor M1 can be compensated for a sufficient length of time.

[0126] Subsequently, in the fourth period P4, the scan driver 200 may again supply the first scan signal to the first scan line S1i. Thus, the fourth transistor M4 and the eighth transistor M8 may be turned on. When the fourth transistor M4 is turned on, the voltage of the first power source VEH may be supplied to the first node N1.

[0127] The influence of the strong on-bias applied in the second period P2 can be suppressed by data signal writing and threshold voltage compensation operations. In an embodiment, for example, the voltage difference between the gate voltage and the source voltage (and the drain voltage) of the first transistor M1 can be significantly reduced by threshold voltage compensation in the third period P3. Then, the characteristics of the first transistor M1 may change again, and the driving voltage in the emission period EP may increase or a change in the black grayscale may be observed.

[0128] To prevent this characteristic change, the fourth transistor M4 may be turned on in the fourth period P4. Therefore, the voltage of the first power supply VEH is supplied to the source electrode of the first transistor M1 in the fourth period P4, so that the first transistor M1 may be set to an on-bias state.

[0129] It is desirable that there is sufficient idle time between the fourth period P4 and the emission period EP so that the first transistor M1 is set to a stable on-bias state by the operation in the fourth period P4. Therefore, a fifth period P5 in which no scan signal is supplied may be inserted between the fourth period P4 and the emission period EP.

[0130] In an embodiment, the fifth period P5 may correspond to four horizontal periods. In an embodiment, the time length of the fifth period P5 may be equal to or greater than about 10 microseconds (μs). Therefore, the first transistor M1 may have a stable on-bias state before the emission period EP. Therefore, even if repeated Figure 5 Even during the frame period FP shown in , the emission brightness can be stably maintained.

[0131] In an embodiment, the Figure 2 The first scan driver 220 , the second scan driver 240 , the third scan driver 260 , and the fourth scan driver 280 shown in FIG. 1 supply the first to fourth scan signals.

[0132] Figure 6A and Figure 6B It shows that according to Figure 3 FIG. 1 is a diagram showing an embodiment of a change in the driving current of the first transistor according to the bias state of the first transistor of the pixel.

[0133] Reference Figure 3 、 Figure 4 、 Figure 6A and Figure 6B , driving current I D The characteristics of the change may vary depending on whether the second period P2 is included in the display scan period DSP.

[0134] Figure 6A It shows that in the driving of the second period P2 which is not included in the display scanning period DSP, the gate-source voltage V GS The driving current I D changes.

[0135] The first curve CURVE1 represents the gate-source voltage V after the first transistor M1 is set to a cut-off bias state. GS With the driving current I D and the second curve CURVE2 represents the gate-source voltage V after the first transistor M1 is set to the on-bias state. GS With the driving current I D That is, the IV curve and the threshold voltage of the first transistor M1 may change according to the change of the bias state.

[0136] exist Figure 6A In the embodiment, for example, a driving current I corresponding to point A may be generated in the first frame. D , a driving current I corresponding to point B can be generated in the second frame D , and a driving current I corresponding to point C can be generated in the third frame D .

[0137] like Figure 6A As shown in the figure, the driving current I D The brightness changes rapidly according to the change of the bias state, and thus the change of brightness can be observed.

[0138] Figure 6B FIG. 1 shows an IV curve in a configuration in which the second period P2 is included in the display scan period DSP. That is, by turning on the seventh transistor M7 in the second period P2, the first curve CURVE1 may be shifted to the third curve CURVE3. In an embodiment, for example, the third curve CURVE3 may be similar to the second curve CURVE2 as the IV curve in the on-bias state. The IV curve of the first transistor M1 may be shifted from the first curve CURVE1 to the third curve CURVE3.

[0139] The order of the second curve CURVE2 is changed, so that the response speed of the first transistor M1 can be improved.

[0140] That is, before writing the data signal, the first transistor M1 is biased to be turned on so that the driving current I D The order of A'→B'→C can be changed. Since the IV curve is shifted due to the initialization of the gate voltage of the first transistor M1 in the second period P2, the response speed of the first transistor M1 is improved, so that the driving current I D and brightness fluctuations are minimized.

[0141] Figure 7 is shown to be supplied to Figure 3 1 is a timing diagram of another embodiment of pixel signals shown in FIG. Figure 8 is shown to be supplied to Figure 3 1 is a timing diagram of another embodiment of the pixel signals shown in .

[0142] In addition to the pulse width and supply timing of some scanning signals, Figure 7 and Figure 8 The timing diagram shown in Figure 4 The timing diagram shown in is the same or similar to that shown in Figure 4 Components that are the same as or correspond to those shown in Detailed Description are denoted by the same reference numerals, and duplicate descriptions will be omitted.

[0143] Reference Figure 7 and Figure 8 , the non-emission period NEP of the display scan period DSP may include a first period P1 to a fifth period P5.

[0144] In an embodiment, Figure 7 As shown in FIG, the second period P2 and the third period P3 may partially overlap each other. That is, in a state where the seventh transistor M7 is turned on, the third transistor M3 may be turned on in response to the second scan signal. The voltage of the first initialization power supply Vint1 is in a state where the voltage of the first initialization power supply Vint1 has been supplied to the third node N3 and the first transistor M1 has been turned on. Therefore, the first transistor M1 is biased according to Figure 7 The characteristics of the signal supply shown in FIG can be similar to the first transistor M1 according to Figure 4 The driving characteristics in the second period P2 and the third period P3 are shown in FIG.

[0145] In an embodiment, Figure 8 As shown in FIG, after the supply of the second scan signal is suspended in the first period P1, the supply of the first scan signal may be suspended. In the first period P1, the fourth transistor M4 may be turned on after the third transistor M3 is turned on, and turned off after the third transistor M3 is turned off. Since a voltage having a level similar to that of the voltage of the first power source VEH is supplied to the second node N2, Figure 8 The characteristics of the first transistor M1 in the first period P1 shown in FIG may be similar to those in FIG. Figure 4 Characteristics of the first transistor M1 in the first period P1 are shown in FIG.

[0146] As described above, some scan signals may be output with a predetermined margin according to the waveform of the clock signal supplied to the scan driver 200 , output characteristics of circuits included in the scan driver 200 , and the like.

[0147] Figure 9 It is shown that the Figure 1 0 is a circuit diagram of another embodiment of a pixel in a display device shown in .

[0148] In addition to the fourth transistor M4, Figure 9 The pixel 11 shown in FIG has the same Figure 3 The configuration and operation of the pixel 10 described above are the same as those of the pixel 10 described above. Figure 3 Components that are the same as or correspond to those shown in Detailed Description are denoted by the same reference numerals, and duplicate descriptions will be omitted.

[0149] Reference Figure 9 , the pixel 11 may include a light emitting device LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.

[0150] In an embodiment, one electrode of the fourth transistor M4 may be coupled to the second node N2, and the other electrode of the fourth transistor M4 may be coupled to the first power source VEH. The fourth transistor M4 may supply a voltage of the first power source VEH to the second node N2 in response to a first scan signal supplied to the first scan line S1i. As described above, a voltage for a conduction bias may be supplied to either the source electrode or the drain electrode of the first transistor M1.

[0151] In an embodiment, the other electrode of the fourth transistor M4 may be coupled to the emission control line Ei instead of the first power source VEH. When the fourth transistor M4 is turned on, a logic high level of the emission control signal may be supplied to the second node N2.

[0152] As described above, in the display device according to the embodiment of the present invention, in the display scanning period of variable frequency driving and low frequency driving, before writing the data signal, the fourth transistor M4 is turned on while the third transistor M3 is turned on. Therefore, the brightness uniformity can be improved and the occurrence of flicker can be minimized.

[0153] During a time period equal to or greater than 10 μs between the fourth period in which the voltage of the first power supply VEH is supplied to the pixel and the start of the emission period, all transistors of the pixel are turned off (i.e., no scan signal is supplied), so that the on-bias state of the first transistor M1 can be reset before light emission. Therefore, an unexpected increase in brightness caused by initialization of the gate voltage of the first transistor M1 (i.e., in the second period) can be suppressed or prevented.

[0154] Therefore, the image quality of the display device to which the variable frame frequency driving including a plurality of emission periods and a plurality of non-emission periods in one frame period is applied can be improved.

[0155] Embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.

Claims

1. A display device, comprising: a pixel including a first transistor coupled between a first node and a second node to generate a driving current, the pixel being connected to a first scan line, a second scan line, a third scan line, a fourth scan line, an emission control line, and a data line; a transmit driver that supplies a transmit control signal to the transmit control line at a first frequency; a scan driver configured to supply a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the first scan line, the second scan line, the third scan line, and the fourth scan line, respectively, during a period in which the emission control signal is supplied; a data driver that supplies a data signal to the data line; and a timing controller for controlling the driving of the scan driver, the emission driver, and the data driver; The first scan signal controls the timing of supplying the voltage of the first power supply to the first node or the second node. The second scan signal controls a timing at which the first electrode of the first transistor and the gate electrode of the first transistor are connected to each other. The scan driver controls a bias state of the first transistor by supplying the first scan signal and the second scan signal a plurality of times in a non-emission period in which the emission control signal is supplied, The scan driver supplies the third scan signal and the fourth scan signal at a second frequency equal to or less than a frame frequency, and The second frequency is lower than the first frequency.

2. The display device according to claim 1, wherein The pixel further comprises: Light-emitting devices; a second transistor coupled between the data line and the first node, the second transistor being turned on in response to the fourth scan signal supplied to the fourth scan line; a third transistor coupled between the second node and a third node connected to the gate electrode of the first transistor, the third transistor being turned on in response to the second scan signal; a fourth transistor that is turned on in response to the first scan signal supplied to the first scan line to apply a voltage of the first power supply to the first transistor; a fifth transistor coupled between a driving power source and the first node, the fifth transistor being turned off in response to the emission control signal supplied to the emission control line; and a sixth transistor coupled between the second node and the first electrode of the light emitting device, the sixth transistor being turned off in response to the emission control signal supplied to the emission control line, and In the first period of the non-emission period, the scan driver supplies the second scan signal to the second scan line and supplies the first scan signal to the first scan line.

3. The display device according to claim 2, wherein: In the first period, the fourth transistor is turned on after the third transistor is turned on.

4. The display device according to claim 3, wherein In the first period, a duration during which the third transistor is turned on is longer than a duration during which the fourth transistor is turned on.

5. The display device according to claim 2, wherein The pixel further comprises: a seventh transistor coupled between the third node and a second power source, the seventh transistor being turned on in response to the third scan signal supplied to the third scan line, Wherein, the scanning driver: supplying the third scan signal to the third scan line in a second period in the non-emission period; and supplying the second scan signal to the second scan line in a third period in the non-emission period, and The second time period starts between the first time period and the third time period. The display device according to claim 5 , wherein: In the third period, the scan driver supplies the fourth scan signal to the fourth scan line while overlapping a portion of the second scan signal.

7. The display device according to claim 5, wherein: The scan driver supplies the first scan signal to the first scan line again in a fourth period after the third period, wherein, during a remaining period after the fourth period in the non-emission period, supply of the first scanning signal to the fourth scanning signal is suspended, and The remaining period is longer than the pulse width of the first scanning signal.

8. The display device according to claim 5, wherein The pixel further comprises: An eighth transistor is coupled between the first electrode of the light emitting device and a third power source, and is turned on in response to the first scan signal.

9. The display device according to claim 2, wherein: The scanning driver comprises: a first scan driver that supplies a plurality of first scan signals to the first scan lines during the non-emission period; a second scan driver that supplies a plurality of second scan signals to the second scan lines during the non-emission period; a third scan driver configured to supply the third scan signal to the third scan line between times when the plurality of second scan signals are supplied; and A fourth scan driver supplies the fourth scan signal to the fourth scan line while overlapping with a portion of the plurality of second scan signals.

10. The display device according to claim 7, wherein: The scan driver supplies the third scan signal and the fourth scan signal at the second frequency corresponding to the frame frequency, The frame period includes multiple non-transmission periods. wherein the scan driver supplies the first scan signal during the plurality of non-emission periods, and The scan driver supplies the second scan signal, the third scan signal, and the fourth scan signal only in a first non-emission period among the plurality of non-emission periods.

Images