Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

The present application relates to a semiconductor memory device and a manufacturing method of a semiconductor memory device. A semiconductor memory device and a manufacturing method thereof are provided, the semiconductor memory device including: a plurality of source channels penetrating a source selection line; a gate stack structure overlapping the source selection line; a connection pattern disposed between the source selection line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; and a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method for manufacturing the same. Background Art

[0002] A semiconductor memory device includes memory cells capable of storing data. A three-dimensional semiconductor memory device includes memory cells arranged three-dimensionally so that the area occupied by the memory cells per unit area of ​​a substrate can be reduced. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a semiconductor memory device may include: a plurality of source channels, the plurality of source channels penetrating a source selection line; a gate stack structure, the gate stack structure overlapping the source selection line; a connection pattern, the connection pattern being arranged between the source selection line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; and a plurality of vertical channels, the plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.

[0004] A semiconductor memory device according to an embodiment of the present disclosure may include: a first source channel and a second source channel, the first source channel and the second source channel extending parallel to each other; a first source select line, the first source select line surrounding the first source channel; a second source select line, the second source select line surrounding the second source channel; a gate stack structure, the gate stack structure overlapping the first source select line, the gate stack structure extending to overlap the second source select line; a first vertical channel, the first vertical channel penetrating a first region of the gate stack structure overlapping the first source select line ; a second vertical channel, which penetrates a second area of ​​the gate stack structure overlapping with the second source selection line; a first connection pattern, which connects the first source channel and the first vertical channel between the first source selection line and the gate stack structure; a second connection pattern, which connects the second source channel and the second vertical channel between the second source selection line and the gate stack structure; and a source side slit, which is arranged between the first source selection line and the second source selection line, and extends between the first connection pattern and the second connection pattern.

[0005] According to an embodiment of the present disclosure, a semiconductor memory device may include: a plurality of source channels, the plurality of source channels penetrating a source selection line; a gate stack structure, the gate stack structure overlapping the source selection line; a plurality of vertical channels, the plurality of vertical channels penetrating the gate stack structure; and a connection pattern, the connection pattern being arranged between the source selection line and the gate stack structure to connect the plurality of vertical channels to the plurality of source channels, wherein a thickness of each of the plurality of vertical channels is different from a thickness of each of the plurality of source channels.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device may include the following steps: forming a preliminary gate stack structure having multiple interlayer insulating layers and multiple conductive patterns alternately stacked on a first area of ​​a sacrificial substrate, wherein the preliminary gate stack structure is penetrated by a memory layer and multiple vertical channels; forming a conductive layer connected to the multiple vertical channels on the preliminary gate stack structure; forming a first insulating layer and a selection gate layer on the conductive layer; and forming a source side slit penetrating the first insulating layer, the selection gate layer and the conductive layer, so that the selection gate layer is isolated into multiple source selection lines, and the conductive layer is isolated into multiple connection patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. Like reference numerals represent like elements throughout.

[0008] Figure 1 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 is a perspective view schematically showing a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figures 3A to 3C Layouts of source selection lines, gate stack structures, and bit lines of a semiconductor memory device according to an embodiment of the present disclosure are shown.

[0011] Figure 4A and Figure 4B A gate stack structure and a layout of bit lines of a semiconductor memory device according to an embodiment of the present disclosure are shown.

[0012] Figures 5A to 5C are plan views illustrating various embodiments of source channels.

[0013] Figures 6A to 6C is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0014] 7A to 7B is an enlarged view showing a cross section of a vertical channel and a cross section of a source channel according to an embodiment of the present disclosure.

[0015] Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E 、 Figure 10F 、 Figure 11 、 Figure 12A 、 Figure 12B and Figure 12C is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 13 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0017] Figure 14 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] For the purpose of describing the embodiments of the concepts according to the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. The embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0019] Hereinafter, the terms "first" and "second" are used to distinguish one component from another component, and are not intended to imply a specific number or order of the components. The terms may be used to describe various components, but the components are not limited by these terms.

[0020] Furthermore, it will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements.

[0021] Embodiments provide a semiconductor memory device and a method for manufacturing the semiconductor memory device, which can improve stability of a manufacturing process of a three-dimensional semiconductor memory device and improve operational reliability of the three-dimensional semiconductor memory device.

[0022] Figure 1 is a circuit diagram illustrating a memory block BLK of a semiconductor memory device according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , a semiconductor memory device may include a plurality of memory blocks BLK. Each memory block BLK may include a plurality of memory cell strings MS1 and MS2 connected to a common source layer CSL and a bit line BL.

[0024] Multiple memory cell strings MS1 and MS2 may be connected to a common source layer CSL through source selection transistors SST. Multiple memory cell strings MS1 and MS2 may be connected to a bit line BL through drain selection transistors DST. Each of the memory cell strings MS1 and MS2 may include multiple memory cells MC connected in series.

[0025] The gate of the source select transistor SST may be connected to source select lines SSL1 and SSL2, which are isolated from each other. The gate of the drain select transistor DST may be connected to drain select lines DSL1 and DSL2, which are isolated from each other. The gates of the plurality of memory cells MC may be connected to a plurality of word lines WL. The word lines WL may be arranged at different heights, and the gates of the memory cells MC arranged at the same height may be connected to a single word line WL.

[0026] Hereinafter, the present disclosure will be described mainly based on an embodiment in which a memory block BLK includes first and second source select lines SSL1 and SSL2 that are isolated from each other, and first and second drain select lines DSL1 and DSL2 that are isolated from each other. However, the present disclosure is not limited thereto, and the memory block BLK may include three or more source select lines isolated from each other and three or more drain select lines isolated from each other.

[0027] A plurality of memory cell strings MS1 and MS2 may be connected to respective word lines WL. The plurality of memory cell strings MS1 and MS2 may include a first group and a second group that may be individually selected by a first source select line SSL1 and a second source select line SSL2. The first group may include a first memory cell string MS1, and the second group may include a second memory cell string MS2.

[0028] The first memory cell strings MS1 can be connected to the bit lines BL through drain selection transistors DST connected to the first drain selection lines DSL1. The second memory cell strings MS2 can be connected to the bit lines BL through drain selection transistors DST connected to the second drain selection lines DSL2. In other words, a pair of first and second memory cell strings MS1 and MS2 among the first and second memory cell strings MS1 and MS2 can be connected to the bit lines BL corresponding to the pair of first and second memory cell strings MS1 and MS2.

[0029] The first memory cell string MS1 can be connected to the common source layer CSL via a source select transistor SST connected to a first source select line SSL1, and the second memory cell string MS2 can be connected to the common source layer CSL via a source select transistor SST connected to a second source select line SSL2. Therefore, multiple memory cell strings MS1 and MS2 can be simultaneously isolated into multiple groups, and these groups can be individually selected for each of the source select lines SSL1 and SSL2 during a read operation or a verify operation. In an embodiment, during a read operation or a verify operation, one of the first source select line SSL1 and the second source select line SSL2 is selected so that one of the first group of the first memory cell string MS1 and the second group of the second memory cell string MS2 can be connected to the common source layer CSL. Therefore, in the present disclosure, channel resistance can be reduced compared to when the first memory cell string MS1 and the second memory cell string MS2 are simultaneously connected to the common source layer CSL during a read operation or a verify operation. Therefore, in the present disclosure, read disturbance can be reduced.

[0030] Figure 2 is a perspective view schematically showing a semiconductor memory device according to an embodiment of the present disclosure.

[0031] Reference Figure 2 , the semiconductor memory device may include: source selection lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B], which are isolated from each other by source side slits SS1 and SS2; source channels SC1[A], SC2[A], SC1[B], and SC2[B], which penetrate the source selection lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B]; connection patterns CP1[A], CP2[A], CP1[B], and CP2[ B], which overlap with the source selection lines SSL1[A], SSL2[A], SSL1[B] and SSL2[B] respectively; vertical channels VC1[A], VC2[A], VC1[B] and VC2[B], which are in contact with the connection patterns CP1[A], CP2[A], CP1[B] and CP2[B]; and gate stack structures GST[A] and GST[B], which surround the vertical channels VC1[A], VC2[A], VC1[B] and VC2[B].

[0032] The semiconductor memory device may include a first gate stack structure GST[A] and a second gate stack structure GST[B] isolated from each other by a slit SI.

[0033] The first gate stack structure GST[A] may include a plurality of word lines WL[A] and drain selection lines overlapping the plurality of word lines WL[A] and isolated from each other by drain side slits SD.

[0034] In embodiments, the first gate stack structure GST[A] may include a first drain select line DSL1[A] overlapping the first region R1 of the plurality of word lines WL[A] and a second drain select line DSL2[A] overlapping the second region R2 of the plurality of word lines WL[A]. The plurality of word lines WL[A] may include a third region R3. The third region R3 may be disposed between the first region R1 and the second region R2 and may connect the first region R1 and the second region R2 to each other. A drain-side slit SD may be disposed between the first drain select line DSL1[A] and the second drain select line DSL2[A] and may overlap the third region R3 of the word lines WL[A].

[0035] The first drain select line DSL1[A] and the first region R1 of the word line WL[A] may be penetrated by a plurality of first vertical channels VC1[A] extending in the first direction D1. The second drain select line DSL2[A] and the second region R2 of the word line WL[A] may be penetrated by a plurality of second vertical channels VC2[A] extending in the first direction D1.

[0036] Each of the word line WL[A], the first drain select line DSL1[A], and the second drain select line DSL2[A] may extend along a plane intersecting the first direction D1. In an embodiment, each of the word line WL[A], the first drain select line DSL1[A], and the second drain select line DSL2[A] may extend in a second direction D2 and a third direction D3. The slit S1 and the drain-side slit SD may extend in the second direction D2. The first drain select line DSL1[A] and the second drain select line DSL2[A] may be adjacent to each other in the third direction D3. The first direction D1, the second direction D2, and the third direction D3 may correspond to directions facing the X-axis, the Y-axis, and the Z-axis, respectively, in an XYZ coordinate system.

[0037] The third region R3 of the word line WL[A] may be penetrated by a plurality of dummy channels DVC[A]. The dummy channels DVC[A] may be arranged in a row in the second direction D2. The drain-side slit SD may overlap with the dummy channels DVC[A]. In another embodiment, the dummy channels DVC[A] may be omitted. Figure 2 Compared to the illustrated embodiment, in the embodiment where the dummy channel DVC[A] is omitted, the distance defined between the first drain select line DSL1[A] and the second drain select line DSL2[A] in the third direction D3 may be narrowed.

[0038] Similar to the first gate stack structure GST[A], the second gate stack structure GST[B] may include a plurality of word lines WL[B] and a first drain select line DSL1[B] and a second drain select line DSL2[B] isolated from each other by a drain-side slit SD. Furthermore, similar to the first gate stack structure GST[A], the second gate stack structure GST[B] may be penetrated by a plurality of first vertical channels VC1[B], a plurality of second vertical channels VC2[B], and a plurality of dummy channels DVC[B].

[0039] The first gate stack structure GST[A] and the second gate stack structure GST[B] may overlap with the source select lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B]. The source select lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B] may be isolated from each other at substantially the same height. The source select lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B] may include a first group of first source select lines SSL1[A] and second source select lines SSL2[A] and a second group of first source select lines SSL2[A] and second source select lines SSL2[B]. The first group of first source select lines SSL1[A] and second source select lines SSL2[A] may be disposed between the first gate stack structure GST[A] and the common source layer CSL. The first and second source select lines SSL2 [A] and SSL2 [B] of the second group may be disposed between the second gate stack structure GST [B] and the common source layer CSL.

[0040] The plurality of word lines WL[A] of the first gate stack structure GST[A] may extend to overlap with the first and second source select lines SSL1[A] of the first group. A first region R1 of the word line WL[A] may overlap with the first source select line SSL1[A] of the first group, and a second region R2 of the word line WL[A] may overlap with the second source select line SSL2[A] of the first group. The first source select line SSL1[A] of the first group may be separated from the second source select line SSL2[A] of the first group by a first source-side slit SS1 extending in the second direction D2.

[0041] Similar to the first gate stack structure GST[A], the plurality of word lines WL[B] of the second gate stack structure GST[B] may overlap with the first and second source select lines SSL1[B] and SSL2[B] of the second group that are spaced apart from each other. The first and second source select lines SSL1[A] and SSL2[A] of the first group may be spaced apart from the first and second source select lines SSL1[B] and SSL2[B] of the second group by second source-side slits SS2 extending in the second direction D2.

[0042] The source channels SC1 [A], SC2 [A], SC1 [B], and SC2 [B] may include a first group of source channels SC1 [A] and SC2 [A] and a second group of source channels SC1 [B] and SC2 [B].

[0043] The first group of source channels SC1[A] and SC2[A] may include a plurality of first source channels SC1[A] and a plurality of second source channels SC2[A]. The plurality of first source channels SC1[A] may be surrounded by a first group of first source select lines SSL1[A]. The plurality of second source channels SC2[A] may be surrounded by a first group of second source select lines SSL2[A].

[0044] Similar to the source channels SC1[A] and SC2[A] of the first group, the source channels SC1[B] and SC2[B] of the second group may include a plurality of first source channels SC1[B] surrounded by a first source selection line SSL1[B] of the second group and a plurality of second source channels SC2[B] surrounded by a second source selection line SSL2[B] of the second group.

[0045] The source channels SC1 [A], SC2 [A], SC1 [B], and SC2 [B] of the first and second groups may extend in the first direction D1 to be commonly connected to the common source layer CSL.

[0046] The first source-side slit SS1 and the second source-side slit SS2 may extend between the connection patterns CP1[A], CP2[A], CP1[B], and CP2[B]. The connection patterns CP1[A], CP2[A], CP1[B], and CP2[B] may be arranged at substantially the same height. The connection patterns CP1[A], CP2[A], CP1[B], and CP2[B] may include a first group of first and second connection patterns CP1[A] and a second group of first and second connection patterns CP1[B] and CP2[B].

[0047] The first connection pattern CP1[A] of the first group may be disposed between the first source select line SSL1[A] of the first group and the first gate stack structure GST[A]. The second connection pattern CP2[A] of the first group may be disposed between the second source select line SSL2[A] of the first group and the first gate stack structure GST[A]. The first connection pattern CP1[A] and the second connection pattern CP2[A] of the first group may extend parallel to the first source select line SSL1[A] and the second source select line SSL2[A] of the first group.

[0048] The plurality of first source channels SC1[A] may extend to contact the first connection pattern CP1[A]. The plurality of first vertical channels VC1[A] may be commonly connected to the first connection pattern CP1[A] and may be connected to the plurality of first source channels SC1[A] via the first connection pattern CP1[A]. The plurality of second source channels SC2[A] may extend to contact the second connection pattern CP2[A]. The plurality of second vertical channels VC2[A] may be commonly connected to the second connection pattern CP2[A] and may be connected to the plurality of second source channels SC2[A] via the second connection pattern CP2[A].

[0049] The first and second connection patterns CP1[B] and CP2[B] of the second group may have a similar structure to the first and second connection patterns CP1[A] and CP2[A] of the first group. The slits S1 may extend between the first and second connection patterns CP1[A] and CP2[A] of the first group and the first and second connection patterns CP1[B] and CP2[B] of the second group, and the slits S1 may be connected to the second source-side slits SS2.

[0050] Figures 3A to 3C Layouts of source selection lines, gate stack structures, and bit lines of a semiconductor memory device according to an embodiment of the present disclosure are shown.

[0051] Figure 3A 1 is a plan view showing an embodiment of a first group of first and second source select lines SSL1 [A] and SSL2 [A] and a second group of first source select lines SSL [B].

[0052] Reference Figure 3A Source select lines SSL1[A], SSL2[A], and SSL1[B] may respectively surround source channels SC1[A], SC2[A], and SC1[B] extending in a first direction D1. A sidewall of each of the source channels SC1[A], SC2[A], and SC1[B] may be surrounded by a gate insulating layer GI. In other words, the gate insulating layer GI may be provided between each of the source select lines SSL1[A], SSL2[A], and SSL1[B] and each of the source channels SC1[A], SC2[A], and SC1[B].

[0053] The first source-side slit SS1 and the second source-side slit SS2 may extend in the second direction D2. Each of the first source-side slit SS1 and the second source-side slit SS2 may have various shapes such as a wavy shape and a linear shape.

[0054] Figure 3B is shown with Figure 3AThe first gate stack structure GST[A] and the first gate stack structure GST[A] overlapped with the first source selection line SSL1[A] and the second source selection line SSL2[A] of the first group shown in FIG. Figure 3A FIG. 1 is a plan view of a second gate stack structure GST[B] overlapped with the first source selection line SSL1[B] of the second group.

[0055] Reference Figure 3B The plurality of word lines WLA and drain select lines DSL1[A] and DSL2[A] of the first gate stack structure GST[A] may be separated from the plurality of word lines WL[B] and drain select line DSL1[B] of the second gate stack structure GST[B] by slits SI. The drain-side slits SD overlapping the word lines (e.g., WL[A]) may overlap the dummy channels (e.g., DVC[A]).

[0056] Each of the slits S1 and the drain side slits SD may have various shapes such as a wave shape and a linear shape. In an embodiment, each of the slits S1 and the drain side slits SD may have a linear shape.

[0057] The word lines WL[A] and WL[B] and the drain select lines DSL1[A], DSL2[A], and DSL1[B] may surround the vertical channels VC1[A], VC2[A], and VC1[B]. The sidewalls of each of the vertical channels VC1[A], VC2[A], and VC1[B] may be surrounded by the memory layer ML. In other words, the memory layer ML may be provided between the word lines WL[A] and WL[B] and each of the drain select lines DSL1[A], DSL2[A], and DSL1[B] and each of the vertical channels VC1[A], VC2[A], and VC1[B].

[0058] The cross-sectional area of ​​each of the source channels SC1[A], SC2[A], and SC1[B] may be wider than the cross-sectional area of ​​each of the vertical channels VC1[A], VC2[A], and VC1[B]. The central axis of some of the vertical channels VC1[A], VC2[A], and VC1[B] may not overlap with the central axis of the source channels SC1[A], SC2[A], and SC1[B], but may be misaligned with the central axis of the source channels SC1[A], SC2[A], and SC1[B]. Some of the vertical channels VC1[A], VC2[A], and VC1[B] may not overlap with the source channels SC1[A], SC2[A], and SC1[B]. Two or more of the vertical channels VC1[A], VC2[A], and VC1[B] may overlap with some of the source channels SC1[A], SC2[A], and SC1[B].

[0059] The dummy channels DVC[A] may not overlap with the source channels SC1[A], SC2[A], and SC1[B]. The dummy channels DVC[A] may be arranged in a row along an extending direction of the drain-side slits SD.

[0060] Figure 3C is shown with Figure 3B A plan view of the bit line BL where vertical channels VC1[A], VC2[A], and VC1[B] overlap is shown.

[0061] Reference Figure 3C Each bit line BL can be connected to a reference Figure 3B The vertical channels VC1[A], VC2[A] and VC1[B] connected to a single bit line can be individually controlled by different drain select lines DSL1[A], DSL2[A] and DSL1[B], such as Figure 3B shown.

[0062] Figure 4A and Figure 4B A gate stack structure and a layout of bit lines of a semiconductor memory device according to an embodiment of the present disclosure are shown.

[0063] Figure 4A 1 is a plan view showing a first gate stacked structure GST[A] and a second gate stacked structure GST[B]. Figure 4A Layouts of a plurality of word lines WL[A] and drain select lines DSL1[A] and DSL2[A] of the first gate stack structure GST[A] and a plurality of word lines WL[B] and drain select line DSL1[B] of the second gate stack structure GST[B] are shown.

[0064] Reference Figure 4A The drain-side slits SD overlapping the plurality of word lines (e.g., WL[A]) may have a shape different from the slits S1 between the first and second gate stack structures GST[A] and GST[B]. In an embodiment, the slits S1 may extend linearly in the second direction D2, and the drain-side slits SD may extend in a wavy shape in the second direction D2.

[0065] The first gate stack structure GST[A] and the second gate stack structure GST[B] may be penetrated by the vertical channels VC1[A], VC2[A], and VC1[B] surrounded by the memory layer ML. The vertical channels VC1[A], VC2[A], and VC1[B] may be arranged in a zigzag shape. The drain-side slit SD may have wavy sidewalls corresponding to the sidewall shapes of adjacent vertical channels (e.g., VC1[A] and VC2[A]), and the drain-side slit SD is interposed between the vertical channels (VC1[A] and VC2[A]).

[0066] Figure 4B is shown with Figure 4A A plan view of the bit line BL where vertical channels VC1[A], VC2[A], and VC1[B] overlap is shown.

[0067] Reference Figure 4B Each bit line BL can be connected to a reference Figure 4A The vertical channels VC1[A], VC2[A] and VC1[B] connected to a single bit line can be individually controlled by different drain select lines DSL1[A], DSL2[A] and DSL1[B], such as Figure 4A shown.

[0068] Figures 5A to 5C 1 and 2 are plan views showing various embodiments of the source channel CS.

[0069] Reference Figures 5A to 5C , each source channel SC may be surrounded by a source select line SSL with a gate insulating layer GI interposed therebetween. The source channel SC may have various layouts.

[0070] Reference Figures 5A to 5C , each source channel SC may extend in the first direction D1 and have an elliptical cross-sectional shape. The cross-sectional shape of each source channel SC is not limited to the elliptical shape and may have various shapes such as a circular shape and a polygonal shape.

[0071] Reference Figure 5A In an embodiment, the minor axis and the major axis of the elliptical shape may be parallel to the axis extending in the second direction D2 and the axis extending in the third direction D3, respectively. Figure 5B and Figure 5C In another embodiment, the minor axis and the major axis of the elliptical shape may face in inclined directions with respect to the axis extending in the second direction D2 and the axis extending in the third direction D3, respectively.

[0072] Reference Figures 5A to 5C , the source channel SC may include channel columns arranged along the second direction D2. In an embodiment, as Figure 5A and Figure 5C As shown, the source channel SC may include a channel column. In another embodiment, as shown in FIG. Figure 5B As shown, the source channel SC may include two channel columns. However, the present disclosure is not limited thereto, and the source channel SC may include three or more channel columns.

[0073] Figures 6A to 6C is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure. Figure 6A and Figure 6C shows a cell array region of a semiconductor memory device, Figure 6B Shows the connection area of ​​a semiconductor memory device.

[0074] Reference Figures 6A to 6C , a semiconductor memory device may include: a peripheral circuit structure 10; a gate stack structure GST, which overlaps with the peripheral circuit structure 10 and surrounds a plurality of vertical channels VC1 and VC2; a common source layer CSL, which is arranged between the gate stack structure GST and the peripheral circuit structure 10; source selection lines SSL1 and SSL2, which are arranged at substantially the same height between the common source layer CSL and the gate stack structure GST to be spaced apart from each other; connection patterns CP1 and CP2, which are arranged at substantially the same height between the source selection lines SSL1 and SSL2 and the gate stack structure GST to be spaced apart from each other; and a bit line BL, which overlaps with the connection patterns CP1 and CP2, with the gate stack structure GST interposed therebetween.

[0075] The gate stack structure GST may include interlayer insulating layers 51 and conductive patterns 53 alternately stacked in a first direction D1 in which vertical channels VC1 and VC2 extend. The conductive patterns 53 may be formed of various conductive materials. The conductive patterns 53 may include drain select lines DSL1 and DSL2 overlapping source select lines SSL1 and SSL2, respectively, and word lines WL spaced apart from each other and disposed between the drain select lines DSL1 and DSL2 and the source select lines SSL1 and SSL2.

[0076] The gate stack structure GST may be penetrated by vertical channels VC1 and VC2. Each of the vertical channels VC1 and VC2 may include a vertical core insulating layer 43 and a vertical channel layer 41. The vertical channel layer 41 may extend along the sidewalls of the vertical core insulating layer 43 and along the surface of the vertical core insulating layer 43 facing the bit line BL. The vertical channel layer 41 may include a semiconductor layer that may serve as a channel for the memory cell string. In an embodiment, the vertical channel layer 41 may include silicon.

[0077] The sidewall of each of the vertical channels VC1 and VC2 may be surrounded by the memory layer ML. A partial area of ​​the memory layer ML may be used as a data storage area. A partial area of ​​the memory layer ML may be defined at an intersection of each of the vertical channels VC1 and VC2 and the word line WL.

[0078] The bit lines BL may be formed of various conductive materials. The bit lines BL may be spaced apart from the gate stack structure GST. In an embodiment, the bit lines BL may be insulated from the gate stack structure GST by a first upper insulating layer 83 and a second upper insulating layer 87. The first upper insulating layer 83 and the second upper insulating layer 37 may extend between the bit lines BL and the gate stack structure GST. The bit lines BL may be connected to the vertical channels VC1 and VC2 via contact plugs CT formed of a conductive material. Each contact plug CT may penetrate the upper insulating layers 83 and 87 and the memory layer ML between the vertical channel layer 41 and the bit lines BL and may contact the vertical channel layer 41 and the bit lines BL.

[0079] Each of the connection patterns CP1 and CP2 may include a doped semiconductor layer 47. In an embodiment, the doped semiconductor layer 47 may include a doped silicon layer. The doped semiconductor layer 47 may include conductive impurities. In an embodiment, the doped semiconductor layer 47 may include n-type impurities such as phosphorus. The doped semiconductor layer 47 may include a line portion 47A extending parallel to each of the source select lines SSL1 and SSL2 and a protrusion 47B protruding from the line portion 47A toward the vertical core insulating layer 43. The protrusion 47B of the doped semiconductor layer 47 may have sidewalls surrounded by the vertical channel layer 41.

[0080] The vertical channel layer 41 may protrude further than the vertical core insulating layer 43 toward the line portion 47A of the doped semiconductor layer 47 to surround the sidewall of the protrusion 74B of the doped semiconductor layer 47. The vertical channel layer 41 may contact the protrusion 47B of the doped semiconductor layer 47. Since the protrusion 47B includes a conductive dopant, the specific resistance of the protrusion 47B may be lower than that of the undoped semiconductor layer. Since the vertical channel layer 41 contacts the protrusion 47B having a low specific resistance, the channel current in the vertical channel layer 41 may be improved.

[0081] Source select lines SSL1 and SSL2 may be formed of various conductive materials. Source select lines SSL and SSL2 may be spaced apart from connection patterns CP1 and CP2 and the common source layer CSL. In an embodiment, source select lines SSL and SSL2 may be insulated from connection patterns CP1 and CP2 by a first insulating layer 55 and from the common source layer CSL by a second insulating layer 59. The first insulating layer 55 may extend between connection patterns CP1 and CP2 and source select lines SSL1 and SSL2. The second insulating layer 59 may extend between source select lines SSL1 and SSL2 and the common source layer CSL.

[0082] The first insulating layer 55, the source select lines SSL1 and SSL2, and the second insulating layer 59 may be penetrated by the source channels SC1 and SC2. Each of the source channels SC1 and SC2 may include a source core insulating layer 63 and a source channel layer 61. The source channel layer 61 may extend along the sidewalls of the source core insulating layer 63 and may extend along the surface of the source core insulating layer 63 facing the connection patterns CP1 and CP2. The source channel layer 61 may include a semiconductor layer that may serve as a channel of the source select transistor. In an embodiment, the source channel layer 61 may include silicon. The sidewalls of each of the source channels SC1 and SC2 facing the source select lines SSL and SSL2 may be surrounded by a gate insulating layer GI.

[0083] The common source layer CSL may include a line portion 67A extending parallel to the source select lines SSL1 and SSL2, and a protrusion 67B protruding from the line portion 67A toward the source core insulating layer 63. The common source layer CSL may include a doped semiconductor layer. In an embodiment, the common source layer CSL may include a doped silicon layer. The doped semiconductor layer of the common source layer CSL may include conductive impurities. In an embodiment, the doped semiconductor layer of the common source layer CSL may include n-type impurities such as phosphorus. The protrusion 67B of the common source layer CSL may have sidewalls surrounded by the source channel layer 61.

[0084] The source channel layer 61 may protrude further than the source core insulating layer 63 toward the line portion 67A of the common source layer CSL to surround the sidewalls of the protrusion 67B of the common source layer CSL. The source channel layer 61 may contact the protrusion 67B of the common source layer CSL. Since the protrusion 67B includes a conductive dopant, the specific resistance of the protrusion 67B may be lower than that of the undoped semiconductor layer. Since the source channel layer 61 contacts the protrusion 67B having a low specific resistance, the channel current in the source channel layer 61 may be improved.

[0085] The first bonding insulating layer 71 may be disposed between the common source layer CSL and the peripheral circuit structure 10. The first bonding insulating layer 71 may protrude further than each of the gate stack structure GST, the source selection lines SSL1 and SSL2, and the common source layer CSL in the second direction D2. Figure 6B The space between the first upper insulating layer 83 and the portion of the first bonding insulating layer 71 that protrudes further than the common source layer CSL in the second direction D2 may be filled with the first insulating structure 90, as shown. Figure 6B shown.

[0086] The peripheral circuit structure 10 may include: a substrate 1 including a plurality of transistors 20; a second insulating structure 31 covering the first substrate 1; a plurality of interconnect structures 29 buried in the second insulating structure 31; and a second bonding insulating layer 33 covering the plurality of interconnect structures 29 and the second insulating structure 31. The interconnect structures 29 may be connected to the transistors 20 and may transmit electrical signals.

[0087] Substrate 1 may include a semiconductor substrate such as a silicon substrate or a germanium substrate. First substrate 1 may include an active region separated by an isolation layer 3. Transistors 20 may be provided on the active region. Each transistor 20 may include a gate insulating layer 11 and a gate electrode 13 stacked on the active region of substrate 1, and junctions 15 defined in substrate 1 on both sides of gate electrode 13. Junctions 15 may be defined when at least one of p-type and n-type impurities is doped into the active region of substrate 1.

[0088] A plurality of transistors 20 may be included in a peripheral circuit to control the operation of a semiconductor memory device. In an embodiment, at least one transistor 20 may be included in a source control circuit 5. The source control circuit 5 may be connected to a common source layer CSL through some interconnect structures 29 and may control the discharge of the common source layer CSL. In an embodiment, the interconnect structure 29 connected to the source control circuit 5 may include a lower contact structure 21, an interconnect line 23, and an upper contact structure 25. The lower contact structure 21 may be connected to a junction 15 of the source control circuit 5, as shown in FIG. Figure 6A As shown. The lower contact structure 21 may include patterns 21A, 21B and 21C sequentially stacked on the junction 15. The upper contact structure 25 may be provided in the connection area. The interconnection line 23 may be connected to the Figure 6A The lower contact structure 21 is shown in contact and may extend to Figure 6B The connection region is shown to be in contact with the upper contact structure 25. In other words, the lower contact structure 21 and the upper contact structure 25 may be connected to each other through the interconnection line 23.

[0089] The second insulating structure 31 may include a plurality of insulating layers, each including two or more layers.

[0090] The first bonding insulation layer 71 and the second bonding insulation layer 33 may be bonded to each other, thereby forming a bonding structure BS.

[0091] Figure 6A is a cross-sectional view of the semiconductor memory device taken along a line intersecting the bit line BL, and corresponds to a cross-sectional view of the semiconductor memory device taken along a line intersecting the bit line BL. Figure 4B A cross-sectional view taken along line AA' is shown.

[0092] Reference Figure 6A, the source channels SC1 may be connected to the connection pattern CP1 at a lower density than the vertical channels VC1 in the same region. In an embodiment, the number of source channels SC1 connected to the connection pattern CP1 may be smaller than the number of vertical channels VC1 connected to the connection pattern CP1.

[0093] The source channel layer 61 may include a semiconductor layer having a contact pattern 61A and a pillar portion 61B. The contact pattern 61A may be connected to the connection pattern CP1. The pillar portion 61B may extend from the edge of the contact pattern 61A toward the common source layer CSL in a first direction D1. The sidewalls of the source core insulating layer 63 may be surrounded by the pillar portion 61B of the source channel layer 61 between the contact pattern 61A and the common source layer CSL. The pillar portion 61B of the source channel layer 61 may extend to surround the protrusion 67B of the common source layer CSL.

[0094] Impurities of the doped semiconductor layer 47 may diffuse into the contact pattern 61A, and impurities of the common source layer CSL may diffuse into a portion of the pillar portion 61B that contacts the protrusion 67B of the common source layer CSL. The pillar portion 61B may include an undoped area UA. The undoped area UA of the pillar portion 61B may be defined as a region into which impurities of the doped semiconductor layer 47 and impurities of the common source layer CSL are not diffused. More specifically, a portion of the pillar portion 61B may remain as the undoped area UA at a height between the connection pattern CP1 and the common source layer CSL. In an embodiment, the undoped area UA of the pillar portion 61B may remain at a height where the source select line SSL1 is set. The undoped area UA of the pillar portion 61B may improve the cutoff characteristics of the source select transistor connected to the source select line SSL1.

[0095] The vertical core insulating layer 43 may include a first surface SU1 and a second surface SU2 facing opposite directions. The first surface SU1 may face the connection pattern CP1, and the second surface SU2 may face the bit line BL. The vertical channel layer 41 may extend along the second surface SU2 of the vertical core insulating layer 43 and may extend between the vertical core insulating layer 43 and the gate stack structure GST.

[0096] The bit lines BL may be arranged at a pitch narrower than that of the vertical channels VC1 in the second direction D2 . The bit lines BL may penetrate the third upper insulating layer 99 and may make contact with the contact plugs CT.

[0097] Figure 6B Show Figure 6A The source select line SSL and the end portion of the common source layer CSL are shown. Figure 6B is a cross-sectional view of the common source layer CSL and the source selection line SSL1 taken along a line parallel to the second direction D2.

[0098] Reference Figure 6BThe common source layer CSL and the source select line SSL1 may extend in the second direction D2. Ends of the source select line SSL1 and the common source layer CSL may form a stepped structure. More specifically, the common source layer CSL may include a contact area CTA that protrudes further in the second direction D2 than the source select line SSL1.

[0099] The common source layer CSL may be connected to the interconnect structure 29 through a first vertical contact plug 85A, an upper conductive pattern UCP, and a second vertical contact plug 85B. The first vertical contact plug 85A may contact the contact area CTA of the common source layer CSL, and the second vertical contact plug 85B may contact the interconnect structure 29. The upper conductive pattern UCP may connect the first vertical contact plug 85A and the second vertical contact plug 85B to each other.

[0100] The first vertical contact plug 85A and the second vertical contact plug 85B may extend parallel to each other to penetrate the first insulating structure 90 and the first upper insulating layer 83, and may be formed of various conductive materials. The first insulating structure 90 may include multiple insulating layers. In an embodiment, the first insulating structure 90 may include a first filling insulating layer 91, a second filling insulating layer 95, and a third filling insulating layer 97. The first filling insulating layer 91 may be as shown in FIG. Figure 6A The second filling insulating layer 95 is disposed at the same height as the stacked structure of the gate electrode GST and may extend to the height at which the line portion 47A of the doped semiconductor layer 47 is disposed. The second filling insulating layer 95 may be disposed at the same height as the stacked structure of the source selection line SSL1 and the first insulating layer 55. The third filling insulating layer 97 may be disposed at the same height as the stacked structure of the second insulating layer 59 and the common source layer CSL.

[0101] The first vertical contact plug 85A may extend in the first direction D1 to penetrate the first upper insulating layer 83, the first filling insulating layer 91, the second filling insulating layer 95, and the second insulating layer 59. The first vertical contact plug 85A may include a surface contacting the contact area CTA of the common source layer CSL.

[0102] The second vertical contact plug 85B may extend in the first direction D1 to penetrate the first upper insulating layer 83, the first filling insulating layer 91, the second filling insulating layer 95, the third filling insulating layer 97, and the bonding structure BS. The second vertical contact plug 85B may include a surface that contacts the upper contact structure 25 of the interconnection structure 29. The upper contact structure 25 may be a portion of the interconnection structure 29 connected to the source control circuit 5, as shown in FIG. Figure 6A The upper contact structure 25 may include a via plug contacting the interconnection line 23 and a pad pattern 25B disposed between the via plug 25A and the second vertical contact plug 85B.

[0103] The upper conductive pattern UCP may be connected to the first vertical contact plug 85A and the second vertical contact plug 85B through the first via plug 89A and the second via plug 89B. The first via plug 89A and the second via plug 89B may be formed of the same conductive material as the contact plug CT, such as Figure 6A The first and second via plugs 89A and 89B may penetrate the second upper insulating layer 87 and may contact the first and second vertical contact plugs 85A and 85B, respectively. The upper conductive pattern UCP may penetrate the third insulating layer 99 and may extend from the first via plug 89A toward the second via plug 89B.

[0104] Figure 6C is a cross-sectional view of the semiconductor memory device taken along a line parallel to the bit line BL. Figure 6C Corresponding to along Figure 4B A cross-sectional view taken along line BB' is shown.

[0105] Reference Figure 6C , the source channels SC1 and SC2 may include a first source channel SC1 and a second source channel SC2 extending parallel to each other.

[0106] The source select lines SSL1 and SSL2 may include a first source select line SSL1 and a second source select line SSL2 isolated from each other by a source-side slit SS. The first source select line SSL1 may surround a sidewall of the first source channel SC1, and the second source select line SSL2 may surround a sidewall of the second source channel SC2.

[0107] The vertical channels VC1 and VC2 may include a first vertical channel VC1 and a second vertical channel VC2. The first vertical channel VC1 may overlap with the first source selection line SSL1. The second vertical channel VC2 may overlap with the second source selection line SSL2.

[0108] The connection patterns CP1 and CP2 may include a first connection pattern CP1 and a second connection pattern CP2 isolated from each other by a source-side slit SS. The first connection pattern CP1 may connect the first source channel SC1 and the first vertical channel VC1 between the first source select line SSL1 and the gate stack structure GST. The second connection pattern CP2 may connect the second source channel SC2 and the second vertical channel VC2 between the second source select line SSL2 and the gate stack structure GST.

[0109] The second insulating layer 59 may extend to fill the source-side slit SS. In an embodiment, the second insulating layer 59 may be disposed between the first source select line SSL1 and the second source select line SSL2. In addition, the second insulating layer 59 may penetrate the first insulating layer 55 and extend between the first connection pattern CP1 and the second connection pattern CP2.

[0110] The drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2 isolated from each other by a drain-side slit SD. The first drain select line DSL1 may overlap the first source select line SSL1 and surround the first vertical channel VC1. The second drain select line DSL2 may overlap the second source select line SSL2 and surround the second vertical channel VC2.

[0111] Each conductive pattern 53 serving as a word line WL may surround the first vertical channel VC1 between the first drain select line DSL1 and the first connection pattern CP1. Each conductive pattern 53 serving as a word line WL may extend between the second drain select line DSL2 and the second connection pattern CP2 to surround the second vertical channel VC2.

[0112] The first upper insulating layer 83 may extend to fill the drain-side slit SD. In an embodiment, the first upper insulating layer 83 may penetrate the interlayer insulating layer adjacent to the first upper insulating layer 83 among the interlayer insulating layers 51 and may extend between the first drain select line DSL1 and the second drain select line DSL2. The first vertical channel VC1 and the second vertical channel VC2 may extend into the interior of the first upper insulating layer 83.

[0113] The bit line BL may extend in the third direction D3 to overlap the first and second connection patterns CP1 and CP2 , and may be connected to a pair of first and second vertical channels VC1 and VC2 corresponding to the bit line BL through a contact plug CT.

[0114] 7A to 7B is an enlarged view showing a cross section of a vertical channel VC and a cross section of a source channel SC according to an embodiment of the present disclosure.

[0115] Reference Figure 7A , the vertical channel VC may be surrounded by the conductive pattern 53, and the memory layer ML is interposed between the vertical channel VC and the conductive pattern 53. The memory layer ML may include a tunnel insulating layer TI, a data storage layer DS, and a blocking insulating layer BI.

[0116] The tunnel insulating layer TI may extend along the surface of the vertical channel layer 41. The tunnel insulating layer TI may include an insulating material through which charges can tunnel. In an embodiment, the tunnel insulating layer TI may include a silicon oxide layer.

[0117] The data storage layer DS may extend along the surface of the tunnel insulating layer TI. The data storage layer DS may include a material layer capable of storing data. In an embodiment, the data storage layer DS may include a nitride layer capable of storing data changed by Fowler-Nordheim tunneling.

[0118] The blocking insulating layer BI may extend along the surface of the data storage layer DS. The blocking insulating layer BI may include an oxide layer.

[0119] The vertical core insulating layer 43 of the vertical channel VC may be spaced apart from the memory layer ML by the vertical channel layer 41 .

[0120] Reference Figure 7B The source core insulating layer 63 of the source channel SC may be separated from the source select line SSL by the gate insulating layer GI and the source channel layer 61. The pillar portion 61B of the source channel layer 61 may be surrounded by the source select line SSL with the gate insulating layer GI interposed therebetween.

[0121] Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E 、 Figure 10F 、 Figure 11 、 Figure 12A 、 Figure 12B and Figure 12C is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0122] Figure 8A and Figure 8B is a cross-sectional view illustrating a process of forming the preliminary gate stack structure 110 , the conductive layer 137 , and the selection gate layer 143 .

[0123] Reference Figure 8A A preliminary gate stack structure 110 penetrated by a memory layer 123 and a plurality of vertical channels 130 may be formed on a sacrificial substrate 101 including a first region A1 and a second region A2. The sacrificial substrate 101 may be a silicon substrate.

[0124] The preliminary gate stack structure 110 may be formed on the first area A1 of the sacrificial substrate 101. The preliminary gate stack structure 110 may be penetrated by a plurality of vertical channel holes 121 extending in the first direction D1. The plurality of vertical channel holes 121 may extend into the first area A1 of the sacrificial substrate 101.

[0125] The memory layer 123 may extend along the surface of each vertical channel hole 121. The memory layer 123 may include Figure 7A The blocking insulating layer BI, the data storage layer DS and the tunnel insulating layer TI are shown.

[0126] Each vertical channel 130 may include a vertical channel layer 131 and a vertical core insulating layer 133. The vertical channel layer 131 may extend along the surface of the memory layer 123, and the central region of the vertical channel hole 121 may be open. The vertical channel layer 131 may include a semiconductor layer. In an embodiment, the vertical channel layer 131 may include undoped silicon. The vertical core insulating layer 133 may be disposed in the central region of the vertical channel hole 121 that is open through the vertical channel layer 131.

[0127] The preliminary gate stack structure 110 may include interlayer insulating layers 111 and conductive patterns 113 alternately stacked on the first area A1 of the sacrificial substrate 101. The interlayer insulating layers 111 and the conductive patterns 113 may surround a plurality of vertical channels 130, with the memory layer 123 interposed between the plurality of vertical channels 130 and each of the interlayer insulating layers 111 and the conductive patterns 113. The plurality of vertical channels 130 may include a first vertical channel 130A and a second vertical channel 130B.

[0128] Subsequently, a conductive layer 137 connected to the plurality of vertical channels 130 may be formed on the preliminary gate stack structure 110. The conductive layer 137 may include a doped semiconductor layer. In an embodiment, the conductive layer 137 may include a doped silicon layer, and the doped silicon layer may include n-type impurities. The conductive layer 137 may extend toward the center region of each vertical channel hole 121.

[0129] In an embodiment, the process of forming the conductive layer 137 may include etching a portion of the vertical core insulating layer 133 to define a first recessed region 135 in a central region of the vertical channel hole 121, and forming a doped semiconductor layer on the preliminary gate stack structure 110 to fill the first recessed region 135. A portion of an inner wall of the vertical channel layer 131 may be exposed through the first recessed region 135.

[0130] The conductive layer 137 and the preliminary gate stack structure 110 may be patterned so as not to overlap with the second region A2 of the sacrificial substrate 101. The second region A2 may be a region extending from the first region A1 of the sacrificial substrate 101. In an example, the second region A2 may extend from the first region A1 in a second direction D2 intersecting the plurality of vertical channels 130.

[0131] Subsequently, a first filling insulating layer 115 may be formed to cover the second region A2 of the sacrificial substrate 101 opened by the conductive layer 137 and the preliminary gate stack structure 110. The first filling insulating layer 115 may extend to a height at which the conductive layer 137 is provided.

[0132] Reference Figure 8B, a first insulating layer 141 and a selection gate layer 143 may be formed on the conductive layer 137. The first insulating layer 141 and the selection gate layer 143 may extend to cover the first filling insulating layer 115. The selection gate layer 143 may be formed of various conductive materials.

[0133] Figure 9A and Figure 9B is shown in reference Figure 8B A cross-sectional view of a process of forming a source selection line 143S continues after the described process. Figure 9A is a cross-sectional view taken along an axis parallel to one of the source selection lines 143S. Figure 9B It is a cross-sectional view taken along an axis crossing the source selection line 143S.

[0134] Reference Figure 9A and Figure 9B , a penetration layer may be formed by etching the selection gate layer 143, the first insulating layer 141 and the conductive layer 137 Figure 8B The selection gate layer 143, the first insulating layer 141, and the source-side slits 145 of the conductive layer 137 are shown. Therefore, the selection gate layer 143 can be isolated into a plurality of source selection lines 143S, and the conductive layer 137 can be isolated into a plurality of connection patterns 137CP.

[0135] The plurality of source selection lines 143S may include a first source selection line and a second source selection line, and the plurality of connection patterns 137CP may include a first connection pattern and a second connection pattern. The first connection pattern may contact the first vertical channel 130A, and the second connection pattern may contact the second vertical channel 130B. Figure 9B As shown, the first source select line may overlap the first vertical channel 130A, and the second source select line may overlap the second vertical channel.

[0136] Each of the source selection lines 143S may include an end portion EG[S] overlapping the first filling insulation layer 115 .

[0137] 10A to 10F is shown in reference Figure 9A and Figure 9B A cross-sectional view of a process continuing after the described process. 10A to 10F Each of them is a cross-sectional view taken along an axis parallel to one of the source selection lines 143S.

[0138] Reference Figure 10A A second filling insulating layer 151 covering the end portion EG[S] of the source selection line 143S may be formed on the first filling insulating layer 115 .

[0139] Subsequently, a second insulating layer 153 may be formed. The second insulating layer 153 may cover the source selection line 143S. The second insulating layer 153 may extend to cover the second filling insulating layer 151.

[0140] Subsequently, source channel holes 157 may be formed. The source channel holes 157 may penetrate the second insulating layer 153, the source select lines 143S, and the first insulating layer 141, and may expose the connection pattern 137CP. Subsequently, a gate insulating layer 155 may be formed on the sidewalls of the source select lines 143S exposed by the respective source channel holes 157.

[0141] In an embodiment, the gate insulating layer 155 may be formed through an oxidation process. During the oxidation process of forming the gate insulating layer 155, an oxide layer formed on the surface of the connection pattern 137CP may be removed through an etch-back process.

[0142] Reference Figure 10B , can be filled with source channel 160 Figure 10A A source channel hole 157 is shown. The source channel 160 may contact the connection pattern 137CP.

[0143] The process of forming the source channel 160 may include: Figure 10A The process of forming an undoped semiconductor layer 161 on the surface of each source channel hole 157 and the process of forming a source core insulating layer 163 on the undoped semiconductor layer 161. In an embodiment, the undoped semiconductor layer 161 may include undoped silicon. The undoped semiconductor layer 161 may be separated from the source selection line 143S by the gate insulating layer 155. The source core insulating layer 163 may be filled with Figure 10A The central area of ​​each source channel hole 157 is shown.

[0144] Subsequently, a portion of the source core insulating layer 163 may be etched, thereby defining a second recessed region 165 . A portion of an inner wall of the undoped semiconductor layer 161 may be exposed through the second recessed region 165 .

[0145] Reference Figure 10C A doped semiconductor layer may be formed on the second insulating layer 153 to Figure 10B The second recessed region 165 is shown filled. In an embodiment, the doped semiconductor layer may include n-type impurities and may include a doped silicon layer.

[0146] Subsequently, the doped semiconductor layer and the second insulating layer 153 may be etched. Thus, the doped semiconductor layer may remain as a common source layer 167L connected to the source channel 160.

[0147] The common source layer 167L may include an end portion EG[C] overlapping the second filling insulating layer 151. The end portion EG[C] of the common source layer 167L may protrude further toward the second direction D2 than the end portion EG[S] of the source selection line 143S.

[0148] The common source layer 167L may include a line portion 167A and a protrusion 167B. The line portion 167A may be parallel to the source selection line 143S. The protrusion 167B may extend from the line portion 167A toward the source core insulating layer 163. Figure 10B The illustrated second recessed region 165 may be filled with a protrusion 167B corresponding to the second recessed region 165 . In addition, the protrusion 167B corresponding to the second recessed region 165 may contact an inner wall of the undoped semiconductor layer 161 .

[0149] Reference Figure 10D , a third filling insulating layer 169 may be formed on the second filling insulating layer 151. The third filling insulating layer 169 may cover an end portion EG[C] of the common source layer 167L.

[0150] Subsequently, a first bonding insulation layer 171 may be formed. The first bonding insulation layer 171 may cover the common source layer 167L. The first bonding insulation layer 171 may extend to cover the third filling insulation layer 169 .

[0151] Reference Figure 10E , a peripheral circuit structure 200 formed by a separate process can be provided. Figure 6A and Figure 6B As described, the peripheral circuit structure 200 may include a substrate 201 having a plurality of transistors 210 , an insulating structure 231 covering the substrate 201 , a plurality of interconnect structures buried in the insulating structure 231 , and a second bonding insulating layer 233 covering the plurality of interconnect structures and the insulating structure 231 .

[0152] The transistors 210 may be insulated from each other by an isolation layer 203 formed in the substrate 201. At least one transistor 210 may be included in the source control circuit 205. The interconnect structure connected to the source control circuit 205 may include a lower contact structure 221, an upper contact structure 225, and an interconnect line 223. The lower contact structure 221 may be connected to the transistor 210 of the source control circuit 205. The upper contact structure 225 may not overlap with the transistor 210 of the source control circuit 250. The interconnect line 223 may connect the lower contact structure 221 and the upper contact structure 225. The lower contact structure 221 may include patterns 221A, 221B, and 221C sequentially stacked between the transistor 210 of the source control circuit 205 and the interconnect line 223. The transistor 210 of the source control circuit 205 may be connected to the interconnect line 223 via the lower contact structure 221. The interconnect line 223 may extend in the second direction D2 toward the upper contact structure 225. The upper contact structure 225 may include a via plug 225A and a pad pattern 225B. The via plug 225A may contact the interconnection line 223. The pad pattern 225B may be disposed on the via plug 225A.

[0153] The sacrificial substrate 101 may overlap the peripheral circuit structure 200 such that the first bonding insulation layer 171 faces the second bonding insulation layer 233 of the peripheral circuit structure 200. Subsequently, a process of bonding the first bonding insulation layer 171 and the second bonding insulation layer 233 to each other may be formed.

[0154] Reference Figure 10F , can be removed Figure 10E The sacrificial substrate 101 is shown. Therefore, the memory layer 123 penetrating the preliminary gate stack structure 110 may be exposed. Subsequently, conductive impurities may be implanted into the ends of each vertical channel 130. In an embodiment, n-type impurities may be implanted into the ends of the vertical channels 130.

[0155] Figure 11 is shown in reference Figure 10F A cross-sectional view of a process of forming a drain select line 113D continues after the described process. Figure 11 It is a cross-sectional view taken along an axis crossing the source selection line 143S.

[0156] Reference Figure 11 , a drain side slit 181 can be formed. The drain side slit 181 can penetrate Figure 10F A portion of the preliminary gate stack structure 110 is shown, such that Figure 10F At least one conductive pattern among the conductive patterns 113 of the preliminary gate stack structure 110 is isolated into a drain select line 113D. The drain select lines 113D may overlap with the source select lines 143S, respectively. Thus, a gate stack structure 110G may be defined.

[0157] The drain side slit 181 may extend to penetrate Figure 10F At least one conductive pattern among the conductive patterns 113 of the preliminary gate stack structure 110 is shown.

[0158] The conductive pattern stacked between the drain select line 113D and the source select line 143S to be spaced apart from each other is not penetrated by the drain side slit 181, but may remain as the word line 113W. The drain select line 113D may include a first drain select line surrounding the first vertical channel 130A and a second drain select line surrounding the second vertical channel 130B.

[0159] 12A to 12C Is shown in the implementation of the reference Figure 11 A cross-sectional view of an embodiment of a process continuing after the described process. 12A to 12C Each of them is a cross-sectional view taken along an axis parallel to one of the source selection lines 143S.

[0160] Reference Figure 12A , a first upper insulating layer 183 may be formed. The first upper insulating layer 183 may cover the gate stack structure 110G and the memory layer 123. The first upper insulating layer 183 may extend to overlap the peripheral circuit structure 200, with the first filling insulating layer 115, the second filling insulating layer 151, and the third filling insulating layer 169 interposed between the first upper insulating layer 183 and the peripheral circuit structure 200.

[0161] Subsequently, vertical contact plugs 185A and 185B may be formed. The vertical contact plugs 185A and 185B may penetrate the first upper insulating layer 183, the first filling insulating layer 115, and the second filling insulating layer 151. The vertical contact plugs 185A and 185B may include a first vertical contact plug 185A and a second vertical contact plug 185B.

[0162] First vertical contact plug 185A may extend toward common source layer 167L. First vertical contact plug 185A may extend to penetrate second insulating layer 153 disposed between common source layer 167L and second filling insulating layer 151. First vertical contact plug 185A may contact common source layer 167L. Second vertical contact plug 185B may extend toward pad pattern 225B connected to source control circuit 205. Second vertical contact plug 185B may extend to penetrate third filling insulating layer 169, first bonding insulating layer 171, and second bonding insulating layer 233 disposed between pad pattern 225B and second filling insulating layer 151. Second vertical contact plug 185B may contact pad pattern 225B.

[0163] Reference Figure 12B, a second upper insulating layer 187 may be formed on the first upper insulating layer 183. The second upper insulating layer 187 may extend to cover the first vertical contact plug 185A and the second vertical contact plug 185B.

[0164] Subsequently, contact holes 189A and 189B may be formed. The contact holes 189A and 189B may penetrate the second upper insulating layer 187. The contact holes 189A and 189B may include a first contact hole 189A and a second contact hole 189B.

[0165] The first contact holes 189A may extend toward the vertical channels 130, respectively. Each of the first contact holes 189A may extend to penetrate the first upper insulating layer 183 and the memory layer 123 disposed between the vertical channel layer 131 and the second upper insulating layer 187. The vertical channel layer 131 may be exposed through the first contact holes 189A.

[0166] The second contact hole 189B may be formed to expose the first vertical contact plug 185A and the second vertical contact plug 185B.

[0167] Reference Figure 12C , can be filled with conductive materials Figure 12A Each of the first contact hole 189A and the second contact hole 189B is shown. Thus, a contact plug 191A and a via plug 191B may be formed.

[0168] Each contact plug 191A may be provided at Figure 12A The first contact hole 189A is shown and can contact the channel layer 131 of the vertical channel 130. The via plug 191B can be provided Figure 12A The second contact holes 189B are shown and may contact the first vertical contact plug 185A and the second vertical contact plug 185B, respectively.

[0169] Subsequently, subsequent processes of forming bit lines and upper conductive patterns may continue.

[0170] Figure 13 is a block diagram illustrating a configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0171] Reference Figure 13 , the memory system 1100 includes a memory device 1120 and a memory controller 1110 .

[0172] The memory device 1120 may include a source channel penetrating a source select line, a gate stack structure overlapping the source select line, a connection pattern disposed between the source select line and the gate stack structure, and a vertical channel connected to the source channel through the connection pattern and penetrating the gate stack structure.

[0173] The memory device 1120 may be a multi-chip package configured using a plurality of flash memory chips.

[0174] The memory controller 1110 may control the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as an operating memory for the CPU 1112, which performs overall control operations for data exchange with the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors included in data read from the memory device 1120. The memory interface 1115 interfaces with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM) for storing code data, etc., used for interfacing with the host.

[0175] Figure 14 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0176] Reference Figure 14 , the computing system 1200 may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0177] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include a source channel penetrating a source select line, a gate stack structure overlapping the source select line, a connection pattern disposed between the source select line and the gate stack structure, and a vertical channel connected to the source channel through the connection pattern and penetrating the gate stack structure.

[0178] According to the present disclosure, the vertical channel penetrating the gate stack structure and the source channel penetrating the source selection line can be connected to each other through a connection pattern provided between the gate stack structure and the source selection line. Therefore, the process load for ensuring the alignment margin between the vertical channel and the source channel can be reduced.

[0179] According to the present disclosure, the source channel can be aligned on the connection pattern extending parallel to the gate stack structure. Therefore, the stability of the process of aligning the source channel on the connection pattern can be improved, and the degree of freedom of arrangement of the source channel can be improved.

[0180] According to the present disclosure, for each source select line isolated from each other by a source-side slit, memory cell strings can be divided into groups that can be individually selected simultaneously. Therefore, read disturbance can be reduced, thereby improving the operational reliability of the semiconductor memory device.

[0181] CROSS-REFERENCE TO RELATED APPLICATIONS

[0182] This application claims the benefit of Korean Patent Application No. 10-2020-0110556, filed on August 31, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a plurality of source channels, wherein the plurality of source channels penetrate the source selection line; a gate stack structure, the gate stack structure overlapping the source selection line; a connection pattern, the connection pattern being disposed between the source selection line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; as well as a plurality of vertical channels, the plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern, wherein the connection pattern continuously extends through the plurality of source channels and the plurality of vertical channels, and The connection pattern protrudes into a central region of each of the plurality of vertical channels.

2. The semiconductor memory device according to claim 1, wherein A cross-sectional area of ​​each of the source channels is wider than a cross-sectional area of ​​each of the vertical channels.

3. The semiconductor memory device according to claim 1, wherein There is at least one case where one source channel among the plurality of source channels overlaps with two or more vertical channels among the plurality of vertical channels.

4. The semiconductor memory device according to claim 1, wherein At least one vertical channel among the plurality of vertical channels does not overlap with the plurality of source channels.

5. The semiconductor memory device according to claim 1, wherein The number of the source channels connected to the connection pattern is smaller than the number of the vertical channels connected to the connection pattern.

6. The semiconductor memory device according to claim 1, further comprising: a common source layer commonly connected to the plurality of source channels, the common source layer overlapping the connection pattern, the plurality of source channels being interposed between the common source layer and the connection pattern; as well as A plurality of bit lines are respectively connected to the vertical channels, the bit lines overlap the connection patterns, and the plurality of vertical channels are interposed between the bit lines and the connection patterns.

7. The semiconductor memory device according to claim 1, wherein The gate stack structure includes a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked in a direction in which the plurality of vertical channels extend, and Wherein, the conductive pattern includes: a drain select line, the drain select line overlapping the source select line; and A word line is provided between the drain select line and the source select line.

8. The semiconductor memory device according to claim 1, further comprising: a common source layer, the common source layer being commonly connected to the plurality of source channels; a substrate overlapping the gate stack structure, the common source layer being interposed between the substrate and the gate stack structure, the substrate including a transistor; and A bonding structure is provided between the substrate and the common source layer.

9. The semiconductor memory device according to claim 1, wherein The connection pattern extends parallel to the source selection line.

10. The semiconductor memory device according to claim 1, further comprising a common source layer commonly connected to the plurality of source channels, in, The common source layer includes a contact region protruding further than the source select line in a direction crossing the plurality of vertical channels.

11. The semiconductor memory device according to claim 10, further comprising: a first vertical contact plug, the first vertical contact plug being in contact with the contact region of the common source layer, the first vertical contact plug extending in a direction in which the plurality of vertical channels extend; a source control circuit, the source control circuit overlapping the gate stack structure, the common source layer interposed between the source control circuit and the gate stack structure, the source control circuit comprising a transistor; an interconnect structure connected to the source control circuit; a second vertical contact plug connected to the interconnect structure, the second vertical contact plug extending parallel to the first vertical contact plug; as well as An upper conductive pattern connects the first vertical contact plug and the second vertical contact plug.

12. The semiconductor memory device according to claim 1, further comprising: a gate insulating layer, the gate insulating layer being disposed between each of the source channels and the source selection line; as well as A memory layer is provided between each of the vertical channels and the gate stack structure.

13. The semiconductor memory device according to claim 1 , further comprising a common source layer commonly connected to the plurality of source channels, in, Each of the source channels includes: a semiconductor layer including a contact pattern connected to the connection pattern and a pillar portion extending from an edge of the contact pattern toward the common source layer; and A source core insulating layer is surrounded by a pillar portion of the semiconductor layer between the contact pattern of the semiconductor layer and the common source layer.

14. The semiconductor memory device according to claim 13, wherein The pillar portion of each of the source channels includes an undoped region defined at a height between the contact pattern and the common source layer.

15. The semiconductor memory device according to claim 13, wherein The common source layer includes a doped semiconductor layer, and Wherein, the doped semiconductor layer of the common source layer includes: a line portion extending parallel to the source select line; and A protrusion is surrounded by the pillar portion of the semiconductor layer between the line portion and the source core insulating layer.

16. The semiconductor memory device according to claim 1, wherein Each of the vertical channels comprises: a vertical core insulating layer having a first surface facing the connection pattern and a second surface facing a direction opposite to the first surface, the vertical core insulating layer penetrating the gate stack structure; and A semiconductor layer extends along the second surface of the vertical core insulating layer, and the semiconductor layer extends between the gate stack structure and the vertical core insulating layer.

17. The semiconductor memory device according to claim 16, wherein The connection pattern includes a doped semiconductor layer, and Wherein, the doped semiconductor layer comprises: a line portion extending parallel to the source select line; and A protrusion extends from the line portion toward the vertical core insulating layer, the protrusion being surrounded by the semiconductor layer.

18. A semiconductor memory device, comprising: a first source channel and a second source channel, the first source channel and the second source channel extending parallel to each other; a first source selection line surrounding the first source channel; a second source selection line surrounding the second source channel; a gate stack structure, the gate stack structure overlapping the first source select line, the gate stack structure extending to overlap the second source select line; a first vertical channel penetrating a first region of the gate stack structure overlapping the first source selection line; a second vertical channel penetrating a second region of the gate stack structure overlapping the second source selection line; a first connection pattern connecting the first source channel and the first vertical channel between the first source select line and the gate stack structure, wherein the first connection pattern continuously extends through the first source channel and the first vertical channel, and wherein the first connection pattern protrudes into a central region of the first vertical channel; a second connection pattern connecting the second source channel and the second vertical channel between the second source select line and the gate stack structure, wherein the second connection pattern continuously extends through the second source channel and the second vertical channel, and wherein the second connection pattern protrudes into a central region of the second vertical channel; and A source-side slit is provided between the first source selection line and the second source selection line, and extends between the first connection pattern and the second connection pattern.

19. The semiconductor memory device according to claim 18 further comprises a common source layer overlapping with the gate stack structure, and the first source selection line and the second source selection line are inserted between the common source layer and the gate stack structure, and the common source layer is connected to the first source channel and the second source channel.

20. The semiconductor memory device according to claim 18, further comprising a bit line overlapping the first connection pattern and the second connection pattern, the gate stack structure being interposed between the bit line and the first connection pattern and the second connection pattern, the bit line being connected to the first vertical channel and the second vertical channel.

21. The semiconductor memory device according to claim 18, wherein The gate stack structure includes a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked in a direction in which the first vertical channel and the second vertical channel extend, and Wherein, the conductive pattern includes: a first drain selection line, the first drain selection line overlapping the first connection pattern and surrounding the first vertical channel; a second drain selection line overlapping the second connection pattern, the second drain selection line surrounding the second vertical channel; and A word line surrounds the first vertical channel between the first drain select line and the first connection pattern, and extends between the second drain select line and the second connection pattern to surround the second vertical channel.

22. The semiconductor memory device according to claim 21, further comprising a wavy slit extending between the first drain select line and the second drain select line in a direction crossing the first vertical channel and the second vertical channel, the wavy slit overlapping the word line.

23. The semiconductor memory device according to claim 21, further comprising: a drain-side slit extending between the first drain selection line and the second drain selection line in a direction crossing the first vertical channel and the second vertical channel; as well as A dummy channel is provided, the dummy channel overlaps the drain-side slit, and the dummy channel penetrates the word line.

24. A semiconductor memory device, comprising: a plurality of source channels, wherein the plurality of source channels penetrate the source selection line; a gate stack structure, the gate stack structure overlapping the source selection line; a plurality of vertical channels, wherein the plurality of vertical channels penetrate the gate stack structure; as well as a connection pattern disposed between the source selection line and the gate stack structure to connect the plurality of vertical channels to the plurality of source channels, wherein a thickness of each of the plurality of vertical channels is different from a thickness of each of the plurality of source channels, wherein the connection pattern continuously extends through the plurality of source channels and the plurality of vertical channels, and The connection pattern protrudes into a central region of each of the plurality of vertical channels.

25. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a preliminary gate stack structure having a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked on a first region of a sacrificial substrate, wherein the preliminary gate stack structure is penetrated by a memory layer and a plurality of vertical channels; forming a conductive layer connected to the plurality of vertical channels on the preliminary gate stack structure; forming a first insulating layer and a selection gate layer on the conductive layer; and A source-side slit is formed penetrating the first insulating layer, the selection gate layer, and the conductive layer, so that the selection gate layer is isolated into a plurality of source selection lines and the conductive layer is isolated into a plurality of connection patterns.

26. The method according to claim 25, further comprising the steps of: A plurality of source channels respectively penetrating the source selection lines are formed, and the plurality of source channels are respectively connected to the connection patterns.

27. The method according to claim 26, wherein The step of forming the source channel comprises the following steps: forming a second insulating layer covering the source selection line; forming a plurality of source channel holes penetrating the second insulating layer, wherein the plurality of source channel holes respectively expose the connection patterns; forming an undoped semiconductor layer along the surface of each of the source channels; and A source core insulating layer is formed in a central region of each of the source channel holes opened through the undoped semiconductor layer.

28. The method according to claim 27, further comprising the steps of: Before forming the undoped semiconductor layer, a gate insulating layer is formed on the sidewalls of each of the source selection lines exposed by the source channel holes.

29. The method according to claim 27, further comprising the steps of: etching a portion of the source core insulating layer to define a recessed area; as well as A common source layer is formed to fill the recessed area, and the common source layer is connected to the source channel.

30. The method according to claim 29, wherein The step of forming the common source layer includes the following steps: forming a doped semiconductor layer filling the recessed area, wherein the doped semiconductor layer covers the second insulating layer.

31. The method according to claim 26, further comprising the steps of: Before forming the first insulating layer and the selection gate layer, forming a filling insulating layer on the second area of ​​the sacrificial substrate; as well as After forming the source channel, forming a common source layer connected to the source channel, wherein each of the source selection lines extends to overlap with the filling insulating layer, and The common source layer protrudes further than the source selection line in a direction intersecting the vertical channel.

32. The method according to claim 31 , further comprising the steps of: forming a first bonding insulating layer on the common source layer; forming a peripheral circuit structure having a transistor, an interconnection structure connected to the transistor, and a second bonding insulating layer overlapping the transistor and the interconnection structure; bonding the second bonding insulating layer to the first bonding insulating layer; removing the sacrificial substrate; forming an upper insulating layer overlapping the peripheral circuit structure, the filling insulating layer being interposed between the upper insulating layer and the peripheral circuit structure; as well as A plurality of vertical contact plugs are formed penetrating the upper insulating layer and the filling insulating layer, wherein the plurality of vertical contact plugs are in contact with the common source layer and the interconnection structure, respectively.

33. The method according to claim 26, further comprising the steps of: forming a common source layer connected to the source channel; forming a first bonding insulating layer on the common source layer; forming a substrate having a transistor and a peripheral circuit structure including a second bonding insulating layer overlapping the transistor; bonding the second bonding insulating layer to the first bonding insulating layer; removing the sacrificial substrate; forming a drain-side slit penetrating at least one conductive pattern among the plurality of conductive patterns so that the at least one conductive pattern is isolated into a plurality of drain selection lines respectively overlapping the source selection lines; forming an upper insulating layer covering the drain selection line; as well as A plurality of contact plugs are formed penetrating the upper insulating layer and the memory layer, the plurality of contact plugs being in contact with the vertical channels, respectively.

34. The method of claim 25, wherein: The memory layer extends along a surface of a vertical channel hole penetrating the gate stack structure, the vertical channel hole extending into the first region of the sacrificial substrate, and Each of the vertical channels includes a vertical channel layer extending along a surface of the memory layer and a vertical core insulating layer disposed in a central region of the vertical channel hole opened by the vertical channel layer.

35. The method according to claim 34, wherein The step of forming the conductive layer comprises the following steps: etching a portion of the vertical core insulating layer to define a recessed area; and A doped semiconductor layer is formed on the preliminary gate stack structure to fill the recessed area.

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