Semiconductor structure and its fabrication method, three-dimensional memory

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a three-dimensional memory, relating to the field of semiconductor chip technology, to reduce RC delay and power consumption. The semiconductor structure includes a substrate, a memory stack layer disposed on the substrate, and the memory stack layer including alternating layers of first gate conductive layers and multiple dielectric layers. Each of the multiple first gate conductive layers sequentially includes at least one word line layer and at least one top select gate. A first channel via penetrates the at least one top select gate, a second gate conductive layer is disposed within the first channel via, and a first channel structure is disposed within the first channel via. The first channel structure includes a second gate conductive layer covering the sidewalls of the first channel via, a gate dielectric layer covering the second gate conductive layer, and a first channel layer covering the gate dielectric layer. The second gate conductive layer is connected to the top select gate. This semiconductor structure is applied in a three-dimensional memory to realize data read and write operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, and a three-dimensional memory. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of process technology, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate.

[0003] In 3D NAND, memory cells are arranged three-dimensionally on the substrate. The gate is divided into three parts: the bottom select gate, the middle control gate, and the top select gate (TSG). This distributes the gate signal among the three sets of gates to reduce crosstalk between signals.

[0004] However, the current TSG material is doped polycrystalline silicon, which has high resistivity and will generate RC (resistance-capacitance) delay, increasing power consumption. Summary of the Invention

[0005] Embodiments of this disclosure provide a semiconductor structure and its fabrication method, as well as a three-dimensional memory, to reduce RC delay and power consumption.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On one hand, a semiconductor structure is provided. The semiconductor structure includes a substrate, a memory stack layer, and a first channel structure. The memory stack layer is disposed on the substrate and includes alternating layers of first gate conductive layers and layers of dielectric layers. Along the thickness direction of the substrate and away from the substrate, the multiple layers of first gate conductive layers sequentially include at least one word line layer and at least one top select gate. The memory stack layer has a first channel via penetrating the at least one top select gate. The first channel structure is disposed within the first channel via and includes a second gate conductive layer, a gate dielectric layer, and a first channel layer. The second gate conductive layer covers the sidewall of the first channel via and is connected to the at least one top select gate. The gate dielectric layer is disposed on the side of the second gate conductive layer opposite to the sidewall of the first channel via, and the first channel layer is disposed on the side of the gate dielectric layer opposite to the second gate conductive layer.

[0008] The semiconductor structure provided in the above embodiments of this disclosure includes a second gate conductive layer within a first channel via, which covers the sidewalls of the first channel via and is electrically connected to a top-select gate. In this case, the first channel structure consists of a second gate conductive layer, a gate dielectric layer, and a first channel layer. That is, since the top-select transistor does not require storage functionality, it can be constructed as a simple transistor, thereby avoiding the process of depositing a barrier layer, a storage layer, and a tunneling layer stacked within the first channel via, thus reducing costs. Furthermore, the first and second gate conductive layers can be made of different materials. For example, the first gate conductive layer can be made of a material with low resistance to reduce RC delay and power consumption; the gate conductive layer can be made of a material with a high work function to meet the preset threshold voltage of the top-select transistor.

[0009] In some embodiments, the material of the first gate conductive layer includes a metal, and the work function of the material of the second gate conductive layer is greater than 4.6 eV.

[0010] In some embodiments, the memory stack layer further has a second channel via penetrating the at least one word line layer and the at least one bottom select gate, the second channel via communicating with the first channel via. The semiconductor structure further includes a second channel structure disposed within the second channel via, the second channel structure comprising a memory functional layer and a second channel layer disposed sequentially, one end of the second channel layer being electrically connected to the first channel layer, and the other end being electrically connected to the substrate; both the memory functional layer and the second channel layer are electrically insulated from the second gate conductive layer.

[0011] In some embodiments, the orthographic projection of the second channel layer on the substrate is separate from the orthographic projection of the second gate conductive layer on the substrate.

[0012] In some embodiments, the second channel structure further includes an insulating pad disposed on the side of the storage functional layer away from the substrate, wherein the orthographic projection of the storage functional layer on the substrate and the orthographic projection of the second gate conductive layer on the substrate are both located within the orthographic projection of the insulating pad on the substrate.

[0013] In some embodiments, the second channel structure further includes a second channel filling layer and a second connection pad. The second channel filling layer is disposed in a gap inside the second channel layer. The second connection pad is disposed on the side of the second channel filling layer away from the substrate, and the second connection pad is electrically connected to the second channel layer.

[0014] In some embodiments, along the thickness direction of the substrate, the height of the second channel fill layer is less than the height of the second channel layer to form a second groove, the second groove exposing a portion of the sidewalls of the second channel layer. A second connector pad is disposed within the second groove and is in electrical contact with the exposed sidewalls of the second channel layer, the orthographic projection of the first channel layer onto the substrate overlapping the orthographic projection of the second connector pad onto the substrate.

[0015] In some embodiments, the second channel structure further includes a second channel filler layer that fills the gaps inside the second channel layer; the height of the second channel filler layer is less than the height of the second channel layer along the thickness direction of the substrate to form a second groove that exposes a portion of the sidewalls of the second channel layer. The first channel layer extends into the second groove and is in electrical contact with the exposed sidewalls of the second channel layer.

[0016] In some embodiments, the memory stack layer further has a dicing trench extending through the at least one top select gate, the dicing trench extending along a first direction in a plane parallel to the substrate to divide the at least one top select gate into multiple regions; the sidewalls of the dicing trench extending along the first direction are defined by the second gate conductive layer exposed on the side of the dicing trench and by a film layer in the memory stack layer corresponding to the second gate conductive layer exposed on the side of the dicing trench. The semiconductor structure further includes a dicing structure disposed within the dicing trench. The dicing structure contacts the second gate conductive layer exposed on the side of the dicing trench and the film layer in the memory stack layer corresponding to the second gate conductive layer exposed on the side of the dicing trench.

[0017] In some embodiments, the orthographic projection of the first channel structure onto the substrate lies within the orthographic projection of the second channel structure onto the substrate.

[0018] In some embodiments, the first channel structure extends into the dielectric layer between the at least one word line layer and the at least one top select gate.

[0019] In some embodiments, the thickness of the dielectric layer between the at least one word line layer and the at least one top select gate is greater than the thickness of the other dielectric layers in the memory stack.

[0020] In some embodiments, the first channel structure further includes a first channel filler layer and a first connection pad. The first channel filler layer is disposed in a gap inside the first channel layer. The first connection pad is disposed on the side of the first channel filler layer away from the substrate, and the first connection pad is electrically connected to the first channel layer.

[0021] In some embodiments, along the thickness direction of the substrate, the height of the first channel fill layer is less than the height of the first channel layer to form a first groove, the first groove exposing a portion of the sidewall of the first channel layer. The first connection pad is disposed within the first groove and is in electrical contact with the exposed sidewall of the first channel layer.

[0022] On the other hand, a method for fabricating a semiconductor structure is provided. The method includes: fabricating an intermediate semiconductor structure; the intermediate semiconductor structure includes: a substrate; an intermediate stacked layer disposed on the substrate; the intermediate stacked layer includes alternating layers of sacrificial layers and layers of dielectric layers, along the thickness direction of the substrate and away from the substrate, the layers of sacrificial layers sequentially including at least one word line sacrificial layer and at least one top select gate sacrificial layer; the intermediate stacked layer has a first channel via penetrating the at least one top select gate sacrificial layer. A first channel structure is formed within the first channel via; the first channel structure includes a second gate conductive layer, a gate dielectric layer, and a first channel layer, the second gate conductive layer covering the sidewall of the first channel via; the gate dielectric layer is disposed on the side of the second gate conductive layer opposite to the sidewall of the first channel via, and the first channel layer is disposed on the side of the gate dielectric layer opposite to the second gate conductive layer.

[0023] In some embodiments, the fabrication method further includes: replacing the sacrificial layer with a gate material to form a first gate conductive layer; wherein the first gate conductive layer replacing the top select gate sacrificial layer is a top select gate, and the second gate conductive layer is connected to the top select gate.

[0024] In some embodiments, the fabrication of the intermediate semiconductor structure includes: forming a second sub-intermediate stack layer on the substrate; the second sub-intermediate stack layer includes alternating sacrificial layers and multiple dielectric layers, the multiple sacrificial layers including at least one word line sacrificial layer. A first sub-intermediate stack layer is formed on the side of the second sub-intermediate stack layer away from the substrate, the first sub-intermediate stack layer including at least one alternating top select gate sacrificial layer and at least one dielectric layer. A first channel via is formed through the at least one top select gate sacrificial layer.

[0025] In some embodiments, the fabrication of the intermediate semiconductor structure between forming the second sub-intermediate stack layer and forming the first sub-intermediate stack layer further includes: forming a second channel via penetrating the second sub-intermediate stack layer, the second channel via communicating with the first channel via. A second channel structure is formed within the second channel via; the second channel structure includes a storage functional layer and a second channel layer disposed sequentially, the second channel layer being electrically connected to the first channel layer, and both the storage functional layer and the second channel layer being electrically insulated from the second gate conductive layer.

[0026] In some embodiments, during the process of forming the second channel structure in the second channel hole, an insulating pad is also formed. The insulating pad is disposed on the side of the storage functional layer away from the substrate. The orthographic projection of the storage functional layer on the substrate and the orthographic projection of the second gate conductive layer on the substrate are both located within the orthographic projection of the insulating pad on the substrate.

[0027] In some embodiments, during the formation of the second channel structure within the second channel hole, a second channel filling layer is also formed, which fills the gaps on the inner side of the second channel layer. The fabrication method further includes: etching the second channel filling layer to form a second groove; the second groove exposes a portion of the sidewalls of the second channel layer. A second connection pad is formed within the second groove; the second connection pad is in electrical contact with the exposed sidewalls of the second channel layer, and the orthographic projection of the first channel layer onto the substrate overlaps with the orthographic projection of the second connection pad onto the substrate.

[0028] In some embodiments, after replacing the sacrificial layer with gate material, the method further includes: forming a photoresist layer covering the memory stack layer; using the photoresist layer and the second gate conductive layer as a mask, etching the memory stack layer to form dicing trenches; the dicing trenches extend along a first direction to divide the top select gate into multiple regions; filling the dicing trenches with dicing structures; the dicing structures contacting the second gate conductive layer; and removing the photoresist layer.

[0029] In some embodiments, the sidewalls of the cutting trench extending along the first direction are defined by the second gate conductive layer exposed to the side of the cutting trench, and by a film layer in the storage stack layer corresponding to the second gate conductive layer exposed to the side of the cutting trench.

[0030] In some embodiments, during the process of forming the first channel structure within the first channel hole, a first channel filling layer is also formed; the first channel filling layer fills the gaps on the inner side of the first channel layer. The fabrication method further includes: etching the first channel filling layer to form a first groove; the first groove exposes a portion of the sidewall of the first channel layer; forming a first connecting pad within the first groove; the first connecting pad making electrical contact with the exposed sidewall of the first channel layer.

[0031] Furthermore, a three-dimensional memory is provided. It includes a semiconductor structure, which is the semiconductor structure described in any of the above embodiments or prepared by the method described in any of the above embodiments.

[0032] It is understood that the beneficial effects of the semiconductor structure preparation method and three-dimensional memory provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0034] Figure 1 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0035] Figure 2 for Figure 1 A cross-sectional view of a string of storage cells in a three-dimensional memory along section line AA;

[0036] Figure 3 for Figure 1 The equivalent circuit diagram of a string of storage cells in a three-dimensional memory is shown.

[0037] Figure 4 This is a cross-sectional view of a semiconductor structure according to some embodiments;

[0038] Figure 5 This is a top view of a semiconductor structure according to some embodiments;

[0039] Figure 6 This is a diagram illustrating the fabrication steps of a semiconductor structure fabrication method according to some embodiments;

[0040] Figure 7 This is a diagram illustrating the fabrication steps of a semiconductor structure fabrication method according to some embodiments;

[0041] Figure 8 This is a diagram illustrating the fabrication steps of a semiconductor structure fabrication method according to some embodiments;

[0042] Figure 9 This is a diagram illustrating the fabrication steps of a semiconductor structure fabrication method according to some embodiments;

[0043] Figure 10 This is a diagram illustrating the fabrication steps of a semiconductor structure fabrication method according to some embodiments;

[0044] Figure 11 for Figure 5The cross-sectional view of the semiconductor structure shown is along section line AA'.

[0045] Figure 12 for Figure 5 The cross-sectional view of the semiconductor structure shown is along the section line BB'.

[0046] Figure 13 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0047] Figure 14 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0048] Figure 15 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0049] Figure 16 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0050] Figure 17 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Detailed Implementation

[0051] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0052] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0053] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0055] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0056] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0057] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0058] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0059] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0060] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0061] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0062] As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined when the substrate is in a third-party Z-direction (refer to...). Figure 1 When the device is located in the lowest plane of the semiconductor device (i.e., in the thickness direction), it is determined relative to the substrate of the semiconductor device in the third direction Z. The same concept is used throughout this disclosure to describe spatial relationships.

[0063] Please see Figures 1-4 , Figure 1 This is a schematic diagram of the three-dimensional structure of the three-dimensional memory 100 provided in some embodiments of this disclosure. Figure 2 for Figure 1 A cross-sectional view of a string of storage cells in a three-dimensional memory 100 along section line AA'. Figure 3 for Figure 1 The equivalent circuit diagram of a string of storage cells in a three-dimensional memory 100. Figure 4 Cross-sectional views of semiconductor structures provided for some embodiments of this disclosure.

[0064] like Figure 1 and Figure 4 As shown, the three-dimensional memory 100 includes a substrate 10 and a memory stack layer 20 formed on the substrate 10. The memory stack layer 20 has a stepped morphology and includes multiple alternating layers of first gate conductive layers 21 and multiple layers of dielectric layers 22. Figure 1 (Not shown in the diagram). Along the third direction Z (perpendicular to the substrate 10), at least one of the lowermost first gate conductive layers 21 in the multilayer first gate conductive layers 21 is configured as a bottom select gate SGS. Figure 1 In the diagram, a first gate conductive layer 21 is configured as a bottom selection gate (SGS); in the multi-layer first gate conductive layer 21, at least the uppermost first gate conductive layer 21 is configured as a top selection gate (SGD). Figure 1 In the diagram, a first gate conductive layer 21 is constructed as the top selection gate SGD; at least one first gate conductive layer 21 located in the middle layer of the multi-layer first gate conductive layers 21 is constructed as the word line layer WL (i.e., the middle layer control gate). Figure 1 The first gate conductive layer 21 of the four layers is constructed as a word line layer WL for illustration.

[0065] like Figure 1 and Figure 2 As shown, the three-dimensional memory 100 also includes an array of channel structures 30 that extend along the third direction Z through the top select gate (SGD), word line layer (WL), and bottom select gate (SGS). The channel structures 30 connect the top select gates (SGD), word line layers (WL), and bottom select gates (SGS) in series to form a memory cell string 40.

[0066] See Figure 3 The first end of the memory cell string 40 is connected to the bit line BL, and the second end is connected to the source line SL. That is, the memory cell string 40 includes a plurality of transistors connected in series between the first end and the second end, and the plurality of transistors include at least one top select transistor Q1, at least one storage transistor M, and at least one bottom select transistor Q2.

[0067] Combination Figure 1 The gate of the top select transistor Q1 (top select gate SGD) is connected to the serial select line SSL, and the gate of the bottom select transistor Q2 (bottom select gate SGD) is connected to the ground select line GSL. The gate of the storage transistor M (word line layer WL) is connected to the corresponding word line (one of word lines WL1 to WL4).

[0068] In some embodiments, the top selection gate SGD is divided into different gate lines by gate line slots. The gate lines of the top selection gate SGDs corresponding to multiple channel structures 30 in the same row are connected to the same serial selection line SSL (one of serial selection lines SSL1 to SSL4).

[0069] In some embodiments, the word line layer WL is divided into different gate lines by gate line gaps. The gate lines of the word line layer WL on the same layer are electrically connected to the corresponding interconnect layer 102 via their respective first conductive channels 101, and then electrically connected to the corresponding word line (one of the word lines WL1 to WL4) via the second conductive channel 103.

[0070] In some embodiments, the bottom select gate (SGD) is divided into different gate lines by gate line slots. The gate lines of the bottom select gate (SGD) are electrically connected to the corresponding interconnect layer (102) via their respective first conductive channels (101), and then connected to the same ground select line (GSL) via second conductive channels (103).

[0071] During a write operation, the memory cell string 40 uses Fowler-Nordheim (FN) tunneling efficiency to write data to a selected memory transistor in the memory transistor M.

[0072] For example, the selected storage transistor is Figure 3 The second storage transistor M2 in the middle, see Figures 1-3 With the source line SL grounded, the ground select line GSL is biased to approximately zero volts, causing the bottom select transistor Q2 corresponding to the ground select line GSL to turn off; the string select line SSL is biased to a high voltage VDD, causing the top select transistor Q1 corresponding to the string select line SSL to turn on. Then, the bit line BL2 is grounded, and the word line WL2 is biased to the programming voltage VPG, for example, around 20V. The remaining word lines (word lines WL1, WL3, and WL4) are biased to a low voltage VPS1. Since only the word line WL2 of the second storage transistor M2 has a voltage higher than the tunneling voltage, data is converted into charge and stored in the storage transistor M2.

[0073] During the read operation, the storage cell string 40 determines the amount of stored charge based on the conduction state of the selected storage transistor in the storage transistor M, thereby obtaining the data represented by the amount of charge.

[0074] For example, the selected storage transistor is Figure 3 The second storage transistor M2 in the middle, see Figures 1-3Word line WL2 is biased at the read voltage VRD, while the remaining word lines (word lines WL1, WL3, and WL4) are biased at the high voltage VPS2. The conduction state of storage transistor M2 is related to its threshold voltage, i.e., to the amount of charge stored, thus the data value can be determined based on the conduction state of storage transistor M2. Specifically, the first storage transistor M1, the third storage transistor M3, and the fourth storage transistor M4 are always in the on-state; therefore, the conduction state of the memory cell string 40 depends on the conduction state of the second storage transistor M2. At this time, the control circuit determines the conduction state of the second storage transistor M2 based on the electrical signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the second storage transistor M2.

[0075] In some related technologies, the material of the first gate conductive layer on the substrate is tungsten, and the channel structure through the top select gate, word line layer and bottom select gate is consistent, including a barrier layer, a storage layer, a tunneling layer and a channel layer.

[0076] In other related technologies, the top select gate is made of doped polysilicon, so the channel structure through the top select gate can consist of only the gate dielectric layer and the channel layer, thus constructing a simple metal-oxide-semiconductor (MOS) transistor.

[0077] However, in the first related technology, the channel structure through the top select gate requires a process of depositing a stacked structure of a barrier layer, a storage layer, and a tunneling layer, which is costly; in the second related technology, the top select gate has a high resistivity, which will generate RC delay and increase power consumption.

[0078] Based on this, please see Figure 4 Some embodiments of this disclosure provide a semiconductor structure 200, which includes a substrate 10, a memory stack layer 20, and a first channel structure 31.

[0079] It should be noted that the substrate 10 may be made of at least one of silicon, silicon-germanium, germanium and silicon-on-insulator thin film, and this disclosure is not limited thereto.

[0080] See Figure 1 and Figure 4 The storage stack layer 20 is disposed on the substrate 10, and the storage stack layer 20 includes multiple alternating layers of first gate conductive layers 21 and multiple layers of dielectric layers 22. Figure 1 (Not shown in the diagram). Along the thickness direction of the substrate 10 and away from the substrate 10 (third direction Z), the multilayer first gate conductive layer 21 sequentially includes at least one bottom select gate SGS, at least one word line layer WL and at least one top select gate SGD. Figure 1The example is illustrated by the multilayer first gate conductive layer 21, which sequentially includes a bottom select gate (SGS), four word line layers (WL), and a top select gate (SGD).

[0081] It should be noted that the material of the dielectric layer 22 includes an insulating material. Exemplarily, the material of the dielectric layer 22 includes silicon oxide and / or silicon nitride. For example, the material of the dielectric layer 22 includes silicon dioxide and / or silicon nitride.

[0082] To reduce programming interference and prevent leakage, the multilayer first gate conductive layer 21 typically includes a multilayer top select gate (SGD) to reduce programming interference and lower the risk of leakage, thereby maintaining an effective programming voltage. Figure 4 Taking the multilayer first gate conductive layer 21, which includes 4 top select gates (SGD), as an example.

[0083] Among them, see Figure 4 The storage stack layer 20 has a first channel hole CH1 that runs through all the top select gates SGD (see [link]). Figure 8 It should be noted that the first channel hole CH1 (see...) Figure 8 The shape of the () can be cylindrical. For example, see... Figure 5 First channel hole CH1 (see Figure 8 The shape of the ) can be cylindrical or prismatic, but this disclosure is not limited thereto.

[0084] like Figure 4 As shown, a first channel structure 31 is disposed within a first channel hole CH1. The first channel structure 31 includes a second gate conductive layer 316, a gate dielectric layer 311, and a first channel layer 312. The second gate conductive layer 316 covers the first channel hole CH1 (see [reference]). Figure 8 The sidewall of ) and in the first channel hole CH1 (see Figure 8 The first gate conductive layer 21 and the second gate conductive layer 316 are connected to the top select gate (SGD). In this case, the first gate conductive layer 21 and the second gate conductive layer 316 can be made of different materials. The gate dielectric layer 311 is disposed on the second gate conductive layer 316 away from the first channel via CH1 (see...). Figure 8 On one side of the sidewall of the gate dielectric layer 311, the first channel layer 312 is disposed on the side of the gate dielectric layer 311 away from the second gate conductive layer 316 to form the top select transistor Q1.

[0085] In this way, the first channel structure 31 is composed of a second gate conductive layer 316, a gate dielectric layer 311, and a first channel layer 312. That is to say, since the top-select transistor Q1 does not require storage function, the top-select transistor Q1 can be constructed as a simple MOS transistor, resulting in lower manufacturing costs.

[0086] It should be noted that the material of the gate dielectric layer 311 includes silicon oxide, but this disclosure is not limited thereto. The material of the first channel layer 312 includes a semiconductor material. Exemplarily, the material of the first channel layer 312 includes polycrystalline silicon and / or monocrystalline silicon.

[0087] As described above, the semiconductor structure 200 provided in the above embodiments of this disclosure has a second gate conductive layer 316 disposed within the first channel hole CH1, and the second gate conductive layer 316 covers the sidewall of the first channel hole CH1 and is electrically connected to the top select gate SGD. In this case, the first channel structure 31 is composed of the second gate conductive layer 316, the gate dielectric layer 311, and the first channel layer 312. That is, since the top select transistor Q1 does not require storage function, the top select transistor Q1 can be constructed as a simple MOS transistor, thereby avoiding the process of depositing a barrier layer, storage layer, and tunneling layer stacked structure within the first channel hole CH1, reducing costs. In addition, the first gate conductive layer 21 and the second gate conductive layer 316 can be made of different materials. For example, the first gate conductive layer 21 can be made of a material with low resistance to reduce RC delay and power consumption; the gate conductive layer 316 can be made of a material with a high work function to meet the preset threshold voltage of the top select transistor Q1.

[0088] The material of the first gate conductive layer 21 may include a metal; for example, the material of the first gate conductive layer 21 may include at least one of tungsten, cobalt, copper, and aluminum, but this disclosure is not limited thereto. The material of the second gate conductive layer 316 has a work function greater than 4.6 eV; exemplaryly, the material of the second gate conductive layer 316 may include at least one of a metal, boron-doped polysilicon, gallium-doped polysilicon, and indium-doped polysilicon, but this disclosure is not limited thereto; for example, the material of the second gate conductive layer 316 is boron-doped polysilicon, and the doping concentration of the boron-doped polysilicon is 1 eV. 18 ~5e 21 atoms / cm 3 .

[0089] It should be noted that, see Figure 1 The substrate 10 extends in the XY plane. The first direction X and the second direction Y are, for example, two orthogonal directions in the plane of the substrate 10: the first direction X is the extension direction of the word line (one of the word lines WL1 to WL4), and the second direction Y is the extension direction of the bit line BL. The third direction Z is perpendicular to the substrate 10, that is, perpendicular to the XY plane.

[0090] In some embodiments, such as Figure 4As shown, the first channel structure 31 also includes a first channel filling layer 313 and a first connection pad 314. The first channel filling layer 313 fills the gap inside the first channel layer 312 to reduce structural stress. The first connection pad 314 is disposed on the side of the first channel filling layer 313 away from the substrate 10, and the first connection pad 314 is electrically connected to the first channel layer 312 to facilitate the electrical connection between the first channel layer 312 and the bit line BL in subsequent processes.

[0091] It should be noted that the material of the first channel filling layer 313 includes an insulating material, for example, the material of the first channel filling layer 313 includes silicon dioxide. The material of the first connection pad 314 includes a conductive material, for example, the material of the first connection pad 314 includes a metal and / or doped polysilicon.

[0092] Based on this, such as Figure 4 As shown, along the thickness direction of the substrate 10, the height of the first channel fill layer 313 is less than the height of the first channel layer 312 to form the first groove 315 (see Figure 1). Figure 9 The first groove 315 exposes a portion of the inner wall of the first channel layer 312. The first connecting pad 314 is disposed in the first groove 315 and is in electrical contact with the exposed sidewall of the first channel layer 312, so that the first connecting pad 314 is electrically connected to the first channel layer 312.

[0093] In some embodiments, such as Figure 4 As shown, the memory stack layer 20 also has a second channel via CH2 extending through at least one word line layer WL and at least one bottom select gate SGD (see [reference]). Figure 6 The second channel hole CH2 is connected to the first channel hole CH1. The second channel hole CH2 (see...) Figure 6 The shape of the () can be cylindrical. For example, see... Figure 5 Second channel hole CH2 (see Figure 6 The shape of the ) can be cylindrical or prismatic, and this disclosure is not limited thereto. It should be noted that the first channel hole CH1 (see...) Figure 8 The shape of the second channel hole CH2 (see) Figure 6 They have the same shape.

[0094] like Figure 2 and Figure 4 As shown, the semiconductor structure 200 also includes a second channel structure 32, which is disposed in the second channel hole CH2 (see...). Figure 6Within the first channel layer 312, the second channel structure 32 includes a storage layer 320 and a second channel layer 324 sequentially disposed therein. One end of the second channel layer 324 is electrically connected to the first channel layer 312, and the other end is electrically connected to the substrate 10. Both the storage layer 320 and the second channel layer 324 are electrically insulated from the second gate conductive layer 316. It should be noted that the material of the second channel layer 324 includes semiconductor materials. For example, the material of the second channel layer 324 includes polycrystalline silicon and / or monocrystalline silicon.

[0095] In some embodiments, see Figure 4 and Figure 8 The second channel structure 32 also includes an insulating pad 329, which is disposed on the side of the storage function layer 320 away from the substrate 10. The orthographic projection of the storage function layer 320 on the substrate 10 and the orthographic projection of the second gate conductive layer 316 on the substrate 10 are both located within the orthographic projection of the insulating pad 329 on the substrate 10, so that the storage function layer 320 is electrically insulated from the second gate conductive layer 316.

[0096] It should be noted that the material of the insulating pad 329 includes insulating materials; exemplarily, the material of the insulating pad 329 includes silicon oxide and / or silicon nitride; for example, the material of the insulating pad 329 includes silicon dioxide, but this disclosure is not limited thereto.

[0097] In some embodiments, such as Figure 4 As shown, the storage layer 320 includes a barrier layer 321, a storage layer 322, and a tunneling layer 323 arranged sequentially. The barrier layer 321 covers the sidewall of the second channel via CH2 to prevent charge transfer to the first gate conductive layer 21; the storage layer 322 covers the barrier layer 321 and is used to store charge; the tunneling layer 323 covers the storage layer 322. In this case, during a write operation, when the voltage of the word line (any one of word lines WL1 to WL4) is higher than the tunneling voltage, electrons in the second channel layer 324 reach the storage layer 322 via the tunneling layer 323, thereby converting data into charge and storing it in the storage layer 322 of the corresponding storage transistor M.

[0098] The barrier layer 321 may include a single layer, for example, a SiO2 layer; or it may include multiple layers, for example, a SiO2 and Al2O3 stack. The storage layer 322 may include a single layer, for example, a SiN layer; or it may include multiple layers, for example, a SiN, SiON, and SiN stack. The tunneling layer 323 may include multiple layers, for example, a SiO, SiON, and SiO stack.

[0099] In some embodiments, see Figure 4 , Figure 6 and Figure 8The first channel hole CH1 extends into the dielectric layer 22 between at least one word line layer WL and at least one top select gate SGD, that is, the first channel structure 31 extends into the dielectric layer 22 between at least one word line layer WL and at least one top select gate SGD, so as to reduce the risk of electrical connection between the second gate conductive layer 316 and the second channel layer 324 and the word line layer WL during the fabrication process.

[0100] In some embodiments, see Figure 4 The thickness of the dielectric layer 22 between at least one word line layer WL and at least one top select gate SGD is greater than the thickness of other dielectric layers 22 in the memory stack layer 20 to reduce programming interference. Furthermore, the dielectric layer 22 between at least one word line layer WL and at least one top select gate SGD can consist of two layers: one covering the word line layer WL and fabricated together with the portion of the memory stack layer 20 corresponding to the word line layer WL, and the other covered by the top select gate SGD and fabricated together with the portion of the memory stack layer 20 corresponding to the top select gate SGD, thereby reducing the risk of electrical connection between the second gate conductive layer 316 and the second channel layer 324 during fabrication.

[0101] In some embodiments, see Figure 4 The orthographic projection of the second channel layer 324 on the substrate 10 is separated from the orthographic projection of the second gate conductive layer 316 on the substrate 10, so that the second channel layer 324 and the second gate conductive layer 316 are electrically insulated. For example, the orthographic projection of the second channel layer 324 on the substrate 10 is located within the orthographic projection of the second gate conductive layer 316 on the substrate 10, to avoid the second channel layer 324 and the second gate conductive layer 316 contacting and forming an electrical connection. Furthermore, since the material of the gate dielectric layer 311 is an insulating material, electrical insulation between the second channel layer 324 and the second gate conductive layer 316 can be guaranteed.

[0102] In some embodiments, such as Figure 2 and Figure 4 As shown, the second channel structure 32 also includes a second channel filling layer 325 and a second connecting pad 326. The second channel filling layer 325 fills the gaps inside the second channel layer 324 to reduce structural stress. The second connecting pad 326 is disposed on the side of the second channel filling layer 325 away from the substrate 10, and the second connecting pad 326 is electrically connected to the second channel layer 324. In this case, the first channel layer 312 can be electrically connected to the second channel layer 32 through the second connecting pad 326, which is easy to manufacture; and the second connecting pad 326 can increase the contact area of ​​the first channel layer 312 and the second channel layer 32, improving the reliability of the electrical connection between the first channel layer 312 and the second channel layer 324.

[0103] It should be noted that the material of the second channel filling layer 325 includes an insulating material, for example, the material of the second channel filling layer 325 includes SiO2. The material of the second connection pad 326 includes a conductive material, for example, the material of the second connection pad 326 includes a metal and / or doped polycrystalline silicon.

[0104] Based on this, such as Figure 4 As shown, along the thickness direction of the substrate 10, the height of the second channel fill layer 325 is less than the height of the second channel layer 324 to form the second groove 327 (see Figure 10). Figure 7 The second groove 327 exposes a portion of the inner wall of the second channel layer 324. A second connecting pad 326 is disposed within the second groove 327 and is in electrical contact with the exposed sidewall of the second channel layer 324, thereby electrically connecting the second connecting pad 326 to the second channel layer 324. The orthographic projection of the first channel layer 312 onto the substrate 10 overlaps with the orthographic projection of the second connecting pad 326 onto the substrate 10, meaning that the end of the first channel layer 312 closest to the substrate is in electrical contact with the second connecting pad 326, thereby electrically connecting the first channel layer 312 and the second channel layer 324 through the second connecting pad 326.

[0105] In other embodiments, such as Figure 7 and Figure 8 As shown, the second channel structure 32 further includes a second channel filling layer 325, which fills the gaps inside the second channel layer 324. Along the thickness direction of the substrate 10 ( Figure 1 In the third direction Z), the height of the second channel filling layer 325 is less than the height of the second channel layer 324 to form a second groove 327, which exposes a portion of the inner wall of the second channel layer 324. In this case, the first channel layer 312 extends into the second groove 327 and makes electrical contact with the exposed portion of the sidewall of the second channel layer 324, so that the first channel layer 312 is electrically connected to the second channel layer 324.

[0106] In some embodiments, such as Figure 5 and Figure 11 As shown, the storage stack layer 20 also has cutting grooves 50 for dividing the storage stack layer 20 into multiple storage blocks. Figure 5 (Not shown in the diagram), a dicing trench 50 penetrates the top select gate SGD. The dicing trench 50 extends along a first direction X in a plane parallel to the substrate 10 to divide at least one layer of the top select gate SGD into multiple regions. The dicing trench 50 extends along the first direction X (see...). Figure 1 The extended sidewalls are defined by the second gate conductive layer 316 exposed to the side of the dicing trench 50, and by the film layer in the storage stack layer 20 corresponding to the second gate conductive layer 316 exposed to the side of the dicing trench 50. That is, the portion of the sidewalls of the dicing trench 50 extending along the first direction X that passes through the second gate conductive layer 316 is an arc-shaped surface.

[0107] In this case, the top selection gate SGD is divided into multiple regions, for each memory cell string 40 (see...). Figure 1 It can achieve more precise control, reduce power consumption, and reduce RC delay.

[0108] In the process of forming the dicing trench 50, the second gate conductive layer 316 and the photoresist 60 (see [reference]) can be used. Figure 5 Simultaneously, the photoresist 60 is used as a mask for etching. This means the etching options for the second gate conductive layer 316 and the memory stack layer 20 are relatively large. When using the photoresist 60 as a mask to form the dicing trench 50, the second gate conductive layer 316 will not be etched away, avoiding the problem of the dicing trench 50 shrinking and reducing the process difficulty. For details, please refer to the fabrication method of the semiconductor structure 200 below; it will not be elaborated here.

[0109] In some embodiments, such as Figure 5 , Figure 10 and Figure 11 As shown, the semiconductor structure 200 also includes a dicing structure 51 disposed within the dicing trench 50. The dicing structure 51 and the second gate conductive layer 316 are exposed on the side of the dicing trench 50, and the film layer in the storage stack layer 20 corresponding to the second gate conductive layer 316 is exposed on the side of the dicing trench 50 in contact with it.

[0110] It should be noted that the material of the cutting structure 51 includes insulating material; for example, the material of the cutting structure 51 includes at least one of SiN, SiO, SiON, SiOCN and SiCN.

[0111] like Figure 13 As shown, some embodiments of this disclosure also provide a semiconductor structure 200 (see...). Figure 4 The preparation methods of ) include S1 to S2.

[0112] S1: See Figure 8 and Figure 13 , to prepare intermediate semiconductor structure 210.

[0113] In the above steps, the intermediate semiconductor structure 210 includes a substrate 10, an intermediate stacked layer 201, and a second channel structure 32. The intermediate stacked layer 201 is disposed on the substrate 10 and includes alternating layers of sacrificial layers 24 and dielectric layers 22, located along the thickness direction (third direction Z) of the substrate 10 and away from the substrate 10. The multiple sacrificial layers 24 sequentially include at least one word line sacrificial layer and at least one top select gate sacrificial layer. The intermediate stacked layer 201 has a first channel via CH1 and a second channel via CH2 (see...). Figure 6 The first channel hole CH1 penetrates the top selected gate sacrificial layer.

[0114] It should be noted that the dielectric layer 22 is made of silicon oxide and / or silicon nitride, and the sacrificial layer 24 is made of at least one of silicon, silicon oxide, silicon carbide, and silicon nitride. The materials of the dielectric layer 22 and the sacrificial layer 24 are different.

[0115] S2: See also Figure 8 , Figure 9 and Figure 13 A first channel structure 31 is formed within the first channel hole CH1.

[0116] In the above steps, the first channel structure 31 includes a second gate conductive layer 316, a gate dielectric layer 311, and a first channel layer 312. The second gate conductive layer 316 covers the sidewall of the first channel hole CH1, and the gate dielectric layer 311 is disposed on the second gate conductive layer 316 away from the first channel hole CH1 (see...). Figure 8 On one side of the sidewall of the gate dielectric layer 311, the first channel layer 312 is disposed on the side of the gate dielectric layer 311 away from the second gate conductive layer 316. The first channel layer 312 is electrically connected to the second channel layer 324. The storage function layer 320 and the second channel layer 324 are both electrically insulated from the second gate conductive layer 316.

[0117] The second gate conductive layer 316 can be formed by depositing boron-doped polysilicon in the first channel hole CH1 using a deposition process, and then etching away the boron-doped polysilicon at the bottom of the first channel hole CH1 to form the second gate conductive layer 316 covering the sidewall of the first channel hole CH1.

[0118] Alternatively, a deposition process can be used to first deposit silicon oxide inside the second gate conductive layer 316 within the first channel hole CH1, and then etch away the silicon oxide at the bottom of the first channel hole CH1, thereby forming a gate dielectric layer 311 disposed inside the second gate conductive layer 316. Then, a deposition process can be used to first deposit polysilicon inside the gate dielectric layer 311 within the first channel hole CH1, and then etch away the polysilicon at the bottom of the first channel hole CH1, thereby forming a first channel layer 312 disposed inside the gate dielectric layer 311.

[0119] In some embodiments, after S2, such as Figure 13 As shown, the method for fabricating the semiconductor structure 200 also includes step S3.

[0120] S3: See also Figure 10 , Figure 11 and Figure 13 The sacrificial layer 24 is replaced with a gate material to form the first gate conductive layer 21.

[0121] In the above steps, the first gate conductive layer 21 that replaces the word line sacrificial layer is the word line layer WL, and the first gate conductive layer 21 that replaces the top select gate sacrificial layer is the top select gate SGD; the second gate conductive layer 316 is connected to the top select gate SGD, for example, the second gate conductive layer 316 and the top select gate SGD are electrically connected by contact.

[0122] For example, the sacrificial layer 24 is removed and replaced with a metal layer 211 and a high-dielectric-constant layer 212 covering the metal layer 211. The high-dielectric-constant layer 212 may be made of at least one of alumina, hafnium oxide, tantalum oxide and a material with a high dielectric constant. The metal layer 211 may be made of tungsten and / or cobalt.

[0123] It should be noted that, see Figure 10 The aforementioned sacrificial layer 24 may not be replaced simultaneously. For example, the sacrificial layer 24 included in the second sub-intermediate stack 202 may be replaced first, and then the sacrificial layer 24 included in the first sub-intermediate stack 203 may be replaced.

[0124] In some embodiments, during process S2, a first channel filling layer 313 is also formed. The first channel filling layer 313 fills the gaps inside the first channel layer 312. The first channel filling layer 313 can be formed after the formation of the first channel layer 312 by a deposition process. Based on this, as... Figure 14 As shown, the method for fabricating the semiconductor structure 200 also includes steps S21 to S22.

[0125] S21: See also Figure 9 and Figure 14 The first channel filling layer 313 is etched to form the first groove 315.

[0126] In the above steps, the first groove 315 exposes part of the sidewall of the first channel layer 312.

[0127] S22: See also Figure 9 , Figure 10 and Figure 14 A first connecting pad 314 is formed in the first groove 315.

[0128] In the above steps, the first connection pad 314 is in electrical contact with the exposed sidewall of the first channel layer 312, so as to facilitate the electrical connection between the first channel layer 312 and the bit line BL. For example, doped polysilicon, which is the first connection pad 314, is formed in the first groove 315 by deposition and ion doping processes.

[0129] In some embodiments, such as Figure 15 As shown, S1 includes S11 to S13.

[0130] S11: See also Figure 6 and Figure 15A second sub-intermediate stack layer 202 is formed on the substrate 10.

[0131] In the above steps, the second sub-intermediate stack 202 includes alternating layers of sacrificial layers 24 and layers of dielectric layers 22. The layers of sacrificial layers 24 of the second sub-intermediate stack 202 include at least one word line sacrificial layer. It should be noted that the layers of sacrificial layers 24 of the second sub-intermediate stack 202 may also include at least one bottom select gate sacrificial layer, which is located between the word line sacrificial layer and the substrate 10. In this case, the first gate conductive layer 21 that replaces the bottom select gate sacrificial layer in S3 above is the bottom select gate SGS.

[0132] S12: See also Figure 8 and Figure 15 A first sub-intermediate stack 203 is formed on the side of the second sub-intermediate stack 202 away from the substrate 10.

[0133] In the above steps, the first sub-intermediate stack layer 203 includes at least one top select gate sacrificial layer and at least one dielectric layer 22 that are alternately arranged.

[0134] It should be noted that the dielectric layer 22 of the first sub-intermediate stack 203 near the substrate 10 covers the dielectric layer 22 of the second sub-intermediate stack 202 away from the substrate 10.

[0135] S13: See also Figure 8 and Figure 15 A first channel hole CH1 is formed that penetrates at least one top selected gate sacrificial layer.

[0136] In the above steps, the first channel hole CH1 can be formed by etching.

[0137] In some embodiments, such as Figure 15 As shown, between S11 and S12, the aforementioned S1 also includes S14 to S15.

[0138] S14: See also Figure 6 and Figure 15 A second channel hole CH2 is formed that penetrates at least one word line sacrificial layer and at least one bottom select gate sacrificial layer.

[0139] In the above steps, the second channel hole CH2 can be formed by etching. The first channel hole CH1 and the second channel hole CH2 (see...) Figure 6 (Connected.) It should be noted that the first channel hole CH1 and the second channel hole CH2 have the same shape, but their dimensions may be different. In addition, the first channel hole CH1 and the second channel hole CH2 are coaxially arranged.

[0140] S15: See also Figure 7 and Figure 15A second channel structure 32 is formed within the second channel hole CH2.

[0141] In the above steps, the second channel structure 32 includes a storage function layer 320 and a second channel layer 324 arranged sequentially. The second channel layer 324 is electrically connected to the first channel layer 312, and both the storage function layer 320 and the second channel layer 324 are electrically insulated from the second gate conductive layer 21.

[0142] For example, see Figure 7 The storage functional layer 320 includes a barrier layer 321, a storage layer 322, and a tunneling layer 323 arranged sequentially. When forming the second channel structure 32, a deposition process can first be used in the second channel hole CH2 (see...). Figure 6 First, SiO2 is deposited inside, then the CH2 in the second channel hole is etched away (see...). Figure 6 SiO2 at the bottom is deposited to form a barrier layer 321 covering the sidewalls of the second channel structure 32. Then, a deposition process is used to deposit CH2 in the second channel hole (see...). Figure 6 SiN is first deposited on the inner side of the barrier layer 321 within the ) and then the second channel hole CH2 is etched away (see Figure 6 SiN at the bottom is deposited to form a storage layer 322 covering the barrier layer 321. Then, a deposition process is used in the second channel hole CH2 (see...) Figure 6 Inside the storage layer 322, a SiO, SiON, and SiO stack is first deposited, and then the second channel hole CH2 is etched away (see...). Figure 6 The bottom layer consists of SiO, SiON, and SiO stacks, forming a tunneling layer 323 that covers the memory layer 322. Finally, polysilicon is deposited inside the tunneling layer 323 using a deposition process to form a second channel layer 324.

[0143] In some embodiments, during process S15, see Figure 8 and Figure 9 An insulating pad 329 is also formed. The insulating pad 329 is disposed on the side of the storage functional layer 320 away from the substrate 10. The orthographic projection of the storage functional layer 320 on the substrate 10 and the orthographic projection of the second gate conductive layer 316 on the substrate 10 are both located within the orthographic projection of the insulating pad 329 on the substrate 10, so that the storage functional layer 320 is electrically insulated from the second gate conductive layer 316.

[0144] After forming the storage functional layer 320 and the second channel layer 324, the storage functional layer 320 is first etched such that the side of the storage functional layer 320 away from the substrate 10 is lower than the side of the second channel layer 324 away from the substrate 10, forming a third groove 328; then, an insulating pad 329 is formed in the third groove 328. Exemplarily, the insulating pad 329 is formed in the second groove 327 by depositing an insulating material.

[0145] In some embodiments, during process S15, a second channel filling layer 325 is also formed. The second channel filling layer 325 fills the gaps inside the second channel layer 324. The second channel filling layer 325 can be formed after the formation of the second channel layer 324 by a deposition process. Based on this, as... Figure 16 As shown, the method for fabricating the semiconductor structure 200 also includes steps S151 to S152.

[0146] S151: See also Figure 7 and Figure 16 The second channel filling layer 325 is etched to form the second groove 327.

[0147] In the above steps, the second groove 327 exposes part of the sidewall of the second channel layer 324.

[0148] S152: See also Figure 7 , Figure 8 and Figure 16 A second connecting pad 326 is formed in the second groove 327.

[0149] In the above steps, the second connecting pad 326 is in electrical contact with the exposed sidewall of the second channel layer 324, and the orthographic projection of the first channel layer 312 onto the substrate 10 overlaps with the orthographic projection of the second connecting pad 326 onto the substrate 10. That is, the end of the first channel layer 312 near the substrate is in electrical contact with the second connecting pad 326, so that the first channel layer 312 and the second channel layer 324 are electrically connected through the second connecting pad 326. Exemplarily, doped polysilicon is formed in the second groove 327 by deposition and ion doping processes, and the formed doped polysilicon is the second connecting pad 326.

[0150] In some embodiments, after S3, such as Figure 17 As shown, the method for fabricating the semiconductor structure 200 also includes steps S4 to S7.

[0151] S4: See also Figure 11 , Figure 12 and Figure 17 A photoresist layer 60 is formed covering the storage stack layer 20.

[0152] In the above steps, the photoresist layer 60 exposes multiple regions extending along the first direction X to initially define the etching area of ​​the cutting trench 50.

[0153] S5: See also Figure 11 , Figure 12 and Figure 17 Using the photoresist layer 60 and the second gate conductive layer 316 as a mask, the storage stack layer 20 is etched to form a cutting trench 50.

[0154] In the above steps, the dicing trench 50 extends along the first direction X to divide the top select gate (SGD) into multiple regions. The sidewalls of the dicing trench 50 extending along the first direction X are defined by the second gate conductive layer 316 exposed on the side of the dicing trench 50, and by the film layer in the storage stack layer 20 corresponding to the second gate conductive layer 316 exposed on the side of the dicing trench 50. That is, the portion of the sidewalls of the dicing trench 50 extending along the first direction X that passes through the second gate conductive layer 316 is an arc-shaped surface.

[0155] S6: See also Figure 11 , Figure 12 and Figure 17 The cutting structure 51 is filled into the cutting groove 50.

[0156] In the above steps, the dicing structure 51 and the second gate conductive layer 316 are exposed on the side of the dicing trench 50, and the film layer in the storage stack layer 20 corresponding to the second gate conductive layer 316 is exposed on the side of the dicing trench 50 in contact with it. The dicing structure 51 can be formed by filling the dicing trench 50 with SiCN using a deposition process.

[0157] S7: Remove photoresist layer 60.

[0158] It should be noted that the order of S6 and S7 is not limited here. S6 can be executed first and then S7, or S7 can be executed first and then S6.

[0159] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A memory stack layer disposed on the substrate, the memory stack layer comprising alternating layers of first gate conductive layers and layers of dielectric layers; Along the thickness direction of the substrate and away from the substrate, the multilayer first gate conductive layer sequentially includes at least one word line layer and at least one top select gate; the memory stack layer has a first channel via penetrating the at least one top select gate and a second channel via penetrating the at least one word line layer, the second channel via communicating with the first channel via; A first channel structure is disposed within the first channel aperture. The first channel structure includes a second gate conductive layer, a gate dielectric layer, and a first channel layer. The second gate conductive layer covers the sidewall of the first channel aperture and is connected to the at least one top selection gate. The gate dielectric layer is disposed on the side of the second gate conductive layer opposite to the sidewall of the first channel aperture, and the first channel layer is disposed on the side of the gate dielectric layer opposite to the second gate conductive layer. A second channel structure is disposed within the second channel hole. The second channel structure includes a storage function layer and a second channel layer disposed sequentially. The second channel layer is electrically connected to the first channel layer. The second channel structure also includes: An insulating pad is disposed on the side of the storage functional layer away from the substrate. The orthographic projection of the storage functional layer on the substrate and the orthographic projection of the second gate conductive layer on the substrate are both located within the orthographic projection of the insulating pad on the substrate and are in contact with the insulating pad respectively. The second channel layer covers the sidewalls of the insulating pad and the storage functional layer.

2. The semiconductor structure according to claim 1, characterized in that, The material of the first gate conductive layer includes metal, and the work function of the material of the second gate conductive layer is greater than 4.6 eV.

3. The semiconductor structure according to claim 1, characterized in that, The orthographic projection of the second channel layer on the substrate is separate from the orthographic projection of the second gate conductive layer on the substrate.

4. The semiconductor structure according to claim 1, characterized in that, The second channel structure also includes: The second channel filling layer is disposed in the gap inside the second channel layer; A second connection pad is disposed on the side of the second channel filling layer away from the substrate, and the second connection pad is electrically connected to the second channel layer.

5. The semiconductor structure according to claim 4, characterized in that, Along the thickness direction of the substrate, the height of the second channel filling layer is less than the height of the second channel layer to form a second groove, the second groove exposing a portion of the sidewall of the second channel layer; The second connecting pad is disposed in the second groove and is in electrical contact with the exposed sidewall of the second channel layer, wherein the orthographic projection of the first channel layer on the substrate overlaps with the orthographic projection of the second connecting pad on the substrate.

6. The semiconductor structure according to claim 1, characterized in that, The second channel structure also includes: A second channel filler layer fills the gap inside the second channel layer; along the thickness direction of the substrate, the height of the second channel filler layer is less than the height of the second channel layer to form a second groove, the second groove exposing a portion of the sidewall of the second channel layer; The first channel layer extends into the second groove and is in electrical contact with the exposed sidewall of the second channel layer.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The storage stack layer also has a dicing trench extending through the at least one top select gate, the dicing trench extending along a first direction in a plane parallel to the substrate to divide the at least one top select gate into multiple regions; The sidewall of the cutting groove extending along the first direction is defined by the second gate conductive layer exposed on the side of the cutting groove, and by the film layer in the storage stack layer corresponding to the second gate conductive layer exposed on the side of the cutting groove. The semiconductor structure also includes: A cutting structure is provided within the cutting groove; The cutting structure and the second gate conductive layer are exposed on the side of the cutting trench, and the film layer in the storage stack layer corresponding to the second gate conductive layer is exposed on the side of the cutting trench in contact.

8. The semiconductor structure according to claim 7, characterized in that, The orthographic projection of the first channel structure onto the substrate lies within the orthographic projection of the second channel structure onto the substrate.

9. The semiconductor structure according to claim 1, characterized in that, The first channel structure extends into the dielectric layer between the at least one word line layer and the at least one top select gate.

10. The semiconductor structure according to claim 9, characterized in that, The thickness of the dielectric layer between the at least one word line layer and the at least one top select gate is greater than the thickness of the other dielectric layers in the memory stack.

11. The semiconductor structure according to claim 1, characterized in that, The first channel structure also includes: The first channel filling layer is disposed in the gap inside the first channel layer; A first connection pad is disposed on the side of the first channel filling layer away from the substrate, and the first connection pad is electrically connected to the first channel layer.

12. The semiconductor structure according to claim 11, characterized in that, Along the thickness direction of the substrate, the height of the first channel filling layer is less than the height of the first channel layer to form a first groove, the first groove exposing a portion of the sidewall of the first channel layer; The first connecting pad is disposed in the first groove and is in electrical contact with the exposed sidewall of the first channel layer.

13. A method for fabricating a semiconductor structure, characterized in that, include: Preparation of intermediate semiconductor structures; The intermediate semiconductor structure includes: a substrate; an intermediate stacked layer disposed on the substrate, the intermediate stacked layer including alternating layers of sacrificial layers and layers of dielectric layers along the thickness direction of the substrate and away from the substrate, the layers of sacrificial layers sequentially including at least one word line sacrificial layer and at least one top select gate sacrificial layer; the intermediate stacked layer having a first channel via penetrating the at least one top select gate sacrificial layer; The preparation of the intermediate semiconductor structure includes: A second sub-intermediate stack layer is formed on the substrate, the second sub-intermediate stack layer comprising alternating layers of sacrificial layers and layers of dielectric layers; the layers of sacrificial layers include at least one word line sacrificial layer; Forming a second channel hole that penetrates the second sub-intermediate stack layer; A second channel structure is formed within the second channel hole; the second channel structure includes a storage functional layer and a second channel layer arranged sequentially; during the formation of the second channel structure within the second channel hole, an insulating pad is also formed, the insulating pad being disposed on the side of the storage functional layer away from the substrate; the second channel layer covers the insulating pad and the sidewall of the storage functional layer; A first sub-intermediate stack layer is formed on the side of the second sub-intermediate stack layer away from the substrate; the first sub-intermediate stack layer includes at least one top select gate sacrificial layer and at least one dielectric layer alternately arranged; A first channel hole is formed penetrating the at least one top selective gate sacrificial layer; a second channel hole communicates with the first channel hole; A first channel structure is formed within the first channel hole; the first channel structure includes a second gate conductive layer, a gate dielectric layer, and a first channel layer, wherein the second gate conductive layer covers the sidewall of the first channel hole; the gate dielectric layer is disposed on the side of the second gate conductive layer opposite to the sidewall of the first channel hole, and the first channel layer is disposed on the side of the gate dielectric layer opposite to the second gate conductive layer; the second channel layer is electrically connected to the first channel layer; the orthographic projection of the storage functional layer on the substrate and the orthographic projection of the second gate conductive layer on the substrate are both located within the orthographic projection of the insulating pad on the substrate and are in contact with the insulating pad respectively.

14. The preparation method according to claim 13, characterized in that, Also includes: The sacrificial layer is replaced with a gate material to form a first gate conductive layer; wherein the first gate conductive layer that replaces the top select gate sacrificial layer is a top select gate, and the second gate conductive layer is connected to the top select gate.

15. The preparation method according to claim 13, characterized in that, During the process of forming the second channel structure in the second channel hole, a second channel filling layer is also formed, which fills the gap inside the second channel layer. The preparation method further includes: The second channel filling layer is etched to form a second groove; the second groove exposes a portion of the sidewall of the second channel layer. A second connection pad is formed within the second groove; the second connection pad is in electrical contact with the exposed sidewall of the second channel layer, and the orthographic projection of the first channel layer on the substrate overlaps with the orthographic projection of the second connection pad on the substrate.

16. The preparation method according to claim 14, characterized in that, After replacing the sacrificial layer with a gate material to form a memory stack layer, the fabrication method further includes: Form a photoresist layer covering the storage stack layer; Using the photoresist layer and the second gate conductive layer as a mask, the storage stack layer is etched to form a dicing trench; the dicing trench extends along a first direction to divide the top select gate into multiple regions; A cutting structure is filled within the cutting groove; the cutting structure is in contact with the second gate conductive layer. Remove the photoresist layer.

17. The preparation method according to claim 16, characterized in that, The sidewall of the cutting groove extending along the first direction is defined by the second gate conductive layer exposed on the side of the cutting groove, and by the film layer in the storage stack layer corresponding to the second gate conductive layer exposed on the side of the cutting groove.

18. The preparation method according to claim 13, characterized in that, During the process of forming the first channel structure in the first channel hole, a first channel filling layer is also formed, which fills the gap inside the first channel layer. The preparation method further includes: The first channel filling layer is etched to form a first groove; the first groove exposes a portion of the sidewall of the first channel layer. A first connecting pad is formed within the first groove; the first connecting pad is in electrical contact with the exposed sidewall of the first channel layer.

19. A three-dimensional memory, characterized in that, Includes a semiconductor structure, wherein the semiconductor structure is the semiconductor structure as described in any one of claims 1 to 12 or is prepared by the method for preparing the semiconductor structure as described in any one of claims 13 to 18.

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