Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel includes a display area and a non-display area surrounding the display area; the display area includes a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction, wherein the first direction and the second direction intersect; the non-display area includes a bonding area, the bonding area includes a plurality of pads arranged in a third direction, and the direction perpendicular to the third direction is a fourth direction, and the angle formed by the second direction and the fourth direction is θ, where 0° < θ < 90°. According to the embodiments of the present application, the diverse needs of users can be met.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of display technologies and the diverse requirements of users for the appearance of display devices, relevant display panel manufacturers have begun to design and produce special-shaped display panels, such as circular display panels that can be applied to devices such as watches or wearable mobile phones.

[0003] However, the current special-shaped display panels and display devices still need to be improved. Summary of the Invention

[0004] This application provides a display panel and a display device, which can meet the diverse requirements of users.

[0005] In a first aspect, an embodiment of this application provides a display panel, which includes: a display area and a non-display area surrounding the display area; the display area includes a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction, where the first direction and the second direction intersect; the non-display area includes a bonding area, the bonding area includes a plurality of pads arranged in a third direction, the direction perpendicular to the third direction is a fourth direction, and the angle formed by the second direction and the fourth direction is θ, where 0° < θ < 90°.

[0006] In a second aspect, based on the same inventive concept, an embodiment of this application provides a display device, which includes the display panel according to the embodiment of the first aspect.

[0007] According to the display panel and the display device provided by the embodiments of this application, by disposing the bonding area offset from the lower border or the upper border of the display panel, the space of the lower border or the upper border of the display panel can be saved, thereby meeting the user's requirement for the space limitation of the lower border; in addition, other functional modules can be disposed at the lower border or the upper border to meet the diverse requirements of users. Description of the Drawings

[0008] By reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, other features, objects, and advantages of this application will become more apparent, where the same or similar reference numerals represent the same or similar features, and the drawings are not drawn to actual scale.

[0009] Figure 1 A schematic structural diagram of a display panel provided by the related art is shown;

[0010] Figure 2 A schematic structural diagram of a display panel provided by an embodiment of this application is shown;

[0011] Figure 3Schematic diagram showing the structure of a display panel provided by another embodiment of the present application;

[0012] Figures 4 to 6 Schematic diagram showing the structure of a display panel provided by some other embodiments of the present application;

[0013] Figure 7 Showing Figure 6 Schematic cross-sectional structure diagram in the A-A direction;

[0014] Figures 8 to 9 Schematic diagram showing the structure of a display panel provided by some other embodiments of the present application;

[0015] Figure 10 Showing Figure 9 Enlarged schematic diagram of the Q1 area;

[0016] Figure 11 Showing a Figure 9 Schematic diagram of a structure in the Q3 area;

[0017] Figure 12 Schematic diagram showing the structure of a display panel provided by another embodiment of the present application;

[0018] Figure 13 Showing a Figure 9 Schematic diagram of another structure in the Q3 area; Figure 14 Schematic diagram showing the structure of a display panel provided by another embodiment of the present application;

[0019] Figure 15 Showing Figure 12 Enlarged schematic diagram of the Q2 area;

[0020] Figure 16 Showing Figure 12 Schematic cross-sectional structure diagram in the B-B direction;

[0021] Figure 17 Schematic diagram showing the structure of a multiplexing unit provided by an embodiment of the present application;

[0022] Figure 18 Showing Figure 13 Schematic cross-sectional structure diagram in the C-C direction;

[0023] Figure 19 Schematic diagram showing the structure of a display panel provided by another embodiment of the present application;

[0024] Figure 20 Showing Figure 19 Schematic cross-sectional structure diagram in the D-D direction;

[0025] Figure 21Schematic structural diagram of a display panel provided by another embodiment of the present application;

[0026] Figure 22 Shows Figure 21 Schematic cross-sectional structure diagram in the E-E direction;

[0027] Figure 23 Schematic structural diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0028] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only provided to provide a better understanding of the present application by showing examples of the present application.

[0029] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "comprising..." do not exclude the presence of additional identical elements in the process, method, article or device comprising the said elements.

[0030] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is turned over, this layer or region will be "below" or "beneath" the other layer or region.

[0031] In the embodiments of the present application, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected via one or more other components.

[0032] Without departing from the spirit or scope of the present application, various modifications and variations can be made in the present application, which will be apparent to those skilled in the art. Therefore, the present application is intended to cover modifications and variations of the present application that fall within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the present application can be combined with each other without conflict.

[0033] Before describing the technical solutions provided in the embodiments of the present application, for the convenience of understanding the embodiments of the present application, the present application first specifically describes the problems existing in the prior art:

[0034] With the continuous development of display technology and the diverse needs of users for the appearance of display devices, more and more manufacturers have begun to design and produce special-shaped display panels, such as circular display panels that can be applied to devices such as watches or wearable mobile phones. As Figure 1 shown, the display panel includes a display area AA' and a non-display area NA'. In order to narrow the non-display area NA' of the circular display panel 100', the Chip on Film (COF) technology is often used in the related art, that is, the driving IC 10' is integrated onto a flexible printed circuit (FPC) 20' to form a COF flexible circuit board, and then the COF flexible circuit board is bent to the back of the display panel 100' to save the space of the lower border.

[0035] In the related art, a bonding area NA1' is set at the lower border, and then the FPC 20' is bonded to the bonding area NA1'. However, in the case where the user has a space limitation requirement for the lower border or other functional modules need to be set at the lower border, the bonding area NA1' cannot be set at the lower border.

[0036] In view of this, the embodiments of the present application provide a display panel and a display device, which can meet the diverse needs of users.

[0037] As Figure 2 shown, the display panel 100 provided in the embodiments of the present application includes a display area AA and a non-display area NA surrounding the display area AA. Different from the conventional rectangular display panel, the display panel 100 provided in this embodiment can be special-shaped, and its outer contour includes arc segments. Exemplarily, the shape of the display area AA of the display panel can include a circle for further application to wearable devices such as watches. Of course, in some other embodiments of the present application, the display panel 100 can also be oval or polygonal, fully meeting the diverse needs of users for different display panel shapes. The present application does not limit the specific shape of the display panel 100. The embodiments of the present application take the display panel 100 as a circle as an example, which does not limit the present application.

[0038] Please continue to refer to Figure 2 , the display area AA may be provided with scan lines 11 and data lines 12, and the non-display area NA may include a bonding area NA1, and the bonding area NA1 may be provided with a plurality of pads 20.

[0039] A plurality of scan lines 11 may extend along the first direction X and be spaced apart in the second direction Y. A plurality of data lines 12 may extend along the second direction Y and be spaced apart in the first direction X. The first direction X intersects the second direction Y. Exemplarily, the first direction X may be perpendicular to the second direction Y, the first direction X may be the row direction, and the second direction Y may be the column direction. The plurality of pads 20 are arranged along the third direction Z, and the direction perpendicular to the third direction Z is the fourth direction W, and the second direction Y and the fourth direction W form an angle θ, 0° < θ < 90°. That is to say, in the embodiments of the present application, the bonding area NA1 is no longer arranged on the lower border or the upper border of the display panel, but the bonding area NA1 is arranged offset from the lower border or the upper border of the display panel, so as to perform an offset design on the bonding area NA1. It can be understood that, relative to Figure 1 in which the bonding area NA1' is arranged on the lower border of the display panel, in the embodiments of the present application, the bonding area NA1 is rotated by an angle θ and the bonding area NA1 is arranged on the right border or the left border.

[0040] It can be understood that the third direction Z is different from the first direction X, and the third direction Z is different from the second direction Y. The first direction X, the second direction Y, the third direction Z, and the fourth direction W are all directions parallel to the plane where the display panel 100 is located.

[0041] It should be noted that the number and size of the scan lines 11, the data lines 12, and the pads 20 in the drawings provided in this embodiment do not represent the actual number and size, but are only for illustrative purposes.

[0042] In the embodiments of the present application, by arranging the bonding area NA1 offset from the lower border or the upper border of the display panel, the space of the lower border or the upper border of the display panel can be saved, so as to meet the user's space limitation requirements for the lower border; in addition, other functional modules can be arranged at the lower border or the upper border to meet the diverse needs of users.

[0043] Exemplarily, the driving IC may be integrated on the FPC, and the FPC is bonded to the pads 20 of the bonding area NA1. The driving IC may provide a data signal to the data line 12, and further control the display panel 100 to display. Exemplarily, such as Figure 3As shown, the fan-out trace 13 can be electrically connected between the pad 20 and the data line 12, so that the driving IC can transmit data signals to the data line 12 through the fan-out trace 13. If the bias of the bonding area NA1 is larger, that is, the angle θ formed by the second direction Y and the fourth direction W is larger, the trace length of the fan-out trace 13 needs to be set longer. If the trace length of the fan-out trace 13 is longer, in order to accommodate more fan-out traces 13, the size of the non-display area NA needs to be increased, which is not conducive to realizing a narrow border, and the signal transmission delay of the longer fan-out trace 13 is also long, which is not conducive to the timeliness of signal transmission.

[0044] In some alternative embodiments, the angle θ formed by the second direction Y and the fourth direction W can satisfy 0° < θ ≤ 45°, so as to avoid excessive bias of the bonding area NA1, thereby avoiding a long trace length of the fan-out trace 13, which is conducive to realizing a narrow border and the timeliness of signal transmission.

[0045] Exemplarily, the angle θ formed by the second direction Y and the fourth direction W can be 5°, 15°, 25°, 35°, 45°, etc.

[0046] In some alternative embodiments, as Figure 4 shown, the non-display area NA may include at least part of the first power bus 31 surrounding the display area AA, and the pad 20 may include at least one first conductive pad 21. The first power bus 31 may include a first connection node N1. The display area NA may further include a bus connection portion 40. The first power bus 31 is connected to the first conductive pad 21 through the bus connection portion 40 at the first connection node N1. It can be understood that the bus connection portion 40 is connected between the first connection node N1 and the first conductive pad 21, and the voltage signal on the first conductive pad 21 is transmitted to the first connection node N1 through the bus connection portion 40.

[0047] The number of the first connection nodes N1 is at least one. Of course, the number of the first connection nodes N1 can be two or more. Optionally, as Figure 4 shown, taking the number of the first connection nodes N1 as one as an example, the bus connection portion 40 can extend along the fourth direction Y. It can be understood that in this case, the extending direction of the bus connection portion 40 is perpendicular to the third direction Z, and the bus connection portion 40 is the shortest path between the first power bus 31 and the pad 20, so that the trace length of the bus connection portion 40 can be reduced, thereby reducing the voltage drop of the bus connection portion 40.

[0048] Optionally, as Figure 5As shown, still taking the number of the first connection node N1 as one, the first connection node N1 can be located at about the six o'clock position of the display panel. To better understand the position of the first connection point N1, a first straight line L1 and the center point O1 of the display area AA are introduced here. The first straight line L1 passes through the center point O1 of the display area AA and extends along the second direction Y. Exemplarily, the first straight line L1 can pass through the first connection node N1, or the vertical distance between the first connection node N1 and the first straight line L1 is relatively short. In this way, the voltage signal on the first conductive pad 21 can be transmitted from the center of the display area AA to both sides in the first direction X. It can be understood that the voltage signal on the first conductive pad 21 first reaches the central area of the display area and then reaches both side areas of the display area in the first direction X. In this way, it can be ensured that the first conductive pad 21 supplies power to the display area evenly, and the problem of uneven display caused by the voltage signal on the first conductive pad 21 starting to supply power from one side area of the display area in the first direction X can be avoided.

[0049] Exemplarily, a plurality of voltage signal transmission lines 14 can be arranged in the display area AA of the display panel 100. The plurality of voltage signal transmission lines 14 can extend along the second direction Y. The voltage signal transmission line 14 is electrically connected to the first power bus 31. The first power bus 31 can be used to transmit a positive voltage signal to the voltage signal transmission line 14, and the voltage signal transmission line 14 can also be called a PVDD trace.

[0050] For example, the first power bus 31 can be electrically connected to any end of the voltage signal transmission line 14; for another example, the first power bus 31 can be electrically connected to both ends of the voltage signal transmission line 14. Exemplarily, as Figure 4 shown, the first power bus 31 can be a closed trace arranged around the display area AA, or, as Figure 5 shown, the first power bus 31 can also be a non-closed trace that only partially surrounds the display area AA.

[0051] In some alternative embodiments, as Figure 6 shown, a second power bus 32 can also be arranged in the non-display area NA. The second power bus 32 at least partially surrounds the display area AA. The second power bus 32 can be located between the first power bus 31 and the display area AA. The second power bus 32 is electrically connected to the first power bus 31.

[0052] Exemplarily, at least part of the plurality of voltage signal transmission lines 14 in the display area AA can be electrically connected to the second power bus 32, and the voltage signal on the first conductive pad 21 can be transmitted to the display area AA through the bus connection part 40, the first power bus 31, and the second power bus 32 in sequence.

[0053] In the embodiments of the present application, by providing a first power bus 31 and a second power bus 32 which are electrically connected, thus, the first power bus 31 and the second power bus 32 can be regarded as being connected in parallel, which can reduce the voltage drop of the first power bus 31 and the second power bus 32 and improve the display uniformity.

[0054] Exemplarily, the first power bus 31 and the second power bus 32 can be provided on the same film layer, and the materials of the first power bus 31 and the second power bus 32 can also be the same, so that the first power bus 31 and the second power bus 32 can be formed simultaneously in the same process step. Optionally, the first power bus 31, the second power bus 32 and the bus connection part 40 can be provided on the same film layer, and the materials of the first power bus 31, the second power bus 32 and the bus connection part 40 can also be the same, so that the first power bus 31, the second power bus 32 and the bus connection part 40 can be formed simultaneously in the same process step.

[0055] Exemplarily, as Figure 7 shown, the display panel 100 may include a substrate 01 and a driving device layer 02 provided on one side of the substrate 01. The driving device layer 02 may include a semiconductor layer 021, a first metal layer M1, a second metal layer M2, and a third metal layer M3 that are sequentially stacked in a direction away from the substrate 01. A gate insulating layer 022 may be provided between the first metal layer M1 and the semiconductor layer 021, a capacitive insulating layer 023 may be provided between the second metal layer M2 and the first metal layer M1, an interlayer dielectric layer 025 may be provided between the third metal layer M3 and the second metal layer M2, and an interlayer dielectric layer 025 may be additionally provided to cover the third metal layer M3. The first power bus 31, the second power bus 32, and the bus connection part 40 may all be provided on the third metal layer M3. The scanning line 11 may be provided on the first metal layer M1, and the data line 12 and the voltage signal transmission line 14 may also be provided on the third metal layer M3. The second metal layer M2 may be used to provide the electrodes of the capacitor.

[0056] Exemplarily, the second power bus 32 may be electrically connected to any one end of the voltage signal transmission line 14; alternatively, the second power bus 32 may be electrically connected to both ends of the voltage signal transmission line 14. Exemplarily, the second power bus 32 may be a closed trace provided around the display area AA, or the second power bus 32 may also be a non-closed trace that only partially surrounds the display area AA.

[0057] Exemplarily, the first power bus 31 may include a second connection node N2, which is different from the first connection node N1. The second power bus 32 may be in contact connection with the first power bus 31 at the second connection node N2. When the first power bus 31 includes the second connection node N2, the first power bus 31 may only include the trace portion between the first connection node N1 and the second connection node N2, such that the first power bus 31 is a non-closed trace that only partially surrounds the display area AA.

[0058] Taking the number of the second connection nodes N2 as one for example, the second connection node N2 may be located at approximately the six o'clock position of the display panel. For a better understanding of the position of the second connection node N2, the first straight line L1 and the center point O1 of the display area AA are still introduced here. The first straight line L1 passes through the center point O1 of the display area AA and extends along the second direction Y. Exemplarily, the first straight line L1 may pass through the second connection node N2, or the vertical distance between the second connection node N2 and the first straight line L1 is relatively short. In this way, the voltage signal on the first conductive pad 21 can be transmitted from the center of the display area AA to both sides in the first direction X. It can be understood that the voltage signal on the first conductive pad 21 first reaches the central area of the display area and then reaches both side areas of the display area in the first direction X. In this way, it can be ensured that the first conductive pad 21 supplies power to the display area evenly, and the problem of uneven display caused by the voltage signal on the first conductive pad 21 starting to supply power from one side area of the display area in the first direction X can be avoided.

[0059] Of course, the number of the second connection nodes N2 can also be two or more. The positions of the multiple second connection nodes N2 can be reasonably set to ensure that the voltage signal on the first conductive pad 21 can be evenly transmitted to the display area.

[0060] In some alternative embodiments, please continue to refer to Figure 6 , the second connection node N2 may be located on the side of the first power bus 31 along the second direction Y close to the bonding area NA1. For example, if the bonding area NA1 is arranged at the lower right of the display panel, the second connection node N2 may be arranged directly below the display area AA. Since the second connection node N2 is arranged close to the bonding area NA1, it is equivalent to that the voltage signal of the first conductive pad 21 in the bonding area NA1 can reach the second power bus along a shorter path, which can reduce the voltage drop caused by the first power bus 31.

[0061] In some alternative embodiments, such as Figure 8As shown, the first power supply bus 31 may be recessed in the direction of the display area AA at the second node N2. It can be understood that the second connection node N2 has a certain length, and the first power supply bus 31 contacts the second power supply bus 32 at the second connection node N2, such that the width of the contact overlap between the first power supply bus 31 and the second power supply bus 32 at the second connection node N2 is greater than the width of other areas. Compared with the first power supply bus 31 and the second power supply bus 32 being electrically connected or overlapped through vias, the embodiment of the present application can make the parallel region of the first power supply bus 31 and the second power supply bus 32 wider, thereby being able to better reduce the voltage drop.

[0062] Exemplarily, the first power supply bus 31 may include a first branch 311 and a second branch 312 connected to each other. The first branch 311 extends along the direction surrounding the display area AA, and the extending direction of the second branch 312 may intersect with that of the first branch 311. The second branch 312 may be located on the side of the first branch 311 closer to the display area AA. The second branch 312 is connected between the first branch 311 and the second connection node N2. The first branch 311, the second branch 312, the second connection node N2, and the second power supply bus 32 may be disposed on the same film layer.

[0063] Exemplarily, when the first power supply bus 31 may be recessed in the direction of the display area AA at the second node N2, the first straight line L1 may still pass through the second connection node N2.

[0064] In some alternative embodiments, as Figure 9 shown, the bus connection portion 40 may include a first sub-connection portion 41 and at least one second sub-connection portion 42. The first sub-connection portion 41 extends along the third direction Z, and the second sub-connection portion 42 extends along the fourth direction W. Both ends of the first sub-connection portion 41 are respectively connected to the first conductive pads 21. It can be understood that the number of the first conductive pads 21 is at least two, and both ends of the first sub-connection portion 41 may be respectively connected to one first conductive pad 21 each. One end of the second sub-connection portion 42 is connected to the third connection node N3 between both ends of the first sub-connection portion 41, and the other end of the second sub-connection portion 42 is connected to the first connection node N1. Additionally, when the number of the second sub-connection portions 42 is multiple, it can be understood that the number of the third connection nodes N3 between both ends of the first sub-connection portion 41 may also be multiple, and the multiple second sub-connection portions 42 may correspond to the multiple third connection nodes N3 one by one.

[0065] The number of the second sub-connection parts 42 can be one or more. When the number of the second sub-connection parts 42 is one, the line width of the second sub-connection part 42 can be set wider. For example, the line width of the second sub-connection part 42 can be greater than the line width of the fan-out trace. Optionally, the trace width of the second sub-connection part 42 is greater than the trace width of the voltage signal transmission line 14. The second sub-connection part 42 includes a hollow structure, and a plurality of hollow structures can be arranged along the extension direction of the fourth direction W. Optionally, groove structures are arranged on the opposite edges of the second sub-connection part 42 along the third direction Z, so as to prevent the intrusion of water and oxygen. When the number of the second sub-connection parts 42 is multiple, other traces can be arranged between adjacent second sub-connection parts 42. For example, a control signal line of a switch can be arranged between adjacent second sub-connection parts 42, and the control signal line of the switch can be connected to the control end of the multiplexing unit, which will be introduced in detail below. The second sub-connection part 42 transmits a fixed voltage signal, while the control signal line of the switch transmits a signal with alternating high and low levels. The second sub-connection part 42 can function as a shielding structure to shield the coupling capacitance formed between the control signal line of the switch and other signal lines, thereby ensuring signal stability.

[0066] In some alternative embodiments, in order to distinguish the two first conductive pads 21 respectively connected to the two ends of the first sub-connection part 41, refer to Figure 9 and Figure 10 , one of the first conductive pads 21 is called the first sub-conductive pad 211, and the other first conductive pad 21 is called the second sub-conductive pad 212. Taking the number of the second sub-connection parts 42 being two as an example, regarding the two second sub-connection parts 42 as a whole, therefore, in the third direction Z, the distance from the first sub-conductive pad 211 to a second sub-connection part 42 on the left side as shown in the figure is d1, and the distance from the second sub-conductive pad 212 to a second sub-connection part 42 on the right side as shown in the figure is d2, and d1 > d2. In another embodiment, when the number of the second sub-connection parts 42 is 1, it can be understood that the distances from the second sub-connection part 42 to the first sub-conductive pad 211 and the second sub-conductive pad 212 are d1 and d2 respectively. In this way, the position of the second sub-connection part 42 relative to the first sub-connection part 41 can be defined as asymmetric, that is, a non-centered position. Taking the center point O2 of the first sub-connection part 41 in the third direction Z as an example, it can be understood that the third connection node N3 is arranged on one side of the center point O2 of the first sub-connection part 41 close to one end of the first sub-connection part 41. That is to say, the second sub-connection part 42 is no longer located at the center of the first sub-connection part 41 or the second sub-connection part 42 is no longer symmetric about the center of the first sub-connection part 41, and the second sub-connection part 42 also has an offset design.

[0067] Combined with reference to Figure 11 and Figure 3, the fan-out trace 13 includes a fan-out trace portion 131 that at least partially extends around the display area AA. Since some of the multiple pads 20 need to be electrically connected to the fan-out trace 13, when the bonding area NA1 is offset, as shown in the figure, when the bonding area NA1 is offset to the non-display area on the right side, it generally causes a large number of fan-out traces to gather in the area on the left side of the bonding area. In one case, if the second sub-connection portion 42 is disposed in the middle area of the bonding area with respect to the bonding area NA1, that is, the second sub-connection portion 42 is disposed in the middle area of the first sub-connection portion 41, that is, near the center point O2 as shown above, it will cause a large overlap between the fan-out traces near the left side of the bonding area and the second sub-connection portion 42, and the fan-out traces at the far end of the center point O2 will not overlap with the second sub-connection portion 42. As a result, on the one hand, the parasitic capacitance caused by the overlap between the fan-out traces affects the transmission of data signals, and on the other hand, the degree of overlap in the overlapping area formed by the fan-out traces and the second sub-connection portion is different, including the number of times the fan-out traces and the second sub-connection portion overlap, so that the signals of the fan-out traces are non-uniform due to the number of overlaps, ultimately affecting the display effect.. In the embodiment of the present application, as Figure 11 shown, since the second sub-connection portion 42 is no longer located near the center of the first sub-connection portion 41, or the second sub-connection portion 42 is no longer symmetric about the center of the first sub-connection portion 41, this can avoid the overlap between the second sub-connection portion 42 and the fan-out traces, and finally result in the same number of overlaps between the fan-out traces and the first power bus. For example, they can overlap once. In this way, on the one hand, it ensures that the number of overlaps between the fan-out traces and the first power bus is reduced to one, minimizing the influence of the coupling capacitance as much as possible, and on the other hand, it can ensure that the number of overlaps between the fan-out traces and the first power bus is the same, ensuring the uniformity of the coupling capacitance of each fan-out trace, thereby improving the display effect.

[0068] In some alternative embodiments, as Figure 12 、 13 shown, the non-display area NA further includes a gate driving circuit 50 and a clock signal line 51 disposed on both sides of the display panel 100 in the first direction X. The clock signal line 51 is disposed on one side of the first power bus 31 close to the display area AA. The clock signal line 51 includes a first type of clock signal line 511 and a second type of clock signal line 512 that respectively drive the gate driving circuits 50 on both sides. The gate driving circuit 50 can be electrically connected to the scan line 11 for transmitting a scan signal and / or a light emission control signal to the scan line 11. One gate driving circuit 50 can be disposed on each side of the display panel 100 in the first direction X. The present application does not limit the respective numbers of the first type of clock signal line 511 and the second type of clock signal line 512. For the clarity of the drawings, in the drawings of the present application, the numbers of the first type of clock signal line 511 and the second type of clock signal line 512 are both shown as one for illustration, which is not used to limit the present application.

[0069] Exemplarily, the gate driving circuit 50 may be disposed on one side of the first power supply bus 31 close to the display area AA. For example, the gate driving circuit 50 and the clock signal line 51 may be disposed between the first power supply bus 31 and the second power supply bus 32. The gate driving circuit 50 may be disposed on one side of the clock signal line 51 close to the display area AA.

[0070] Exemplarily, the gate driving circuit 50 may include a plurality of cascaded shift register units 501. The display panel 100 may further include a first trigger signal line 531 and a second trigger signal line 532 for driving the gate driving circuits 50 on both sides respectively. In the drawings herein, it is shown in a reverse scan manner, and the first trigger signal line 531 and the second trigger signal line 532 may be electrically connected to the last-stage shift register units 501 of the gate driving circuits 50 on both sides respectively.

[0071] As described above, the bus connection portion 40 may include at least one second sub-connection portion 42 extending in the fourth direction W. In this article, it is shown by way of example that the number of the second sub-connection portions 42 is two.

[0072] As Figure 12 and Figure 14 shown, the pad 20 may further include a plurality of second conductive pads 22. The clock signal line 51 is electrically connected to the plurality of second conductive pads 22 through the clock signal connection line 52. The clock signal connection line 52 includes a first clock signal connection portion 521 extending in the fourth direction W. It can be understood that since the clock signal line 51 includes a first type of clock signal line 511 and a second type of clock signal line 512, the number of the clock signal connection lines 52 may be multiple, and some of the clock signal connection lines 52 are electrically connected to the first type of clock signal line 511, and some of the clock signal connection lines 52 are electrically connected to the second type of clock signal line 512.

[0073] The clock signal connection line 52 may include a first clock signal connection portion 521 extending in the fourth direction W. A plurality of first clock signal connection portions 521 may be disposed on both sides of the second sub-connection portion 42 in the third direction Z. It can be understood that when the number of the second sub-connection portions 42 is two, there is no first clock signal connection portion 521 between the two second sub-connection portions 42.

[0074] Exemplarily, with reference to Figure 12 and Figure 14, the non-display area NA may further include a multiplexing unit 60 and a plurality of fan-out traces 13. The pad 20 may further include a plurality of third conductive pads 23. One end of the fan-out trace 13 is electrically connected to the input end of the multiplexing unit 60, and the other end is electrically connected to the third conductive pad 23. The output end of the multiplexing unit 60 may be connected to the data line 12 for transmitting a data signal to the data line 12. The multiplexing unit 60 may include a plurality of output ends, and each output end is connected to at least one data line 12. By providing the multiplexing unit 60 as compared to directly connecting the fan-out trace 13 to the data line 12, the number of fan-out traces 13 can be reduced, thereby achieving a narrow border; and the number of third conductive pads 23 can be reduced, and further the number of output pins in the driving IC can be reduced, which can reduce the cost.

[0075] Exemplarily, with reference to Figure 12 and Figure 14 , the fan-out trace 13 includes a first fan-out trace portion 131 extending along the periphery of the display area AA, and the first clock signal connection portion 521 and the first fan-out trace portion 131 extending along the periphery of the display area AA may have no overlap. Since the signals on the fan-out trace 13 and the first clock signal connection portion 521 are constantly changing within one frame time, if there is an overlap between the two, the parasitic capacitance between the two will be relatively large, and the potential change of one will seriously affect the potential change of the other, and this situation can also be referred to as signal coupling caused by parasitic capacitance. In the case where the first clock signal connection portion 521 and the first fan-out trace portion 131 extending along the periphery of the display area AA have no overlap, the instability of the signals on the fan-out trace 13 and / or the first clock signal connection portion 521 caused by signal coupling can be reduced; in addition, the overlap situation between each first fan-out trace portion 131 extending along the periphery of the display area AA and the first clock signal connection portion 521 is the same, so each first fan-out trace portion 131 extending along the periphery of the display area AA is uniformly affected by the first clock signal connection portion 521, and thus the display uniformity can be improved.

[0076] Exemplarily, the pad 20 may further include a fifth conductive pad 25, and the first trigger signal line 531 and the second trigger signal line 532 are each electrically connected to the fifth conductive pad 25. The fifth conductive pad 25 and the second pad 22 are adjacent to each other. In the third direction Z, the fifth conductive pad 25 may be located on the side of the second pad 22 closer to the second sub-connection portion 42.

[0077] In some alternative embodiments, with reference to Figure 12 , Figure 14 and Figure 15, at least part of the clock signal connection line 52 may further include a second clock signal connection portion 522. The second clock signal connection portion 522 extends along the third direction Z, and at least part of the first clock signal connection portion 521 is electrically connected to the second conductive pad 22 through the second clock signal connection portion 522. The second clock signal connection portion 522 may be disposed on a side of the first clock signal connection portion 521 away from the second sub-connection portion 42. Exemplarily, at least part of the first clock signal connection portion 521 and the second conductive pad 22 electrically connected thereto are not on the same straight line.

[0078] Exemplarily, the fan-out trace 13 may include a second fan-out trace portion 132 extending along the fourth direction W. In the third direction Z, the first clock signal connection portion 521 may be disposed between the second fan-out trace portion 132 and the second sub-connection portion 42. Since the second clock signal connection portion 522 is disposed on a side of the first clock signal connection portion 521 away from the second sub-connection portion 42, the distance d3 between the adjacent first clock signal connection portion 521 and the second fan-out trace portion 132 in the third direction Z is increased, that is, the first clock signal connection portion 521 and the second fan-out trace portion 132 can be spaced apart by a certain distance. As described above, the signals on the fan-out trace 13 and the first clock signal connection portion 521 are constantly changing within one frame time. Since the distance between the first clock signal connection portion 521 and the second fan-out trace portion 132 is increased, the signal coupling between the two can be reduced, and the degree of mutual influence between the signals of the two can be avoided.

[0079] In some alternative embodiments, such as Figure 14 shown, the first clock signal line 511 is disposed on a side of the first power bus 31 close to the display area AA, and the clock signal connection line 52 is disposed on a side of the first power bus 31 away from the display area AA. That is to say, the first clock signal line 511 and the clock signal connection line 52 are disposed on both sides of the first power bus 31. At least part of the first clock signal line 511 may be connected to the clock signal connection line 52 through the first jumper 541. The first jumper 541 overlaps with the first power bus 31 and is disposed on different layers.

[0080] Exemplarily, the first jumper 541, the first clock signal line 511, and the clock signal connection line 52 may all be disposed on different layers, and the first jumper 541 may be connected to the first clock signal line 511 and the clock signal connection line 52 through vias respectively. For example, as Figure 16 shown, the first jumper 541 may be disposed on the first metal layer M1, and the first clock signal line 511 and the clock signal connection line 52 may be disposed on the third metal layer M3. The first power bus 31 may also be disposed on the third metal layer M3.

[0081] In some alternative embodiments, please continue to refer to Figure 12, still taking the input end of the multiplexing unit 60 being connected through the fan-out routing 13 and the third conductive pad 23, and the output end of the multiplexing unit 60 being connected to the data line 12 as an example. Along the third direction Z, the third conductive pad 23 can be arranged between two first conductive pads 21. Exemplarily, the first conductive pad 21 includes a first sub-conductive pad 211 and a second sub-conductive pad 212. Along the third direction Z, the third conductive pad 23 can be arranged between the first sub-conductive pad 211 and the second sub-conductive pad 212. It can be understood that along the third direction Z, the first sub-conductive pad 211 and the second sub-conductive pad 212 are respectively arranged near two edges of the bonding area NA1.

[0082] Still taking the bus connection portion 40 including a first sub-connection portion 41 extending along the third direction Z and at least one second sub-connection portion 42 extending along the fourth direction W as an example. As described above, in the case where the bonding area NA1 is offset, the second sub-connection portion 42 is also offset. The second sub-connection portion 42 is no longer located at the center of the first sub-connection portion 41 or the second sub-connection portion 42 is no longer symmetric about the center of the first sub-connection portion 41. Therefore, along the third direction Z, the number of third conductive pads 23 on both sides of the second sub-connection portion 42 can also be different. Exemplarily, along the third direction Z, the number of third conductive pads 23 on one side of the second sub-connection portion 42 is greater than the number of third conductive pads 23 on the other side of the second sub-connection portion 42. For example, along the third direction Z, the difference between the number of third conductive pads 23 on one side of the second sub-connection portion 42 and the number of third conductive pads 23 on the other side of the second sub-connection portion 42 is greater than or equal to 2. It can be understood that the plurality of third conductive pads 23 are no longer symmetrically distributed about the second sub-connection portion 42.

[0083] Exemplarily, the first conductive pad 21 can include a first sub-conductive pad 211 and a second sub-conductive pad 212. The clock signal line 51 is electrically connected to the second conductive pad 22. Along the third direction Z, some of the third conductive pads 23 can be located between the first sub-conductive pad 211 and the second conductive pad 22, and some of the third conductive pads 23 can be located between the second sub-conductive pad 212 and the second conductive pad 22. There may be no third conductive pads 23 between the second conductive pads 22. The number of third conductive pads 23 between the first sub-conductive pad 211 and the second conductive pad 22 can be greater than the number of third conductive pads 23 between the second sub-conductive pad 212 and the second conductive pad 22.

[0084] The second sub-connection part 42 is no longer located at the center of the first sub-connection part 41 or the second sub-connection part 42 is no longer symmetric about the center of the first sub-connection part 41. Along the third direction Z, the number of the third conductive pads 23 on the side of the second sub-connection part 42 close to the first sub-conductive pad 211 can be greater than the number of the third conductive pads 23 on the side of the second sub-connection part 42 close to the second sub-conductive pad 212. The first sub-conductive pad 211 is close to the first straight line L1, and the second sub-conductive pad 212 is far from the first straight line L1. The side of the second sub-connection part 42 close to the first sub-conductive pad 211 can be understood as the side of the second sub-connection part 42 close to the first straight line L1, and the side of the second sub-connection part 42 close to the second sub-conductive pad 212 can be understood as the side of the second sub-connection part 42 far from the first straight line L1.

[0085] In the embodiment of the present application, the multiple third conductive pads 23 are no longer symmetrically distributed about the second sub-connection part 42. In this way, the non-uniform overlap times between each fan-out wire 13 and the first power bus 31 can be avoided, and each fan-out wire 13 can overlap with the first power bus 31 once, thereby improving the display uniformity.

[0086] Exemplarily, for better understanding of the setting position of the multiplexing unit 60, as Figure 12 shown in FIG. 13, taking the second straight line L2 and the center point O1 of the display area AA as an example, the second straight line L2 passes through the center point O1 of the display area AA and extends along the first direction X, and the multiple multiplexing units 60 can be distributed on the side of the second straight line L2 close to the bonding area NA1. In this way, the routing length of the signal line between the multiplexing unit 60 and the pad can be shortened. For example, the routing length of the fan-out wire 13 can be shortened. Exemplarily, the multiple multiplexing units 60 can also be symmetrically distributed about the first straight line L1.

[0087] In some alternative embodiments, as Figure 14 shown in FIG. 13, still taking the fan-out wire 13 including the first fan-out wire part 131 as an example, the extending direction of the first fan-out wire part 131 can include the third direction Z and / or the direction around the display area AA, and each first fan-out wire part 131 can have no overlap with the first power bus 31. That is to say, the situation that the first power bus 31 overlaps with some first fan-out wire parts 131 and does not overlap with some first fan-out wire parts 131 is avoided, so as to avoid the situation that the display is non-uniform due to the non-uniform overlap situation between the first power bus 31 and each first fan-out wire part 131. It can also be understood that, generally speaking, each fan-out wire 13 can overlap with the first power bus 31 once.

[0088] Exemplarily, when the first fan-out wire part 131 has no overlap with the first power bus 31, the first fan-out wire part 131 can also have no overlap with the second sub-connection part 42.

[0089] In some alternative embodiments, such as Figure 17 shown, the multiplexing unit 60 may include a plurality of switches 61. For example, the number of switches 61 included in the multiplexing unit 60 may be 2, 3, 4, 6, 12, etc. In the accompanying drawings of the present application, the number of switches 61 included in the multiplexing unit 60 is schematically shown as 2, which is not intended to limit the present application. Exemplarily, the switch 61 may be a thin film transistor. For example, the switch 61 may be a low temperature polysilicon transistor or an oxide transistor, etc. The control terminal of the switch 61 is connected to the control signal line 62, the input terminal of the switch 61 may be electrically connected to the fan-out trace 13, and the output terminal of the switch 61 may be electrically connected to the data line 12.

[0090] Such as Figure 13 shown, the control signal line 62 may extend around the display area AA. Exemplarily, the control signal line 62 may be located on the side of the first power bus 31 close to the display area AA. The control signal line 62 may be provided with a line change at the second connection node N2. For example, the display panel 100 may include a line change connection line 63. As described above, the first power bus 31 may include a first section 311 and a second section 312 connected to each other, and the second section 312 is connected between the first section and the second connection node N2. The line change connection line 63 may extend along the direction around the display area AA, the line change connection line 63 overlaps with the second section 312, and the line change connection line 63 is connected between the control signal lines 62. The display panel may further include a control signal connection line 64, and the control signal connection line 64 is located on the side of the first power bus 31 away from the display area AA. One end of the control signal connection line 64 is connected to the line change connection line 63, and the other end is connected to the fourth conductive pad 24.

[0091] Exemplarily, the control signal connection line 64, the first section 311, and the second section 322 may be provided in the same film layer. The line change connection line 63 and the second section 322 are provided in different film layers. For example, as Figure 18 shown, the control signal connection line 64, the first section 311, and the second section 322 may be provided in the third metal layer M3, and the line change connection line 63 may be provided in the first metal layer M1. The control signal line 62 may also be provided in the third metal layer M3. The line change connection line 63 is connected to the control signal lines 62 on both sides thereof through vias, and the line change connection line 63 is connected to the control signal connection line 64 through vias.

[0092] Exemplarily, the control signal connection line 64 may include a control signal connection portion 641 extending along the fourth direction W, and the control signal connection portion 641 is connected to the fourth conductive pad 24. The control signal connection portion 641 may be located between adjacent second sub-connection portions 42. The signals on the control signal connection portion 641 and the clock signal connection lines 52 on both sides of the second sub-connection portion 42 change continuously within one frame time, while the second sub-connection portion 42 transmits a fixed voltage signal. Therefore, the second sub-connection portion 42 can function as a shielding structure to shield the coupling capacitance formed between the control signal connection portion 641 and the clock signal connection lines 52, thereby ensuring signal stability.

[0093] Exemplarily, in the third direction Z, the fourth conductive pad 24 may be disposed between the fifth conductive pads 25. Additionally, the pad 20 may further include a sixth conductive pad 26 for transmitting a negative voltage signal to the display area AA. For example, the sixth conductive pad 26 may be electrically connected to the cathode of the light-emitting element in the display area AA. The sixth conductive pad 26 may be disposed adjacent to the first conductive pad 21. For example, in the third direction Z, the sixth conductive pad 26 may be located on a side of the first conductive pad 21 away from the second sub-connection portion 42.

[0094] Exemplarily, with reference to Figure 12 and Figure 7 , in the case where the display panel 100 includes a first metal layer M1, a second metal layer M2, and a third metal layer M3 stacked on top of each other, the control signal connection portion 641, the first clock signal connection portion 521, and the second clock signal connection portion 522 may be disposed on the first metal layer M1, and the first sub-connection portion 41 and the second sub-connection portion 42 may be disposed on the third metal layer M3.

[0095] In some alternative embodiments, as Figure 19 shown, the display panel 100 may further include a packaging structure 70 disposed between the display area AA and the bonding area NA1. Still taking the bus connection portion 40 including a first sub-connection portion 41 extending along the third direction Z and at least one second sub-connection portion 42 extending along the fourth direction W as an example, in a direction perpendicular to the plane of the display panel 100, the first fan-out routing portion 131 close to the second sub-connection portion 42 overlaps with the packaging structure 70.

[0096] It is understandable that the first fan-out routing portion 131 extends along the direction around the display area AA, and a plurality of first fan-out routing portions 131 are arranged in sequence in the direction away from the display area AA. The first fan-out routing portion 131 close to the second sub-connection portion 42 is the first fan-out routing portion 131 close to the display area AA in the direction pointing from the edge of the display panel to the display area AA. Therefore, it can be understood that in the direction pointing from the edge of the display panel to the display area AA, the first fan-out routing portion 131 close to the display area AA overlaps with the encapsulation structure 70.

[0097] For a better understanding of the location of the first fan-out routing portion 131 that overlaps with the encapsulation structure 70, taking the example that the fan-out routing 13 further includes a second fan-out routing portion 132 extending along the fourth direction W, a part of the second fan-out routing portion 132 is connected to the first fan-out routing portion 131. The first fan-out routing portion 131 close to the second sub-connection portion 42 is the first fan-out routing portion 131 connected to the second fan-out routing portion 132 close to the second sub-connection portion 42 in the third direction Z. Therefore, it can be understood that in the third direction Z, the first fan-out routing portion 131 connected to the second fan-out routing portion 132 close to the second sub-connection portion 42 overlaps with the encapsulation structure 70.

[0098] In the embodiment of the present application, relative to the side of the first fan-out routing portion 131 away from the display area AA with respect to the encapsulation structure 70, since the first fan-out routing portion 131 close to the second sub-connection portion 42 overlaps with the encapsulation structure 70, it is equivalent to moving the encapsulation structure 70 towards the display area AA, thereby reducing the size of the non-display area AA and achieving a narrow border.

[0099] In some alternative embodiments, with reference to Figure 19 and Figure 20 , the encapsulation structure 70 may include encapsulation glue 71. In the direction perpendicular to the plane of the display panel, the encapsulation glue 71 does not overlap with the display area AA. Exemplarily, the material of the encapsulation glue 71 may include glass frit. The display panel may further include an encapsulation cover plate 72 and a light-emitting layer 03, and the light-emitting layer 03 is disposed on the side of the driving device layer 02 facing away from the substrate 01. The encapsulation cover plate 72 is located on the side of the light-emitting layer 03 facing away from the substrate 01, and the encapsulation cover plate 72 extends to the non-display area NA. The encapsulation glue 71 may be connected between the encapsulation cover plate 72 and the driving device layer 02. Exemplarily, the encapsulation cover plate 72 may be a glass cover plate, and the light-emitting layer 03 may be a light-emitting layer including an organic light-emitting diode. In addition, for clearly showing the overall structure of the display panel, Figure 20 the first power bus, the second power bus, the scanning line, the data line, etc. are hidden and illustrated in

[0100] The encapsulation glue 71 is generally light-impermeable. In the embodiments of the present application, by setting the encapsulation glue 71 and the display area AA not to overlap, it is possible to prevent the encapsulation glue 71 from reducing the screen occupation ratio of the display panel.

[0101] Exemplarily, in the process of preparing the encapsulation glue 71, processes such as laser can be used. In order to prevent components such as transistors of the display panel from being burned during the preparation of the encapsulation glue 71, the encapsulation glue 71 can be arranged on the side of the gate driving circuit 50 away from the display area AA, and there is a certain distance between the encapsulation glue 71 and the gate driving circuit 50.

[0102] In the embodiments of the present application, since the bonding area NA1 is offset by a certain angle, and the second sub-connection part 42 connecting the first power bus 31 is no longer located at the center of the first sub-connection part 41 or is no longer symmetric about the center of the first sub-connection part 41, it results in more fan-out traces 13 on one side of the second sub-connection part 42 in the third direction Z than on the other side. Because the number of fan-out traces 13 on one side is relatively large, this side will occupy a wider non-display area. And there should also be a certain distance between the encapsulation glue 71 and the gate driving circuit 50. If the encapsulation glue 71 is still arranged on the side of the fan-out trace part 131 of the fan-out trace 13 away from the display area, it will cause the width of the non-display area to become larger, that is, it will cause the display panel to have a larger border. The embodiments of the present application are no longer limited to arranging the encapsulation glue 71 on the side of the fan-out trace part 131 of the fan-out trace 13 away from the display area, but arranging the encapsulation glue 71 to overlap with the fan-out trace part 131. Compared with arranging the encapsulation glue 71 on the side of the fan-out trace part 131 of the fan-out trace 13 away from the display area, it can be understood that the encapsulation glue 71 moves towards the display area, which is beneficial to achieving a narrow border. In some optional embodiments, with reference to Figure 21 and Figure 22 , the display panel includes an encapsulation film 73 covering the display area AA, and the encapsulation film 73 extends to the organic clearance area 80 of the non-display area NA. The encapsulation structure 70 includes a blocking part 74 arranged in the organic clearance area 80. In addition, the encapsulation structure further includes the above-mentioned encapsulation film. The blocking part and the encapsulation film jointly protect the display light-emitting device and prevent water and oxygen from invading.

[0103] Exemplarily, the display area AA of the display panel may include a light-emitting layer 03, the light-emitting layer 03 is disposed on a side of the driving device layer 02 facing away from the substrate 01, and the encapsulation film 73 is located on a side of the light-emitting layer 03 facing away from the substrate 01. The encapsulation film 73 may include multiple stacked inorganic layers and organic layers to prevent water and oxygen from invading the light-emitting layer 03. In the drawings of the present application, the encapsulation film 73 is exemplified as including a first inorganic layer 731, an organic layer 732, and a second inorganic layer 733 stacked in sequence in a direction away from the substrate 01. Exemplarily, the inorganic layer of the encapsulation film 73 may be prepared by chemical vapor deposition (CVD), and the organic layer of the encapsulation film 73 may be prepared by ink jet printing (IJP). Since the organic layer material flows during the preparation of the organic layer, in the embodiments of the present application, by providing a blocking portion 74, the organic layer material can be prevented from flowing out of the display panel.

[0104] It can be understood that the blocking portion 74 is a retaining wall surrounding the display area AA. In order to better prevent the organic layer material from flowing out of the display panel, two or more circles of blocking portions 74 may be provided. In the embodiments of the present application, two circles of blocking portions 74 are schematically shown, which is not intended to limit the present application.

[0105] Exemplarily, the first fan-out routing portion 131 close to the second sub-connection portion 42 may be located in the organic clearance area 80. Similarly, the first fan-out routing portion 131 extends along a direction surrounding the display area AA, and multiple first fan-out routing portions 131 are arranged in sequence in a direction away from the display area AA. The first fan-out routing portion 131 close to the second sub-connection portion 42 is the first fan-out routing portion 131 close to the display area AA in a direction from the edge of the display panel to the display area AA. Therefore, it can be understood that in a direction from the edge of the display panel to the display area AA, the first fan-out routing portion 131 close to the display area AA is located in the organic clearance area 80.

[0106] To better understand the location of the first fan-out routing portion 131 located in the organic clearance area 80, taking the fan-out routing 13 further including a second fan-out routing portion 132 extending along the fourth direction W as an example, a part of the second fan-out routing portion 132 is connected to the first fan-out routing portion 131. The first fan-out routing portion 131 close to the second sub-connection portion 42 is the first fan-out routing portion 131 connected to the second fan-out routing portion 132 close to the second sub-connection portion 42 in the third direction Z. Therefore, it can be understood that in the third direction Z, the first fan-out routing portion 131 connected to the second fan-out routing portion 132 close to the second sub-connection portion 42 is located in the organic clearance area 80.

[0107] Relative to the organic clearance area 80, on the side of the first fan-out wiring portion 131 away from the display area AA. In the embodiment of the present application, since the first fan-out wiring portion 131 close to the second sub-connection portion 42 is located in the organic clearance area 80, that is to say, the first fan-out wiring portion 131 close to the second sub-connection portion 42 overlaps with the organic clearance area, which is equivalent to moving the organic clearance area 80 towards the display area AA, thereby reducing the size of the non-display area AA and achieving a narrow border. Since the organic clearance area 80 is moved towards the display area AA, therefore, the blocking portion 74 provided in the organic clearance area 80 is also equivalent to moving towards the display area AA, thereby further reducing the size of the non-display area NA and achieving a narrow border.

[0108] Exemplarily, the organic clearance area 80 can be provided on the side of the gate driving circuit 50 away from the display area AA, and there is a certain distance between the organic clearance area 80 and the gate driving circuit 50.

[0109] Similarly, in the embodiment of the present application, it is biased at a certain angle, and the second sub-connection portion 42 connected to the first power bus 31 is no longer located at the center of the first sub-connection portion 41 or is no longer symmetric about the center of the first sub-connection portion 41, resulting in the fan-out wiring 13 on one side of the second sub-connection portion 42 in the third direction Z being more than that on the other side. Since the number of fan-out wirings 13 on one side is larger, this side will occupy a wider non-display area. And there is still a certain distance between the organic clearance area 80 and the gate driving circuit 50. If the organic clearance area 80 is still provided on the side of the fan-out wiring portion 131 of the fan-out wiring 13 away from the display area, it will cause the width of the non-display area to become larger, that is, the display panel has a larger border. In the embodiment of the present application, it is no longer limited to setting the organic clearance area 80 on the side of the fan-out wiring portion 131 of the fan-out wiring 13 away from the display area, but setting the organic clearance area 80 to overlap with the fan-out wiring portion 131. Relative to setting the organic clearance area 80 on the side of the fan-out wiring portion 131 of the fan-out wiring 13 away from the display area, it can be understood that the organic clearance area 80 is moved towards the display area, which is beneficial to achieving a narrow border.

[0110] Exemplarily, Figure 22Also shown is a planarization layer 04, which is located between the light-emitting layer 03 and the driving device layer 02. The light-emitting layer 03 may include a pixel definition layer 031 and a light-emitting element. The light-emitting element may include a stacked first electrode 032, a light-emitting layer 033, and a second electrode 034. The pixel definition layer 031 has an opening that exposes the first electrode 032 of the light-emitting element. The light-emitting layer 033 is disposed within the opening of the pixel definition layer 031. The second electrode 033 may be a planar electrode. In addition, the display panel may further include support pillars 05, which do not overlap with the opening of the pixel definition layer 031 and are located on the side of the pixel definition layer 031 facing away from the substrate 01. The shift register unit 501 of the gate driving circuit 50 may be disposed within the driving device layer 02.

[0111] It should be noted that, without conflict, the various embodiments provided in the present application may be combined with each other.

[0112] The present application also provides a display device, including the display panel provided in the present application. Please refer to Figure 23 , Figure 23 which is a schematic structural diagram of a display device provided by an embodiment of the present application. Figure 23 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of the present application. Figure 23 The embodiment only takes a wearable product as an example to illustrate the display device 1000. It can be understood that the display device provided by the embodiments of the present application may be other display devices with a display function such as a mobile phone, a computer, a television, a vehicle-mounted display device, etc. The present application does not make specific limitations in this regard. The display device provided by the embodiments of the present application has the beneficial effects of the display panel provided by the embodiments of the present application. For specific descriptions of the display panel, reference may be specifically made to the above embodiments. Details will not be repeated in this embodiment.

[0113] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, Comprising: A display area and a non-display area surrounding the display area; The display area includes a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction, wherein the first direction and the second direction intersect; The non-display area includes a bonding area, the bonding area includes a plurality of pads arranged in a third direction, a direction perpendicular to the third direction is a fourth direction, and an angle formed by the second direction and the fourth direction is θ, where 0° < θ < 90°; The non-display area includes at least a part of a first power bus surrounding the display area, the pad includes at least one first conductive pad (PVDD), the first power bus includes a first connection node, and the first power bus is connected to the first conductive pad at the first connection node through a bus connection portion; The non-display area further includes at least a part of a second power bus surrounding the display area, the second power bus is located between the first power bus and the display area, and the second power bus is electrically connected to the first power bus; The display area includes voltage signal transmission lines extending in the second direction, the second power bus is electrically connected to at least a part of the voltage signal transmission lines, and transmits voltage signals to the display area; The first power bus further includes a second connection node, and the first power bus is electrically connected to the second power bus at the second connection node, wherein, The first connection node and the second connection node are different, and the second connection node is located on a side of the first power bus closer to the bonding area along the second direction.

2. The display panel according to claim 1, wherein 0° < θ ≤ 45°.

3. The display panel according to claim 1, characterized in that, The first power bus is recessed in a direction towards the display area at the second connection node.

4. The display panel according to claim 1, wherein The bus connection portion includes a first sub-connection portion extending in the third direction and at least one second sub-connection portion extending in the fourth direction; Both ends of the first sub-connection portion are respectively connected to the first conductive pad; One end of the second sub-connection portion is connected to a third connection node between both ends of the first sub-connection portion, and the other end of the second sub-connection portion is connected to the first connection node.

5. The display panel according to claim 4, wherein The first conductive pads connected to both ends of the first sub-connection portion include a first sub-conductive pad and a second sub-conductive pad. Along the third direction, the distance from the first sub-conductive pad to the second sub-connection portion is greater than the distance from the second sub-conductive pad to the second sub-connection portion.

6. The display panel according to claim 1, wherein, The non-display area further includes a gate driving circuit and a clock signal line arranged on both sides of the display panel. The clock signal line is arranged on a side of the first power bus closer to the display area. The clock signal line includes a first type of clock signal line and a second type of clock signal line respectively driving the gate driving circuits on both sides; the bus connection portion includes at least one second sub-connection portion extending in the fourth direction; The pad further includes a plurality of second conductive pads, the clock signal line is electrically connected to the plurality of second conductive pads through a clock signal connection line, the clock signal connection line includes a first clock signal connection portion extending along the fourth direction, and the first clock signal connection portion is disposed on both sides of the second sub-connection portion.

7. The display panel according to claim 6, wherein At least a part of the first clock signal connection portion is electrically connected to the second conductive pad through a second clock signal connection portion extending along the third direction, wherein, the second clock signal connection portion is disposed on a side of the first clock signal connection portion away from the second sub-connection portion.

8. The display panel according to claim 6, wherein At least a part of the first clock signal line is connected to the clock signal connection line through a first jumper wire, wherein, the first jumper wire and the first power bus overlap and are disposed on different layers, and the clock signal connection line is disposed on a side of the first power bus away from the display area.

9. The display panel according to claim 1, wherein The non-display area further includes a multiplexing unit and a plurality of fan-out traces, and the pad includes a plurality of third conductive pads; The input end of the multiplexing unit is connected to the third conductive pad through the fan-out trace, and the output end of the multiplexing unit is connected to the data line; In the third direction, the third conductive pad is disposed between the two first conductive pads.

10. The display panel according to claim 9, wherein The bus connection portion includes a first sub-connection portion extending along the third direction and at least one second sub-connection portion extending along the fourth direction; In the third direction, the number of the third conductive pads on one side of the second sub-connection portion is greater than the number of the third conductive pads on the other side of the second sub-connection portion.

11. The display panel according to claim 9, wherein The fan-out trace includes a first fan-out trace portion, and the first fan-out trace portion and the first power bus do not overlap.

12. The display panel according to claim 9, wherein, The display panel further includes a packaging structure disposed between the display area and the bonding area; The bus connection portion includes a first sub-connection portion extending along the third direction and at least one second sub-connection portion extending along the fourth direction; In a direction perpendicular to the plane of the display panel, the first fan-out trace portion close to the second sub-connection portion and the packaging structure overlap.

13. The display panel according to claim 12, wherein The packaging structure includes a packaging glue, and the packaging glue and the display area do not overlap.

14. The display panel according to claim 12, wherein The display panel includes a packaging film, the packaging film covers the display area and extends to the organic clearance area of the non-display area, and the packaging structure includes a blocking portion disposed in the organic clearance area.

15. The display panel according to claim 9, wherein The pad includes a plurality of fourth conductive pads, the multiplexing unit includes a plurality of switches and control signal lines for controlling the switches, the control signal lines are wire-changed at the second connection node and are connected to the fourth conductive pads through control signal connection lines; wherein, the control signal lines are disposed on a side of the first power bus close to the display area, and the control signal connection lines are disposed on a side of the first power bus away from the display area.

16. The display panel according to claim 1, wherein The shape of the display area includes a circle.

17. A display device, characterized in that, A display panel including any one of claims 1 to 16.

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