Fabrication of a solar cell emitter region having separate P-type and N-type structures and including point diffusion

Abstract

Methods of making a solar cell emitter region having a distinct P-type and N-type architecture and including a point-like diffusion, and the resulting solar cell are described herein. In one example, the solar cell includes a substrate having a light receiving surface and a back surface. A first polysilicon emitter region of a first conductivity type is disposed on a first thin dielectric layer, the first thin dielectric layer being disposed on the back surface of the substrate. A second polysilicon emitter region of a second different conductivity type is disposed on a second thin dielectric layer, the second thin dielectric layer being disposed in a plurality of non-continuous grooves on the back surface of the substrate.

Description

[0001] This application is a divisional application of a Chinese patent application filed on September 15, 2015, with application number 2015800565777 and invention name “Manufacturing of a solar cell emitter region having separate P-type and N-type structures and comprising point diffusion”. Technical Field

[0002] Embodiments of the present disclosure belong to the field of renewable energy, and in particular, to methods of manufacturing a solar cell emitter region having differentiated P-type and N-type architectures and including point-like diffusions, and the resulting solar cell. Background Art

[0003] Photovoltaic cells (often referred to as solar cells) are well-known devices for converting solar radiation directly into electrical energy. Generally speaking, solar cells are manufactured on semiconductor wafers or substrates using semiconductor processing techniques to form pn junctions near the surface of the substrate. Solar radiation that impinges on the substrate surface and enters the substrate forms electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby generating a voltage difference between the doped regions. The doped regions are connected to conductive regions on the solar cell to direct current from the cell to an external circuit coupled thereto.

[0004] Efficiency is an important characteristic of solar cells because it is directly related to the ability of the solar cell to generate electricity. Likewise, the efficiency of preparing solar cells is directly related to the cost-effectiveness of such solar cells. Therefore, techniques for improving the efficiency of solar cells or techniques for improving the efficiency of manufacturing solar cells are generally needed. Some embodiments of the present disclosure allow for improving the manufacturing efficiency of solar cells by providing new processes for manufacturing solar cell structures. Some embodiments of the present disclosure allow for improving the efficiency of solar cells by providing new solar cell structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1 to 6 sectional views and plan views of various stages in the manufacture of a solar cell according to an embodiment of the present disclosure are shown, wherein:

[0006] Figure 1 shows a cross-sectional view of a stage in the manufacture of a solar cell involving forming a first silicon layer of a first conductivity type on a first thin dielectric layer formed on a back surface of a substrate;

[0007] Figure 2 Shows Figure 1 A cross-sectional view and a corresponding plan view of a structure of wherein the structure is subjected to patterning of an insulating layer and a first silicon layer to form a first silicon region of a first conductivity type having an insulating cap thereon;

[0008] Figure 3 Shows Figure 2 a cross-sectional view of a structure wherein the structure is groove surface texturing to form a textured recess or groove having a textured surface in a substrate;

[0009] Figure 4 The second and third thin dielectric layers and the second silicon layer are formed. Figure 3 A cross-sectional view and a corresponding plan view of the structure;

[0010] Figure 5 Shows Figure 4 a cross-sectional view and a corresponding plan view of a structure of the present invention, wherein the structure is formed by patterning a second silicon layer to form isolated second silicon regions and forming contact openings in a plurality of regions of the second silicon layer; and

[0011] Figure 6 shows the formation of multiple conductive contacts Figure 5 A cross-sectional view of the structure.

[0012] Figure 7 is a flowchart according to an embodiment of the present disclosure, which lists Figures 1 to 6 The corresponding operations are in the method for manufacturing a solar cell.

[0013] Fig. 8A and Figure 8B Cross-sectional views showing various stages in the manufacture of another solar cell according to another embodiment of the present disclosure are shown.

[0014] Fig. 9 is a flowchart listing operations in another method of manufacturing a solar cell according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "used as an example, instance, or illustration". Any implementation described herein as exemplary is not necessarily understood to be preferred or advantageous over other implementations. In addition, it is not intended to be bound by any express or implied theory presented in the aforementioned technical field, background technology, summary of the invention, or the following detailed description.

[0016] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0017] Terminology. The following paragraphs provide definitions and / or context for terms found in this disclosure, including the appended claims:

[0018] "Comprising". This term is open ended. As used in the appended claims, this term does not exclude other structures or steps.

[0019] "Configured to". Various units or components may be described or stated as being "configured to" perform one or more tasks. In such contexts, "configured to" is used to imply structure by indicating that the unit / component includes structure to perform one or more of those tasks during operation. Thus, even when the specified unit / component is not currently in operation (e.g., not turned on / activated), the unit / component may be said to be configured to perform a task. Reciting that a unit / circuit / component is "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, with respect to that unit / component.

[0020] "First", "second", etc. As used herein, these terms serve as labels for the nouns that follow them, and do not imply any type of order (e.g., spatial, temporal, logical, etc.). For example, referring to a "first" solar cell does not necessarily imply that the solar cell is the first solar cell in a sequence; rather, the term "first" is used to distinguish the solar cell from another solar cell (e.g., a "second" solar cell).

[0021] "Coupled" - The following description refers to elements or nodes or structural features being "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element / node / feature is directly or indirectly connected to (or directly or indirectly communicates with) another element / node / feature, and not necessarily mechanically.

[0022] "Prevent" - As used herein, prevent is used to describe reducing or minimizing an effect. When a component or feature is described as preventing an action, movement, or condition, it may completely prevent a certain result or consequence or future state. Additionally, "prevent" may also refer to reducing or minimizing a certain consequence, manifestation, and / or effect that may occur. Thus, when a component, element, or feature is said to prevent a result or state, it does not necessarily completely prevent or eliminate that result or state.

[0023] In addition, certain terms are used in the following description for reference purposes only and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," or "below" refer to directions in the accompanying drawings for which reference is provided. Terms such as "front," "back," "rear," "side," "outside," and "inside" describe the orientation and / or position of certain portions of a component within a consistent but arbitrary reference system, which orientation and / or position can be clearly understood by reference to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0024] Described herein are methods of manufacturing a solar cell emitter region having separate P-type and N-type architectures and containing point diffusion, and the resulting solar cell. In the following description, many specific details are given, such as specific process flow operations, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be implemented without these specific details. In other cases, well-known manufacturing techniques, such as lithography and patterning techniques, are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the figures are exemplary displays and are not necessarily drawn to scale.

[0025] Solar cells are disclosed herein. In one embodiment, the solar cell includes a substrate having a light receiving surface and a back surface. A first polysilicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polysilicon emitter region of a second different conductivity type is disposed on a second thin dielectric layer disposed in a plurality of non-continuous grooves on the back surface of the substrate.

[0026] Also disclosed herein is a method for manufacturing a solar cell. In one embodiment, a method for manufacturing a solar cell involves forming a first silicon layer of a first conductivity type on a first thin dielectric layer formed on a back surface of a substrate to provide a first emitter region of the solar cell. The substrate has a light receiving surface and a back surface. The method also includes forming an insulating layer on the first silicon layer. The method also includes forming a plurality of openings in the insulating layer and the first silicon layer, and forming a corresponding plurality of non-continuous grooves in the back surface of the substrate. The method also includes forming a second silicon layer of a second different conductivity type on a second thin dielectric layer formed in the plurality of non-continuous grooves to provide a second emitter region of the solar cell.

[0027] In another embodiment, a method for manufacturing alternating N-type emitter regions and P-type emitter regions of a solar cell involves forming a P-type silicon layer on a first thin dielectric layer formed on the back surface of an N-type single crystal silicon substrate. The method also involves forming an insulating layer on the P-type silicon layer. The method also involves patterning the insulating layer and the P-type silicon layer by laser ablation to form a P-type silicon region having an insulating cap thereon and exposing multiple regions of the N-type single crystal silicon substrate, each of the multiple regions of the N-type single crystal silicon substrate having multiple non-continuous grooves formed in the N-type single crystal silicon substrate. The method also involves forming a second thin dielectric layer on the exposed side of the P-type silicon region. The method also involves forming an N-type silicon layer on the second thin dielectric layer, on the insulating cap of the P-type silicon region, and on a third thin dielectric layer, wherein the third thin dielectric layer is formed in each of the multiple non-continuous grooves in each of the multiple regions of the N-type single crystal silicon substrate. The method also involves patterning the N-type silicon layer to form isolated N-type silicon regions, and forming contact openings in regions of the N-type silicon layer above the insulating cap of the P-type silicon regions, each isolated N-type silicon region being electrically coupled to a corresponding one of a plurality of regions of the N-type single crystal silicon substrate. The method also involves forming a plurality of conductive contacts, each conductive contact being electrically connected to one of the P-type silicon regions or one of the isolated N-type silicon regions.

[0028] One or more embodiments described herein relate to the fabrication of solar cells with point diffusions. In one embodiment, a point diffusion design with separate P-type and N-type architectures is implemented to enable the fabrication of laser patterned emitters with more stable and lower reverse bias breakdown. The point diffusions can be fabricated using laser ablation, as described in more detail below. However, in other embodiments, non-laser island diffusion formation can also be achieved, such as by using a printed etchant, or by a mask and etch method.

[0029] To illustrate the background, using lasers to pattern the emitter in a traditional solar cell structure can be challenging because for a linear emitter, large areas of material need to be removed. When using a diode pumped solid-state (DPSS) laser, the removal can be difficult to perform and can cause challenges in unit productivity per hour (UPH). Some designs also rely on edge vertical sidewall junctions as a path for reverse bias breakdown, so they need to be very uniform. In the case of overlapping points, it can be difficult to form such edge vertical sidewall junctions using a "cleaning" laser process, as is the case for pulsed lasers that form continuous emitters. The reverse breakdown voltage is also proportional to the length of the butt junction used as the breakdown region.

[0030] To address one or more of the above issues, in one embodiment, a dot design is provided, in which the spot size can be easily controlled and a high density of dots can be placed, resulting in improved device breakdown performance. In a specific embodiment, forming an array of dots as an emitter can achieve faster laser processing, more uniform ablation (e.g., non-overlapping dots) to obtain better sidewalls, use lower energy (e.g., opening the UV laser opening can make the sidewall uniformity better), and can improve the breakdown voltage. Other benefits of using a point emitter design with separate P-type and N-type architectures may include one or more of the following: (1) increasing the junction area to achieve lower breakdown voltage; (2) eliminating the need for overlap to form a continuous emitter; (3) improving UPH problems; (4) improving edge overlap and control problems; (5) reducing island contact problems by using blanket N-type amorphous silicon (na-Si) deposition; (6) enabling the formation of single-row, double-row, triple-row, etc. discrete N-type regions ('N-islands') of the substrate; (7) enabling the size of the island to be adjusted; and / or (8) enabling the use of UV or CO2-based laser sources to remove the oxide cleanly and produce clean sidewalls without severely damaging the emitter.

[0031] In a first exemplary process flow, Figures 1 to 6 Cross-sectional views are shown of various stages in the fabrication of a solar cell according to an embodiment of the present disclosure. Figure 7 is a flowchart 700 according to an embodiment of the present disclosure, which lists Figures 1 to 6 The corresponding operations are in the method for manufacturing a solar cell.

[0032] See also Figure 1 The method of fabricating alternating N-type and P-type emitter regions of a solar cell, corresponding to operation 702 of flowchart 700 , involves forming a first silicon layer 106 of a first conductivity type on a first thin dielectric layer 104 formed on a back surface of a substrate 102 .

[0033] In one embodiment, substrate 102 is a single crystal silicon substrate, such as a bulk single crystal N-type doped silicon substrate. However, it should be understood that substrate 102 can be a layer disposed on the entire solar cell substrate, such as a polysilicon layer. In one embodiment, first thin dielectric layer 104 is a thin oxide layer, such as a tunnel dielectric silicon oxide layer having a thickness of about 2 nanometers or less.

[0034] In one embodiment, the first silicon layer 106 is a polycrystalline silicon layer, which is doped to have a first conductivity type by in-situ doping, post-deposition implantation, or a combination thereof. In another embodiment, the first silicon layer 106 is an amorphous silicon layer such as a hydrogenated silicon layer represented by a-Si:H, which is implanted with a dopant of the first conductivity type after the amorphous silicon layer is deposited. In one such embodiment, the first silicon layer 106 is then annealed (at least at some subsequent stage of the process flow) to ultimately form a polycrystalline silicon layer. In one embodiment, for either the polycrystalline silicon layer or the amorphous silicon layer, if a post-deposition implantation is performed, the implantation is performed by using an ion beam implantation or a plasma immersion implantation. In one such embodiment, the implantation is performed using a shielding mask. In a specific embodiment, the first conductivity type is P-type (e.g., formed using boron impurity atoms).

[0035] See again Figure 1 And now referring to corresponding operation 704 of Flowchart 700, an insulating layer 108 is formed on the first silicon layer 106. In one embodiment, the insulating layer 108 comprises silicon dioxide.

[0036] See also Figure 2 At operation 706 of flowchart 700, insulating layer 108 and first silicon layer 106 are patterned to form first silicon region 110 of the first conductivity type with insulating cap 112 thereon. In one embodiment, insulating layer 108 and first silicon layer 106 are patterned using a laser ablation process (e.g., direct write). Where applicable, in one embodiment, first thin dielectric layer 104 is also patterned in this process, such as Figure 2 It should be understood that Figure 2 The cross-sectional view is along Figure 2 The plane diagram is intercepted along the a-a' axis.

[0037] In one embodiment, Figure 2 The laser ablation process exposes a plurality of regions 109 of the N-type single crystal silicon substrate 102. Each of the plurality of regions 109 of the N-type single crystal silicon substrate 102 can be regarded as a plurality of non-continuous trenches (visible in the cross-sectional view) having intervals (intervals visible in the plan view) between the trenches formed in the N-type single crystal silicon substrate 102. Figure 2 The cross-sectional view of FIG. 1 shows that the trench has a depth 111 or thickness selection into the substrate. In one such embodiment, each trench in the plurality of non-continuous trenches is formed at a non-zero depth 111 of less than about 10 microns into the substrate 102 when laser ablated.

[0038] As described above, a plurality of openings and a corresponding plurality of non-continuous grooves can be formed by applying a laser ablation process. In one embodiment, a laser ablation process is used to provide a width (e.g., a maximum diameter) in the range of about 30 microns to 60 microns for each of the plurality of non-continuous grooves. In one such embodiment, the sequentially arranged non-continuous grooves in the plurality of non-continuous grooves are formed to be separated by a distance approximately in the range of 50 microns to 300 microns. A distance much less than 50 microns may result in the possibility of groove overlap, which may be undesirable, as described above. On the other hand, a distance much greater than 300 microns may result in an increase in the contact resistance of subsequently formed contacts and connect several grooves. In one embodiment, the laser ablation process involves the use of a laser beam having a nearly Gaussian profile or having a nearly flat-top profile.

[0039] See also Figure 3 Alternatively, the surface of the groove may be textured to form a textured recess 114 or groove having a textured surface 116 in the substrate 102. In the same or similar process, the light receiving surface 101 of the substrate 102 may also be textured, such as Figure 3 As shown. In one embodiment, a hydroxide-based wet etchant is used to form at least a portion of the recess 114 and / or to texture the exposed portion of the substrate 102. The textured surface can be a surface with a regular or irregular shape, which is used to scatter incident light, reduce the amount of light reflected away from the light receiving surface and / or exposed surface of the solar cell. However, it should be understood that the texturing of the back surface and even the recess formation can be omitted from the workflow. It should also be understood that, if implemented, the texturing can cause the depth of the groove to continue to increase from the depth initially formed.

[0040] See also Figure 4 At operation 708 of flowchart 700, a second thin dielectric layer 118 is formed on the exposed side of the first silicon region. In one embodiment, the second thin dielectric layer 118 is formed in an oxidation process and is a thin oxide layer, such as a tunnel dielectric silicon oxide layer having a thickness of about 2 nanometers or less. In another embodiment, the second thin dielectric layer 118 is formed in a deposition process and is a thin silicon nitride layer or a silicon oxynitride layer. It should be understood that Figure 4 The cross-sectional view is along Figure 4 The plane diagram is intercepted along the b-b' axis.

[0041] See again Figure 4And now referring to the corresponding operation 710 of the flowchart 700, a second silicon layer 120 of a second different conductivity type is formed on the third thin dielectric layer 122 formed on the exposed portion of the back surface of the substrate 102 (e.g., formed in each of the plurality of non-continuous trenches in each of the plurality of regions of the N-type single crystal silicon substrate 102), and on the second thin dielectric layer 118 and the insulating cap 112 of the first silicon region 110. As seen in the cross-sectional view and the plan view, the second silicon layer 120 (from a top-down perspective) covers the trench region.

[0042] See again Figure 4 In the same or similar process operation, a corresponding thin dielectric layer 122' of the second conductivity type and a second silicon layer 120' may also be formed on the light receiving surface 101 of the substrate 102, and also as shown in FIG. Figure 4 In addition, although not shown, an ARC layer may be formed on the corresponding second silicon layer 120'.

[0043] In one embodiment, the third thin dielectric layer 122 is formed in the oxidation process and is a thin oxide layer, such as a tunnel dielectric silicon oxide layer having a thickness of about 2 nanometers or less. In one embodiment, the second silicon layer 120 is a polycrystalline silicon layer, which is doped to have a second conductivity type by in-situ doping, post-deposition implantation, or a combination thereof. In another embodiment, the second silicon layer 120 is an amorphous silicon layer such as a hydrogenated silicon layer represented by a-Si:H, which is implanted with a dopant of the second conductivity type after the amorphous silicon layer is deposited. In one such embodiment, the second silicon layer 120 is then annealed (at least at some subsequent stage of the process flow) to finally form a polycrystalline silicon layer. In one embodiment, for either the polycrystalline silicon layer or the amorphous silicon layer, if a post-deposition implantation is performed, the implantation is performed by using an ion beam implantation or a plasma immersion implantation. In one such embodiment, the implantation is performed using a shadow mask. In a specific embodiment, the second conductivity type is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms).

[0044] See also Figure 5 At operation 712 of flowchart 700, the second silicon layer 120 is patterned to form isolated second silicon regions 124 of a second conductivity type, and contact openings 126 are formed in the area of ​​the second silicon layer 120 above the insulating cap 112 of the first silicon region 110. In one embodiment, each isolated N-type silicon region is electrically coupled to a corresponding one (or more) of the plurality of regions 109 of the N-type single crystal silicon substrate 102. In one embodiment, the discrete regions of silicon may remain as an artifact of the patterning process. In one embodiment, the second silicon layer 120 is patterned using a laser ablation process. It should be understood that Figure 5 The cross-sectional view is along Figure 5 The plane diagram is intercepted along the c-c' axis.

[0045] See again Figure 5 , the insulating cap 112 is patterned to pass through the contact opening 126 to expose a portion of the first silicon region 110. In one embodiment, the insulating cap 112 is patterned using a laser ablation process. For example, in one embodiment, the second silicon layer 120 is patterned using a first laser pass, including forming the contact opening 126. The insulating cap 112 is patterned using a second laser pass in the same position as the contact opening 126. Figure 5 As can be seen from the plan view of FIG. 1 , in one embodiment, from a top-down perspective, a single isolation region (eg, a single isolated N-type silicon region) covers a strip of multiple regions 109 (in FIG. 1 ). Figure 5 A strip of three openings per single isolation region is shown in FIG.

[0046] See also Figure 6 and corresponding operation 714 of flowchart 700, forming a plurality of conductive contacts, each conductive contact being electrically connected to one of the P-type silicon regions or one of the isolated N-type silicon regions. In an exemplary embodiment, a metal seed layer 128 is formed on the exposed portion of the first silicon region 110 and on the isolated second silicon region 124. A metal layer 130 is then electroplated on the metal seed layer to form a first conductive contact structure 132 of the first silicon region 110 and a second conductive contact structure 134 of the isolated second silicon region 124, respectively. In one embodiment, the metal seed layer 128 is an aluminum-based metal seed layer, and the metal layer 130 is a copper layer. In one embodiment, a mask is first formed to expose only the exposed portions of the first silicon region 110 and the isolated second silicon region 124 so as to guide the formation of the metal seed layer 128 to a restricted position.

[0047] Thus, one or more embodiments described herein relate to forming P+ and N+ polysilicon emitter regions of a solar cell, wherein the respective structures of the P+ and N+ polysilicon emitter regions are different from each other. Such methods may be implemented to simplify the solar cell manufacturing process. Furthermore, the resulting structure may provide an associated lower breakdown voltage and lower power loss compared to other solar cell architectures.

[0048] See again Figure 6 In one embodiment, the manufactured solar cell includes a substrate 102 having a light receiving surface 101 and a corresponding back surface. A first polysilicon emitter region of a first conductivity type is disposed on a first thin dielectric layer 104, which is disposed on the back surface of the substrate 102. A second polysilicon emitter region of a second different conductivity type is disposed on a third thin dielectric layer 122, which is disposed in a plurality of non-continuous grooves on the back surface of the substrate 102 (in Figure 6In one embodiment, the substrate 102 is an N-type single crystal silicon substrate, the first conductivity type is P-type, and the second conductivity type is N-type. In one embodiment, the solar cell is a back contact solar cell, such as Figure 6 shown.

[0049] In one embodiment, each of the plurality of non-continuous grooves has a width in the range of about 30 microns to 60 microns, such as in combination with Figure 2 In one embodiment, the sequentially arranged non-continuous grooves in the plurality of non-continuous grooves are spaced apart by a distance in the range of about 50 microns to 300 microns, and further as in combination Figure 2 In one embodiment, each of the plurality of non-continuous grooves has a depth in the range of about 0.5 microns to 10 microns from the back surface into the substrate 102. The final groove depth can be formed by laser ablation, texturing process, or both. In one embodiment, each non-continuous groove has an approximately circular shape, such as Figure 2 , Figure 4 and Figure 5 As shown in the plan view. Figure 6 As shown, each non-continuous groove has a textured surface.

[0050] See again Figure 6 In one embodiment, the solar cell further comprises a third thin dielectric layer 122 disposed laterally directly between the first polysilicon emitter region and the second polysilicon emitter region. In one embodiment, the solar cell further comprises a first conductive contact structure 132 electrically connected to the first polysilicon emitter region, and a second conductive contact structure 134 electrically connected to the second polysilicon emitter region. In one embodiment, the solar cell further comprises an insulating cap 112 disposed on the first polysilicon emitter region. The first conductive contact structure 132 is disposed through the insulating cap 112. In one such embodiment, a portion of the second polysilicon emitter region overlaps the insulating cap 112, but is separated from the first conductive contact structure 132, as shown in FIG. Figure 6 In another embodiment, the second conductivity type polysilicon region 125 is disposed on the insulating cap 112, and the first conductive contact structure 132 is disposed through the second conductivity type polysilicon region 125 and through the insulating cap 112, as shown in FIG. Figure 6 shown.

[0051] In another aspect, one or more embodiments described herein relate to silicide formation for solar cell manufacturing. The silicide material may be incorporated into a final solar cell structure, such as a back contact solar cell structure or a front contact solar cell structure. Using the silicide material for metallization of the polysilicon emitter region of a solar cell may provide a simpler metallization process for such solar cells. For example, as described in more detail below, the use of silicide technology effectively removes masking operations from the metal seed layer process for contact formation. In addition, since the silicide process is a self-aligned process, alignment issues may be reduced.

[0052] In a second exemplary process flow, FIG. 8A to FIG. 8B A cross-sectional view of various stages in the manufacture of another solar cell according to another embodiment of the present disclosure is shown. Figure 5 The structure is moved to Fig. 8A structure.

[0053] See also Fig. 8A , before patterning the second silicon layer 120 and the insulating cap 112 (such as combining Figure 5 After the above), a metal silicide layer 828 is formed by the exposed surface of the patterned second silicon layer and by the exposed portion of the first silicon region 110. In one embodiment, the metal silicide layer is formed by: Figure 5 A blanket metal layer is formed over the entire structure, and the blanket metal layer is heated to react with the exposed silicon and form a metal silicide. The unreacted portion of the blanket metal layer is then removed, for example, using a wet chemical cleaning process that is optional for the formed silicide material. In one embodiment, the metal silicide layer 828 comprises a material such as, but not limited to, titanium silicide (TiSi2), cobalt silicide (CoSi2), tungsten silicide (WSi2), or nickel silicide (NiSi or NiSi2). In one embodiment, the silicide is formed using a rapid thermal processing (RTP) anneal. In this embodiment, dopants in the silicon layer of the emitter region are activated in the same RTP process. In one embodiment, the RTP process is performed in an oxygen-free or low-oxygen epoxy to reduce oxidation of the silicide metal. However, in another embodiment, the silicide process temperature is lower than the temperature of a separate anneal for dopant activation.

[0054] See also Figure 8B , a metal layer 830 is electroplated on the metal silicide layer to form a conductive contact 832 of the first silicon region 110 and a conductive contact 834 isolating the second silicon region 124, respectively. In one embodiment, the metal layer 830 is a copper layer. In one embodiment, the metal silicide layer is chemically activated before the metal is electroplated on the layer. In another embodiment, the contact formation is completed using an aluminum (Al) foil welding process instead of electroplating the metal.

[0055] It should be understood that compared to combining Figure 6 The contact formation, combined Fig. 8A and Figure 8B The described silicidation process for contact formation uses one less mask. Specifically, there is no need to guide the seed layer through a mask during the silicidation process, because the silicide will only form on areas of exposed silicon, which have been patterned. Therefore, in one embodiment, the silicidation process is a self-aligned process, which can be implemented to alleviate alignment issues and potentially reduce the pitch achievable for cell contact manufacturing.

[0056] Perhaps more generally, combined Fig. 9 A process including the above-mentioned two process flows is described. Fig. 9 FIG. 9 is a flowchart 900 that lists operations in another method of manufacturing a solar cell according to an embodiment of the present disclosure. Fig. 9 At operation 902 of flowchart 900 of the method of manufacturing a solar cell, a first silicon layer of a first conductivity type is formed on a first thin dielectric layer formed on a back surface of a substrate. In one embodiment, the process operation provides a first emitter region of a solar cell. Fig. 9 At operation 904 of flowchart 900, the method further involves forming an insulating layer on the first silicon layer. Fig. 9 At operation 906 of flowchart 900, the method further involves forming a plurality of openings in the insulating layer and the first silicon layer, and forming a corresponding plurality of non-continuous trenches in the back surface of the substrate. Fig. 9 At operation 908 of flowchart 900, the method further involves forming a second silicon layer of a second different conductivity type on the second thin dielectric layer formed in the plurality of non-continuous trenches. In one embodiment, the process operations provide a second emitter region of the solar cell.

[0057] Although certain materials are specifically described with reference to the above embodiments, in other such embodiments, other materials may be easily substituted for some of the materials, and these embodiments remain within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, a substrate of a different material, such as a substrate of a III-V material, may be used in place of a silicon substrate. In addition, although primarily reference is made to a back-contact solar cell arrangement, it should be understood that the methods described herein may also be applied to front-contact electrode solar cells. In other embodiments, the above methods may be applicable to the manufacture of things other than solar cells. For example, the manufacture of light emitting diodes (LEDs) may benefit from the methods described herein.

[0058] Additionally, in one embodiment, a cluster plasma enhanced chemical vapor deposition (PECVD) tool may be used to combine many of the process operations described above in a single pass in a process tool. For example, in one such embodiment, up to four different PECVD operations and one RTP operation may be performed in a single pass in a cluster tool. The PECVD operations may include depositing layers such as the backside P+ polysilicon layer, the frontside N+ polysilicon layer, and the backside N+ polysilicon layer and the ARC layer described above.

[0059] Thus, a method of fabricating a solar cell emitter region having distinct P-type and N-type architectures and including a point-like diffusion, and the resulting solar cell has been disclosed.

[0060] Although specific embodiments have been described above, even if only a single embodiment is described with respect to a particular feature, these embodiments are not intended to limit the scope of the present disclosure. The examples of features provided in the present disclosure are intended to be illustrative rather than restrictive, unless otherwise stated. The above description is intended to cover those alternatives, modifications, and equivalents that will be apparent to those skilled in the art that have the beneficial effects of the present disclosure.

[0061] The scope of the present disclosure includes any feature or combination of features disclosed herein (expressly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be made for any such combination of features during the examination of the present application (or an application claiming priority thereto). In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims, and features from corresponding independent claims may be combined in any appropriate manner, and not just in the specific forms enumerated in the appended claims.

[0062] In one embodiment, a solar cell includes: a substrate having a light receiving surface and a back surface; a first polysilicon emitter region of a first conductivity type disposed on a first thin dielectric layer, the first thin dielectric layer being disposed on the back surface of the substrate; and a second polysilicon emitter region of a second different conductivity type disposed on a second thin dielectric layer, the second thin dielectric layer being disposed in a plurality of non-continuous grooves in the back surface of the substrate.

[0063] In one embodiment, each trench of the plurality of non-continuous trenches has a width approximately in the range of 30 microns to 60 microns, and sequential trenches of the plurality of non-continuous trenches are separated by a distance approximately in the range of 50 microns to 300 microns.

[0064] In one embodiment, each trench of the plurality of non-continuous trenches has a depth in the range of about 0.5 microns to 10 microns from the back surface into the substrate.

[0065] In one embodiment, each non-continuous groove has an approximately circular shape.

[0066] In one embodiment, each non-continuous groove has a textured surface.

[0067] In one embodiment, the solar cell further includes a third thin dielectric layer disposed directly and laterally between the first polysilicon emitter region and the second polysilicon emitter region.

[0068] In one embodiment, the solar cell further includes a first conductive contact structure electrically connected to the first polysilicon emitter region, and a second conductive contact structure electrically connected to the second polysilicon emitter region.

[0069] In one embodiment, the solar cell further includes an insulating layer disposed on the first polysilicon emitter region, the first conductive contact structure is disposed through the insulating layer, and a portion of the second polysilicon emitter region overlaps the insulating layer but is separated from the first conductive contact structure.

[0070] In one embodiment, the solar cell further comprises an insulating layer disposed on the first polysilicon emitter region, and a second conductivity type polysilicon layer disposed on the insulating layer, and the first conductive contact structure is disposed through the second conductivity type polysilicon layer and through the insulating layer.

[0071] In one embodiment, the substrate is an N-type single crystal silicon substrate, the first conductivity type is a P-type, the second conductivity type is an N-type, and the solar cell is a back contact solar cell.

[0072] In one embodiment, a method for manufacturing a solar cell includes: forming a first silicon layer of a first conductivity type on a first thin dielectric layer formed on a back surface of a substrate to provide a first emitter region of the solar cell, wherein the substrate has a light receiving surface and a back surface; forming an insulating layer on the first silicon layer; forming a plurality of openings in the insulating layer and the first silicon layer, and forming a corresponding plurality of discontinuous grooves in the back surface of the substrate; and forming a second silicon layer of a second different conductivity type on a second thin dielectric layer formed in the plurality of discontinuous grooves to provide a second emitter region of the solar cell.

[0073] In one embodiment, forming the plurality of openings and the corresponding plurality of non-continuous trenches includes applying a laser ablation process.

[0074] In one embodiment, applying the laser ablation process includes forming each of the plurality of non-continuous grooves having a width approximately in the range of 30 microns to 60 microns, and forming sequentially arranged grooves of the plurality of non-continuous grooves separated by a distance approximately in the range of 50 microns to 300 microns.

[0075] In one embodiment, applying the laser ablation process includes forming each of the plurality of non-continuous trenches to a non-zero depth of less than about 10 microns into the substrate.

[0076] In one embodiment, applying the laser ablation process includes using a laser beam having a nearly Gaussian profile or having a nearly flat-top profile.

[0077] In one embodiment, the method further includes texturing a bottom surface of each of the plurality of non-continuous trenches before forming the second silicon layer and the second thin dielectric layer in the plurality of non-continuous trenches.

[0078] In one embodiment, a method for manufacturing alternating N-type emitter regions and P-type emitter regions of a solar cell includes: forming a P-type silicon layer on a first thin dielectric layer formed on a back surface of an N-type single crystal silicon substrate; forming an insulating layer on the P-type silicon layer; patterning the insulating layer and the P-type silicon layer by laser ablation to form a P-type silicon region having an insulating cap thereon and exposing a plurality of regions of the N-type single crystal silicon substrate; each of the plurality of regions of the N-type single crystal silicon substrate includes a plurality of non-continuous trenches formed in the N-type single crystal silicon substrate; forming a second thin dielectric layer on the exposed side of the P-type single crystal silicon substrate; and An N-type silicon layer is formed on the dielectric layer, on the insulating cap of the P-type silicon region, and on the third thin dielectric layer, wherein the third thin dielectric layer is formed in each of the multiple non-continuous grooves in each of the multiple regions of the N-type single crystal silicon substrate; the N-type silicon layer is patterned to form isolated N-type silicon regions and contact openings are formed in the regions of the N-type silicon layer above the insulating cap of the P-type single crystal silicon substrate; each isolated N-type silicon region is electrically coupled to a corresponding one of the multiple regions of the N-type single crystal silicon substrate; and a plurality of conductive contacts are formed, each conductive contact being electrically connected to one of the P-type silicon regions or one of the isolated N-type silicon regions.

[0079] In one embodiment, the P-type silicon layer and the N-type silicon layer are formed as amorphous silicon layers, and the method further includes annealing the P-type silicon layer and the N-type silicon layer to form a P-type polysilicon layer and an N-type polysilicon layer, respectively.

Claims

1. A solar cell comprising: a substrate having a light receiving surface and a back surface; a first thin dielectric layer disposed on the back surface of the substrate; a first polysilicon emitter region of a first conductivity type disposed on the first thin dielectric layer; a second thin dielectric layer disposed over the plurality of non-continuous trenches at the back surface of the substrate; a plurality of isolated second polysilicon emitter regions of a second conductivity type disposed on the second thin dielectric layer; a first conductive contact structure electrically connected to the first polysilicon emitter region; an insulating layer disposed on the first polysilicon emitter region, wherein the first conductive contact structure is disposed through the insulating layer, and wherein a portion of the second polysilicon emitter region overlaps the insulating layer but is separated from the first conductive contact structure; a second conductive contact structure electrically connected to the plurality of isolated second polysilicon emitter regions, wherein the second conductive contact structure is disposed over the plurality of isolated second polysilicon emitter regions and a first portion of the insulating layer, wherein the plurality of non-continuous trenches are non-overlapping points; a third thin dielectric layer between the first polysilicon emitter region and at least one second polysilicon emitter region of the plurality of isolated second polysilicon emitter regions, the third thin dielectric layer having an uppermost surface coplanar with an uppermost surface of the first polysilicon emitter region; and in The first polysilicon emitter region is laterally adjacent to at least one of the plurality of isolated second polysilicon emitter regions and is electrically isolated from the plurality of isolated second polysilicon emitter regions by the third thin dielectric layer, which is discontinuous with the second thin dielectric layer.

2. The solar cell according to claim 1, wherein the first portion of the insulating layer is disposed between two non-continuous grooves at the back surface of the substrate.

3. The solar cell according to claim 1, wherein each of the plurality of non-continuous grooves has a width in a range of 30 microns to 60 microns, and wherein continuous regions in the plurality of non-continuous grooves are spaced apart by a distance in a range of 50 microns to 300 microns.

4. The solar cell of claim 1, wherein each of the plurality of non-continuous trenches has a depth from the back surface into the substrate in a range of 0.5 microns to 10 microns.

5. The solar cell according to claim 1, wherein each of the plurality of non-continuous grooves has an approximately circular shape.

6. The solar cell according to claim 1, wherein each of the plurality of non-continuous grooves has a textured surface.

7. The solar cell of claim 6, wherein the second thin dielectric layer is confined to the plurality of non-continuous trenches and conforms to the textured surface of the plurality of non-continuous trenches.

8. The solar cell of claim 1, wherein the second thin dielectric layer is physically separated from the first conductive contact structure.

9. The solar cell according to claim 1, wherein the third thin dielectric layer has a vertical thickness and a lateral thickness, and the vertical thickness is greater than the lateral thickness.

10. A solar cell comprising: a substrate having a light receiving surface and a back surface; a first thin dielectric layer disposed on the back surface of the substrate; A first polysilicon emitter region of N+ conductivity type, which is disposed on the first thin dielectric layer; a second thin dielectric layer disposed over the plurality of non-continuous trenches at the back surface of the substrate; a plurality of isolated P+ conductive type second polysilicon emitter regions disposed on the second thin dielectric layer; a first conductive contact structure electrically connected to the first polysilicon emitter region; an insulating layer disposed on the first polysilicon emitter region, wherein the first conductive contact structure is disposed through the insulating layer, and wherein a portion of a plurality of isolated second polysilicon emitter regions overlaps the insulating layer but is separated from the first conductive contact structure; a second conductive contact structure electrically connected to the plurality of isolated second polysilicon emitter regions, wherein the second conductive contact structure is disposed over the plurality of isolated second polysilicon emitter regions and a first portion of the insulating layer, wherein the plurality of non-continuous trenches are non-overlapping points; a third thin dielectric layer between the first polysilicon emitter region and at least one second polysilicon emitter region of the plurality of isolated second polysilicon emitter regions, the third thin dielectric layer having an uppermost surface coplanar with an uppermost surface of the first polysilicon emitter region; and in The first polysilicon emitter region is laterally adjacent to at least one of the plurality of isolated second polysilicon emitter regions and is electrically isolated from the plurality of isolated second polysilicon emitter regions by the third thin dielectric layer, which is discontinuous with the second thin dielectric layer.

11. The solar cell according to claim 10, wherein the first portion of the insulating layer is disposed between two non-continuous trenches at the back surface of the substrate.

12. The solar cell of claim 10, wherein each of the plurality of non-continuous grooves has a width in a range of 30 microns to 60 microns, and wherein continuous regions in the plurality of non-continuous grooves are spaced apart by a distance in a range of 50 microns to 300 microns.

13. The solar cell of claim 10, wherein each of the plurality of non-continuous trenches has a depth from the back surface into the substrate in a range of 0.5 microns to 10 microns.

14. The solar cell according to claim 10, wherein each of the plurality of non-continuous grooves has an approximately circular shape.

15. The solar cell of claim 10, wherein the second thin dielectric layer is physically separated from the first conductive contact structure.

16. The solar cell of claim 10, wherein the third thin dielectric layer has a vertical thickness and a lateral thickness, and the vertical thickness is greater than the lateral thickness.

Images