High speed data weighted average (DWA) to binary conversion circuit
By detecting the logical 1-bit string position of the DWA data word in the high-speed data converter and using a multiplexer to select the binary value, the problem of increased noise caused by mismatch of unary output components is solved, thereby improving the signal-to-noise ratio and conversion efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STMICROELECTRONICS INT NV
- Filing Date
- 2021-08-30
- Publication Date
- 2026-06-09
AI Technical Summary
Existing high-speed data converters suffer from increased noise and reduced signal-to-noise ratio due to mismatch in uni-element output components when using data weighted averaging algorithms, especially in ultra-high-speed modulators where critical path delay has a significant impact.
A high-speed DWA to binary converter circuit is adopted. By detecting the start and end positions of the logic 1-bit string in the DWA data word, and combining multiplexers and logic circuits, a suitable binary value is selected for conversion, which uniformly actuates all unary output elements of the DAC.
It effectively reduces noise, uniformly actuates DAC output components, improves signal-to-noise ratio and conversion efficiency, and is suitable for ultra-high-speed data processing.
Smart Images

Figure CN114124101B_ABST