Programmable initial packet rejection in display system interface

Abstract

A processing circuit coupled to an imaging device includes: a bus interface circuit configured to communicatively couple the processing circuit to the imaging device via a multipoint differential serial link; a detector circuit configured to detect a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets via the multipoint differential serial link; and a controller. The controller is configured to: discard data packets received after the imaging device is powered on or initialized until the imaging device is indicated to be in an active operating state; count a transition sequence between a first signaling state and a second signaling state of the multipoint differential serial link; and indicate that the imaging device is in the active operating state after a pre-configured number of data packets have been discarded.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 096,102, filed January 12, 2023, which is assigned to the assignee of this patent application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] This disclosure generally relates to serial communication via a serial bus in wireless communication devices, and more specifically to discarding erroneous data sent after the initialization of a peripheral device. Background Technology

[0004] Mobile communication devices typically comprise various components, such as circuit boards, integrated circuit (IC) devices, application-specific integrated circuit (ASIC) devices, and / or system-on-a-chip (SoC) devices. These components can include processing circuitry, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus can operate according to either a standardized or proprietary protocol. In one example, the serial bus may operate according to an inter-integrated circuit (I2C) communication protocol. The I2C bus is configured as a multi-point bus and was developed to connect low-speed peripheral devices to a processor. The two wires of the I2C bus include a serial data line (SDA) carrying data signals and a serial clock line (SCL) carrying clock signals.

[0005] In another example, the serial bus can operate according to the Serial Peripheral Interface (SPI) communication protocol, where a clock signal controls the synchronous serial data exchange between the master and subordinate devices. The SPI protocol enables the use of two or more data lines on the serial bus to transmit data and allows the serial bus to be configured for multi-point operation. Since one or more data lines can be shared by the receiving device, select signals provided to the devices coupled to the bus are used to control access to the shared data lines.

[0006] In another example, the serial bus can operate according to a multi-master protocol, allowing one or more devices to be designated as bus masters or host devices for the serial bus. A device can act as a bus master or host in some transmissions and as a slave or subordinate device in others. In one example, the Improved Inter-Integrated Circuit (I3C) protocol can be used to control operation on the serial bus. The I3C protocol is defined by the Mobile Industry Processor Interface (MIPI) Alliance and derives certain implementation aspects from the I2C protocol. In another example, the RF Front-End (RFFE) interface defined by the MIPI Alliance provides a communication interface for controlling various RF front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices can be cascaded in a single IC device or provided in multiple IC devices. Multiple antennas and radio transceivers can be provided in mobile communication devices to support multiple concurrent RF links. In another example, the System Power Management Interface (SPMI) defined by the MIPI Alliance provides a hardware interface that can be implemented between the baseband or application processor and peripheral components. SPMI can be used to support power management and other operations within a device or system.

[0007] Several standards define certain types of components used for interconnecting mobile communication devices. For example, there are multiple types of interfaces defined for communication between the application processor and the display or camera components in a mobile communication device. Some components employ interfaces that conform to one or more standards or protocols specified by the MIPI Alliance, including standards or protocols for the Camera Serial Interface (CSI) and Display Serial Interface (DSI).

[0008] The MIPI Alliance DSI, DSI-2 (referred to individually or collectively as DSI herein), and CSI and CSI-2 (referred to individually or collectively as CSI herein) standards define wired interfaces that can be deployed within an IC or between some combination of IC devices and SoC devices. The CSI protocol can be used to couple a camera and an application processor. The DSI protocol can be used to couple an application processor and a display subsystem. The low-level physical layer (PHY) interface in each of these applications can be implemented according to the MIPI Alliance C-PHY or D-PHY standards and protocols. High-speed and low-power modes of communication are defined for the C-PHY and D-PHY interfaces. The C-PHY high-speed mode uses low-voltage multiphase signals transmitted in different phases over a 3-wire link. The D-PHY high-speed mode uses multiple 2-wire channels to carry low-voltage differential signals. The low-power modes of the C-PHY and D-PHY interfaces provide lower data rates and transmit signals at higher voltages than the high-speed modes.

[0009] As device technology improves, serial buses configured for multipoint operation can be used to serve increased functionality. However, multipoint serial buses frequently require support for hot-access and hot-plug capabilities, which can disrupt continuous communication over the multipoint serial bus. There is a ongoing need to improve the resilience and reliability of multipoint serial bus operation during interruption events. Summary of the Invention

[0010] Certain aspects of this disclosure relate to systems, apparatus, methods, and techniques that enable mobile communication devices and other portable devices to discard a certain number of data packets after an imaging device has been turned on. The number of data packets to be discarded can be calculated or configured to ensure that corrupted data packets are discarded before processing begins.

[0011] In various aspects of this disclosure, a processing circuit coupled to an imaging device includes: a bus interface circuit configured to communicatively couple the processing circuit to the imaging device via a multipoint differential serial link; a detector circuit configured to detect a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets via the multipoint differential serial link; and a controller. The controller may be configured to: discard data packets received after the imaging device is powered on or initialized until the imaging device is indicated to be in an active operating state; count a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link; and indicate that the imaging device is in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0012] In various aspects of this disclosure, a method for operating processing circuitry coupled to an imaging device includes: configuring bus interface circuitry to communicatively couple the processing circuitry to the imaging device via a multipoint differential serial link; detecting a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets via the multipoint differential serial link; discarding data packets received after the imaging device is powered on or initialized until the imaging device is indicated to be in an active operating state; counting a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link; and indicating that the imaging device is in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0013] In various aspects of this disclosure, an apparatus includes: components for configuring bus interface circuitry to communicatively couple the apparatus to an imaging device via a multipoint differential serial link; components for detecting a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets via the multipoint differential serial link; and components for counting a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link. Data packets received after the imaging device is powered on or initialized are discarded until the imaging device is indicated to be in an active operating state. The imaging device is indicated to be in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0014] In various aspects of this disclosure, a processor-readable storage medium includes code that, when executed by processing circuitry, causes the processing circuitry to: configure bus interface circuitry to communicatively couple to an imaging device via a multipoint differential serial link; detect a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets via the multipoint differential serial link; discard data packets received after the imaging device is powered on or initialized until the imaging device is indicated to be in an active operating state; count a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link; and indicate that the imaging device is in the active operating state after a pre-configured number (N) of data packets have been discarded. Attached Figure Description

[0015] Figure 1 An example is shown of a device that employs a data link between IC devices and operates selectively according to a standard or proprietary protocol.

[0016] Figure 2 Examples of interface circuits that can be adapted to certain aspects of this disclosure are illustrated.

[0017] Figure 3 The system architecture of a device employing data links between IC devices is illustrated.

[0018] Figure 4 Examples of C-PHY interfaces that can be adapted according to certain aspects disclosed herein are provided.

[0019] Figure 5 Examples of D-PHY interfaces that can be adapted according to certain aspects disclosed herein are shown.

[0020] Figure 6 The signaling associated with the transmission of high-speed data bursts via a data communication link operating according to the DSI protocol is illustrated.

[0021] Figure 7 Examples of systems, including imaging devices, utilizing CSI data links according to certain aspects of this disclosure are illustrated.

[0022] Figure 8 An example of a system that uses a multi-point CSI data link is shown.

[0023] Figure 9 An example is given of the rejection of data packets or other transmissions after power-on or initialization of a camera subsystem in a system configured according to certain aspects of this disclosure.

[0024] Figure 10 An example of an apparatus employing processing circuitry adaptable to certain aspects disclosed herein is illustrated.

[0025] Figure 11 This is a flowchart illustrating a method for operating a bus interface circuit according to certain aspects disclosed herein.

[0026] Figure 12 A first example of a hardware implementation of a bus interface device adapted to certain aspects disclosed herein is illustrated. Detailed Implementation

[0027] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing the only configuration in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0028] Several aspects of the invention will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0029] Data communication links used by SoCs and other IC devices to connect the processor to modems and other peripherals can operate according to industry or proprietary standards or protocols associated with certain functions or types of devices. In examples such as display panels, display subsystems, and display drivers, communication standards and protocols defined by the MIPI Alliance are frequently used. For instance, display serial interfaces... C-PHY and D-PHY standards and protocols are provided for defining, configuring, and controlling the high-speed serial interface between the host processor and the display module. Control and management protocols can be used to operate other serial buses coupling the host processor and the display module; these protocols may include SPMI, I2C, I3C, and / or other protocols.

[0030] Mobile phones typically support a low-power operating mode that can be initiated when the phone is idle. In conventional mobile phones that use the DSI protocol to manage certain serial data links, there is little difference between the high-speed mode and the low-power operating mode of the serial data link. Therefore, when the phone is idle and the serial data link is managed using the DSI protocol, it may be difficult or impossible to allow the processor in the host device, which includes the serial data link or related circuitry, to enter a low-power mode. According to certain aspects of this disclosure, when the low-power mode is activated, data communication between the host device and the display driver can be transferred to a low-power serial data link. The DSI physical layer circuitry can be idle, and the processor in the host device can enter a sleep mode.

[0031] Example of a device using a serial data link

[0032] According to certain aspects of this disclosure, serial data links can be used to interconnect electronic devices that are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similar functional devices.

[0033] Figure 1 An example of a device 100 employing a data communication bus is illustrated. Device 100 may include processing circuitry 102 having multiple circuits or devices 104, 106, and / or 108, which may be implemented in one or more ASICs or in a SoC. In one example, device 100 may be a communication device, and processing circuitry 102 may include processing devices provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 enabling the device to communicate with a radio access network, a core access network, the Internet, and / or another network via antenna 124.

[0034] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functions. Processing circuitry 102 may be controlled by an operating system that provides an application programming interface (API) layer, enabling one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage device 122 provided on processing circuitry 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage device 122. ASIC 104 may access its onboard memory 114, processor-readable storage device 122, and / or storage devices external to processing circuitry 102. Onboard memory 114 and processor-readable storage device 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. Processing circuitry 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating device 100 and / or processing circuitry 102. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, floppy disk, or hard disk, etc. Processing circuitry 102 may also be operatively coupled to external devices such as antenna 124, display 126, operator controls such as switches or buttons 128, 130 and / or an integrated or external keyboard 132, and other components. The user interface module may be configured to operate with display 126, external keyboard 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0035] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 enabling communication between two or more devices 104, 106, and / or 108. In one example, ASIC 104 may include one or more bus interface circuits 116, which include a combination of circuits, counters, timers, control logic units, and other configurable circuitry or modules. In one example, bus interface circuitry 116 may be configured to operate according to a standard-defined communication specification or protocol. Processing circuitry 102 may include or control power management functions for configuring and managing the operation of device 100.

[0036] Figure 2Examples of interface circuitry that may be employed or adapted according to certain aspects of this disclosure are illustrated. A first interface circuit is configured as a camera subsystem 200, and a second interface circuit is configured as a display subsystem 250. For example, the interface circuitry may be deployed in a mobile communication device. The camera subsystem 200 may include a CSI-2 defined communication link between an image sensor 202 and an application processor 212. The communication link may include a high data rate data transmission link 210 used by the image sensor 202 to transmit image data to the application processor 212 using a transmitter 206. The high data rate data transmission link 210 may be configured and operated according to a D-PHY or C-PHY protocol. The application processor 212 may include a crystal oscillator (XO 214) or other clock source to generate a clock signal 222 that controls the operation of the transmitter 206. The clock signal 222 may be processed by a phase-locked loop (PLL) 204 in the image sensor 202. In some cases, the clock signal 222 may also be used by a D-PHY or C-PHY receiver 216 in the application processor 212. The communication link may include a Camera Control Interface (CCI), which is essentially similar to an Inter-Integrated Circuit (I2C) interface. The CCI bus may include a Serial Clock (SCL) line carrying a clock signal and a Serial Data (SDA) line carrying data. CCI link 220 may be bidirectional and may operate at a lower data rate than the high-data-rate data transmission link 210. Application processor 212 may use CCI link 220 to exchange control and configuration information with image sensor 202. Application processor 212 may include a CCI bus master PHY 218, and image sensor 202 may include a CCI subordinate PHY 208.

[0037] Display subsystem 250 may include a unidirectional data link 258 that can be configured and operated according to a D-PHY or C-PHY protocol. In application processor 252, a clock source such as PLL 254 may be used to generate a bit clock signal used by D-PHY or C-PHY receiver 256 to control transmissions on data link 258. At display driver 260, D-PHY or C-PHY receiver 262 may extract embedded clock information from a sequence of symbols transmitted on the data link or from a clock channel provided in data link 258.

[0038] Some aspects disclosed herein relate to systems, apparatus, and methods that support a wide range of interface protocols and can operate using different physical media. For example... Figure 2As shown, for example, camera subsystem 200 and / or display subsystem 250 may use D-PHY or C-PHY protocols to convey high data rate information. In some configurations, camera subsystem 200 and / or display subsystem 250 may communicate using a reverse channel (e.g., CCI link 220) used to configure image sensor 202 or other devices. In some cases, a low-power operating mode may be defined for links using either D-PHY or C-PHY protocols.

[0039] Figure 3 An example of a device 300 employing a data link that can be used to communicatively couple two or more devices, sub-components, or circuits is illustrated. Here, device 300 includes multiple devices 302 and 3220 to 3220 coupled to a two-wire serial bus 320. N Equipment 302 and 3220 to 322 N It can be implemented in one or more semiconductor IC devices (such as application processors, SoCs, or ASICs). In various specific implementations, devices 302 and 3220 to 322... N Some of the devices may include, support modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, media players, transceivers, and / or other such components or devices, or operate as such. In some examples, one or more devices 3220 to 322 N It can be used to control, manage, or monitor sensor devices. Devices 302 and 3220 to 322 are connected via serial bus 320. N Communication between them is controlled by the host device 302. Some types of buses can support multiple bus masters 302.

[0040] In one example, host device 302 may include an interface controller 304 that manages access to the serial bus, configures dynamic addresses for subordinate devices, and / or generates a clock signal 328 to be transmitted on clock line 318 of the serial bus 320. Host device 302 may include a configuration register 306 or other storage device 324, and other control logic components 312 configured to process protocols and / or higher-level functions. Control logic components 312 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. Host device 302 includes a transceiver 310 and line drivers / receivers 314a and 314b. Transceiver 310 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in the clock signal 328 provided by clock generation circuitry 308. Additional timing clocks 326 may be used by control logic components 312 and other functions, circuitry, or modules.

[0041] At least one device 3220 to 322 N The device 3220 can be configured to operate as a subordinate device on a serial bus 320 and may include circuitry and modules supporting a display, an image sensor, and / or controlling and communicating with one or more sensors that measure environmental conditions. In one example, the device 3220 configured to operate as a subordinate device may provide control functions, physical layer circuitry 332 including circuitry and modules for supporting a display, an image sensor, and / or controlling and communicating with one or more sensors that measure environmental conditions. In this example, the device 3220 may include a configuration register 334 or other storage device 336, control logic unit 342, transceiver 340, and line drivers / receivers 344a and 344b. The control logic unit 342 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. The transceiver 340 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in a clock signal 348 provided by clock generation and / or recovery circuitry 346. In some cases, clock signal 348 can be derived from the signal received from clock line 318. Other timing clocks 338 can be used by control logic unit 342 and other functions, circuits, or modules.

[0042] The serial bus 320 can operate according to RFFE, I2C, I3C, SPI, SPMI, or another suitable protocol. In some cases, two or more devices 302, 3220-322... N It can be configured to operate as a host device on serial bus 320. In some cases, device 300 includes multiple serial buses 320, 352a and / or 352b, which couple devices 302, 3220-322. N Two or more devices or devices 302, 3220-322 N The device includes a display or camera 350 and peripheral devices such as a display or camera 350 or an radio frequency IC (RFIC). In some examples, a subordinate device 3220 is configured to operate as a display or camera coupled to the display or camera 350. The latter subordinate device 3220 may include physical layer circuitry 332 configured to operate as a C-PHY or D-PHY interface controller that communicates with the display or camera 350 via a serial bus 352a or 352b operating according to the C-PHY protocol or D-PHY protocol.

[0043] In certain aspects of this disclosure, systems and apparatuses may employ a multiphase data encoding and decoding interface approach to communicate between IC devices. A multiphase encoder may drive multiple conductors (i.e., three conductors). Each conductor may be referred to as a wire, but it may include conductive traces on a circuit board or traces or interconnects within the conductive layer of a semiconductor IC device. In one example, a physical layer interface (i.e., a C-PHY interface) implemented using C-PHY technology and protocols defined by the MIPI Alliance can be used to connect a camera or display to an application processor. The C-PHY interface employs tri-phase symbol encoding to transmit data symbols on a 3-wire channel or “trio”, where each trio includes an embedded clock. A trio may be referred to herein as a channel. Multiple trios can be used to establish multi-channel C-PHY communication channels to carry data exchanged between a pair of devices, where each channel includes a trio carrying a portion of data that can be independently encoded according to the C-PHY protocol.

[0044] The C-PHY interface provides a three-phase encoding scheme for three-wire systems, allowing the definition of three phase states and two polarities, thus providing six states and five possible transitions for each state. It can detect and decode deterministic voltage and / or current changes to extract data from the three wires.

[0045] Figure 4 Examples are shown that can be used to implement Figure 3 The C-PHY interface 400 is depicted in certain aspects of the serial bus 352a or 352b. The illustrated example may involve a three-wire link configured to carry three-phase polarity encoded data according to the DSI protocol. The use of three-phase polarity encoding provides high-speed data transmission and can consume half or less power than other interfaces at the desired operating frequency because fewer than three drivers are active in the C-PHY link at any given time. The C-PHY interface 400 uses three-phase polarity encoding to encode multiple bits for each sign transition on the three-wire link. In one example, a combination of three-phase encoding and polarity encoding can be used to support a wide video graphics array (WVGA), 80 frames per second liquid crystal display driver IC without a frame buffer, delivering pixel data at 810 Mbps for display refresh via three or more wires.

[0046] In the depicted C-PHY interface 400, three-phase polarity coding is used to control the signaling state of connectors, wires, traces, and other interconnects providing the communication channel. In the illustrated example, a combination of three wires (tri-wire group 420) is used to provide a single unidirectional channel or path. Each wire of the tri-wire group 420 can be undriven, positively driven, or negatively driven in any symbol transmission interval. In some cases, the undriven signal line of the tri-wire group 420 may be in a high-impedance state. In some cases, the undriven signal line of the tri-wire group 420 may be driven or pulled to a voltage level substantially intermediate between the positive and negative voltage levels provided on the driven signal line. In some cases, no current may flow through the undriven signal line of the tri-wire group 420. The driver 408 controls the signal lines coupled to the tri-wire group 420 such that only one wire of the tri-wire group 420 is in each of the three states (represented as +1, -1, or 0) in each symbol interval.

[0047] In one example, driver 408 may include a cell-level current-mode driver. In another example, driver 408 may drive opposite polarity voltages on two signals transmitted on two signal lines of three-wire group 420, while a third signal line is at high impedance and / or pulled to ground. For each transmitted symbol interval, at least one signal is in an undriven (0) state, while one signal is driven positive (+1 state) and one signal is driven negative (-1 state), such that the sum of the currents flowing to the receiver is always zero. For each symbol, the state of at least one signal line of three-wire group 420 changes from the symbol transmitted in the previous transmitted interval.

[0048] In the C-PHY interface 400, a mapper 402 can receive a 16-bit input data word 418 and can map the input data word 418 to seven symbols 412 for sequential transmission via the signal lines of the three-wire group 420. An M-line, N-phase encoder 406, configured for three-wire, three-phase encoding, receives the seven symbols 412 generated by the mapper one symbol 414 at a time and calculates the state of each signal line of the three-wire group 420 for each symbol interval based on the preceding state of the signal lines of the three-wire group 420. The seven symbols 412 can be serialized using, for example, a parallel-to-serial converter 404. The encoder 406 provides a control signal 416 to define the output of the driver 408. The encoder 406 selects the state of the signal lines of the three-wire group 420 based on the input symbol 414 and the previous state of the signal lines of the three-wire group 420, and can provide the control signal 416 to cause the driver 408 to generate the desired signaling state on the three-wire group 420.

[0049] The use of three-wire, three-phase coding allows multiple bits to be encoded in multiple symbols, where the bits in each symbol are not integers. In an example of a three-wire, three-phase system, there are three available combinations of two wires that can be driven simultaneously, and two possible polarity combinations on a pair of wires driven simultaneously, resulting in six possible states. Since each transition begins from the current state, five of the six states are available at each transition. For the five states, each symbol transition can encode... Therefore, the mapper can accept a 16-bit word and convert it into 7 symbols, since 7 symbols, each with 2.32 bits, can encode 16.24 bits. In other words, the combination of seven symbols encoding five states has 5 7 (78,125) permutations. Therefore, 7 symbols can be used to represent 16-bit 2... 16 Encode 65,536 possible permutations.

[0050] The receiver in the C-PHY interface 400 includes a comparator 422 and a decoder 424, which are configured to provide a digital representation of the state of each of the three signal lines of the three-wire group 420, and the change in the state of the three signal lines compared to the state transmitted in a previous symbol period. Seven consecutive states are combined by a serial-to-parallel converter 426 to generate a set of seven symbols to be processed by a demapper 428 to obtain 16 bits of data that can be buffered in a first-in-first-out (FIFO) memory device 430, which may be implemented using, for example, registers.

[0051] Based on certain aspects disclosed herein, systems and devices can employ a combination of differential coding and single-ended coding to communicate between IC devices. In one example, the “D-PHY” physical layer interface technology defined by the MIPI Alliance can be used to connect a camera and display device to an application processor. The D-PHY interface can switch in real-time between differential (high-speed) mode and single-ended low-power (LP) mode as needed to facilitate the transmission of large amounts of data or save power and extend battery life. The D-PHY interface can operate in simplex or duplex configurations with a single data channel or multiple data channels with a unidirectional clock channel driven by the host device. In one example, a single wire is used to implement the data channel. The single-wire channel can be used at a lower data rate to generate a data signal that can be transmitted with limited loss, allowing the receiver to easily decode the data carried on the data channel. The dual-wire channel carrying differentially coded clock and data signals provides common-mode rejection of electromagnetic interference and can limit the attenuation of higher frequency components in the signal transmitted on the channel.

[0052] Figure 5This illustrates a generalized example of a D-PHY interface 500, which includes a host device 502 and a subordinate device 504 coupled using a set of wires 510, which provides a clock channel 506 and one or more data channels 5081-508. N For high-speed operation, clock channel 506 and data channels 5081-508... N Each device can be configured to carry a differential signal using a pair of wires. In one example, subordinate device 504 is located in a display driver IC (DDIC) associated with the display panel, and host device 502 is included in an application processor or provided by another processing circuit.

[0053] In the illustrated example, the clock signal is transmitted on clock channel 506, and data is transmitted on one or more data channels 5081-508. N The host device 502 includes a clock generation circuit 512, which can be configured to generate a clock signal 514, which is transmitted on clock channel 506 to control data channels 5081-508. N The frequency of clock signal 514 can be configured during system initialization or configuration and / or dynamically configured based on the operating mode of D-PHY interface 500, application requirements, the amount of data to be transmitted, and power saving requirements. Data channels 5081-508 are set or active in the device. N The number can be configured during system initialization or configuration and / or can be dynamically configured based on the operating mode of the D-PHY interface 500, application requirements, the amount of data to be transmitted, and power saving requirements.

[0054] Figure 6An example of signaling associated with the transmission of high-speed data bursts on a data communication link 602 operating according to the DSI protocol is illustrated. While timing diagram 600 illustrates data packet transmission according to the C-PHY protocol, certain general concepts also apply to the D-PHY protocol, including signaling for transitioning between high-speed and low-power operating modes. A high-speed transaction is illustrated, and the high-speed mode is initiated by high-speed transition signaling 630. At a first time point 604, data communication link 602 is operating in low-power mode, and the transition to high-speed mode is initiated by LP-111 signaling state 622, in which each wire of at least one differential channel is driven to a high signaling state. At the second time point 606, when one conductor of the differential channel (e.g., the non-inverting conductor 602a in the D-PHY channel) is driven to a low signaling state while the other conductor of the differential channel (e.g., the inverting conductor 602b in the D-PHY channel) is maintained in a high signaling state, the system enters LP-001 signaling state 624. At the third time point 608, when all conductors of the differential channel are driven to a low signaling state, the system enters LP-000 signaling state 626. This initiation sequence puts the receiving device into high-speed mode and prepares it for synchronization and / or one or more data packets. In high-speed mode 610, low-voltage differential signaling is used. Regarding the illustrated example, the C-PHY protocol defines a 3-phase differential signaling scheme.

[0055] The illustrated high-speed data transmission includes data packets 616 and control signaling, which includes training, synchronization, and termination signaling. For example, according to the C-PHY protocol, data packets 616 are led during transmission by a preamble 612 and a synchronization word 614, and data transmission is terminated by a POST mode 618. POST mode 618 is provided at the end of high-speed data transmission to provide the receiver with reliable notification of the end of the high-speed burst.

[0056] Figure 7An application of a system 700, including an imaging device, utilizing a CSI data link according to certain aspects of this disclosure is illustrated. The illustrated system 700 includes a SoC 702 and a camera subsystem 704 communicatively coupled using a high-speed serial bus 706 and a low-power serial bus 708. In the illustrated example, the SoC 702 may include multiple processors, including a central processing unit or image processor 712, one or more microcontrollers, digital signal processors, finite state machines, or other sequential logic components. For the purposes of this disclosure, an example of a high-speed serial data link may be described as being controlled and managed using the CSI protocol, while an example of a low-speed serial data link may be described as being controlled and managed using the SPI protocol. In other examples, other types of communication protocols may be used to control or manage the high-speed and low-speed serial data links. In the illustrated example, the SoC 702 includes a CSI physical interface (CSIPHY 714) and an SPI physical interface (SPIPHY 716).

[0057] Camera subsystem 704 includes a sensor controller 722 configured to control and configure the operation of image sensor 730. Sensor controller 722 may include one or more processing circuitry, such as one or more microcontrollers, digital signal processors, finite state machines, or other sequential logic components. Sensor controller 722 may include a CSI physical interface (CSIPHY 724) configured as a transmit interface coupled to a high-speed serial bus 706. The illustrated sensor controller 722 also includes a low-power serial bus 708. An SPI physical interface (SPIPHY 726) in camera subsystem 704 is coupled to SPIPHY 716 in SoC 702 via low-power serial bus 708 and can be configured to support bidirectional full-duplex operation.

[0058] The capabilities and applications of CSI and DSI data links, as defined by the MIPI Alliance, continue to evolve. For example, in some applications, CSI data links can be implemented as multipoint data links. Figure 8 An example is illustrated using a multi-point CSI data link in a system 800. In one example, system 800 could be deployed in an automotive application with multiple cameras 8020 to 8020. M Image data can be sent to multiple application processors or SoCs 8040 to 8040. N In the illustrated example, each camera has 8020 to 802... M Through the corresponding multi-point CSI data links 8060 to 806 M Send image data. In some cases, the camera 8020 to 802... MOne of the cameras can send data streams to the SoC8040 to 8040. N One of the SoCs is configured to host an application that provides driver assistance while the vehicle is parked, and the camera can be an SoC 8040 to 8040. N One of several SoCs used by the guidance system during the autonomous operation of the vehicle. In some cases, various cameras 8020 to 802... M Data streams can be sent to SoC 8040 to 804 N One or more SoCs used to manage vehicle security (including access control and / or support for anti-theft systems). In some cases, this is achieved by cameras 8020 to 802... M Images generated by one or more cameras can be sent concurrently to multiple SoCs 8040 to 8040. N Or, in collaboration with application processors to provide redundant autonomous driving capabilities, such as SoCs 8040 to 8040. N Each SoC in the SoC can be used in other SoCs 8040 to 8040. N Reliable operation when one or more SoCs in the system fail, produce errors or invalid results, or enter an idle state. Multipoint CSI data links 8060 to 806 M It can be used to support a single camera, 8020 to 802. M It can be composed of multiple 8040 to 804 N These and other specific implementations are monitored. An application processor, SoC, or other video processor that receives data streams from one or more devices may be referred to herein as video processing circuitry, regardless of whether the application processor, SoC, or other video processor uses, modifies, or manipulates the data streams or merely relays the data streams to another device.

[0059] Certain aspects of this disclosure provide systems, circuits, methods, and techniques for managing multipoint CSI or DSI data links. In one aspect, systems, apparatus, and methods are disclosed for detecting invalid transmissions that may occur during camera system initialization, including during hot-access or hot-plug control events. Initialization of a camera system configured to communicate according to the MIPI Alliance protocol can be time-consuming and may result in communication interruptions on the multipoint CSI data link. It is common for image sensors to send some invalid data packets during system initialization, and many image sensor manufacturers can indicate the number of invalid data packets expected during initialization. The number of invalid data packets can be empirically based or derived from simulation. Invalid data packets may corrupt or interrupt the operation of the camera subsystem and / or image processor receiving invalid data packets.

[0060] A system that couples a camera to a processing device using a CSI data link may, according to certain aspects of this disclosure, be configured to reject or drop a certain number of data packets received after the camera subsystem is powered on and / or initialized. The processing device may be included in a System-on-a-Chip (SoC). The processing device may be an imaging processor or an application processor. The processing device may be a communications processor configured to relay image data streams. In some cases, the processing device may receive notification of current or impending power-on and / or initialization of the camera subsystem. In some cases, the processing device may infer, deduce, or otherwise calculate that power-on and / or initialization of the camera subsystem is in progress or is about to occur based on the detection of hot-plug or hot-access events or based on signaling received from the camera subsystem or application processor.

[0061] For example, a hot-plug event may occur when a camera sensor is powered on or otherwise becomes active and begins streaming data via the CSI data link. The CSIPHY circuitry in the camera sensor may interrupt or otherwise affect signaling via the CSI data link when the camera sensor is powered on or becomes active. A hot-access event may occur when an active camera sensor enables the decoder and other circuitry in its CSIPHY circuitry to send a data stream from the CSI data link, and such activation may interrupt or otherwise affect signaling via the CSI data link, and may activate the CSIPHY circuitry in a manner that results in an indeterminate state within the CSIPHY circuitry. For the purposes of this description, examples related to camera subsystem power-on and / or initialization events will be discussed, which are definitively indicated or determined based on errors or interruptions detected on the CSI data link.

[0062] A receiving device configured according to certain aspects of this disclosure may be configured to respond to the occurrence or potential occurrence of power-on and / or initialization of a camera subsystem. In one aspect, the receiving device may be configured to ignore, reject, or discard a pre-configured number of data packets transmitted after power-on and / or initialization of the camera subsystem. The number of data packets to be ignored, rejected, or discarded may be determined based on manufacturer specifications, calibration, simulation, and / or empirical measurements obtained from previous power-on or initialization of the camera subsystem or similar functional systems. In some embodiments, the receiving device is configured to closely monitor... Figure 6 The illustrated high-speed transition signaling 630 is used to determine when a hot-plug event is a possible source of a physical link error.

[0063] Figure 9 An example is given of the rejection of data packets or other transmissions after power-on or initialization of a camera subsystem in a system configured according to certain aspects of this disclosure. Figure 9This includes block diagram 900 and state diagram 940. In block diagram 900, controller 908 is configured to monitor the outputs 912, 914, and 916 of a set of detectors 902, 904, and 906, which monitor channel 910 of the CSI data link for detection. Figure 6 The illustrated high-speed transition signaling 630 corresponds to the occurrence of the following elements. A first detector 902 is configured to detect the occurrence of LP-111 signaling state 622, a second detector 904 is configured to detect the occurrence of LP-001 signaling state 624, and a third detector 906 is configured to detect the occurrence of LP-000 signaling state 626. In the illustrated example, a controller 908 is configured to count the number (N) of transitions from valid LP-000 signaling state 626 to valid LP-111 signaling state 622. In some cases, the controller 908 may be configured to count the occurrences of high-speed transition signaling 630, which is followed by valid LP-111 signaling state 622.

[0064] In one example, controller 908 may be implemented as a finite state machine (FSM) and may receive a timing signal 920 that enables controller 908 to measure the duration of each of LP-111 signaling state 622, LP-001 signaling state 624, and LP-000 signaling state 626. Controller 908 can measure the duration of LP-111 signaling state 622, LP-001 signaling state 624, and LP-000 signaling state 626 by counting the periods or half-cycles of timing signal 920 while the measured state is present on the CSI data link. In some cases, timing signal 920 is derived from a transmitter clock signal used to control data transmission via the CSI data link. In other cases, timing signal 920 is a real-time clock signal or other internal clock signal. The controller can determine the validity of each of the LP-111 signaling states 622, LP-001 signaling states 624, and LP-000 signaling states 626 based on the measured durations. A state is determined to be valid if it has a duration exceeding the minimum duration defined for that state. In some cases, a state is determined to be valid if it has a duration not exceeding the maximum duration defined for that state. The controller can activate the PHY activity signal 918 to enable the CSIPHY 714 (see...) Figure 7It can receive and process data packets after the configured number (N) of transitions from LP-000 signaling state 626 to LP-111 has been counted. The nominal, minimum, and maximum durations of LP-111 signaling state 622, LP-001 signaling state 624, and LP-000 signaling state 626 can be defined by the protocol, by the application, during system configuration, and / or during system initialization.

[0065] The number (N) of transitions from LP-000 signaling state 626 to LP-111 signaling state 622 can be configured by the application and / or during the configuration or initialization of the receiving device. In some embodiments, the controller 908 can be configured to activate the PHY activity signal 918 after a configurable number of LP-000 signaling state 626 to LP-111 signaling state 622 transitions. In some embodiments, the counting of LP-000 signaling state 626 to LP-111 signaling state 622 transitions can be disabled and the PHY activity signal 918 can be activated whenever the CSIPHY 714 in the receiver has been initialized and is active. In some embodiments, the camera subsystem 704 can be configured to suppress the transmission of the configured number (N) of transitions from valid LP-000 signaling state 626 to valid LP-111 signaling state 622 after the camera subsystem 704 experiences a power-on or initialization event.

[0066] State diagram 940 can be implemented by controller 908, regardless of whether controller 908 or detectors 902, 904, 906 measure the duration of LP-111 signaling state 622, LP-001 signaling state 624, and LP-000 signaling state 626. Controller 908 can be co-located with image sensor 730 in camera subsystem 704 and can be configured to cause CSIPHY 724 to suppress a pre-configured number (N) of data packets. Controller 908 can be located in a receiving device (such as SoC 702) and can be configured to discard a pre-configured number (N) of data packets.

[0067] Controller 908 may initially disable the PHY activity signal 918 to cause the CSIPHY circuitry to enter a PHY inactive state 942. Controller 908 may reset a counter configured to count transitions from valid LP-000 signaling state 626 to valid LP-111 signaling state 622 before entering the PHY inactive state 942. In the illustrated example, the counter increments for each detected transition from valid LP-000 signaling state 626 to valid LP-111 signaling state 622. While controller 908 is in the PHY inactive state 942 and / or until controller 908 is indicated to have entered the PHY active state 950, the CSI PHY circuitry or controller 908 may reject, discard, or ignore data packets.

[0068] Upon detecting LP-000 signaling state 626, controller 908 enters LP-000 detection state 944 and waits for the next LP-111 signaling state 622. In some implementations, if LP-000 signaling state 626 is determined to be invalid based on its duration, or if an invalid state sequence occurs before the next LP-111 signaling state 622 is detected, controller 908 may reset the counter at block 952 and re-enter PHY inactive state 942.

[0069] Upon detecting LP-111 signaling state 622, controller 908 transitions to LP-111 detection state 946. If LP-111 signaling state 622 is determined to be invalid based on its duration, controller 908 may reset the counter at block 952 and re-enter PHY inactive state 942. If LP-111 signaling state 622 is valid, controller 908 transitions to packet detection state 948. In packet detection state 948, controller 908 may increment the counter. If the counter has reached a pre-configured number N, controller 908 may configure the CSIPHY circuitry for normal operation before transitioning to PHY active state 950. When controller enters PHY active state 950, it may activate PHY active signal 918. Data packets received while controller 908 is in PHY active state 950 are processed according to the protocol. If the counter has not reached the pre-configured number N after incrementing in the group detection state 948, the controller 908 may return to the PHY inactive state 942 and wait for the next LP-000 signaling state 626.

[0070] According to certain aspects of this disclosure, the number of transitions from LP-000 signaling state 626 to LP-111 signaling state 622, counted before the image sensor is indicated or considered active, can be dynamically configured. The number of transitions may correspond to or be related to the number of data packets that are dropped or suppressed. In some embodiments, different numbers of data packets may be dropped or suppressed when different image sensors or different types of image sensors are powered on or initialized. In some cases, the image processor or application processor may be configured such that no data packets are dropped or suppressed. In some embodiments, the number of data packets to be dropped or suppressed may be changed after initial configuration. In one example, corrupted data packets may be detected after a configured number of data packets have been dropped or suppressed, and the display subsystem or associated processing circuitry may be configured to drop or suppress a larger number of data packets in subsequent image sensor power-on or initialization events.

[0071] Examples of processing circuits and methods

[0072] Figure 10 This is a diagram illustrating an example of a hardware implementation of device 1000. In some examples, device 1000 may perform one or more functions disclosed herein. According to various aspects of this disclosure, processing circuitry 1002 may be used to implement elements, any portion of elements, or any combination of elements as disclosed herein. Processing circuitry 1002 may include one or more processors 1004 controlled by some combination of hardware modules and software modules. Examples of processors 1004 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuitry, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1004 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1016. One or more processors 1004 may be configured by a combination of software modules 1016 loaded during initialization, and further by loading or unloading one or more software modules 1016 during operation.

[0073] In the illustrated example, processing circuitry 1002 can be implemented using a bus architecture, typically represented by bus 1010. Bus 1010 may include any number of interconnect buses and bridges, depending on the specific application of processing circuitry 1002 and overall design constraints. Bus 1010 links together various circuits including one or more processors 1004 and storage devices 1006. Storage devices 1006 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and / or processor-readable media. Bus 1010 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuitry. Bus interface 1008 provides an interface between bus 1010 and one or more transceivers 1012a, 1012b. Transceivers 1012a, 1012b may be provided for each networking technology supported by the processing circuitry. In some cases, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1012a, 1012b. Each transceiver 1012a, 1012b provides components for communicating with various other devices via a transmission medium. In one example, transceiver 1012a may be used to couple device 1000 to a multi-wire bus. In another example, transceiver 1012b may be used to connect device 1000 to a radio access network. Depending on the nature of device 1000, a user interface 1018 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and this user interface may be communicatively coupled to bus 1010 either directly or via bus interface 1008.

[0074] Processor 1004 may be responsible for managing bus 1010 and for general processing, which may include executing software stored in a computer-readable medium that may include storage device 1006. In this regard, processing circuitry 1002 (including processor 1004) may be used to implement any of the methods, functions, and techniques disclosed herein. Storage device 1006 may be used to store data manipulated by processor 1004 during software execution, and the software may be configured to implement certain methods disclosed herein.

[0075] One or more processors 1004 in the processing circuitry 1002 can execute software. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other names. The software may reside in a computer-readable form in storage device 1006 or on an external computer-readable medium. External computer-readable media and / or storage device 1006 may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical discs (e.g., compact discs (CDs) or digital multifunction discs (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer. The computer-readable media and / or storage device 1006 may also include, for example, carrier waves, transmission lines, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. The computer-readable media and / or storage device 1006 may reside in processing circuitry 1002, in processor 1004, outside of processing circuitry 1002, or distributed across multiple entities including processing circuitry 1002. The computer-readable media and / or storage device 1006 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize how best to achieve the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system as a whole.

[0076] Storage device 1006 can maintain and / or organize software in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software module 1016. Each software module in software module 1016 may include instructions and data that, when installed or loaded into processing circuitry 1002 and executed by one or more processors 1004, contribute to a runtime image 1014 controlling the operation of one or more processors 1004. Some instructions, when executed, cause processing circuitry 1002 to perform functions according to certain methods, algorithms, and processes described herein.

[0077] Some software modules in software module 1016 may be loaded during the initialization of processing circuit 1002, and these software modules 1016 may configure processing circuit 1002 to perform the various functions disclosed herein. For example, some software modules 1016 may configure the internal devices and / or logic circuit 1022 of processor 1004, and may manage access to external devices such as transceivers 1012a, 1012b, bus interface 1008, user interface 1018, timers, math coprocessors, etc. Software module 1016 may include control programs and / or operating systems that interact with interrupt handlers and device drivers and control access to various resources provided by processing circuit 1002. Resources may include memory, processing time, access to transceivers 1012a, 1012b, user interface 1018, etc.

[0078] One or more processors 1004 of the processing circuitry 1002 can be multifunctional, whereby some software modules in software module 1016 are loaded and configured to perform different functions or different instances of the same function. One or more processors 1004 may additionally be adapted to manage background tasks initiated in response to inputs, for example, from user interface 1018, transceivers 1012a, 1012b, and device drivers. To support the execution of multiple functions, one or more processors 1004 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks to be served by one or more processors 1004 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 1020 that transfers control of the processors 1004 between different tasks, whereby each task returns control of one or more processors 1004 to the time-sharing program 1020 upon completion of any incomplete operation and / or in response to inputs such as interrupts. When a task has control over one or more processors 1004, the processing circuitry is effectively dedicated to the purpose addressed by the function associated with the control task. The time-sharing program 1020 may include an operating system, a main loop for loop-based transfer control, functions for allocating control of one or more processors 1004 according to function priority, and / or an interrupt-driven main loop for providing control of one or more processors 1004 to processing functions in response to external events.

[0079] Figure 11This is a flowchart 1100 of a method for operating processing circuitry coupled to an imaging device and configured according to certain aspects of this disclosure. At block 1102 of the illustrated method, bus interface circuitry may be configured to communicatively couple the processing circuitry to the imaging device via a multipoint differential serial link. At block 1104 of the illustrated method, a plurality of sequentially occurring signaling states of the multipoint differential serial link may be detected. These sequentially occurring signaling states may be associated with the transmission of data packets via the multipoint differential serial link. At block 1106 of the illustrated method, data packets received after the imaging device is powered on or initialized are discarded until the imaging device is indicated to be in an active operating state. At block 1108 of the illustrated method, a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link is counted. At block 1110 of the illustrated method, the imaging device is indicated to be in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0080] In some implementations, the first signaling state indicates the start of high-speed transmission via the multipoint differential serial link, and the second signaling state indicates the termination of high-speed transmission via the multipoint differential serial link. The first signaling state may correspond to the LP-000 signaling state defined by the protocol specified by the MIPI Alliance. The second signaling state may correspond to the LP-111 signaling state defined by the protocol specified by the MIPI Alliance. Data packets can be received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

[0081] In some examples, the number of data packets to be discarded is defined based on the manufacturer's specifications for the imaging device. Alternatively, the number of data packets to be discarded may be defined based on calibration or empirical results obtained from the initialization of the imaging device.

[0082] In some implementations, each signaling state is verified based on the duration of each of the multiple sequentially occurring signaling states. When one of the multiple sequentially occurring signaling states is determined to be invalid, the counting of the transition sequence can be reset and / or restarted.

[0083] Figure 12This is a diagram illustrating a first example of a hardware implementation of a device 1200 employing processing circuitry 1202. The processing circuitry typically has one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines, and is typically represented by processor 1216. Processing circuitry 1202 can be implemented using a bus architecture, typically represented by bus 1220. Bus 1220 may include any number of interconnect buses and bridges, depending on the specific application of processing circuitry 1202 and overall design constraints. Bus 1220 links together various circuits including multiple processors 1216, modules or circuits 1204, 1206, and 1208, and processor-readable storage medium 1218. Bus interface circuitry and / or modules 1214 may be provided to support communication via multiple serial links 1212. Bus 1220 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and will therefore not be described further.

[0084] Processor 1216 may be responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1218. Processor-readable storage medium 1218 may include non-transitory storage medium. When executed by processor 1216, the software causes processing circuitry 1202 to perform the various functions described above for any particular device. Processor-readable storage medium may be used to store data manipulated by processor 1216 when executing the software. Processing circuitry 1202 further includes at least one of modules 1204, 1206, and 1208. Modules 1204, 1206, and 1208 may be software modules residing in / stored in processor-readable storage medium 1218, running in processor 1216, one or more hardware modules coupled to processor 1216, or some combination thereof. Modules 1204, 1206, and 1208 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0085] In one configuration, the apparatus 1200 includes: a module and / or circuitry 1204 adapted to measure the duration of signaling states of a multi-point differential serial link; a module and / or circuitry 1206 adapted to detect a sequence of signaling states corresponding to transition signaling; and a module and / or circuitry 1208 adapted to manage transitions between operating modes (including a high-speed mode and a low-power mode). Managing transitions between operating modes may include controlling or configuring signals indicating when the imaging device operates in a normal, nominal, or active operating state.

[0086] The apparatus 1200 may include: components for configuring bus interface circuitry to communicatively couple the apparatus to an imaging device via a multipoint differential serial link; components for detecting a plurality of sequentially occurring signaling states of the multipoint differential serial link; and components for counting a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link. The plurality of sequentially occurring signaling states may be associated with or indicate the transmission of data packets via the multipoint differential serial link. Data packets received after the imaging device is powered on or initialized may be discarded until the imaging device is indicated to be in an active operating state. The imaging device may be indicated to be in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0087] In some implementations, the first signaling state indicates the start of high-speed transmission via the multipoint differential serial link. The second signaling state may indicate the termination of high-speed transmission via the multipoint differential serial link. The first signaling state corresponds to the LP-000 signaling state defined by the protocol specified by the MIPI Alliance, and the second signaling state corresponds to the LP-111 signaling state defined by the protocol specified by the MIPI Alliance. Data packets can be received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

[0088] In some examples, the number of data packets to be discarded is defined based on the manufacturer's specifications for the imaging device. In other examples, the number of data packets to be discarded may be defined based on calibration or empirical results obtained from the initialization of the imaging device.

[0089] The component used to detect multiple sequentially occurring signaling states can be configured to verify each signaling state based on the duration of each of the multiple sequentially occurring signaling states. When one of the multiple sequentially occurring signaling states is determined to be invalid, the counting of the transition sequence can be reset or restarted.

[0090] In one aspect, processing circuitry 1202 is coupled to an imaging device and includes: bus interface circuitry configured to communicatively couple processing circuitry 1202 to the imaging device via a multipoint differential serial link 1212; detector circuitry configured to detect a plurality of sequentially occurring signaling states of the multipoint differential serial link 1212; and a controller. The plurality of sequentially occurring signaling states may be associated with or indicate the transmission of data packets via the multipoint differential serial link 1212. The controller may be configured to: discard data packets received after the imaging device is powered on or initialized until the imaging device is indicated to be in an active operating state; count a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link 1212; and indicate that the imaging device is in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0091] In some implementations, the first signaling state indicates the start of high-speed transmission via the multipoint differential serial link 1212. The second signaling state may indicate the termination of high-speed transmission via the multipoint differential serial link 1212. The first signaling state corresponds to the LP-000 signaling state defined by the protocol specified by the MIPI Alliance, and the second signaling state may correspond to the LP-111 signaling state defined by the same protocol specified by the MIPI Alliance. Data packets can be received via the multipoint differential serial link 1212 between each transition from the first signaling state to the second signaling state.

[0092] In some examples, the number of data packets to be discarded is defined based on the manufacturer's specifications for the imaging device. Alternatively, the number of data packets to be discarded may be defined based on calibration or empirical results obtained from the initialization of the imaging device.

[0093] In some specific implementations, the detector circuitry is further configured to verify each signaling state based on the duration of each of the plurality of sequentially occurring signaling states. The controller may be further configured to reset the count for the transition sequence when one of the plurality of sequentially occurring signaling states is determined to be invalid.

[0094] The processor-readable storage medium 1218 may include instructions that, when executed by the processing circuitry 1202, cause the processing circuitry 1202 to: configure bus interface circuitry to communicatively couple the processing circuitry 1202 to the imaging device via a multipoint differential serial link 1212; detect a plurality of sequentially occurring signaling states of the multipoint differential serial link 1212, the plurality of sequentially occurring signaling states being associated with the transmission of data packets via the multipoint differential serial link 1212; discard data packets received after the imaging device is powered on or initialized until the imaging device is indicated to be in an active operating state; count a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link 1212; and indicate that the imaging device is in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0095] In some implementations, the first signaling state indicates the start of high-speed transmission via the multipoint differential serial link 1212, and the second signaling state indicates the termination of high-speed transmission via the multipoint differential serial link 1212. The first signaling state may correspond to the LP-000 signaling state defined by the protocol specified by the MIPI Alliance. The second signaling state may correspond to the LP-111 signaling state defined by the protocol specified by the MIPI Alliance. Data packets can be received via the multipoint differential serial link 1212 between each transition from the first signaling state to the second signaling state.

[0096] In some examples, the number of data packets to be discarded is defined based on the manufacturer's specifications for the imaging device. Alternatively, the number of data packets to be discarded may be defined based on calibration or empirical results obtained from the initialization of the imaging device.

[0097] In some specific implementations, the instruction further instructs the processing circuit 1202 to: verify each signaling state based on the duration of each of the plurality of sequentially occurring signaling states, and reset the count of the transition sequence when one of the plurality of sequentially occurring signaling states is determined to be invalid.

[0098] Some specific implementation examples are described in the following numbered clauses:

[0099] 1. A processing circuit coupled to an imaging device, the processing circuit comprising: a bus interface circuit configured to communicatively couple the processing circuit to the imaging device via a multi-point differential serial link;

[0100] A detector circuit configured to detect a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets through the multipoint differential serial link; and a controller configured to: discard data packets received after the imaging device is powered on or initialized until the imaging device is indicated to be in an active operating state; count the transition sequence between a first signaling state and a second signaling state of the multipoint differential serial link; and indicate that the imaging device is in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0101] 2. The processing circuitry according to Clause 1, wherein the first signaling state indicates the start of high-speed transmission via the multi-point differential serial link, and wherein the second signaling state indicates the termination of high-speed transmission via the multi-point differential serial link.

[0102] 3. The processing circuitry according to Clause 2, wherein the first signaling state corresponds to the LP-000 signaling state defined by the protocol specified by the Mobile Industrial Processor Interface (MIPI) Alliance, and wherein the second signaling state corresponds to the LP-000 signaling state defined by the MIPI Alliance.

[0103] The LP-111 signaling state defined by the protocol specified by the Alliance corresponds to this.

[0104] 4. The processing circuitry according to Clause 2 or Clause 3, wherein data packets are received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

[0105] 5. The processing circuit according to any one of clauses 1 to 4, wherein the number of data packets to be discarded is defined based on the manufacturer's specifications of the imaging device.

[0106] 6. The processing circuit according to any one of clauses 1 to 5, wherein the number of data packets to be discarded is defined based on calibration or empirical results obtained from the initialization of the imaging device.

[0107] 7. The processing circuit according to any one of clauses 1 to 6, wherein the detector circuit is further configured to verify each signaling state based on the duration of each of the plurality of sequentially occurring signaling states, and

[0108] The controller is further configured to reset the count of the transition sequence when one of the plurality of sequentially occurring signaling states is determined to be invalid.

[0109] 8. A method for operating processing circuitry coupled to an imaging device, the method comprising: configuring bus interface circuitry to communicatively couple the processing circuitry to the imaging device via a multipoint differential serial link; detecting a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets via the multipoint differential serial link; discarding data packets received after the imaging device is powered on or initialized until the imaging device is indicated to be in an active operating state; counting a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link; and indicating that the imaging device is in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0110] 9. The method according to Clause 8, wherein the first signaling status indicates high-speed transmission via the multi-point differential serial link.

[0111] The transmission begins, and the second signaling status indicates the termination of high-speed transmission via the multi-point differential serial link.

[0112] 10. The method according to Clause 9, wherein the first signaling state corresponds to the LP-000 signaling state defined by the protocol specified by the Mobile Industrial Processor Interface (MIPI) Alliance, and wherein the second signaling state corresponds to the LP-111 signaling state defined by the protocol specified by the MIPI Alliance.

[0113] 11. The method according to Clause 9 or Clause 10, wherein data packets are received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

[0114] 12. The method according to any one of clauses 8 to 11, wherein the number of data packets to be discarded is defined based on the manufacturer's specifications of the imaging device.

[0115] 13. The method according to any one of clauses 8 to 12, wherein the number of data packets to be discarded is defined based on calibration or empirical results obtained from the initialization of the imaging device.

[0116] 14. The method according to any one of Clauses 8 to 13, the method further comprising: verifying each signaling state based on the duration of each of the plurality of sequentially occurring signaling states; and resetting the count of the transition sequence when one of the plurality of sequentially occurring signaling states is determined to be invalid.

[0117] 15. An apparatus comprising: means for configuring bus interface circuitry to communicatively couple the apparatus to an imaging device via a multipoint differential serial link; means for detecting a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets via the multipoint differential serial link; and means for counting a transition sequence between a first signaling state and a second signaling state of the multipoint differential serial link, wherein data packets received after the imaging device is powered on or initialized are discarded until the imaging device is indicated to be in an active operating state, and wherein, in a pre-configured...

[0118] After a number (N) of data packets have been discarded, the imaging device is indicated to be in the active operating state.

[0119] 16. The apparatus according to Clause 15, wherein the first signaling state indicates the start of high-speed transmission via the multipoint differential serial link, and wherein the second signaling state indicates the termination of high-speed transmission via the multipoint differential serial link.

[0120] 17. The apparatus according to Clause 16, wherein the first signaling state corresponds to the LP-000 signaling state defined by the protocol specified by the Mobile Industrial Processor Interface (MIPI) Alliance, and wherein the second signaling state corresponds to the LP-111 signaling state defined by the protocol specified by the MIPI Alliance.

[0121] 18. The apparatus according to Clause 16 or Clause 17, wherein data packets are received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

[0122] 19. The apparatus according to any one of clauses 15 to 18, wherein the number of data packets to be discarded is defined based on the manufacturer's specifications of the imaging device.

[0123] 20. The apparatus according to any one of clauses 15 to 19, wherein the number of data packets to be discarded is defined based on calibration or empirical results obtained from the initialization of the imaging device.

[0124] 21. The apparatus according to any one of claims 15 to 20, wherein the component for detecting a plurality of sequentially occurring signaling states is configured to verify each signaling state based on the duration of each of the plurality of sequentially occurring signaling states, and wherein when one of the plurality of sequentially occurring signaling states is determined to be invalid, the count of the transition sequence is reset.

[0125] 22. A processor-readable storage medium comprising code, which, when executed by processing circuitry, causes the processing circuitry to: configure bus interface circuitry to communicatively couple the processing circuitry to an imaging device via a multipoint differential serial link; detect a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets via the multipoint differential serial link; discard data packets received after the imaging device is powered on or initialized until the imaging device is indicated to be in an active operating state; count a sequence of transitions between a first signaling state and a second signaling state of the multipoint differential serial link; and indicate that the imaging device is in the active operating state after a pre-configured number (N) of data packets have been discarded.

[0126] 23. The processor-readable storage medium according to Clause 22, wherein the first signaling state indicates the start of high-speed transmission via the multipoint differential serial link, and wherein the second signaling state indicates the termination of high-speed transmission via the multipoint differential serial link.

[0127] 24. The processor-readable storage medium according to Clause 23, wherein the first signaling state corresponds to the LP-000 signaling state defined by the protocol specified by the Mobile Industrial Processor Interface (MIPI) Alliance, and wherein the second signaling state corresponds to the LP-111 signaling state defined by the protocol specified by the MIPI Alliance.

[0128] 25. A processor-readable storage medium as described in Clause 23 or Clause 24, wherein data packets are received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

[0129] 26. A processor-readable storage medium according to any one of clauses 22 to 25, wherein the number of data packets to be discarded is defined based on the manufacturer's specifications of the imaging device.

[0130] 27. A processor-readable storage medium according to any one of clauses 22 to 26, wherein the number of data packets to be discarded is defined based on calibration or empirical results obtained from the initialization of the imaging device.

[0131] 28. A processor-readable storage medium according to any one of clauses 22 to 27, wherein the code further causes the processing circuitry to: verify each signaling state based on the duration of each of the plurality of sequentially occurring signaling states; and reset the count of the transition sequence when one of the plurality of sequentially occurring signaling states is determined to be invalid.

[0132] It should be understood that the specific order or hierarchy of the steps in the disclosed process is an example of the exemplary method. It should be understood that the specific order or hierarchy of the steps in these processes can be rearranged according to design preferences. Furthermore, some steps can be combined or omitted. The appended method claims present elements of multiple steps in a sample order, but are not intended to limit one to the specific order or hierarchy presented.

[0133] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be consistent with the full scope of the language of the claims, wherein an element referred to in the singular is not intended to mean “one and only one,” but rather “one or more” unless specifically stated otherwise. Unless otherwise stated, the term “some” means one or more. All structural and functional equivalents of the elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is expressly recited in the claims. No claim element should be construed as a component plus a function unless the element is expressly stated using the phrase “component for…”.

Claims

1. A processing circuit coupled to an imaging device, the processing circuit comprising: A bus interface circuit, configured to communicatively couple the processing circuit to the imaging device via a multi-point differential serial link; A detector circuit configured to detect a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being associated with the transmission of data packets through the multipoint differential serial link; and The controller is configured to: Data packets received after the imaging device is powered on or initialized are discarded until the imaging device is indicated to be in an active operating state; The number of transitions between the first signaling state and the second signaling state of the multipoint differential serial link is counted, wherein the number of transitions corresponds to the number of data packets dropped; as well as after a preconfigured number of data packets have been discarded N indicating that the imaging device is in the active operating state.

2. The processing circuit according to claim 1, wherein the first signaling state indicates the start of high-speed transmission via the multi-point differential serial link, and wherein the second signaling state indicates the termination of high-speed transmission via the multi-point differential serial link.

3. The processing circuit according to claim 2, wherein the first signaling state corresponds to the LP-000 signaling state defined by the protocol specified by the Mobile Industrial Processor Interface (MIPI) Alliance, and wherein the second signaling state corresponds to the LP-111 signaling state defined by the protocol specified by the MIPI Alliance.

4. The processing circuit of claim 2, wherein data packets are received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

5. The processing circuitry of claim 1, wherein the number of data packets to be discarded is defined based on the manufacturer's specifications of the imaging device.

6. The processing circuitry of claim 1, wherein the number of data packets to be discarded is defined based on calibration or empirical results obtained from the initialization of the imaging device.

7. The processing circuit of claim 1, wherein the detector circuit is further configured to verify each signaling state based on the duration of each of the plurality of sequentially occurring signaling states, and wherein the controller is further configured to: reset the count of the number of transitions when one of the plurality of sequentially occurring signaling states is determined to be invalid by the detector circuit.

8. A method for operating processing circuitry coupled to an imaging device, the method comprising: Configure the bus interface circuitry to communicatively couple the processing circuitry to the imaging device via a multi-point differential serial link; Detect multiple sequentially occurring signaling states of the multipoint differential serial link, the multiple sequentially occurring signaling states being related to the transmission of data packets through the multipoint differential serial link; Data packets received after the imaging device is powered on or initialized are discarded until the imaging device is indicated to be in an active operating state; The number of transitions between the first signaling state and the second signaling state of the multipoint differential serial link is counted, wherein the number of transitions corresponds to the number of data packets dropped; as well as after a preconfigured number of data packets have been discarded N indicating that the imaging device is in the active operating state.

9. The method of claim 8, wherein the first signaling state indicates the start of high-speed transmission via the multi-point differential serial link, and wherein the second signaling state indicates the termination of high-speed transmission via the multi-point differential serial link.

10. The method of claim 9, wherein the first signaling state corresponds to the LP-000 signaling state defined by the protocol specified by the Mobile Industrial Processor Interface (MIPI) Alliance, and wherein the second signaling state corresponds to the LP-111 signaling state defined by the protocol specified by the MIPI Alliance.

11. The method of claim 9, wherein data packets are received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

12. The method of claim 8, wherein the number of data packets to be discarded is defined based on the manufacturer's specifications of the imaging device.

13. The method of claim 8, wherein the number of data packets to be discarded is defined based on calibration or empirical results obtained from the initialization of the imaging device.

14. The method of claim 8, further comprising: Each signaling state is verified based on the duration of each of the plurality of sequentially occurring signaling states; as well as When one of the multiple sequentially occurring signaling states is determined to be invalid, the count of the transition count is reset.

15. An apparatus for operating processing circuitry coupled to an imaging device, the apparatus comprising: Components for configuring bus interface circuitry to communicatively couple the device to an imaging device via a multi-point differential serial link; A component for detecting a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states being related to the transmission of data packets through the multipoint differential serial link; and A component for counting the number of transitions between the first signaling state and the second signaling state of the multipoint differential serial link, wherein the number of transitions corresponds to the number of data packets dropped; Data packets received after the imaging device is powered on or initialized are discarded until the imaging device is indicated to be in an active operating state. wherein the imaging device is instructed to be in the active operating state after a preconfigured number of data packets have been discarded N ​ 16. The apparatus of claim 15, wherein the first signaling state indicates the start of high-speed transmission via the multipoint differential serial link, and wherein the second signaling state indicates the termination of high-speed transmission via the multipoint differential serial link.

17. The apparatus of claim 16, wherein the first signaling state corresponds to an LP-000 signaling state defined by a protocol specified by the Mobile Industrial Processor Interface (MIPI) Alliance, and wherein the second signaling state corresponds to an LP-111 signaling state defined by the protocol specified by the MIPI Alliance.

18. The apparatus of claim 16, wherein data packets are received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

19. The apparatus of claim 15, wherein the number of data packets to be discarded is defined based on the manufacturer's specifications of the imaging device.

20. The apparatus of claim 15, wherein the number of data packets to be discarded is defined based on calibration or empirical results obtained from the initialization of the imaging device.

21. The apparatus of claim 15, wherein the component for detecting a plurality of sequentially occurring signaling states is configured to verify each signaling state based on the duration of each of the plurality of sequentially occurring signaling states, and wherein when one of the plurality of sequentially occurring signaling states is determined to be invalid, the count of the number of transitions is reset.

22. A non-transitory processor-readable storage medium, the non-transitory processor-readable storage medium comprising code, the code causing the processing circuitry, when executed by processing circuitry, to: Configure the bus interface circuitry to communicatively couple the processing circuitry to the imaging device via a multi-point differential serial link; Detect multiple sequentially occurring signaling states of the multipoint differential serial link, the multiple sequentially occurring signaling states being related to the transmission of data packets through the multipoint differential serial link; Data packets received after the imaging device is powered on or initialized are discarded until the imaging device is indicated to be in an active operating state; The number of transitions between the first signaling state and the second signaling state of the multi-point differential serial link is counted, wherein... The number of transformations corresponds to the number of data packets that are discarded. as well as after a preconfigured number of data packets have been discarded N indicating that the imaging device is in the active operating state.

23. The non-transitory processor-readable storage medium of claim 22, wherein the first signaling state indicates the start of high-speed transmission via the multi-point differential serial link, and wherein the second signaling state indicates the termination of high-speed transmission via the multi-point differential serial link.

24. The non-transitory processor-readable storage medium of claim 23, wherein the first signaling state corresponds to the LP-000 signaling state defined by the protocol specified by the Mobile Industrial Processor Interface (MIPI) Alliance, and wherein the second signaling state corresponds to the LP-111 signaling state defined by the protocol specified by the MIPI Alliance.

25. The non-transitory processor-readable storage medium of claim 23, wherein data packets are received via the multipoint differential serial link between each transition from the first signaling state to the second signaling state.

26. The non-transitory processor-readable storage medium of claim 22, wherein the number of data packets to be discarded is defined based on the manufacturer's specifications of the imaging device.

27. The non-transitory processor-readable storage medium of claim 22, wherein the number of data packets to be discarded is defined based on calibration or empirical results obtained from the initialization of the imaging device.

28. The non-transitory processor-readable storage medium of claim 22, wherein the code further enables the processing circuitry to: Each signaling state is verified based on the duration of each of the plurality of sequentially occurring signaling states; and When one of the multiple sequentially occurring signaling states is determined to be invalid, the count of the transition count is reset.

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