Compiler for risc processors with dedicated registers

Abstract

A compiler is disclosed. The compiler is configured to generate executable code based on source code, wherein the source code includes a plurality of variables. The compiler includes an executable code generator configured to allocate a register for each source code variable, wherein the executable code generator is configured to: select a register type to allocate for each variable from a set of register types, wherein the allocated register for each variable corresponds to a determined register type determined for that variable.

Description

[0001] This disclosure claims priority to U.S. non-provisional patent application No. 17 / 037,487, filed on September 29, 2020, entitled “COMPILER FOR RISC PROCESSORHAVING SPECIALIZED REGISTERS”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The topics described in this article relate to compilers for RISC processor architectures, and more specifically, to compilers for RISC processor architectures with dedicated registers. Background Technology

[0003] The compiler generates executable code based on high-level language code. As part of generating the executable code, variables in the high-level language are associated with registers, which are memory elements in the processor used to execute the executable code. Within the processor, registers reside in register files, which serve as temporary memory storage locations for computations performed by the processor to execute the executable code. Register files are used to store various types of computational variables, and therefore each register file is configured for each type of computational variable. Because each register file is capable of being used for each type of computational variable, each register file is implemented with memory circuitry having all the features required for each computational variable. Therefore, each register file requires a certain amount of die area. In this art, register files requiring less die area are needed. Summary of the Invention

[0004] One aspect of the invention is a compiler configured to generate executable code based on source code, wherein the source code includes multiple variables. The compiler includes an executable code generator configured to allocate registers for each source code variable, wherein the executable code generator is configured to select a register type from a set of register types for allocation to each variable, wherein the allocated register for each variable corresponds to a specific register type determined for that variable.

[0005] In some embodiments, the set of register types includes: a first register of a first register file, the first register file including a first number of read ports and write ports; and a second register of a second register file, the second register file including a second number of read ports and write ports, wherein the first number of read ports and write ports and the second number of read ports and write ports are different.

[0006] In some embodiments, the executable code generator is configured to select the register type allocated to each variable by determining how many read ports and write ports the registers allocated to each variable will require when executed.

[0007] In some embodiments, the executable code generator is configured to select the register type assigned to each variable by determining which register types among the register types are suitable for the execution time requirements of each variable.

[0008] In some embodiments, the executable code generator is configured to receive intermediate code generated by the compiler, wherein selecting the register type allocated for each variable includes determining how the variable is used in the intermediate code.

[0009] In some embodiments, the executable code generator is configured to select the register type assigned to each variable by determining which register types among the register types are suitable for the execution time requirements of each variable.

[0010] In some embodiments, the executable code generator is configured to select the register type to be assigned to the particular variable by determining one or more register types to suit the execution time requirements of the particular variable.

[0011] In some embodiments, the executable code generator is configured to select the register type allocated for a particular variable by selecting one of the register types that requires less power to operate compared to other register types that meet the execution time requirements of the particular variable.

[0012] In some embodiments, the executable code generator is configured to select the register type allocated for a particular variable by selecting one of the register types that meet the execution time requirements of the particular variable based on the unused state of a register file that retains registers of one of the register types that meet the execution time requirements of the particular variable.

[0013] In some embodiments, the executable code generator is further configured to: allocate registers of a first register type to variables determined for the first register type as a first register allocation problem, and allocate registers of a second register type to variables determined for the second register type as a second register allocation problem.

[0014] Another aspect of the present invention is a method for generating executable code based on source code using a compiler, wherein the source code includes multiple variables. The method includes using an executable code generator to select a register type to allocate for each variable from a set of register types; and using the executable code generator to allocate a register for each source code variable, wherein the allocated register for each variable corresponds to a specific register type determined for that variable.

[0015] In some embodiments, the set of register types includes: a first register of a first register file, the first register file including a first number of read ports and write ports; and a second register of a second register file, the second register file including a second number of read ports and write ports, wherein the first number of read ports and write ports is different from the second number of read ports and write ports.

[0016] In some embodiments, selecting the register type allocated to each variable includes determining how many read ports and write ports the register allocated to each variable requires when executed.

[0017] In some embodiments, selecting the register type assigned to each variable includes determining which register types among the register types are suited to the execution time requirements of each variable.

[0018] In some embodiments, the method further includes: receiving intermediate code generated by the compiler using the executable code generator, wherein selecting the register type allocated for each variable includes determining how the variable is used in the intermediate code.

[0019] In some embodiments, selecting the register type to assign to each variable includes determining which of the register types are suitable for the execution time requirements of each variable.

[0020] In some embodiments, selecting the register type to assign to a particular variable includes determining one or more register types to suit the execution time requirements of the particular variable.

[0021] In some embodiments, selecting a register type to allocate for a particular variable includes selecting one of the register types that requires less power to operate compared to other register types that meet the execution time requirements of the particular variable.

[0022] In some embodiments, selecting the register type to be allocated for a particular variable includes selecting one of the register types that meet the execution time requirements of the particular variable based on the unused state of a register file that retains registers of one of the register types that meet the execution time requirements of the particular variable.

[0023] In some embodiments, the method further includes: using the executable code generator to allocate registers of a first register type to variables determined for the first register type as a first register allocation problem, and to allocate registers of a second register type to variables determined for the second register type as a second register allocation problem. Attached Figure Description

[0024] The accompanying drawings, which are included in and form part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the specification, help to illustrate some principles associated with the disclosed implementations.

[0025] Figure 1 This is a schematic diagram of an embodiment of the processor circuit.

[0026] Figure 2 This is a flowchart illustrating a method for generating executable code based on high-level language code.

[0027] Figure 3 It is shown as Figure 2 The flowchart is part of the method for allocating registers.

[0028] Figure 4 The illustration shows an example of executable code generated from high-level language code.

[0029] Figure 5 The diagram illustrates the configuration of a computer system constructed in accordance with this disclosure.

[0030] In practical applications, similar reference numerals indicate similar structures, features, or elements. Detailed Implementation

[0031] This article illustrates specific embodiments of the present invention in conjunction with the accompanying drawings.

[0032] This document sets forth various details because they relate to certain embodiments. However, the invention may also be practiced in ways different from those described herein. Modifications to the discussed embodiments can be made by those skilled in the art without departing from the invention. Therefore, the invention is not limited to the specific embodiments disclosed herein.

[0033] The processor register file interfaces with the data path circuitry based on the number of read and write ports it has. The embodiments discussed herein disclose a data path circuitry that interfaces with a dedicated register file having a specific number of read and write ports.

[0034] Processors, such as RISC processors, use a LOAD / CALCULATE / STORE process to handle instructions. In this process, data is loaded into one or more registers, computation is performed on the register data using data path blocks with multiple data path blocks, and the computation results from the data path blocks are stored in one or more registers. Read and write access is provided to each register through read and write ports on both the memory and data path blocks. For implementation, designers determine the number of registers and register files based on trade-offs such as execution speed and circuit die area. Furthermore, designers determine the number of read and write ports for both the memory and the data paths to be used in the register files. Each register file requires a certain amount of circuit die area and a certain amount of power.

[0035] In some embodiments, some register files can be used as general-purpose register files, which have the designed number of each port type. Furthermore, the result variable register file can have two read ports and one write port, and the constant variable register file can have one read port and one write port. In some embodiments, other register files with different port configurations can be used. Because result variable registers and constant variable registers use fewer ports, they use less area and less power. Therefore, for the same number of registers, using these dedicated registers instead of multiple general-purpose registers uses less circuit die area and less power.

[0036] The embodiments of the data path circuitry disclosed herein allow dedicated data path circuitry to interface with dedicated registers. Embodiments of the register files disclosed herein include general-purpose register files having a defined number of read and write ports for memory and data paths, and also dedicated registers that use a different number of ports depending on how each register is to be used.

[0037] A compiler for generating executable code from source code is discussed, wherein the executable code can be executed on processors with various types of register files. References Figure 1 The functionality of a specific processor circuit with a data register file, instruction decoder, and data path block is discussed.

[0038] Figure 1 This is a schematic diagram of an embodiment of processor circuitry 100 that interfaces with memory 50. Processor circuitry 100 includes data register file circuitry 120, data path block circuitry 140, and instruction decoder circuitry 160. (See reference) Figure 2 and Figure 3 Methods for compiling source code are discussed. (References) Figure 4 Examples of source code, intermediate code, and executable code are discussed. References Figure 5 The configuration of a computer system built based on this disclosure is discussed.

[0039] Processor circuitry 100 can be used as part of a central processing unit (CPU) having other processor circuitry known to those skilled in the art. In some embodiments, processor circuitry having features different from those specifically discussed herein may be used.

[0040] As shown in the figure, in this embodiment, each data register file of the data register file circuit 120 includes one of the following:

[0041] Five read ports and two write ports are used to interface with the data path block circuit 140, and one read port and one write port are used to interface with the memory 50.

[0042] A read port and a write port for interfacing with data path block circuit 140, and a read port for interfacing with memory 50; and

[0043] A read port for interfacing with data path block circuit 140, and a write port for interfacing with memory 50.

[0044] The registers of the data register file, which have five read ports and two write ports for interfacing with the data path block circuit 140, and one read port and one write port for interfacing with the memory 50, can be used, for example, as general-purpose registers.

[0045] The register of the data register file, which has a read port and a write port for interfacing with the data path block circuit 140 and a read port for interfacing with the memory 50, can be used, for example, as a result register that stores the result of the computation operation, wherein the result can be stored in the memory 50.

[0046] The registers in the data register file, which have a read port for interfacing with data path block circuit 140 and a write port for interfacing with memory 50, can be used, for example, as constant registers that store constants that do not change due to numerous data path instructions. For instance, a set of data path instructions may be associated with a loop in source code compiled to generate the data path instructions, and the constant register can be used to store values ​​of constants that do not change during the execution of the data path instructions associated with that loop.

[0047] In other embodiments, a register file with an additional number of ports interfaced with the data path block circuit 140 may be used. In other embodiments, a register file with an additional number of ports interfaced with the memory 50 may be used.

[0048] For example, in some embodiments, one or more register files have a read port and a write port for interfacing with data path block circuit 140, and a write port for interfacing with memory. The registers in these register files can be used for variables that are initialized before loop execution, used and modified within the loop, but not used in other code. These registers can be assigned to other variables when their port configuration is suitable for those variables.

[0049] In some embodiments, one or more register files have a write port for interfacing with data path block circuit 140 and a read port for interfacing with memory 50. The registers in these register files can be used for variables, for example, variables created in a loop and subsequently used in other code. These registers can be assigned to other variables when their port configuration is suitable for those variables.

[0050] As those skilled in the art will understand, the memory circuit 50 can be any memory structure. The memory circuit 50 stores at least processing instructions and data. After the processor circuit 100 receives the instructions and data, the processor circuit 100 performs an operation using the read data based on the read instruction.

[0051] Instruction decoder circuit 160 is configured to receive data path instructions from memory circuit 50, wherein the data path instructions cause data path block circuit 140 to produce results stored in data register file circuit 120. Each data path instruction encodes at least the following: the data path operation to be performed, a result register in data register file circuit 120 to store the result of the data path operation, and one or more operand registers in data register file circuit 120 storing data to be used as operands for the data path operation. As those skilled in the art will understand, for some data path instructions, the result register storing the result of the data path operation is the same as the operand register storing the data to be used as operands for the data path operation.

[0052] Based on the data path instructions received from the memory circuit 50, the instruction decoder circuit 160 is configured to generate register signals for the data register file circuit 120, which encode the following: one or more result registers for storing one or more results of one or more data path operations; a write port for each result register for writing one or more results of one or more data path operations to one or more result registers; one or more operand registers within the data register file circuit 120 for storing data to be used as operands for one or more data path operations; and a read port for each operand register for reading operand data from the operand register.

[0053] Furthermore, based on the data path instructions received from the memory circuit 50, the instruction decoder circuit 160 is configured to generate operation signals for the data path block circuit 140, which encode the following: one or more operations to be performed; a write port for each result register, which is to be used to write one or more results of one or more data path operations to one or more result registers; and a read port for each operand register, which is to be used to read operand data from the operand register.

[0054] The data register file circuit 120 is configured to receive register signals from the instruction decoder circuit 160, the register signals encoding the following: one or more result registers; a write port for each result register, for writing one or more results of one or more data path operations to one or more result registers; one or more operand registers; and a read port for each operand register, for reading operand data from the operand register.

[0055] Based on register signals received from instruction decoder circuit 160 that encode one or more registers storing data to be used as operands in one or more data path operations, data register file circuit 120 generates operand data signals for data path block circuit 140. For example, the register signals may identify a specific register file and a specific register within that specific register file for each of the one or more registers storing data to be used as operands in one or more data path operations. In response to the register signals, data from the identified specific register is read and provided as operand data signals to data path block circuit 140.

[0056] Based on the register signal received from the instruction decoder circuit 160, which identifies the read port of each operand register from which operand data is to be read, the data register file circuit 120 reads data from the identified specific register and provides the read data to the read port identified in the received register signal.

[0057] Data path block 140 is configured to receive from instruction decoder circuit 160 operation signals that encode one or more data path operations to be performed. Furthermore, data path block 140 is configured to receive from instruction decoder circuit 160 operation signals that identify the read port for each operand data signal to be used to read operand data.

[0058] Based on the received operation signal, the data path block 140 accesses the identified read port of the data register file circuit 120 to receive the operand data signal, which encodes the data to be used as operands for one or more data path operations.

[0059] Data path block 140 includes multiple logic circuits, each configured to receive a specific number of operands. Each logic circuit is also configured to perform a specific data path operation based on the received operand data signals to generate one or more results. For example, data path block 140 may include one or more of each of the following logic circuits: shifter, adder, and multiplier. As those skilled in the art will understand, data path block 140 may additionally include one or more of each of a plurality of other logic circuits.

[0060] Based on the received operation signals encoded for one or more data path operations to be performed, data path block 140 selects one or more logic circuits. As a result of the selection, the selected logic circuit receives operand data signals encoded for the operands to be used as one or more data path operations.

[0061] As understood by those skilled in the art, in response to operand data signals, the selected logic circuit generates one or more results according to the logic circuit system of the selected logic circuit.

[0062] One or more results generated are provided to the data register file circuit 120.

[0063] In some embodiments, data path block 140 includes a plurality of separate data paths, each data path including a plurality of shifters, adders, multipliers, and other data path logic circuits. In these embodiments, each data path is used to compute a separate result simultaneously. Therefore, in these embodiments, operation signals received by data path block 140 from instruction decoder circuit 160 encode one or more data path operations to be performed using one or more separate data paths. Furthermore, operand data signals received by data path block 140 from data register file circuit 120 encode data to be used as operands for one or more data path operations to be performed using one or more separate data paths.

[0064] Based on the following operation signal received from the instruction decoder circuit 160, which identifies the write port of each result register to be used to write one or more results to one or more result registers of the data register file circuit 120, the data path block circuit 140 provides one or more results to the identified one or more write ports of the data register file circuit 120.

[0065] Based on the following register signal from the instruction decoder 160: the register signal identifies one or more result registers to store one or more results and the write port of each result register to be written, one or more results provided to the identified write port of the data register file circuit 120 are written to the designated register within the data register file circuit 120.

[0066] In some embodiments, instruction decoder circuit 160 decodes one or more data path instructions, and data path block circuit 140 receives operand data signals from data register file circuit 120 and provides one or more results to data register file circuit 120. These one or more results are written to data register file circuit 120 in a single CPU clock cycle. In response to an indication of a new clock cycle, instruction decoder circuit 160 decodes one or more data path instructions. Furthermore, data path block circuit 140 receives operation signals from instruction decoder 160, receives operand data signals from data register file circuit 120, calculates one or more results, and provides these one or more results to data register file circuit 120, which stores the one or more results in one or more registers specified in the one or more data path instructions received by instruction decoder circuit 160.

[0067] The instruction decoder circuit 160 is also configured to receive memory instructions from the memory circuit 50, wherein the memory instructions cause data to be read from or written from the register file circuit 120 to the memory circuit 50. Each memory instruction encodes at least the memory operation to be performed (reading from or writing to the register file circuit 120), the registers to be read from or written to the data register file circuit 120, and the address in the memory 50.

[0068] Based on the memory instructions received from the memory circuit 50, the instruction decoder circuit 160 is configured to generate register signals for the data register file circuit 120 that encode the memory instructions.

[0069] The data register file circuit 120 is configured to receive register signals from the instruction decoder circuit 160. Based on the register signals received from the instruction decoder circuit 160, the data register file circuit 120 interacts with the memory circuit according to memory instructions, for example, by reading data from a specified register and writing the read data to a specified address in memory 50, or by reading data from a specified address in memory 50 and writing the read data to a specified register.

[0070] Figure 2 This is a flowchart illustrating a method 200 for generating executable code based on high-level language code, wherein the generated executable code includes instructions that can be executed by a processor, the processor including processor circuitry, for example... Figure 1 The processor circuit 100. To execute executable code, the instructions for the executable code are stored in memory, for example... Figure 1 The memory 50 is provided to the instruction decoder as needed, for example... Figure 1 The instruction decoder 160.

[0071] Method 200 can be executed, for example, by a compiler that translates high-level language code or source code into executable code. By way of example only, method 200 illustrates various specific compiler aspects, features, and procedures. The inventive aspects discussed herein can be practiced using other methods for compiling or generating executable code based on high-level language code.

[0072] At 210, lexical analysis is performed. For example, high-level language code or source code can be scanned into a set of characters and converted into lexical units, where each lexical unit corresponds to a meaningful unit of code, for example, using a lexical analyzer. In some embodiments, the lexical analyzer includes one or more of a tokenizer and a scanner that generates lexical units corresponding to the lexical units. Any of a variety of lexical analyzers known to those skilled in the art can be used.

[0073] At position 220, syntax analysis is performed. For example, the parser may receive tokens from the lexical analyzer and generate a parse tree or syntax tree based on the tokens. Any of a variety of parsers known to those skilled in the art can be used.

[0074] At position 230, semantic analysis is performed. For example, the semantic analyzer may receive a representation of a parse tree or syntax tree and analyze it for semantic errors. For example, the semantic analyzer may search for errors related to process flow, label usage and referencing, and variable data type usage. Any of several semantic analyzers known to those skilled in the art can be used.

[0075] At position 240, intermediate code is generated using the intermediate code generation module. The intermediate code can be mid-level language code. For example, intermediate code can encode the same functionality as high-level language code, but it is less human-readable compared to executable code. Intermediate code may be more suitable for instruction selection and register allocation compared to high-level language code. Any of a variety of techniques known to those skilled in the art can be used to generate the intermediate code.

[0076] At point 250, executable code is generated. Various steps known to those skilled in the art are used to generate the executable code. For example, executable code generation may include instruction selection, register allocation, and any of many other processes. See below for reference. Figure 3 This section discusses examples of methods for allocating registers.

[0077] Figure 3 This is shown as, for example, as a generation Figure 2 The flowchart of method 300, which is part of the method for allocating registers.

[0078] Method 300 can be executed, for example, by a compiler that translates high-level language code or source code into executable code. Method 300 illustrates one embodiment of a register allocation process that allocates registers for the executable code so that it can be executed by a processor with registers of different types, such as those with… Figure 1 The processor circuit of embodiment 100 executes the processor.

[0079] At position 305, the register allocation module receives intermediate code generated from the source code. The intermediate code can, for example, use the reference above. Figure 2 The process of generating method 200 is discussed.

[0080] At 310, the register allocation module analyzes the intermediate code to identify the register type for each variable used in the intermediate code. For example, the occurrence of each variable can be analyzed to determine how that variable is used, thereby identifying which of several register types is used for that variable. For example, the processor may have three types of register files, where each type of register file is characterized, for example, by the number of read ports and write ports it has for each of the processor's memory circuitry and data path block circuitry.

[0081] For example, multiple general-purpose registers can be grouped into one or more general-purpose register files, wherein each general-purpose register file has five read ports and two write ports for interfacing with data path block circuitry, and one read port and one write port for interfacing with memory circuitry.

[0082] In addition, multiple result registers can be grouped into one or more result register files, wherein each result register file has a read port and a write port for interfacing with the data path block circuit, and a read port for interfacing with the storage circuit.

[0083] In addition, multiple constant registers can be grouped into one or more constant register files, wherein each constant register file has a read port for interfacing with data path block circuitry and a write port for interfacing with memory circuitry.

[0084] In some embodiments, multiple additional registers may be grouped into one or more additional register files. Additional register files may be used in place of general-purpose register files, result register files, and constant register files, or as a supplement to general-purpose register files, result register files, and constant register files.

[0085] For example, in some embodiments, multiple other registers are grouped into one or more other register files, each register file having a read port and a write port for interfacing with data path block circuitry, and a write port for interfacing with memory circuitry.

[0086] In some embodiments, multiple other registers are grouped into one or more other register files, each register file having a write port for interfacing with data path block circuitry and a read port for interfacing with memory circuitry.

[0087] To determine which type of register to assign to a specific variable, the register allocation module can analyze the usage of that variable. In some embodiments, the register allocation module determines which type of register to assign to a specific variable based on its usage within a programming loop. For example, the register allocation module can determine which types of registers are suitable for the execution time requirements of each variable based on, for example, the port configuration of the register file for each variable.

[0088] For example, one of the multiple constant registers in a constant register file can be assigned to a variable that is used as a constant in the context of a programming loop.

[0089] In some embodiments, multiple constant registers in a constant register file can be assigned to variables that are not used as constants in the context of a programming loop. For example, constant registers in a constant register file can be assigned to variables that have a purpose other than constants in the context of a programming loop, but will only require a read port for interfacing with the data path block circuitry and a write port for interfacing with the memory circuitry during execution.

[0090] In addition, one of the multiple result registers in the result register file can be assigned to a variable used as a result in the context of a programming loop.

[0091] In some embodiments, one of the multiple result registers in the result register file may be assigned to a variable that is not used as a result in the programming loop context. For example, a result register in the result register file may be assigned to a variable that has a purpose other than a result in the programming loop context, but during execution, only one read port and one write port for interfacing with the data path block circuitry, and one read port for interfacing with the memory circuitry, will be needed.

[0092] In addition, one of the multiple general-purpose registers in the general-purpose register file can be assigned to a variable that is neither used as a result nor as a constant in the context of a programming loop.

[0093] In some embodiments, one of the result registers in the result register file may be assigned to a variable that is used as a result or constant in the context of the programming loop. For example, a general-purpose register in the general-purpose register file may be assigned to a variable that has a purpose in the programming loop context other than a result or constant, but during execution, one or more read ports and one or more write ports will be needed for interfacing with the data path block circuitry, and one read port and one write port will be needed for interfacing with the memory circuitry.

[0094] In some embodiments, registers with fewer ports are preferentially allocated to variables. For example, a result register file may be preferentially allocated to a variable that will perform correctly if a general-purpose register or a result register is allocated to it. Similarly, a constant register file may be preferentially allocated to a variable that will perform correctly if a result register or a constant register is allocated to it. Furthermore, a constant register file may be preferentially allocated to a variable that will perform correctly if a general-purpose register or a constant register is allocated to it.

[0095] Register allocation based on the number of ports is advantageous, at least because registers in register files with fewer ports use less power during execution. This allocation is also advantageous, at least because registers in register files with fewer ports have less utility, allowing more functional registers to be reserved for other variables that may require greater utility.

[0096] In alternative embodiments, if a specific register file can be avoided, registers from that specific register file can be selectively not assigned to variables. For example, if general-purpose registers and constant registers can be assigned to variables, the register allocation module can selectively not assign one or more result register files to variables to preserve their unused state. This allocation may still occur even though the variable's execution time requirements are met by at least one of the unselected register file types. Similarly, if general-purpose registers can be assigned to variables, the register allocation module can selectively not assign one or more result register files or constant register files to variables to preserve their unused state. This allocation may still occur even though the variable's execution time requirements are met by at least one of the unselected register file types. This type of allocation can be advantageous, at least because if registers from a specific register file are not assigned to variables, the unused register file can be powered down to save power.

[0097] In an alternative embodiment, the source code includes an indication of which type of register is to be assigned to each variable. For example, the text for each variable can encode the register type to be assigned to that variable.

[0098] At 320, a register of a particular register type is assigned to a variable to be assigned to the particular register type. A register allocation method known to those skilled in the art is used to allocate the register. Any method can be used to assign a register of a particular register type to the variable of that particular register type.

[0099] At 330, if one or more other particular register types are to be assigned to the variable, method 300 returns to 320. Otherwise, registers are assigned to all variables and method 300 ends.

[0100] An advantageous aspect of method 300 is that the register allocation problem can be divided into multiple smaller register allocation problems. For example, in some embodiments, the large register allocation problem of allocating registers to all intermediate code variables is split into multiple smaller register allocation problems, where each smaller register allocation problem assigns a register of a single register type to a variable to be assigned to the single register type. Since register allocation is often an NP-complete problem, as understood by those skilled in the art, dividing a larger NP-complete problem into smaller NP-complete problems reduces the processor resources required to compute the solution to the NP-complete problem. For example, the running time and power consumption are reduced.

[0101] Figure 4 An example of source code (high-level language code) and intermediate code and executable code (instruction code) generated by a compiler is shown Figure 2 and Figure 3 is shown.

[0102] High-level language code 410 includes a while loop that executes as long as the variable x that is changed within the loop is greater than the constant Y. Within the loop, the variable n is set to be equal to the sum of the constant A and the constant B. Additionally, within the loop, the variable x is decreased by n.

[0103] Intermediate code 420 encodes the same while loop as high-level language code 410. As shown, intermediate code 420 has a loop, but does not assign the variable n to the value A + B within the loop. Additionally, the new variable _t is given the value of the loop condition (x < Y), and branches to the loop based on the value of _t.

[0104] Instruction code 430 encodes the same while loop as high-level language code 410 and intermediate code 420.

[0105] The intermediate code 420, “n=A+B”, has been translated into “add$R1,$C1,$C2”, where “add” indicates the addition operation, “$R1” identifies the register used for the result of the addition operation, “$C1” identifies the register used for the first operand of the addition operation, and “$C2” identifies the register used for the second operand of the addition operation.

[0106] Since variable n is the result of the operation, the result register $R1 is assigned to variable n. For example, because the register to be assigned to variable n requires a read port and a write port to interface with the data path block circuitry, as mentioned above, either the result register or a general-purpose register can be assigned to variable n. Furthermore, since the result register has fewer ports and / or uses less power, the result register $R1 is assigned to variable n instead of a general-purpose register.

[0107] Because variable A is a constant within the loop, the constant variable $C1 is assigned to variable A. For example, because the register used for variable A needs to be writable from memory and readable by the data path, as mentioned above, either a constant register or a general-purpose register can be assigned to variable A. Furthermore, since constant registers have fewer ports and / or use less power than general-purpose registers, the constant register $C1 is assigned to variable A instead of a general-purpose register.

[0108] Because variable B is a constant within the loop, the constant variable $C2 is assigned to variable B. For example, since the register used for variable B needs to be writable from memory and readable by the data path, as mentioned above, either a constant register or a general-purpose register can be assigned to variable B. Furthermore, since constant registers have fewer ports and / or use less power than general-purpose registers, the constant register $C2 is assigned to variable B instead of a general-purpose register.

[0109] The code “loop:x=xn” in intermediate code 420 has been translated into “loop:sub$GP1,$GP1,$R1”, where “sub” indicates the subtraction operation of the instruction, “$GP1” identifies the register for the result of the subtraction operation, “$GP1” identifies the register for the first operand of the subtraction operation, and “$R1” identifies the register for the second operand of the subtraction operation.

[0110] Since the x variable is defined before the loop execution and used after the loop operation, the general-purpose register $GP1 is allocated to the x variable. For example, since the register for the x variable is required for the read and write ports of the interface with the data path block circuit and for the read and write ports of the interface with the memory, as described above, only the general-purpose register can be allocated to the x variable. Therefore, the general-purpose register $GP1 is allocated to the variable n.

[0111] The code "_t = x < Y" in the intermediate code 420 has been translated into "slt $R2, $GP1, $C3", where "slt" represents the set if less operation of the instruction, "$R2" identifies the register for the result of the slt operation, "$GP1" identifies the register for the first operand of the slt operation, and "$C3" identifies the register for the second operand of the slt operation.

[0112] Since the _t variable is the result of the operation, the result register $R2 is allocated to the _t variable. For example, since the register for the _t variable is required for the read and write ports of the interface with the data path block circuit, as described above, either the result register or the general-purpose register can be allocated to the _t variable. In addition, since the result register has fewer ports and / or uses less power, the result register $R2 instead of the general-purpose register is allocated to the variable _t.

[0113] Since the Y variable is a constant within the loop, the result constant $C3 is allocated to the Y variable. For example, since the register for the Y variable needs to be writable from the memory and readable by the data path, as described above, either the constant register or the general-purpose register can be allocated to the Y variable. In addition, since the constant register has fewer ports and / or uses less power than the general-purpose register, the constant register $C3 instead of the general-purpose register is allocated to the Y variable.

[0114] The code "If _t goto loop" in the intermediate code 420 has been translated into "beq $R2, loop", where "beq" represents the branch if equal operation of the instruction, "$R2" identifies the register for the test condition of the beq operation, and "loop" identifies the instruction label to branch to.

[0115] Figure 5A configuration of a computer system 710 constructed according to this disclosure for performing the steps described herein is shown. The computer system 710 may include a system such as a personal computer or other computer. The computer system 710 may include a network communication interface 712 that allows communication with a network 702. The network interface may include a network interface card (NIC). The computer system 710 can execute instructions to provide a computer system that performs the steps described herein for performing the steps described herein. Figures 1 to 4 The various aspects and principles of the characteristics of a computer.

[0116] Computer system 710 includes a central processing unit (CPU) 716 and a program product reader 718 for receiving a program product medium and reading program instructions recorded thereon, wherein the instructions, when executed by the CPU of the computer system, cause the computer to perform the various aspects, principles, and features described herein. The computer system also includes associated memory 720 and input / output facilities 722, which may include systems such as a display for output and a keyboard and / or mouse for input. The processor 716 of computer system 710 can receive program instructions into the processor's program memory. Program instructions can be received directly, for example via the processor's EEPROM in flash memory, or via a network interface 712, for example by downloading from a connected device or via WAN or LAN network communication. If necessary, program instructions can be stored on a computer program product 714 read by computer system 710 so that the program instructions can be executed later. In other words, program product 714 is used in a system such as computer system 710, wherein the program product includes a tangible, non-transitory recordable medium containing a program of computer-readable instructions executable by CPU 716 to perform the steps described herein. Program product 714 may include, for example, an optical program medium such as a CD or DVD data disc, or a flash drive, or an external storage device, or a floppy disk, etc.

[0117] As those skilled in the art will understand, in some embodiments, a compiler that performs the functional and procedural elements described herein can be generated by writing source code in a high-level language that describes the functionality of the compiler to be generated.

[0118] In the specification and claims, a connected list of elements or features may appear after phrases such as "at least one" or "one or more". The term "and / or" may also appear in a list of two or more elements or features. Unless implied or explicitly contradicted by the context in which it is used, such phrases are intended to mean any one of the elements or features listed individually, or any referenced element or feature combined with any other referenced element or feature. For example, the phrases "at least one of A and B;", "one or more of A and B;", and "A and / or B" respectively mean "A alone, B alone, or A and B together". A similar interpretation applies to lists containing three or more items. For example, the phrases "at least one of A, B, and C;", "one or more of A, B, and C;", and "A, B, and / or C" respectively mean "A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together". The use of the term "based on" in the foregoing and claims is intended to mean "at least partially based on", allowing for the inclusion of features or elements not listed.

[0119] The subject matter described herein can be embodied in systems, devices, methods, and / or articles according to desired configurations. The embodiments set forth in the foregoing description do not represent all embodiments consistent with the subject matter described herein. Rather, they are merely some examples consistent with aspects related to the described subject matter. Although some variations have been described in detail above, other modifications or additions are possible. In particular, additional features and / or variations may be provided in addition to those set forth herein. For example, the above embodiments may involve various combinations and sub-combinations of the disclosed features and / or combinations and sub-combinations of several other features disclosed above. Furthermore, the logical flows depicted in the drawings and / or described herein do not necessarily require the specific order or sequence shown to achieve the desired results. Other implementations may be within the scope of the appended claims.

Claims

1. A compiler configured to generate executable code based on source code for execution on a processor having a plurality of registers of a set of register types, wherein, Each register of a first register type has a first number of read and write ports, and each register of a second register type has a second number of read and write ports, the second number being less than the first number, wherein the source code includes a plurality of variables, each variable having an associated use in the context of a programming loop of the source code, the compiler including an executable code generator configured to assign one of the plurality of registers to each source code variable, wherein the executable code generator is configured to select a register type for assignment to each variable in a set of register types, including: selecting the first register type for assignment to a first variable of the plurality of variables based on the first variable having an associated use associated with the first register type; selecting the second register type for assignment to a second variable of the plurality of variables based on the second variable having an associated use associated with the second register type; and selecting the second register type for assignment to a third variable of the plurality of variables based on the third variable having an associated use associated with the first register type but determined to be supported by the second number of read and write ports of the second register type, wherein the assigned register for each variable corresponds to the register type determined for that variable.

2. The compiler of claim 1, wherein, The set of register types includes: a set of general purpose registers grouped as a first register file, and a set of special purpose registers grouped as a second register file.

3. The compiler of claim 1, wherein, The executable code generator is configured to select the register type for assignment to each variable by determining how many read and write ports the register assigned to each variable will need when executed.

4. The compiler of claim 1, wherein, The executable code generator is configured to select the register type for assignment to each variable by determining which of the register types accommodate the execution time requirements of each variable.

5. The compiler of claim 1, wherein, The executable code generator is configured to receive intermediate code generated by the compiler, wherein selecting the register type for assignment to each variable includes determining how the variable is used in the intermediate code.

6. The compiler of claim 5, wherein, The executable code generator is configured to select the register type for assignment to each variable by determining which of the register types accommodate the execution time requirements of each variable.

7. The compiler of claim 6, wherein, The executable code generator is configured to select the register type for assignment to a particular variable by determining that more than one register type accommodates the execution time requirements of the particular variable.

8. The compiler of claim 7, wherein, The executable code generator is configured to select the register type for assignment to a particular variable by selecting one of the register types that accommodates the execution time requirements of the particular variable based on the selected register type requiring less power to operate compared to other register types that accommodate the execution time requirements of the particular variable.

9. The compiler of claim 7, wherein, The executable code generator is configured to select the register type assigned to a particular variable by selecting one of the register types that accommodates execution time demands of the particular variable based on an unused state of a register file that reserves a register having one of the register types that accommodates execution time demands of the particular variable.

10. The compiler of claim 1, wherein, The executable code generator is further configured to assign registers of a first register type to variables determined for the first register type as a first register allocation problem and to assign registers of a second register type to variables determined for the second register type as a second register allocation problem.

11. A method of generating executable code based on source code using a compiler, the code for execution on a processor having a plurality of registers of a set of register types, wherein, Each register of a first register type has a first number of read and write ports and each register of a second register type has a second number of read and write ports, the second number being less than the first number, wherein the source code includes a plurality of variables each having a respective use in the context of a program loop of the source code, the method comprising: selecting, with an executable code generator, a register type to assign to each variable in a set of register types, including selecting a first register type to assign to a first variable of the plurality of variables based on the first variable having a respective use associated with the first register type, selecting a second register type to assign to a second variable of the plurality of variables based on the second variable having a respective use associated with the second register type, and selecting the second register type to assign to a third variable of the plurality of variables based on the third variable having a respective use associated with the first register type but determined to be supported by the second number of read and write ports of the second register type; automatically assigning, with the executable code generator, one of the plurality of registers to each source code variable, wherein the assigned register of each variable corresponds to a register type determined for that variable.

12. The method of claim 11, wherein, The set of register types includes: a set of general purpose registers grouped as a first register file and a set of special purpose registers grouped as a second register file.

13. The method of claim 11, wherein, Selecting the register type to assign to each variable includes determining how many read and write ports the register assigned to each variable needs when executed.

14. The method of claim 11, wherein, Selecting the register type to assign to each variable includes determining which of the register types accommodate execution time demands of each variable.

15. The method of claim 11, further comprising: Receiving, with the executable code generator, intermediate code generated by the compiler, wherein selecting the register type to assign to each variable includes determining how the variable is used in the intermediate code.

16. The method of claim 15, wherein, Selecting the register type to assign to each variable includes determining which of the register types accommodate execution time demands of each variable.

17. The method of claim 16, wherein, Selecting the register type to assign to a particular variable includes determining that more than one register type accommodates execution time demands of the particular variable.

18. The method of claim 17, wherein, Selecting a register type to assign to a particular variable includes selecting one of the register types that accommodates execution time requirements of the particular variable based on the selected register type requiring less power to operate compared to other register types that accommodate the execution time requirements of the particular variable.

19. The method of claim 17, wherein, Selecting a register type to assign to a particular variable includes selecting one of the register types that accommodates execution time requirements of the particular variable based on reserving a register file of unused registers with one of the register types that accommodates the execution time requirements of the particular variable.

20. The method of claim 11, further comprising, with the executable code generator, assigning registers of a first register type to variables determined for the first register type as a first register assignment problem and assigning registers of a second register type to variables determined for the second register type as a second register assignment problem.

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