Data processing device and system

Abstract

A data processing device comprises: a first transceiver module (7031) for receiving first data sent by a first main control board (701); a second transceiver module (7032) for receiving second data sent by a second main control board (702); a deviation measurement module (7033) for determining a first deviation between the first data and the second data; a feedback module for sending the first deviation to the second main control board (702), the first deviation being used by the first main control board (701) to perform a first deviation compensation on the third data; the first transceiver module (7031) is further used to receive the third data sent by the first main control board (701) after receiving the first data; the second transceiver module (7032) is further used to receive the fourth data sent by the second main control board (702), the fourth data and the third data being backup data for each other; a deviation compensation module (70371) is used to perform a second deviation compensation on the third data based on the fourth data. The device ensures that the opposite end service is not interrupted during the master-slave switching and reduces delay jitter.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a data processing device. Background Art

[0002] Box-type or frame-type devices generally use a hardware solution with two main control boards and interface boards. The two main control boards are used to back up each other's services and ensure normal service transmission. Under normal circumstances, the active main control board and the interface board work together. When an error occurs on the active main control board, a master-slave switchover is triggered, and the services are taken over by the backup main control board. Simultaneously, the interface board completes the service switch from the active main control board to the backup main control board. For example, if the interface board determines that the active main control board has an error, it no longer sends or receives messages to or from the original active main control board. Instead, it sends or receives messages to or from the original backup main control board.

[0003] However, because the processing latency of services on the active and standby main control boards cannot be consistent, the transmission latency between the active and standby main control boards may be asymmetric when services are transmitted within the device. For services with high latency symmetry requirements, the asymmetric transmission latency during active / standby switchover can introduce jitter or even cause service interruption. Therefore, how to reduce the jitter introduced during active / standby switchover and perform the switchover without interrupting services is an urgent issue. Summary of the Invention

[0004] The present application provides a data processing device that reduces the delay jitter introduced when the main control board is switched to the backup main control board, and solves the problem of service interruption of the opposite device when the main and backup main control boards are switched.

[0005] To achieve the above objectives, the present invention provides the following technical solutions:

[0006] In a first aspect, the present application provides a data processing device, which may be a clock data recovery (CDR) or an interface board, and may include: a first transceiver module for receiving first data sent by a first main control board; a second transceiver module for receiving second data sent by a second main control board, wherein the first and second main control boards serve as master and backup main control boards, and the first and second data serve as backup data for each other; a deviation measurement module for determining a first deviation between the first and second data. The data processing device may also include a feedback module for sending a first deviation to the backup main control board, the first deviation being used by the first main control board to perform a first deviation compensation on third data; the feedback module may be the same as or different from the first transceiver module. The first transceiver module is further configured to receive third data sent by the first main control board after receiving the first data; the second transceiver module is further configured to receive fourth data sent by the second main control board, wherein the fourth data and the third data serve as backup data for each other; and a deviation compensation module for performing a second deviation compensation on the third data based on the fourth data. From the first aspect, it can be seen that the backup main control board performs the first deviation compensation on the third data based on the first deviation, and the data processing equipment then performs the second deviation compensation on the third data. After two deviation compensations, the third data and the fourth data can be basically aligned. When the backup main control board is triggered to switch to the main main control board, the delay jitter is reduced.

[0007] Optionally, in combination with the first aspect above, in a first possible implementation, it may further include: a tracking module, which is used to track the third data after the second deviation compensation when the first main control board is switched from the backup main control board to the main main control board. The data processing device may also include a fourth transceiver module, which is used to send the third data to the opposite device. From the first possible implementation of the first aspect, it can be seen that the tracking module only needs to track one channel of data to ensure that the service of the opposite device is not interrupted. For example, before the first main control board is switched to the main main control board, the tracking module tracks the data of the second main control board, that is, the tracking module tracks the data of the main main control board. When the first main control board is switched from the backup main control board to the main main control board, since the third data and the fourth data are already aligned, the tracking module only needs to track the third data to ensure that the service of the opposite device is not interrupted.

[0008] Optionally, in combination with the above-mentioned first aspect or the first possible implementation of the first aspect, in a second possible implementation, the first transceiver module may include a P channel, and the second transceiver module may include a Q channel, where P and Q are both positive integers. The first transceiver module is specifically used to receive the first data through the P channel. The second transceiver module is specifically used to receive the second data through the Q channel. The deviation measurement module is specifically used to determine the first deviation based on the difference between T1 and T2 and the interface rate of the device, where T1 is the arrival time of the last channel in the P channel, and T2 is the arrival time of the last channel in the Q channel. The second possible implementation of the first aspect provides a specific method for determining the first deviation.

[0009] Optionally, in combination with the second possible implementation of the first aspect, in a third possible implementation, each of the P channels may include an alignment marker AM, each of the Q channels may include an AM, T1 is the arrival time of the AM in the last channel in the P channels, and T2 is the arrival time of the AM in the last channel in the Q channels. The third possible implementation of the first aspect provides a specific method for determining the first deviation. The data processing device may determine the first deviation based on the phase offset between the AM words in the first data and the second data.

[0010] Optionally, in combination with the above-mentioned first aspect or the first possible implementation of the first aspect, in a fourth possible implementation, the first transceiver module may include a P channel, and the second transceiver module may include a Q channel, P and Q are both positive integers, and the first transceiver module is specifically used to receive the first data through the P channel. The second transceiver module is specifically used to receive the second data through the Q channel. The device may also include: a cache module, which is used to cache the P channel and the Q channel when receiving data from the first channel. The deviation measurement module is specifically used to determine the first skew based on the first cache and the second cache, the first cache being the cache accumulated by the P channel when the last channel in the P channel arrives, and the second cache being the cache accumulated by the Q channel when the last channel in the Q channel arrives. The fourth possible implementation of the first aspect provides a specific method for determining the first deviation.

[0011] The second aspect of the present application provides a data processing device, which may include: a first transceiver module, used to send first data to an interface board. An acquisition module, used to obtain a first deviation, the first deviation is the deviation between the first data and the second data determined by the interface board, the second data is the data sent by the second main control board, the second data and the first data are backup data of each other, the second main control board and the first main control board are the main and standby main control boards of each other, and the acquisition module is the same as or different from the first transceiver module. A processing module, used to perform deviation compensation on the third data according to the first deviation obtained by the second transceiver module. The first transceiver module is also used to send the third data after deviation compensation.

[0012] The third aspect of the present application provides a data processing system, which includes an interface board and a main control board, wherein the interface board is the data processing device described in the first aspect or any possible implementation of the first aspect, and the main control board is the data processing device described in the second aspect.

[0013] The fourth aspect of the present application provides a data processing system, which includes a clock data recovery CDR chip and a network processor NP chip, wherein the CDR chip is the data processing device described in the first aspect or any possible implementation of the first aspect, and the NP chip is the data processing device described in the second aspect.

[0014] A fifth aspect of the present application provides a packet transport network (PTN) device, which includes an interface board and a main control board, wherein the interface board is a data processing device described in the first aspect or any possible implementation of the first aspect, and the main control board is a data processing device described in the second aspect.

[0015] In a sixth aspect, the present application provides a packet transport network (PTN) device, which includes a clock data recovery (CDR) chip and a network processor (NP) chip, wherein the CDR chip is a data processing device described in the first aspect or any possible implementation of the first aspect, and the NP chip is a data processing device described in the second aspect.

[0016] An embodiment of the present application provides a data processing device, in which an interface board determines the deviation between the data sent by the active main control board and the backup main control board. The backup main control board can adjust the data sent according to the deviation, and the interface board then compensates for the deviation of the data sent by the active main control board and the backup main control board. When an active-standby switching occurs, since the data stream sent by the backup main control board has been aligned with the data sent by the active main control board inside the interface board, after the active-standby switching, the delay jitter introduced by the active-standby switching is reduced, and the problem of service interruption on the opposite end when the active-standby main control boards are switched is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0018] Figure 2 It is a structural diagram of a data processing device;

[0019] Figure 3 is a structural diagram of a data processing device including a first CDR chip;

[0020] Figure 4 is a structural schematic diagram of a data processing device including a second CDR chip;

[0021] Figure 5 This is a schematic diagram of the delay jitter caused by the second CDR chip;

[0022] Figure 6 A schematic diagram of the structure of a data processing device provided in this application;

[0023] Figure 7 This is a schematic diagram of the structure of another data processing device provided in this application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0025] The terms "first," "second," "third," "fourth," and so forth (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that shown or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, product, or apparatus.

[0026] Certain words are used in the specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This specification and the following claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the criterion for distinction. The inclusion or inclusion mentioned in the specification and claims is an open term and should be interpreted as including but not limited to or including but not limited to. In addition, coupling or coupling here includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, or a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0027] Figure 1 A schematic diagram of an application scenario provided by an embodiment of the present invention. Figure 1 As shown in , device 101 is referred to as the local device, and device 102 is referred to as the opposite device, or alternatively, device 102 is referred to as the local device and device 101 is referred to as the opposite device. Devices 101 and 102 are box-type devices or frame-type devices. For example, devices 101 and 102 may be routers, switches, optical transport network (OTN) devices, packet transport network (PTN) devices, or wavelength-division multiplexing (WDM) devices. The embodiments of the present application do not limit the types of the local device and the opposite device to being the same. For example, the local device may be a PTN device or a router, and the opposite device may be a router or a switch.

[0028] At present, the above-mentioned box-type devices or frame-type devices generally adopt a hardware solution of dual main control boards and interface boards. The main control board can include a media access controller (MAC) and a network processor. The main control board can also include multiple MACs and multiple network processors. The MAC in the main control board can be coupled with the network processor in the main control board. The main control board can be implemented by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Figure 2 The figure shows a schematic diagram of the structure of a data processing device, which includes two main control boards, namely the main control board 201 and the backup control board 202. The main control board is referred to as the master main control board and the backup main control board is referred to as the slave main control board. The two main control boards are used to ensure mutual backup of services. To simplify the description, Figure 2 The main control board 201 in FIG. 1 only shows one MAC 2012 and one network processor 2011. Figure 2The standby main control board 202 in the figure only shows one MAC 2022 and one network processor 2021, wherein MAC 2012 is coupled to network processor 2011, and MAC 2022 is coupled to network processor 2021. It should be noted that one MAC and one network processor do not represent a limit on the number, but are only for the convenience of explanation. The following description of the numbers does not limit the number, but is only for the convenience of explanation, and will not be repeated below. The network processor on the main control board implements business processing such as packet forwarding scheduling. For example, network processor 2011 and network processor 2021 can be a network processor (NP), or a packet processor (PP), or a packet engine (PE), or an application specific integrated circuit (ASIC). The network processor 2011 and network processor 2021 can be programmable or non-programmable, and this is not limited in the embodiment of the present invention. It should be noted that in some scenarios, the main control board is also referred to as a forwarding processing board. As mentioned above, those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and the following claims do not distinguish components by name, but rather by functional differences. Interface board 203 utilizes a clock data recovery (CDR) chip 2031 with electronic switching (MUX / DEMUX) functionality. The electronic switch includes a multiplexer circuit (MUX) and a demultiplexer circuit (DEMUX). This implements selective or dual transmission from the line side to the system side, and selective reception from the system side to the line side, supporting switching between the master control board 201 and the slave control board 202. In the embodiments of the present application, the line side refers to the side of the interface board close to the external interface. In other words, the line side refers to the side of the interface board close to the external optical fiber. The system side refers to the side of the interface board close to the internal interface. In other words, the system side refers to the side of the interface board close to the network processor. The selective transmission function refers to the CDR chip 2031 selecting whether to send a message to the master main control board 201 or the slave main control board 202. The dual transmission function refers to the CDR chip 2031 sending a message to the master main control board 201 and the slave main control board 202. The selective reception function refers to the CDR chip 2031 selecting whether to send a message from the master main control board 201 or the slave main control board 202 to the line side. In addition, the main control board and the interface board may also include other components, which are not specifically limited in the embodiments of the present application. For example, the interface board 203 may also include an optical module (optical mpdel) 2032 for converting optical and electrical signals.

[0029] Under normal circumstances, the master control board 201 and the interface board work together. When an exception occurs on the master control board 201, a master-slave switchover is triggered, and the service is taken over by the slave control board 202. At the same time, the CDR chip on the interface board completes the service switch from the master control board 201 to the slave control board 202. For example, when the CDR chip determines that the master control board 201 has an exception, the CDR chip no longer sends messages to the master control board 201 or no longer receives messages from the master control board 201. Instead, it sends messages to the slave control board 202 or receives messages from the slave control board 202.

[0030] For different scenarios, the structure of the CDR chip may be different, such as Figure 3 FIG. 3 is a schematic diagram showing the structure of a device including a first CDR chip 303. Figure 3 The first CDR chip 303 shown includes a serializer / deserializer (SERializer / DESerializer, serdes) and a MUX / DEMUX circuit. For the convenience of explanation, Figure 3Only the serializer / deserializer 3031, serializer / deserializer 3032, serializer / deserializer 3035, serializer / deserializer 3036, and MUX / DEMUX 3033 and MUX / DEMUX 3034 are shown. The MUX / DEMUX 3033 and MUX / DEMUX 3034 circuits are also called electronic switches. The SerDes circuit can convert parallel physical codes into serial physical codes before sending, or convert serial physical codes into parallel physical codes for reception. In this way, data can be transmitted in serial form at a higher transmission rate. To distinguish, this application refers to the SerDes circuit that can convert parallel physical codes into serial physical codes before sending as a serializer (also known as SerDes Tx in English), and the SerDes circuit that can convert serial physical codes into parallel physical codes as a deserializer (also known as SerDes Rx in English). This type of first CDR chip 303 does not support the Ethernet physical coding sublayer (ETH PCS). When an abnormality occurs in the master main control board 301 and the master-slave switching is triggered, the first CDR chip 303 generally switches the service to the slave main control board 302 at any time. However, since the processing delay of the master and slave main control boards cannot be consistent, the ETH protocol words of the master and slave main control boards are also difficult to align. The network side protocol words and messages received by the first CDR chip 303 from the master and slave main control boards are not synchronized. As a result, when the device sends a message outward, the network side protocol words of the message on the device interface side will shift, causing service interruption on the opposite device. The main main control board 301 and the backup main control board 302 can refer to Figure 2 The corresponding main control board 201 and the standby main control board 202 are understood, and the network processor 3011 and the network processor 3021 can refer to Figure 2 The corresponding network processor 2011 and network processor 2021 can be understood, and the media access controller 3012 and media access controller 3022 can refer to Figure 2 The corresponding media access controller 2012 and media access controller 2022 are not repeated here.

[0031] like Figure 4 FIG. 4 is a schematic diagram showing the structure of a device including a second CDR chip 403. Figure 4The second CDR chip 403 shown includes not only serdes and MUX / DEMUX circuits, but also an Ethernet physical coding sublayer, etc. The second CDR chip 403 supports the Ethernet physical coding sublayer, which can parse the 8bit / 10bit encoding or 64bit / 66bit encoding synchronization header, alignment marker (AM), etc. of the ETH protocol. With this technical solution, when a master-slave switch occurs, a lossless switching of the protocol layer from the system side to the line side can be achieved. Figure 4 and Figure 5 A specific explanation is given for this. The master main control board 401 and the slave main control board 402 respectively send data to the second CDR chip 403 through the Ethernet interface. Different Ethernet interfaces correspond to different numbers of channels (lanes). The number of lanes can be understood as the number of links for sending data in parallel. For example, if the Ethernet interface adopts the 25G Ethernet protocol, the corresponding number of lanes can be 1. Taking the master main control board 401 sending data to the second CDR chip 403 as an example, the master main control board 401 can send data to the second CDR chip 403 through 1 lane; if the Ethernet interface adopts the 40G Ethernet protocol, the corresponding number of lanes can be 2 or 4. Taking the master main control board 401 sending data to the second CDR chip 403 as an example, the master main control board 401 can convert the data into 2 lanes and send it to the second CDR chip 403 through 2 lanes. Send data, or the master main control board 401 can send data to the second CDR chip 403 through 4 lanes. If the Ethernet interface adopts the 50G Ethernet protocol, the corresponding number of lanes is 1 or 2. If the Ethernet interface adopts the 100G Ethernet protocol, the corresponding number of lanes can be 1 or 2 or 4 or 10, and so on. The master main control board 401 and the slave main control board 402 can send data to the second CDR chip 403 through P lanes according to the examples given above for the 25G Ethernet protocol and the 40G Ethernet protocol. P is a positive integer and the examples will not be repeated here.

[0032] The number of lanes corresponds to the number of serdes on the second CDR chip 403, and Plane lanes can correspond to Plane serdes on the second CDR chip 403. For example, after the master main control board 401 sends data through Plane lanes, the second CDR chip 403 receives the data on the Plane lanes through Plane serdes. The data in each lane in the Plane lanes are sent serially. After passing through the Plane serdes, the Plane serdes converts the serial data of each lane in the Plane lanes into parallel data. For example, any serial data in the Plane lane is demultiplexed into multiple multi-bit channels through serdes. After the second CDR chip 403 receives the Plane data, it needs to use a clock to process the Plane data stream in the Plane physical channel, for example, using the second CDR chip 403 to process the Plane data stream to ensure the time synchronization of the processed Plane data stream. To simplify the explanation, the following example is given for the case where the Ethernet protocol corresponds to 2 lanes. The master control board 401 converts the data stream into a data stream transmitted on two lanes. Each data stream includes an AM and a data block group. Each data block in the data stream is obtained by physical layer encoding the Ethernet frame stream. After the Ethernet frame stream is physically encoded, the AM is periodically inserted. The physical layer encoding can be 64-bit / 66-bit encoding. When the physical layer encoding is 64-bit / 66-bit encoding, the number of bits contained in a data block is 66. In a 66-bit data block, 2 bits can be synchronization headers. Of course, any bit can be a synchronization header. The 2 bits here do not represent a limit on the number, but are only for illustration. The first Ethernet physical coding sublayer 4034 decodes the data streams received in the two lanes sent by the master main control board 401 and aligns the AMs in the two lanes. The second Ethernet physical coding sublayer 4035 decodes the data received in the two lanes sent by the slave main control board 402 and aligns the AMs in the two lanes. To explain the problem clearly, the two lanes sent by the master main control board 401 are referred to as the first lane and the second lane, and the two lanes sent by the slave main control board 402 are referred to as the third lane and the fourth lane. After being processed by the first Ethernet physical coding sublayer 4034 and the second Ethernet physical coding sublayer 4035, the AMs of the first lane and the second lane are aligned, and the AMs of the third lane and the fourth lane are also aligned. However, as Figure 5As shown, the AMs of the first, second, and third lanes are not necessarily aligned. In other words, the AMs of the data streams sent by the master control board 401 and the slave control board 402 are not necessarily aligned. Therefore, after passing through electronic switch 4037, the second CDR chip 403 uses the AM removal module 4039 to delete all AMs from the first, second, third, and fourth lanes. After passing through buffer 4050, the third Ethernet physical coding sublayer 4060 re-encodes the first, second, third, and fourth lanes at the physical layer and periodically inserts AMs, thereby ensuring that the AMs of the first, second, third, and fourth lanes are aligned. Regarding the process of the second CDR chip 403 receiving the data stream sent by the line side, after the data stream passes through the deserializer, the fourth Ethernet physical coding sublayer 4070 aligns the AM in the data stream and then deletes the AM. After passing through the buffer 4038, the fifth Ethernet physical coding sublayer 4036 reinserts the AM into the data stream according to a certain period.

[0033] The second CDR chip 403 uses AM deletion and reinsertion technology to reinsert the AM into the third Ethernet physical coding sublayer 4060. This ensures that when a master-slave switch occurs, the Ethernet physical coding sublayer of the other device will not experience service interruption, and thus the local device will not be aware of the switch operation. However, this also brings other problems. Since the AM is reinserted into the third Ethernet physical coding sublayer 4060, it is impossible to ensure that the AM position of the data stream sent by the main control board (main and backup main control boards) remains consistent, such as Figure 5 As shown in the figure, for example, the third Ethernet physical coding sublayer 4060 re-encodes the physical layer of the first and second lanes, or the second Ethernet physical coding sublayer 4035 re-encodes the third and fourth lanes, and periodically inserts AMs. The positions of the AMs may differ from the original positions of the AMs in the first, second, third, and fourth lanes. This introduces delay jitter into the data stream after it passes through the second CDR chip 403. This delay jitter has little impact on normal forwarding services, but it can significantly impact 1588 accuracy. For example, if the Ethernet interface is 100GE, the re-inserted AMs are shifted by 1280 unit intervals (UIs). Due to the offset between the receiving and transmitting AM words of the second CDR, one-way delay jitter of approximately 12.8 nanoseconds (1280 / 100Gbps = 12.8ns) is generated. In box-type or chassis-type devices, the main control board performs 1588 stamping and line delay compensation. The smaller the jitter of the data stream on the interface board, the higher the 1588 accuracy of the device.

[0034] In order to solve the above technical problems, the present application provides a data processing device that reduces delay jitter, improves 1588 processing accuracy, and ensures high-precision 1588 system specifications. Before introducing the technical solution provided by the present application, a brief introduction to 1588 is first given. 1588, also known as the Institute of Electrical and Electronics Engineers 1588 (IEEE 1588), is a time synchronization protocol. Currently, mainstream time synchronization technology solutions also include the Network Time Protocol (NTP), synchronous Ethernet, GPS, etc., but these time synchronization solutions have obvious shortcomings compared to IEEE 1588. For example, based on NTP technology, IEEE 1588 can further improve synchronization accuracy. In distributed networks based on Ethernet, the accuracy of the 1588 V2 protocol is improved to the nanosecond level compared to the millisecond-level synchronization accuracy of NTP technology. However, it should be noted that the technical solution provided by the present application is described using IEEE 1588 as an example. Those skilled in the art can naturally apply the technical solution provided by the present application to other time synchronization technology solutions based on the technical solution provided by the present application.

[0035] Figure 6 A schematic diagram of the structure of a data processing device provided in this application.

[0036] like Figure 6 As shown, a data processing device provided by an embodiment of the present application may include: a first main control board 601, a second main control board 602, and an interface board 603, wherein the first main control board 601 and the second main control board 602 are respectively coupled to the interface board 603. The first main control board 601 includes a network processor 6011 and a media access controller 6012, and the media access controller 6012 includes a processing module 6013. The second main control board includes a network processor 6021 and a media access controller 6022, and the media access controller 6022 includes a processing module 6023. The network processor 6011 and the network processor 6021 can refer to Figures 2 to 4 The interface board 603 includes a third CDR chip 6031 and may also include other components, which are not specifically limited in the present embodiment. For example, the interface board 603 may also include an optical module (optical mpdel) 6032 for converting optical and electrical signals.

[0037] The first main control board 601 is configured to send first data to the interface board 603 .

[0038] The second main control board 602 is used to send the second data to the interface board 603. The first main control board 601 and the second main control board 602 are each other's master and standby main control boards, and the first data and the second data are each other's backup data. Under normal circumstances, the master main control board and the interface board 603 work in coordination. When an abnormality occurs in the master main control board, a master-standby switchover is triggered, and the service is taken over by the standby main control board. At the same time, the data processing equipment completes the switching of the service from the master main control board to the standby main control board. For example, when the interface board 603 determines that an abnormality occurs in the master main control board, the interface board 603 no longer sends messages to the master main control board or receives messages from the master main control board, but instead sends messages to the standby main control board or receives messages from the standby main control board.

[0039] The interface board 603 is used to determine the deviation between the first data and the second data (hereinafter referred to as the first deviation). The first deviation refers to the phase offset difference between the first Ethernet protocol word of the first data and the first Ethernet protocol word of the second data, and the first deviation can be at the bit level. For example, when the first Ethernet protocol word is an AM word, the first deviation refers to the phase difference between the AM word in the first data and the AM value in the second data. Because of factors such as the difference in propagation speed of each channel in the medium, multi-channel data transmission may be misaligned. When the interface board 603 receives the first data and the second data, the AM word in the first data and the AM word included in the second data are generally not aligned. For example, it is assumed that after the interface board receives the first data, the AM words of all lanes corresponding to the first data are aligned. After the interface board receives the second data, the AM words of all lanes corresponding to the second data are aligned. However, at this time, the AM words of the first data and the second data are generally not aligned. There are many ways to implement how to determine the deviation between the first data and the second data, which will be combined below. Figure 7 Provide specific instructions.

[0040] The interface board 603 is further configured to send the first deviation to the standby main control board.

[0041] Assuming that the first main control board 601 is the backup main control board at this time, the first main control board 601 is also configured to compensate for the next data to be sent based on the first deviation. The next data here refers to the data most recently sent by the first main control board 601 after receiving the first deviation (hereinafter referred to as the third data). For example, the first main control board may determine to delay sending the third data based on the first deviation, or the first main control board may determine to advance sending the third data based on the first deviation. Specifically, the network processor in the first main control board may compensate for the deviation of the third data based on the first deviation. Because the network processor in the first main control board is coupled to the sending module in the first main control board, the first main control board sending data externally can be understood as the network processor in the first main control board directly or indirectly sending data externally. It should be noted that it is almost impossible for the first main control board to completely eliminate the first deviation, which would increase cost and power consumption. Therefore, in this solution, the first main control board only needs to control the accuracy within a preset range.

[0042] The first main control board 601 is further configured to send third data to the interface board 603 .

[0043] The second main control board 602 is further configured to send fourth data to the interface board 603. The third data and the fourth data serve as backup data for each other. In this embodiment of the present application, the backup main control board compensates the transmitted data according to the first skew, without affecting the data transmission of the main control board or the normal operation of the service.

[0044] The interface board 603 is further configured to perform deviation compensation on the received third data and fourth data.

[0045] As described above, the interface board 603 determines a first deviation based on the first and second data. The first main control board performs a first deviation compensation on the next data to be transmitted, namely, the third data, based on this first deviation, so that the deviation between the third and fourth data (hereinafter referred to as the second deviation) is within a preset range, such as 100 UI. At this point, a portion of the deviation remains uneliminated, namely the difference between the first and second deviations. The interface board can then minimize or eliminate the deviation between the third and fourth data using a deviation compensation circuit. The deviation compensation circuit in this embodiment can be implemented in any manner, such as any deviation compensation circuit capable of performing the functions of a deviation compensation module. Existing deviation compensation circuits are well-known technology and will not be described in detail here. It should be noted that if the first main control board 601 does not compensate the deviation between the third and fourth data to within the preset range, relying solely on the interface board 603 to perform deviation compensation for the third and fourth data, a relatively large amount of buffered data would be required, resulting in increased costs and power consumption. This solution cleverly achieves strict alignment of data transmitted by the first and second main control boards through the cooperation between the interface board 603 and the main control board, using two deviation compensation steps.

[0046] On this basis, the interface board 603 tracks the data stream of the active main control board in the downlink transmission direction to align the output data with the input data. When a master-slave switchover occurs, since the data stream of the first main control board 601 is already aligned with the data stream of the second main control board 602, the data stream sent by the interface board 603 remains consistent after the switchover. When the interface board receives the data stream from the line side, since there is only one data source header, that is, the data stream received by the interface board 603 comes from the same transmitter, the interface board 603 tracks the input data stream, which ensures that the delay jitter of the message passing through the interface board 603 in the uplink direction is close to zero. The following uses the downlink direction as an example to illustrate the effect of this technology. When introducing the second CDR chip 403 above, it was mentioned that the second CDR chip 403 uses the AM deletion and reinsertion technology. Although this can ensure that the opposite device will not experience service interruption when a master-slave switch occurs, it will cause delay jitter when the data stream passes through the second CDR chip. For example, assume that the data blocks before and after the first AM in the first lane sent by the master main control board 401 are the first data block and the second data block, respectively. After receiving the first lane, the second CDR chip 403 will delete the first AM and reinsert the second AM. The position of the second AM is usually different from that of the first AM. Assuming that the second AM is inserted after the second data block, the position of the second data block in the first lane after the insertion of the second AM is different from the position of the second data block in the first lane before the deletion of the first AM. However, the insertion of the second AM will not have a significant impact on the position of the first data block in the first lane. It can be seen that the deletion and insertion of the AM introduces delay jitter after the data stream enters the second CDR chip. The technical solution provided by the present application does not require deletion of AM and insertion of AM. The interface board only tracks one of the data streams, for example, only tracks the AM in the active main control board, thereby achieving AM word alignment of the output data (data sent by the interface board to the opposite end) and the input data (data received by the interface board from the main control board). When sending the master-slave switch, since the present solution pre-aligns the data streams from the first main control board and the second main control board, only tracking the AM in the data stream sent by the switched active main control board can prevent the data stream from being displaced after passing through the interface board, and does not introduce delay jitter.

[0047] Through the above solution, it can be achieved that the upstream and downstream data streams do not shift after passing through the interface board 603, so that the delay jitter of the message in the upstream and downstream directions passing through the third CDR chip 6031 is close to 0. The downstream direction refers to the direction of data flow from the main control board to the interface board, and the upstream direction refers to the direction of data flow from the interface board to the line side, and the line side is the optical fiber side.

[0048] The data processing device provided in the embodiment of the present application is described above. The data processing device may be an interface board. Of course, the data processing device may also be a CDR chip or a data processing circuit. A structural diagram of a third CDR chip 6031 is given below.

[0049] Figure 7 A schematic diagram of the structure of a data processing device provided in this application.

[0050] like Figure 7 As shown, a data processing device provided in an embodiment of the present application may include:

[0051] The first transceiver module 7031, in the downlink direction, is used to receive the first data sent by the first main control board 701. The first transceiver module 7031 may include P channels, where P is a positive integer, and the number of Ps may be 1, 2, or 4, etc. The embodiment of the present application does not limit the number of Ps and can be set according to actual needs. The first transceiver module 7031 can be regarded as the first communication interface of the third CDR chip, for example, the first transceiver module can be regarded as a SerDes circuit.

[0052] The second transceiver module 7032 is used to receive the second data sent by the second main control board 702 when in the downlink direction. The second transceiver module 7032 may include a Q-path channel, where Q is a positive integer, where P and Q may be equal or unequal, and this embodiment of the present application does not limit this. The second transceiver module 7032 can be regarded as the second communication interface of the third CDR chip, for example, the second transceiver module can be regarded as a serdes circuit. The first main control board 701 and the second main control board 702 are mutually master and standby main control boards, that is, when the first main control board 701 is the master main control board, the second main control board 702 is the standby main control board, and when the second main control board 702 is the master main control board, the first main control board 701 is the standby main control board. Under normal circumstances, the master main control board and the third CDR chip 703 work together. When an abnormality occurs in the active main control board, a master-slave switchover is triggered, and the service is taken over by the standby main control board. At the same time, the data processing equipment completes the switching of the service from the active main control board to the standby main control board. For example, when the third CDR chip 703 determines that an abnormality occurs in the active main control board, the third CDR chip 703 no longer sends messages to the active main control board or receives messages from the active main control board, but sends messages to the standby main control board or receives messages from the standby main control board.

[0053] The third transceiver module 7070 is used to send data to the line side, or to send data to the opposite device. The third transceiver module 7070 can be regarded as the third communication interface of the third CDR chip. For example, the third transceiver module can be regarded as a serdes circuit.

[0054] The fourth transceiver module 7080 is used to receive data from the line side, or to receive data sent by the opposite device. The fourth transceiver module 7080 can be regarded as the fourth communication interface of the third CDR chip. For example, the fourth transceiver module can be regarded as a serdes circuit.

[0055] Deviation measurement module 7033, coupled to the first transceiver module and the second transceiver module, is configured to determine the deviation between the first data sent by the first main control board 701 and the second data sent by the second main control board 702. A first deviation refers to the phase offset difference between the first Ethernet protocol word of the first data and the first Ethernet protocol word of the second data. This first deviation can be at the bit level. Hereinafter, the deviation between the data sent by the first main control board 701 and the data sent by the second main control board 702 is referred to as the first deviation.

[0056] In a specific embodiment, assume that the first transceiver module 7031 receives data sent by the first main control board via a P channel (hereinafter referred to as the first data), and the second transceiver module 7032 receives data sent by the second main control board via a Q channel (hereinafter referred to as the second data), with the first data and the second data serving as backup data for each other. P and Q are both positive integers, the arrival time of the last channel in the P channel is T1, and the arrival time of the last channel in the Q channel is T2. The deviation measurement module 7033 determines the first deviation between the data sent by the first main control board 701 and the data sent by the second main control board 702 based on the difference between T1 and T2 and the interface rate of the third CDR chip, with measurement accuracy reaching the bit level.

[0057] In a specific embodiment, it is assumed that the first transceiver module 7031 receives first data through P channels, and the second transceiver module 7032 receives second data through Q channels, P and Q are both positive integers, each channel in the P channels includes an alignment marker AM, each channel in the Q channels includes an AM, T1 is the arrival time of AM in the last channel in the P channels, and T2 is the arrival time of AM in the last channel in the Q channels. The deviation measurement module 7033 determines the deviation between the data sent by the first main control board 701 and the data sent by the second main control board 702 based on the difference between T1 and T2 and the interface rate of the third CDR chip.

[0058] In a specific embodiment, assuming that the first transceiver module receives first data via P channels and the second transceiver module receives second data via Q channels, where P and Q are both positive integers, a cache module (not shown) may also be included, configured to cache the P and Q channels upon receiving data from the first channel. When the last channel in the P channels arrives, the accumulated cache in the P channels serves as a first cache, and when the last channel in the Q channels arrives, the accumulated cache in the Q channels serves as a second cache deviation. The third CDR chip determines the deviation between the data sent by the first main control board 701 and the data sent by the second main control board 702 based on the difference between the first cache and the second cache.

[0059] The third CDR chip can send the first deviation to the first main control board 701 through the first transceiver module 7031. Or the first deviation can be sent to the first main control board 701 through a feedback module (not shown in the figure). The processing module 70121 in the first main control board can adjust the data to be sent next time according to the received deviation, wherein the first main control board can receive the first deviation through the first transceiver module, or the first main control board can obtain the first deviation through an acquisition module (not shown in the figure). For example, the first main control board can obtain the first deviation from the third CDR chip through a software call. The processing module 70121 in the first main control board can adjust the data to be sent next time according to the received deviation. For example, it can perform time delay compensation on the AM word included in the sent data according to the received deviation, and readjust the position of the AM word transmission. The adjustment accuracy is controlled within a smaller range (such as 100UI). The processing module can be integrated in the media access controller of the first main control board. It should be noted that Figure 7 Other components included in the first main control board and the second main control board are not shown one by one, such as a network processor and a media access controller.

[0060] In a specific embodiment, physical medium attachment sublayers (PMA) 7034 and 7035 may also be included. The PMA converts the data bus bit width and clock domain. After passing through the PMA, the interface clock is converted to an internal unified clock for processing, which is beneficial to improving processing accuracy.

[0061] The first transceiver module 7031 is also used to receive the third data sent by the first main control board after adjusting the deviation. The first main control board 701 compensates for the data to be sent next time based on the first deviation. The next data here refers to the data most recently sent by the first main control board 701 after receiving the first deviation (hereinafter referred to as the third data). For example, the first main control board may determine to delay sending the third data based on the first deviation, or the first main control board may determine to send the third data in advance based on the first deviation. It should be noted that it is almost impossible for the first main control board to completely eliminate the first deviation, and the cost and power consumption will increase accordingly. Therefore, in this solution, the first main control board only needs to control the accuracy within a preset range.

[0062] The second transceiver module 7032 is further configured to receive fourth data sent by the second main control board. The third data and the fourth data serve as backup data for each other.

[0063] The sixth Ethernet physical coding sublayer 7037 is configured to decode the third data received from the first main control board 701 and the fourth data received from the second main control board 702. The sixth Ethernet physical coding sublayer 7037 includes a skew compensation module 70371. As previously described, the skew measurement module 7033 determines a first skew based on the first and second data. The first main control board performs skew compensation on the next data to be transmitted, namely, the third data, based on the first skew, so that the skew between the third and fourth data (hereinafter referred to as the second skew) is within a preset range, such as 100 UI. At this point, a portion of the skew remains, namely the difference between the first and second skews. The interface board can then perform skew compensation on the decoded third and fourth data using the skew compensation module 70371. For example, the skew compensation module 70371 can achieve strict alignment of the AM words sent by the first and second main control boards, minimizing or eliminating the time difference between the third and fourth data. The skew compensation module in this embodiment can be implemented in any manner, such as any skew compensation circuit capable of performing the functions of the skew compensation module. The existing deviation compensation circuit is a well-known technology and will not be described in detail here. It should be noted that if the first main control board 701 does not compensate the deviation between the third data and the fourth data to a preset range, and only relies on the deviation compensation module 70371 to compensate the deviation of the third data and the fourth data, a relatively large cache data is required, resulting in an increase in cost and power consumption. This solution cleverly achieves strict alignment of the data sent by the first main control board and the second main control board through the cooperation of the deviation compensation module 70371 and the main control board. On this basis, the eighth Ethernet physical coding sublayer 7050 encodes the data. In addition, the eighth Ethernet physical coding sublayer 7050 is also used to track the third data when sending the master-slave switching, that is, when sending in the downlink direction, it tracks the data stream of the main control board. Specifically, it can track the AM in the data stream of the main control board. Since the deviation compensation module has performed deviation compensation on the data of the first main control board and the data of the second main control board, the data stream of the standby main control board has been aligned with the data stream of the active main control board, that is, the data stream of the first main control board has been aligned with the data stream of the second main control board, for example, the AM word sent by the first main control board has been aligned with the AM word sent by the second main control board. Therefore, after the electronic switch 7039 determines the active-standby switching, the eighth Ethernet physical coding sublayer 7050 only tracks the data in the active main control board, such as tracking the AM word in the third data mentioned in the embodiment of the present application, so as to ensure that the output data and the input data are aligned, that is, the AM word sent by the third CDR chip 703 can still be consistent with the AM word of the first main control board, and the third data is sent to the opposite device through the third transceiver module.Through the above scheme, it can be achieved that the uplink and downlink data flows do not shift after passing through the third CDR chip 703. The following takes the downlink direction as an example to illustrate the effect of this technology. When introducing the second CDR chip 403 above, it is mentioned that the second CDR chip 403 adopts the AM deletion and reinsertion technology. Although it can ensure that the opposite device will not experience service interruption when the master-slave switching occurs, it will cause delay jitter when the data flow passes through the second CDR chip. For example, assuming that the data blocks before and after the first AM in the first lane sent by the master main control board 401 are the first data block and the second data block respectively. Two data blocks. After the second CDR chip 403 receives the first lane, it will delete the first AM and reinsert the second AM. The positions of the second AM and the first AM are usually different. Assuming that the second AM is inserted after the second data block, the position of the second data block in the first lane after the second AM is inserted is different from the position of the second data block in the first lane before the first AM is deleted. However, inserting the second AM will not affect the position of the first data block in the first lane. It can be seen that the deletion and insertion of the AM introduces delay jitter after the data stream enters the second CDR chip. In this solution, there is no need to delete or insert the AM. The interface board only tracks one of the data streams, such as only tracking the AM in the active main control board. When sending a master-slave switch, since this solution pre-aligns the data streams from the first main control board and the second main control board, only tracking the AM in the data stream sent by the switched active main control board can prevent the data stream from being displaced after passing through the interface board and introduce delay jitter.

[0064] It should be noted that the above-described process is the process of the first main control board being triggered to switch from the backup main control board to the active main control board. If the second main control board switches from the backup main control board to the active main control board again, the above process can be used for understanding. For example, when the second main control board is the backup main control board, the deviation compensation module 70381 included in the seventh Ethernet physical coding sublayer 7038 strictly aligns the data sent by the first and second main control boards. This will not be repeated here. The above describes the processing process of downlink data. When in the uplink direction, the ninth Ethernet physical coding sublayer 7060 decodes the data sent by the opposite device received by the fourth transceiver module 7080. In a specific embodiment, it can also include a deviation compensation module 70611 for deskewing the data received from multiple lanes of the opposite device. The tracking module tracks the decoded data, and the tenth Ethernet physical coding sublayer 7040 encodes the data and sends it to the active main control board. In the uplink direction (from the line side to the system side), the third CDR chip 703 implements the data dual-transmission / selective transmission function. Since there is only one copy of the data source, the tracking module tracks the input data stream to make the uplink delay jitter of the message passing through the third CDR chip 703 close to 0.

[0065] The above is a detailed introduction to the data processing equipment and system provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A data processing device, characterized in that: include: A first transceiver module is used to receive first data sent by the first main control board; A second transceiver module is used to receive second data sent by a second main control board, the first main control board and the second main control board are mutually active and standby main control boards, and the first data and the second data are mutually backup data; a deviation measurement module, configured to determine a first deviation between the first data and the second data; The data processing device further includes a feedback module, configured to send the first deviation to a standby main control board among the first main control board and the second main control board, wherein the first deviation is used by the first main control board to perform a first deviation compensation on the third data, and the feedback module is the same as or different from the first transceiver module; The first transceiver module is further configured to receive third data sent by the first main control board after receiving the first data; The second transceiver module is further configured to receive fourth data sent by the second main control board, where the fourth data and the third data serve as backup data for each other; The deviation compensation module is configured to perform a second deviation compensation on the third data according to the fourth data.

2. The device according to claim 1, characterized in that Also includes: A tracking module, configured to track the third data after the second deviation compensation when the first main control board is switched from the standby main control board to the active main control board; The fourth transceiver module is used to send the third data to the opposite device.

3. The device according to claim 1 or 2, characterized in that The first transceiver module includes P channels, and the second transceiver module includes Q channels, where P and Q are both positive integers. The first transceiver module is specifically configured to receive the first data through the P channel; The second transceiver module is specifically configured to receive the second data through the Q channel; The deviation measurement module is specifically used to determine the first deviation based on the difference between T1 and T2 and the interface rate of the device, where T1 is the arrival time of the last channel in the P channel, and T2 is the arrival time of the last channel in the Q channel.

4. The device according to claim 3, characterized in that Each of the P channels includes an alignment mark AM, and each of the Q channels includes an AM. T1 is the arrival time of the AM in the last channel of the P channels, and T2 is the arrival time of the AM in the last channel of the Q channels.

5. The device according to claim 1 or 2, characterized in that The first transceiver module includes P channels, and the second transceiver module includes Q channels, where P and Q are both positive integers. The first transceiver module is specifically configured to receive the first data through the P channel; The second transceiver module is specifically configured to receive the second data through the Q channel; The device further comprises: a cache module, configured to cache the P channel and the Q channel upon receiving data from the first channel; The deviation measurement module is specifically configured to determine a first skew based on a first cache and a second cache, where the first cache is the cache accumulated by the P-path when the last path in the P-path arrives, and the second cache is the cache accumulated by the Q-path when the last path in the Q-path arrives.

6. A data processing device, characterized in that include: A first transceiver module, configured to send first data to the interface board; an acquisition module, configured to acquire a first deviation, where the first deviation is a deviation between the first data and the second data determined by the interface board, the second data is data sent by the second main control board, the first main control board and the second main control board are each other's active and standby main control boards, the second data and the first data are each other's backup data, and the second transceiver module is the same as or different from the first transceiver module; a processing module, configured to perform deviation compensation on the third data according to the first deviation obtained by the second transceiver module; The first transceiver module is further configured to send the third data after deviation compensation.

7. A data processing system, characterized in that: The data processing system includes an interface board and a main control board, wherein: The interface board is a data processing device as described in any one of claims 1 to 5; The main control board is the data processing device described in claim 6.

8. A data processing system, characterized in that: The data processing system includes a clock data recovery (CDR) chip and a network processor (NP) chip, wherein: The CDR chip is a data processing device as described in any one of claims 1 to 5; The NP chip is the data processing device described in claim 6.

9. A packet transport network (PTN) device, characterized in that: The PTN equipment includes an interface board and a main control board, wherein: The interface board is a data processing device as described in any one of claims 1 to 5; The main control board is the data processing device described in claim 6.

10. A packet transport network (PTN) device, characterized in that: The PTN equipment clock data recovery CDR chip and network processor NP chip, wherein, The CDR chip is a data processing device as described in any one of claims 1 to 5; The NP chip is the data processing device described in claim 6.

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