Heterogeneous Processor Data Reading Device and Method Based on Locking and Unlocking Access Mechanisms

Abstract

The present invention belongs to the technical field of aircraft control, and discloses a heterogeneous processor data reading device and method based on a locking and unlocking access mechanism, including: a first processor, a second processor, and a bus interface processing unit; the first processor and the second processor are heterogeneous processors; the bus interface processing unit includes at least two FPGA controllers, denoted as a first FPGA controller and a second FPGA controller; a dual data buffer is arranged in the first FPGA controller; the first processor and the first FPGA controller are bidirectionally connected through a parallel bus; the second processor and the second FPGA controller are bidirectionally connected through a parallel bus; the first FPGA controller and the second FPGA controller are bidirectionally connected through a parallel bus to solve the problem that the existing heterogeneous processor platform cannot simultaneously obtain the same bus input.

Description

Technical Field

[0001] The present invention relates to, but is not limited to, the field of aircraft control technology, and particularly relates to a heterogeneous processor data reading device and method based on a locking and unlocking access mechanism. Background Art

[0002] With the continuous increase in the functions and complexity of aircraft platforms, the application of airborne flight control computer systems in aircraft platforms has been continuously expanded, and the requirements for the performance, safety, and reliability of flight control computer systems have been continuously improved.

[0003] Traditional airborne flight control computers often work in a backup redundancy manner between processors with the same architecture. This method can ensure that when one computer fails, the backup computer can work normally, ensuring the normal operation of the computer system, thereby improving reliability.

[0004] For flight control computer systems with similar redundancy, multiple computers with exactly the same structure run the same program under the same instruction control and are always in the same working state. Therefore, the coupling between channels is very tight. Experience shows that the tighter the coupling of redundancy channels, the greater the possibility of the entire system crashing due to common mode failures. Therefore, how to effectively suppress common mode failures is another key technology in the overall design of flight control computers.

[0005] For large airliners with higher requirements for reliability and safety, non-similar redundancy technology is adopted in the flight control computer system, that is, multiple different versions of programs run on multiple different hardware channels, effectively suppressing some common mode failures, such as system, software and hardware specification errors, software and hardware design and implementation errors, reducing the failure probability of the flight control computer system to 10 -10 / flight hour. Therefore, in an airborne computer system, a heterogeneous processor computing platform is used, where the architectures of the processors are different but the task instructions are the same, to eliminate common mode failures in the processor system.

[0006] There are slight differences in the operation cycles and synchronization of different processor architectures. If the input signals are not processed, there will often be a situation where the data input by heterogeneous processors is different at the same time. Summary of the Invention

[0007] Aiming at the problems and disadvantages in the above background art, the purpose of the present invention is to propose a heterogeneous processor data reading device and method based on a locking and unlocking access mechanism for synchronizing the bus input signals of heterogeneous processors in an airborne flight control computer, so as to solve the problem that the existing heterogeneous processor platform cannot obtain the same bus input simultaneously.

[0008] To achieve the above purpose, the present invention adopts the following technical solutions.

[0009] Technical solution 1:

[0010] A heterogeneous processor data reading device based on a locking and unlocking access mechanism, the device comprising: a first processor, a second processor, and a bus interface processing unit; the first processor and the second processor are heterogeneous processors;

[0011] The bus interface processing unit includes at least two FPGA controllers, denoted as a first FPGA controller and a second FPGA controller; a dual data buffer is provided in the first FPGA controller; the first FPGA controller and the second FPGA controller are heterogeneous FPGA controllers;

[0012] The first processor is bidirectionally connected to the first FPGA controller through a parallel bus;

[0013] The second processor is bidirectionally connected to the second FPGA controller through a parallel bus;

[0014] The first FPGA controller and the second FPGA controller are bidirectionally connected through a parallel bus.

[0015] The first FPGA controller and the second FPGA controller are physically isolated and powered by different power supplies.

[0016] Technical solution 2:

[0017] A heterogeneous processor data reading method based on a locking and unlocking access mechanism, the method is implemented based on the reading device of technical solution 1, and the method includes:

[0018] S1. The first FPGA controller acquires real-time data on the external bus and caches it in the dual data buffer, and the dual data buffer includes multiple buffer areas, denoted as a first buffer area, a second buffer area, etc.;

[0019] S2. The first processor and the second processor respectively send locking signals to the first FPGA controller periodically;

[0020] S3. After receiving the locking signal, the first FPGA controller stops acquiring data on the external bus;

[0021] S4. Taking the first buffer area as an example, the first processor reads the data in the first buffer area and sends an unlocking signal to the first FPGA controller;

[0022] S5. The second processor reads the data in the first buffer area through the second FPGA controller and sends an unlocking signal to the first FPGA controller;

[0023] After the first buffer in the first FPGA controller receives the unlock signals sent by the first processor and the second processor, it acquires the real-time data on the external bus again.

[0024] The features and further improvements of the second technical solution of the present invention are as follows:

[0025] (1) In S2, the lock signals sent by the first processor and the second processor are both used to lock the first buffer.

[0026] (2) In S3, regardless of whether the first FPGA controller receives the lock signal sent by the first processor or the lock signal sent by the second processor, it locks the first buffer.

[0027] (3) In S3, in the locked state, the first buffer cannot acquire the real-time data on the external bus, and the real-time data on the external bus is stored in other unlocked buffers.

[0028] (4) In S6, after the first FPGA controller receives the unlock signals sent by the first processor and the second processor, it releases the first buffer of the dual data buffer and acquires the real-time data on the external bus again;

[0029] (5) In S6, if the first FPGA controller still does not receive the unlock signal sent by the second processor within the preset time after receiving the unlock signal sent by the first processor, it automatically releases the first buffer of the dual data buffer;

[0030] (6) In S6, if the first FPGA controller still does not receive the unlock signal sent by the first processor within the preset time after receiving the unlock signal sent by the second processor, it automatically releases the first buffer of the dual data buffer.

[0031] (7) The preset time is 3 milliseconds.

[0032] (8) In S3, the method further includes:

[0033] After the first FPGA controller receives the lock signal, if the data acquired from the external bus is updated, it sends a data update flag to the first processor and the second processor respectively;

[0034] After the first processor and the second processor receive the data update flag, they start to read the corresponding data in the dual data buffer.

[0035] The technical solution of the present invention provides a heterogeneous processor data reading device and method based on a locking and unlocking access mechanism, including: a first processor, a second processor, and a bus interface processing unit; the first processor and the second processor are heterogeneous processors; the bus interface processing unit includes at least two FPGA controllers, denoted as a first FPGA controller and a second FPGA controller; a dual data buffer is provided in the first FPGA controller; the first processor and the first FPGA controller are bidirectionally connected through a parallel bus; the second processor and the second FPGA controller are bidirectionally connected through a parallel bus; the first FPGA controller and the second FPGA controller are bidirectionally connected through a parallel bus to solve the problem that the existing heterogeneous processor platform cannot obtain the same bus input simultaneously.

[0036] Compared with the prior art, the beneficial effects of the present invention are: the heterogeneous processor data reading device and method based on the locking and unlocking access mechanism realize that the heterogeneous processor platform obtains the same bus input simultaneously, and solve the problem that the calculation results of heterogeneous processors are different due to the inability to synchronize the input. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 FIG. is a schematic structural diagram of a heterogeneous processor data reading device based on a locking and unlocking access mechanism provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation of the present invention; the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance; in addition, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] Embodiment 1

[0041] An embodiment of the present invention provides a heterogeneous processor data reading device based on a locking and unlocking access mechanism, including: a first processor and its peripheral circuit, a second processor and its peripheral circuit, and a bus interface processing unit and its peripheral circuit;

[0042] Among them, the first processor and the second processor are two processors of different suppliers and different processor architectures. The locking and unlocking access mechanism refers to implementing "locking" and "unlocking" of bus data access through a programmable logic controller in the bus interface processing unit.

[0043] The bus interface processing unit is built-in with two FPGA controllers, which are respectively used for bus interface processing and address and data transmission of the first processor and the second processor. One of the FPGAs should be set with a "dual data buffer" for "locking and unlocking" access.

[0044] The two FPGA controllers are two FPGA controllers of different suppliers and different processor architectures.

[0045] After any processor performs a "locking" operation on the "dual data buffer", the locked data buffer area should latch the latest data packet of the corresponding bus input with effective locking validity monitoring.

[0046] When any data buffer area in the dual data buffer is in the "locked" state, the two heterogeneous processors do not respond to the "locking" of the "dual data buffer", that is, when any processor performs locking, the "locking" function is achieved.

[0047] When both heterogeneous processors perform "unlocking" on the "dual data buffer", the FPGA controller releases the current data buffer area. If the unlocking flag of the other party is not waited for 3 ms after one party has been unlocked, the FPGA controller automatically unlocks and releases the buffer.

[0048] The locked data buffer area should support simultaneous read access by the first processor and the second processor.

[0049] Embodiment 2

[0050] An embodiment of the present invention provides a heterogeneous processor data reading device based on a locking and unlocking access mechanism, as Figure 1 shown, the device includes: a first processor, a second processor, and a bus interface processing unit; the first processor and the second processor are heterogeneous processors;

[0051] The bus interface processing unit includes at least two FPGA controllers, denoted as the first FPGA controller and the second FPGA controller; the first FPGA controller and the second FPGA controller are heterogeneous FPGA controllers; a dual data buffer is set in the first FPGA controller;

[0052] The first processor and the first FPGA controller are bidirectionally connected through a parallel bus;

[0053] The second processor and the second FPGA controller are bidirectionally connected through a parallel bus;

[0054] The first FPGA controller and the second FPGA controller are bidirectionally connected through a parallel bus.

[0055] The first FPGA controller and the second FPGA controller are physically isolated and powered by different power supplies.

[0056] The first FPGA controller is used to obtain real-time data on the external bus and cache it in the dual data buffer. The dual data buffer includes multiple buffer areas, denoted as the first buffer area, the second buffer area, etc.;

[0057] The first processor and the second processor are respectively used to periodically send locking signals to the first FPGA controller;

[0058] Taking the first buffer area as an example, the locking signals sent by the first processor and the second processor are used to lock the first buffer area.

[0059] After receiving the locking signal, the first FPGA controller stops obtaining data on the external bus;

[0060] Regardless of whether the first FPGA controller receives the locking signal sent by the first processor or the second processor, it locks the first buffer area.

[0061] In the locked state, the first buffer area cannot obtain real-time data on the external bus, and the real-time data of the external bus is stored in other unlocked buffer areas.

[0062] The first FPGA controller is also used to, after receiving the locking signal, if the data obtained from the external bus is updated, send data update flags to the first processor and the second processor respectively;

[0063] The first processor and the second processor are also used to, after receiving the data update flag, start reading the corresponding data in the dual data buffer.

[0064] The first processor is used to read the data in the first buffer area and send an unlocking signal to the first FPGA controller;

[0065] A second processor, configured to read data in the first buffer through a second FPGA controller and send an unlocking signal to the first FPGA controller;

[0066] The first FPGA controller is configured to, after receiving the unlocking signal sent by the first processor and the unlocking signal sent by the second processor, obtain real-time data on the external bus again.

[0067] After the first FPGA controller receives the unlocking signal sent by the first processor and the unlocking signal sent by the second processor, it releases the dual data buffer and obtains real-time data on the external bus again;

[0068] Or,

[0069] If the first FPGA controller does not receive the unlocking signal sent by the second processor within a preset time after receiving the unlocking signal sent by the first processor, it automatically releases the dual data buffer;

[0070] Or,

[0071] If the first FPGA controller does not receive the unlocking signal sent by the first processor within a preset time after receiving the unlocking signal sent by the second processor, it automatically releases the dual data buffer, and the preset time is 3 milliseconds.

[0072] Specifically, the first processor and its peripheral circuit receive data from the bus interface processing unit through a parallel bus, perform data calculation, and output the result to the bus interface processing unit through the parallel bus. In this example, the MPC5675 chip of FREESCALE company is used as the first processor, that is, the main control processor, and communicates with the interface processing unit through the parallel bus interface provided by it.

[0073] The second processor and its peripheral circuit have the same task-level function as the first processor and its peripheral circuit. It receives data from the bus interface processing unit through a parallel bus, performs data calculation, and outputs the result to the bus interface processing unit through the parallel bus. In this example, the TMS570LS3137 chip of TI company is used as the second processor and communicates with the interface processing unit through the parallel bus interface provided by it.

[0074] The bus interface processing unit has two built-in FPGA controllers with physically isolated electrical signals, which are respectively used for the bus interface processing and address and data transmission of the first processor and the second processor. One of the FPGA controllers should be set with a "dual data buffer" for "locking and unlocking" access. In this example, the XC7A200T_2FGG676I series FPGA of Xilinx Corporation is used as the FPGA where the "dual data buffer" is located, receiving data from the first processor through a parallel data bus and receiving external bus communication signals through an interface at the same time; the M2GL025T_FG484 series FPGA of Actel Corporation is used as the other FPGA to receive data from the second processor through a parallel data bus and send the data to the FPGA controller where the "dual data buffer" is located after conversion.

[0075] Embodiment 3

[0076] An embodiment of the present invention provides a heterogeneous processor data reading method based on a locking and unlocking access mechanism. The method is implemented based on the reading device of Embodiment 2, and the method includes:

[0077] S1. The first FPGA controller acquires real-time data on the external bus and caches it in the dual data buffer. The dual data buffer includes multiple buffer areas, denoted as the first buffer area, the second buffer area, etc.

[0078] S2. The first processor and the second processor respectively send locking signals to the first FPGA controller periodically.

[0079] In S2, taking the first buffer area as an example, the locking signal sent by the first processor and the locking signal sent by the second processor are used to lock the first buffer area.

[0080] S3. After receiving the locking signal, the first FPGA controller stops acquiring data on the external bus.

[0081] In S3, regardless of whether the first FPGA controller receives the locking signal sent by the first processor or the locking signal sent by the second processor, the first buffer area is locked.

[0082] In S3, in the locked state, the first buffer area cannot acquire real-time data on the external bus, and the real-time data of the external bus is stored in other unlocked buffer areas.

[0083] In S3, the method further includes:

[0084] After receiving the locking signal, if the data acquired from the external bus is updated, the first FPGA controller sends a data update flag to the first processor and the second processor respectively.

[0085] After the first processor and the second processor receive the data update flag, they start to read the corresponding data in the dual data buffer.

[0086] S4, the first processor reads the data in the first buffer area and sends an unlock signal to the first FPGA controller;

[0087] S5, the second processor reads the data in the first buffer area through the second FPGA controller and sends an unlock signal to the first FPGA controller;

[0088] S6, after the first FPGA controller receives the unlock signal sent by the first processor and the unlock signal sent by the second processor, it obtains the real-time data on the external bus again.

[0089] In S6, after the first FPGA controller receives the unlock signal sent by the first processor and the unlock signal sent by the second processor, it releases the dual data buffer and obtains the real-time data on the external bus again;

[0090] Or,

[0091] If the first FPGA controller still does not receive the unlock signal sent by the second processor within the preset time after receiving the unlock signal sent by the first processor, it automatically releases the dual data buffer;

[0092] Or,

[0093] If the first FPGA controller still does not receive the unlock signal sent by the first processor within the preset time after receiving the unlock signal sent by the second processor, it automatically releases the dual data buffer, and the preset time is 3 milliseconds.

[0094] Specifically, the first processor and its peripheral circuits receive the data from the bus interface processing unit through the parallel bus, perform data calculation, and output the result to the bus interface processing unit through the parallel bus. In this example, the MPC5675 chip of FREESCALE company is used as the first processor, that is, the main control processor, and communicates with the interface processing unit through the parallel bus interface provided by it.

[0095] The second processor and its peripheral circuits have the same task-level functions as the first processor and its peripheral circuits. They receive the data from the bus interface processing unit through the parallel bus, perform data calculation, and output the result to the bus interface processing unit through the parallel bus. In this example, the TMS570LS3137 chip of TI company is used as the second processor and communicates with the interface processing unit through the parallel bus interface provided by it.

[0096] The bus interface processing unit incorporates two FPGA controllers with electrically isolated physical signals, which are respectively used for the bus interface processing and address and data transmission of the first processor and the second processor. One of the FPGA controllers should be set with a "dual data buffer" for "locking and unlocking" access. In this example, the XC7A200T_2FGG676I series FPGA of Xilinx is used as the FPGA where the "dual data buffer" is located, receiving the data of the first processor through the parallel data bus and receiving the external bus communication signal through the interface at the same time. The M2GL025T_FG484 series FPGA of Actel is used as the other FPGA to receive the data of the second processor through the parallel data bus and send the data to the FPGA controller where the "dual data buffer" is located after conversion.

[0097] The technical solution of the present invention provides a heterogeneous processor data reading device and method based on a locking and unlocking access mechanism, including: a first processor, a second processor and a bus interface processing unit; the first processor and the second processor are heterogeneous processors; the bus interface processing unit includes at least two FPGA controllers, denoted as the first FPGA controller and the second FPGA controller; a dual data buffer is set in the first FPGA controller; the first processor and the first FPGA controller are bidirectionally connected through a parallel bus; the second processor and the second FPGA controller are bidirectionally connected through a parallel bus; the first FPGA controller and the second FPGA controller are bidirectionally connected through a parallel bus to solve the problem that the existing heterogeneous processor platform cannot simultaneously obtain the same bus input.

[0098] Compared with the prior art, the beneficial effect of the present invention is that the heterogeneous processor computing technology based on the locking and unlocking access mechanism realizes that the heterogeneous processor platform can simultaneously obtain the same bus input, and solves the problem that the computing results of heterogeneous processors are different due to the inability to synchronize the input.

[0099] The above has described the preferred embodiments of the present application in detail, but this patent is not limited to the above embodiments. Within the scope of knowledge possessed by those of ordinary skill in the art, various changes can be made without departing from the spirit of this patent.

Claims

1. A heterogeneous processor data reading device based on a locking and unlocking access mechanism, characterized in that, The device includes: a first processor, a second processor, and a bus interface processing unit; the first processor and the second processor are heterogeneous processors; The bus interface processing unit includes at least two FPGA controllers, denoted as the first FPGA controller and the second FPGA controller; a dual data buffer is set in the first FPGA controller; The first processor and the first FPGA controller are bidirectionally connected through a parallel bus; The second processor and the second FPGA controller are bidirectionally connected through a parallel bus; The first FPGA controller and the second FPGA controller are bidirectionally connected through a parallel bus; The first FPGA controller and the second FPGA controller are physically isolated and powered by different power supplies.

2. A heterogeneous processor data reading method based on a locking and unlocking access mechanism, the method being implemented based on the reading device according to claim 1, characterized in that, The method includes: S1, the first FPGA controller acquires real-time data on the external bus and caches it in the dual data buffer, and the dual data buffer includes multiple buffer areas, denoted as the first buffer area, the second buffer area, etc.; S2, the first processor and the second processor respectively send lock signals to the first FPGA controller periodically; S3, after receiving the lock signal, the first FPGA controller stops acquiring data on the external bus; S4, the first processor reads the data in the first buffer area and sends an unlock signal to the first FPGA controller; S5, the second processor reads the data in the first buffer area through the second FPGA controller and sends an unlock signal to the first FPGA controller; S6, after receiving the unlock signal sent by the first processor and the unlock signal sent by the second processor, the first FPGA controller acquires real-time data on the external bus again.

3. The heterogeneous processor data reading method based on a locking and unlocking access mechanism according to claim 2, characterized in that, In S2, both the lock signal sent by the first processor and the lock signal sent by the second processor are used to lock the first buffer area.

4. The heterogeneous processor data reading method based on a locking and unlocking access mechanism according to claim 3, characterized in that, In S3, regardless of whether the first FPGA controller receives the lock signal sent by the first processor or the lock signal sent by the second processor, the first buffer area is locked.

5. The heterogeneous processor data reading method based on a locking and unlocking access mechanism according to claim 2, characterized in that, In S3, in the locked state, the first buffer area cannot acquire real-time data on the external bus, and the real-time data of the external bus is stored in other unlocked buffer areas.

6. The heterogeneous processor data reading method based on a locking and unlocking access mechanism according to claim 2, characterized in that, In S6, after receiving the unlock signal sent by the first processor and the unlock signal sent by the second processor, the first FPGA controller releases the dual data buffer space and acquires real-time data on the external bus again.

7. The heterogeneous processor data reading method based on a locking and unlocking access mechanism according to claim 2, characterized in that, In S6, if the first FPGA controller does not receive the unlock signal sent by the second processor within a preset time after receiving the unlock signal sent by the first processor, it automatically releases the dual data buffer; and acquires real-time data on the external bus again.

8. The heterogeneous processor data reading method based on a locking and unlocking access mechanism according to claim 2, characterized in that, In S6, if the first FPGA controller does not receive the unlock signal sent by the first processor within a preset time after receiving the unlock signal sent by the second processor, it automatically releases the dual data buffer and acquires real-time data on the external bus again.

9. The heterogeneous processor data reading method based on a locking and unlocking access mechanism according to claim 7 or 8, characterized in that, The preset time is 3 milliseconds.

10. The heterogeneous processor data reading method based on a locking and unlocking access mechanism according to claim 2, characterized in that, In S3, the method further includes: After receiving the lock signal, if the data acquired from the external bus is updated, the first FPGA controller sends a data update flag to the first processor and the second processor respectively; After the first processor and the second processor receive the data update flag, they start to read the corresponding data in the dual data buffer.

Images