A method, device and equipment for repairing upper and lower parts of a dual-crystal memory bar

Abstract

The present application provides a method and device for repairing the upper and lower positions of a dual-crystal memory bar, including: grouping the bad ICs according to the type and bad area of ​​the bad ICs; selecting two groups of bad ICs from the A group, the B group, the C group, the D group and the E group, and selecting at least 2 bad ICs from one of the selected groups, and selecting at least 1 bad IC from the other selected group, and dividing the IC bit area of ​​the address line position in the bad IC according to the grouping of the bad ICs and preset rules; adjusting the layout of the PCB board of the ×16IC dual-crystal package according to the IC bit area and the type of the bad IC. The above method can be used to repair the memory of the DDP type package of the defective product, and the defective product of the memory IC shipped from the factory can be used to make it a qualified product through repair, which effectively utilizes the defective product, saves resources, and is also beneficial to environmental protection to a certain extent.

Description

Technical Field

[0001] The present application relates to the field of memory chip technology, and in particular to a method, device and equipment for repairing upper and lower parts of a dual-crystal memory bar. Background Art

[0002] Memory, also known as random access memory (RAM), also known as main memory, is an internal memory that directly exchanges data with the CPU. It can be read and written at any time (except when refreshed) and is very fast. It is usually used as a temporary data storage medium for operating systems or other running programs. When RAM is working, information can be written (stored) or read (retrieved) from any specified address at any time. The biggest difference between it and ROM is the volatility of data, that is, once the power is off, the stored data will be lost. RAM is used in computers and digital systems to temporarily store programs, data, and intermediate results.

[0003] However, memory manufacturers cannot achieve 100% good quality products during wafer production and IC packaging processes.

[0004] At present, the defective products produced by memory manufacturers are around 10~15%, resulting in a large amount of resource waste. Since precious metals are used in the memory IC and packaging process, if the defective products are destroyed, it will also cause further resource waste. The current extraction of precious metals through chemical methods will cause environmental pollution to a certain extent. Summary of the invention

[0005] In view of the above problems, the present application is proposed to provide a method, device and apparatus for repairing upper and lower parts of a dual-die memory bar that overcomes the above problems or at least partially solves the above problems, including:

[0006] A method for repairing the upper and lower parts of a dual-die memory bar is applied to the repackaging of defective ICs in a ×16 dual-die package. The method comprises:

[0007] The bad ICs are grouped according to their types and bad regions; wherein the groups include group A, group B, group C, group D and group E; the bad region type is the address line bit region; wherein the group A region is 0-3 bits, the group B region is 4-7 bits, the group C region is 8-11 bits, the group D region is 12-15 bits, and the group E region is 8-15 bits;

[0008] Selecting two groups of bad ICs from the group A, group B, group C, group D and group E, selecting at least two bad ICs from one of the selected groups, selecting at least one bad IC from the other selected group, and dividing the IC bit area of ​​the address line bits in the bad IC according to the grouping of the bad ICs and a preset rule;

[0009] According to the IC location area and the type of the defective IC, the layout of the PCB board of the ×16 IC dual die package is adjusted.

[0010] Optionally, the step of grouping the bad ICs according to their types and bad areas, and grouping the bad ICs to include group A, group B, group C, group D and group E, comprises:

[0011] Determine a normal diode value and an error threshold of the address line according to a normal address line position of a normal IC corresponding to the bad IC;

[0012] Detecting the diode of each address line of the bad IC, and comparing it with the normal diode value and the error value, if an abnormal value appears, it is determined to be a bad address line;

[0013] The bad area of ​​the bad IC is determined according to the bad address line.

[0014] Optionally, the step of grouping the defective ICs according to their types and defective areas to include Group A, Group B, Group C, Group D and Group E comprises:

[0015] According to the type of the bad IC, the address line of the bad IC is detected, and the bad area of ​​the address line in the bad IC is determined;

[0016] The bad ICs are divided into 5 groups according to the bad areas of the address line bits; wherein the address line groups include group A with bad areas of only 0-3 bits, group B with bad areas of only 4-7 bits, group C with bad areas of only 8-11 bits, group D with bad areas of only 12-15 bits and group E with bad areas of only 8-15 bits.

[0017] Optionally, the step of dividing the IC bit area of ​​the address line bits in the bad IC according to the grouping of the bad IC and a preset rule comprises:

[0018] Determining available address line bits in the bad IC according to the grouping of the bad IC;

[0019] The available address line bits in the bad IC are combined into the IC bit area according to the preset rule.

[0020] Optionally, the step of combining available address line bits in the bad IC into the IC bit area according to the preset rule comprises:

[0021] When the MDQ digital sequence of the PCB board is 64 bits, the IC bit area is determined according to the available address line bits and the types of available address line bits in the defective IC; wherein the number of the IC bit areas is 8, and the IC bit area includes 8 available address line bits.

[0022] Optionally, the step of combining available address line bits in the bad IC into the IC bit area according to the preset rule comprises:

[0023] When the MDQ digital sequence of the PCB board is 32 bits, the IC bit area is determined according to the available address line bits and the types of available address line bits in the defective IC; wherein the number of the IC bit areas is 4, and the IC bit area includes 8 available address line bits.

[0024] Optionally, the step of adjusting the layout of the PCB board of the ×16 IC single crystal package according to the IC location area and the type of the defective IC includes:

[0025] Determining the arrangement order of the bad ICs according to the IC position area;

[0026] Adjusting the layout of the PCB board according to the type of the bad IC and the arrangement order of the bad IC;

[0027] Wherein, the layout adjustment of the PCB board includes:

[0028] Set the resistors R26, R29, R31, R34, R72, R73, R76, R77, R80, R83, R118, and R119 on the memory PCB to 240 ohms, so that the E9 signal bit is grounded through the 240 ohm resistor;

[0029] Setting the memory PCB board T7 pin to ground;

[0030] Short-circuiting the second pin and the third pin of each of the memory PCB board jumpers Y1 to Y6;

[0031] Set the 207th gold finger of the memory PCB board to connect with the M9 signal line.

[0032] Optionally, after the step of adjusting the layout of the PCB board of the ×16 IC dual die package according to the IC location area and the type of the defective IC, the method further comprises:

[0033] Determining the packaging position of the bad IC according to the IC location area, the type of the bad IC and the laid-out PCB board;

[0034] The defective IC is packaged on the laid-out PCB board according to the packaging position.

[0035] A device for repairing the upper and lower parts of a dual-die memory bar is used for repackaging defective ICs of ×16 dual-die packages. The device comprises:

[0036] A grouping module, used for grouping the bad ICs according to the type and bad area of ​​the bad ICs; wherein the grouping includes group A, group B, group C, group D and group E; the bad area type is the address line bit area; wherein the group A area is 0-3 bits, the group B area is 4-7 bits, the group C area is 8-11 bits, the group D area is 12-15 bits, and the group E area is 8-15 bits;

[0037] A selection module is used to select two groups of bad ICs from the group A, group B, group C, group D and group E, select at least two bad ICs from one of the selected groups, select at least one bad IC from the other selected group, and divide the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and a preset rule;

[0038] The adjustment module is used to adjust the layout of the PCB board of the ×16 IC dual-die package according to the IC location area and the type of the defective IC.

[0039] A device comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the method for repairing the upper and lower bits of a dual-chip memory stick as described above are implemented.

[0040] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned method for repairing the upper and lower bits of a dual-chip memory stick are implemented.

[0041] This application has the following advantages:

[0042] In an embodiment of the present application, the bad ICs are grouped according to their types and bad areas; wherein the groups include Group A, Group B, Group C, Group D and Group E; the bad area type is an address line area; wherein the Group A area is 0-3 bits, the Group B area is 4-7 bits, the Group C area is 8-11 bits, the Group D area is 12-15 bits, and the Group E area is 8-15 bits; two groups of bad ICs are selected from the Group A, Group B, Group C, Group D and Group E, and at least 2 bad ICs are selected from one of the selected groups, and at least 1 bad IC is selected from the other selected group, and according to the grouping of the bad ICs and preset rules, the IC area of ​​the address line in the bad IC is divided; according to the IC area and the type of the bad IC, the layout of the PCB board of the ×16IC dual-crystal package is adjusted. The above method can be used to repair defective DDP type packaged memory. Defective memory ICs shipped out of the factory can be repaired to become qualified products, effectively utilizing the defective products and saving resources. At the same time, it is also beneficial to environmental protection to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the description of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0044] Figure 1 This is a flowchart of the steps of a method for repairing the upper and lower parts of a dual-die memory bar provided by an embodiment of the present application;

[0045] Figure 2 It is a structural block diagram of a device for repairing a single crystal memory provided by an embodiment of the present application;

[0046] Figure 3 This is a schematic diagram of a PCB Layout structure corresponding to a memory IC provided in an embodiment of the present application.

[0047] Figure 4 It is a structural schematic diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the objects, features and advantages of the present application more obvious and understandable, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0049] It should be noted that in any embodiment of the present invention, the SDP package of the memory is a package containing a die (here refers to a memory particle, that is, a memory IC), that is, SDP (Signle-Die Package), and the capacity is still the capacity of a memory particle. DDP is a package containing two dies, that is, DDP (Dual-Die Package), and the capacity is the capacity of two memory particles; of course, the DDP packaging method can also be understood as connecting two memory particles in parallel to expand the bit width. For example, two ×8 memory particles are packaged in DDP, and then the whole can be regarded as a ×16 memory particle. IC chip (Integrated Circuit Chip) is an integrated circuit formed by a large number of microelectronic components (transistors) placed on a plastic substrate to make a chip; Package, that is, packaging (circuit integration term) is the process of assembling integrated circuits into chip final products. Simply put, it is to put the integrated circuit die (die) produced by the foundry on a substrate that plays a bearing role, lead out the pins, and then fix the package into a whole.

[0050] Reference Figure 1 , shows a method for repairing a single crystal memory provided by an embodiment of the present application, which is applied to the repackaging of a defective IC in a ×16 dual crystal package, and the method comprises:

[0051] S110, grouping the bad ICs according to the type and bad area of ​​the bad ICs; wherein the grouping includes group A, group B, group C, group D and group E; the bad area type is the address line bit area; wherein the group A area is 0-3 bits, the group B area is 4-7 bits, the group C area is 8-11 bits, the group D area is 12-15 bits, and the group E area is 8-15 bits;

[0052] S120, selecting two groups of bad ICs from the group A, group B, group C, group D and group E, selecting at least two bad ICs from one of the selected groups, selecting at least one bad IC from the other selected group, and dividing the IC bit areas of the address line bits in the bad ICs according to the grouping of the bad ICs and preset rules;

[0053] S130 , adjusting the layout of the PCB board of the ×16 IC dual die package according to the IC location area and the type of the defective IC.

[0054] In the embodiment of the present application, the bad ICs are grouped according to the type and bad area of ​​the bad ICs; two groups of bad ICs are selected from the A group, the B group, the C group, the D group and the E group, and at least 2 bad ICs are selected from one of the selected groups, and at least 1 bad IC is selected from the other selected group, and the IC bit area of ​​the address line in the bad IC is divided according to the grouping of the bad ICs and the preset rules; the layout of the PCB board of the ×16IC dual-crystal package is adjusted according to the IC bit area and the type of the bad IC. The above method is applied to the repackaging of the bad IC of the ×16 dual-crystal package, that is, the DDP type package memory of the bad product ×16IC is repaired, and the bad product of the memory IC shipped from the factory is used to make it a qualified product through repair, which effectively utilizes the bad product, saves resources, and is also beneficial to environmental protection to a certain extent.

[0055] In the above embodiment, bad ICs are grouped, such as group A, group B, group C, group D and group E of the address line group, so that an optimized grouping method can be obtained by combining and matching different methods, thereby obtaining an optimized group matching repair solution.

[0056] Next, a method for repairing a single crystal memory in this exemplary embodiment will be further described.

[0057] In one embodiment of the present invention, the step S110 is grouping the bad ICs according to their types and bad areas, and the steps before the grouping includes Group A, Group B, Group C, Group D and Group E include: determining the normal diode value and error threshold of the address line according to the normal address line of the normal IC corresponding to the bad IC; detecting the diode of each address line of the bad IC, and comparing it with the normal diode value and the error value, if an abnormal value appears, it is determined to be a bad address line; determining the bad area of ​​the bad IC according to the bad address line.

[0058] In one embodiment of the present invention, the address lines of the bad IC are detected based on the type of the bad IC to obtain the address bit detection results including the bad area, including: determining the address line bits of the corresponding normal memory IC based on the type of the bad IC; detecting the address lines of the bad IC based on the address line bits of the normal memory IC to determine the address line bits of the bad area of ​​the bad IC.

[0059] As described in step S110 , the bad ICs are grouped according to the types and bad regions of the bad ICs.

[0060] In an embodiment of the present invention, the specific process of "grouping the bad ICs according to the types and bad areas of the bad ICs" in step S110 can be further explained in combination with the following description.

[0061] As described in the following steps, according to the type of the bad IC, the address line of the bad IC is detected to determine the bad area of ​​the address line in the bad IC;

[0062] As described in the following steps, the bad IC is divided into 5 groups according to the bad areas of the address line bits; wherein the address line groups include group A with bad areas of only 0-3 bits, group B with bad areas of only 4-7 bits, group C with bad areas of only 8-11 bits, group D with bad areas of only 12-15 bits, and group E with bad areas of only 8-15 bits.

[0063] In the above embodiment, the bad ICs are grouped, for example, they are divided into different groups A, B, C, D and E. By combining and matching different methods, an optimized combination method is obtained, thereby obtaining a group matching repair solution, which can optimize the combination method of the bad ICs, improve the utilization rate of the bad ICs, and further avoid the waste caused by directly discarding or destroying the bad ICs.

[0064] As an example, for example, the bad bits in the "address line" or "bit address line" in the test chip can be tested by simulating a test fixture for "memory stick" application and general memory chip testing software (such as memtest / RST / self-developed software) for segmentation and classification; the memory IC can be tested by simulating the memory model to obtain the bad area of ​​the address line in the bad IC. For example, if the bad area is located in the 0-3 bits of the address line, the bad IC is divided into Group A. If the detected bad area is located in the 4-7 bits of the address line, the bad IC is divided into Group B, and so on to Group C and Group D. If the detected bad area is located in the 8-11 and 12-15 bits of the address line, it is divided into Group E. By dividing into different groups and making different combinations, the maximum reuse of the bad IC is achieved.

[0065] It should be noted that memory IC is a type of IC. Due to its high precision, some defective products will be produced during the production of the package, and the defective products cannot be used directly. According to the working principle of the CPU and memory, the data transmission between the CPU and the memory is multiple bits at a time (the specific number of bits is determined by the data bit width matching the CPU and the memory). In the current mainstream PC, it is generally 8 bits, that is, the 8-bit address lines of the memory IC need to receive data at the same time, otherwise the data transmission cannot be completed. Therefore, if there are bad address line bits in the memory IC, the entire memory will be unusable. Similarly, the defective products of the memory IC manufacturer are not directly used in memory production. Through this solution, the defective IC can be reused to reduce waste, while also reducing the defective rate in memory production, greatly reducing the high cost caused by defective products.

[0066] As described in step S120, two groups of bad ICs are selected from the groups A, B, C, D and E, and at least 2 bad ICs are selected from one of the selected groups, and at least 1 bad IC is selected from the other selected group, and the IC bit areas of the address line bits in the bad ICs are divided according to the grouping of the bad ICs and preset rules.

[0067] It should be noted that the IC bit area is a set of 8 address line bits of the same type, such as 0-7 of the LDQS type or 8-15 of the UDQS type.

[0068] In one embodiment of the present invention, the step S120 of “selecting two groups of bad ICs from the group A, group B, group C, group D and group E, selecting at least two bad ICs from one of the selected groups, selecting at least one bad IC from the other selected group, and dividing the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and the preset rule” can be further explained in combination with the following description.

[0069] As described in the following steps, two groups of bad ICs are selected from the group A, group B, group C, group D and group E, and matching schemes of the two groups of bad ICs are determined;

[0070] As described in the following steps, available address line bits in the bad ICs are determined according to the grouping of the bad ICs.

[0071] As described in the following steps, the available address line bits in the bad IC are combined into the IC bit area according to the preset rule.

[0072] In one embodiment of the present invention, the step of combining the available address line bits in the bad IC into the IC bit area according to the preset rule comprises:

[0073] Determining the arrangement order of the address line bits of the good area in the bad IC according to the MDQ digital sequence and the address line bit type; wherein the MDQ digital sequence includes 0-63 bits or 0-31 bits;

[0074] When the MDQ digital sequence of the PCB board is 64 bits, the IC bit area is determined according to the available address line bits in the bad IC and the types of the available address line bits; specifically, when the MDQ digital sequence is 0-63 bits, 4 first bad ICs are selected from one of the selected groups, and 2 second bad ICs are selected from the other group, and the address line bits of the good area are arranged into 8 groups according to the arrangement order; wherein the number of the IC bit areas is 8, and the IC bit areas include 8 available address line bits.

[0075] When the MDQ digital sequence of the PCB board is 32 bits, the IC bit area is determined according to the available address line bits in the bad IC and the types of the available address line bits. Specifically, when the MDQ digital sequence is 0-31 bits, two first bad ICs are selected from one of the selected groups, and one second bad IC is selected from the other group, and the address line bits of the good area are filled with 4 groups according to the arrangement order; wherein the number of the IC bit areas is 4, and the IC bit areas include 8 available address line bits.

[0076] In one embodiment of the present invention, the address line bits of the good area in the bad IC are arranged in an order according to the MDQ digital sequence and the address line bit type; wherein the MDQ digital sequence includes bits 0-63; when the MDQ digital sequence is bits 0-63, four first bad ICs are selected from one of the selected groups, and two second bad ICs are selected from the other group, and the address line bits of the good area are arranged in eight groups according to the arrangement order;

[0077] In the above embodiment, defective ICs are combined into a 64-bit memory stick through the MDQ digital sequence and applied to current mainstream computers.

[0078] In one embodiment of the present invention, the arrangement order of the address line bits of the good area in the bad IC is determined based on the MDQ digital sequence and the address line bit type; wherein the MDQ digital sequence includes bits 0-31; when the MDQ digital sequence is bits 0-31, two first bad ICs are selected from one of the selected groups, and one second bad IC is selected from the other group, and the address line bits of the good area are arranged into 4 groups according to the arrangement order.

[0079] In the above embodiments, the 32-bit memory with the same circuit mode is also the same, and can also be used in product applications based on the master control IC of the "ARM" architecture and the "DSP" architecture.

[0080] It should be noted that if the MDQ digit is 0-127, it can also be used to repair 128-bit wide memory; since 128-bit wide memory is a special memory, the present application method can also be used to repair 128-bit wide memory.

[0081] In one embodiment of the present invention, the arrangement order of the address line bits of the good area in the bad IC is determined according to the MDQ digital sequence and the address line bit type, including: according to the MDQ digital sequence, combining every 8-bit address line bits, and shielding the address line bits of the bad area to determine the arrangement order of the address line bits of the good area in the bad IC; the high bit is the 8-bit UDQS address line, and the low bit is the 8-bit LDQS address line.

[0082] In one example, two groups of bad ICs are selected from the group A, group B, group C, group D and group E, and matching schemes of the two groups of bad ICs are determined. For a clearer explanation, the following will take the group B + group E scheme as an example, but the present application is not limited to the combination of the group B + group E scheme;

[0083] As shown in the following table:

[0084] U1 U1 U2 U2 U3 U6 U7 U7 U8 U8 Group B Group BGroup B Group B Group E FALL FALL Group E Group B Group BGroup B Group B MDQ: 0-7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 UDQS LDQS LDQS UDQS LDQS LDQS UDQS LDQS LDQS UDQS 8-15 0-3 0-3 8-15 0-7 0-7 8-15 0-3 0-3 8-15

[0085] As shown in the table above, 4 first bad ICs of group B and 2 second bad ICs of group E are selected for scheme matching; specifically, since the bad address line bits of group B are 4-7 and those of group E are 8-15, the corresponding good address line bits of group B are 0-3 and 8-15, and the good address line bits of group E are 0-7; the 8-15 bits of the first bad IC are used as the first group IC (U1), the 8-15 bits of the second first bad IC are used as the third group IC (U3), and the 1st and The two groups of 0-3 bits in the second first bad IC are combined into 8 bits to form the second group of IC (U1+U2). The second group of IC is not a separate memory IC, but is mainly composed of some address lines of the first group of IC and the third group of IC. They are arranged to 0-23 bits of the MDQ digit, and then the first second bad IC is arranged to 24-31 bits of the MDQ digit as the fourth group of IC (U3). This is the arrangement of the first half, and the other half and the arrangement combination can be set to mirror the first half to complete the scheme matching;

[0086] In addition, when the bad IC is matched, since the high address line bits 8-15 (UDQS address line) of the first bad IC in group B are completely good, the UDQS corresponding to bits 0-7 in MDQ will be patched accordingly, the 0-3 bits of the first bad IC and the second first bad IC will be patched accordingly to the LDQS corresponding to bits 8-15 in MDQ, the 8-15 bits of the second first bad IC will be patched accordingly to the UDQS corresponding to bits 16-23 in MDQ, and the LDQS corresponding to bits 24-31 in MDQ will be patched accordingly to the memory of the first second bad IC.

[0087] It should be noted that in the complete memory there are address lines and address lines, and the basic component unit of the memory is the memory IC, and the address lines and address lines of the memory are provided by the memory IC, wherein the address lines and address lines of the memory are provided by the memory IC. Figure 3 As shown, the memory IC address lines are DQS0-DQS7; the address lines are A0-An of the IC, wherein the number of address line bits of the memory IC (i.e., the size of n) determines the capacity of the memory IC, for example, when n=11, the memory IC capacity is 128Mbit (i.e., 16MB), when n=12, the memory IC capacity is 256Mbit (32MB), when n=13, the memory IC capacity is 512Mbit (64MB), when n=14, the memory IC capacity is 1024Mbit (128MB), when n=15, the memory IC capacity is 2048Mbit (256MB), when n=16, the memory IC capacity is 4096Mbit (512MB); wherein the address lines also include BA0, BA1, and BG0.

[0088] As described in step S130, the layout of the PCB board of the ×16 IC single crystal package is adjusted according to the IC location area and the type of the defective IC.

[0089] Reference Figure 3 In one embodiment of the present invention, the specific process of "adjusting the layout of the PCB board of the ×16 IC single crystal package according to the IC location area and the type of the defective IC" in step S130 can be further explained in combination with the following description.

[0090] As described in the following steps, determining the arrangement order of the bad ICs according to the IC position area;

[0091] As described in the following steps, the layout of the PCB board is adjusted according to the type of the bad IC and the arrangement order of the bad IC; wherein the layout adjustment of the PCB board includes:

[0092] Set the resistors R26, R29, R31, R34, R72, R73, R76, R77, R80, R83, R118 and R119 on the memory PCB board to 240 ohms, so that the E9 signal bit is grounded through the 240 ohm resistor; set the T7 pin of the memory PCB board to ground; short-circuit the second pin and the third pin of each of the jumpers Y1~Y6 of the memory PCB board; set the 207th gold finger of the memory PCB board to be connected to the M9 signal line.

[0093] In a specific embodiment, according to the type of the defective IC and the matching scheme between the defective ICs, the resistors R26, R29, R31, R34, R72, R73, R76, R77, R80, R83, R118 and R119 on the memory PCB are set to 240 ohms, so that the E9 signal bit is grounded through the 240 ohm resistor; the T7 pin of the memory PCB is set to be grounded; the second pin and the third pin of each of the jumpers Y1~Y6 of the memory PCB are short-circuited; when the memory PCB is used for DDR4 (4th generation memory), the 207th gold finger of the memory PCB is set to be connected to the M9 signal line.

[0094] It should be noted that Figure 3 The E9 signal pin of U1 on the memory PCB is connected to the signal pin through the resistor R26. The E9 signal lines at other IC positions are connected to the resistors R29, R31, R34, R72, R73, R76, R77, R80, R83, R118 and R119 in the same way as the resistor R26. Therefore, Figure 3 Not shown, the jumper connection method of Y2-Y6 is the same, please refer to Figure 3 Jumper for Y1 in the middle.

[0095] In the above embodiment, according to the set memory PCB board and the bad IC with matched address lines, the address bus, data bus and control bus of the bad IC and the memory PCB board are connected to perform memory repair. Specifically, the LDQS of the bad IC corresponds to the LDQS position of the memory PCB board to be repaired; the UDQS of the bad IC corresponds to the UDQS of the memory PCB board to be repaired, wherein the LDQS includes LDQS_t+LDQS_c, and the control address bits are 0-7; the uDQS includes UDQS_t+UDQS_c, and the control address bits are 8-15.

[0096] As described in step S140, two groups of defective ICs are packaged on the already set memory PCB board according to the matching solution of the two groups of defective ICs.

[0097] In one embodiment of the present invention, the layout of the PCB board of the ×16 IC dual die package is adjusted according to the IC location area and the type of the defective IC.

[0098] As described in the following steps, the packaging position of the bad IC is determined according to the matching scheme between the bad ICs and the laid out PCB board;

[0099] As described in the following steps, the defective IC is packaged on the laid-out PCB board according to the packaging position.

[0100] It should be noted that the ×8IC in this application means an IC with a particle width of 8 bits, and ×16 means an IC with a particle width of 16 bits.

[0101] In the above embodiment, the memory PCB board is set according to the JEDEC (Solid State Technology Association is a standard organization for the microelectronics industry) specification; the segmentation and classification of bad bits in the defective IC chip and the re-circuit design of the PCB are all based on the "JEDEC" specification as the principle of application design to avoid related "compatibility" and electrical problems.

[0102] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0103] Reference Figure 2 , shows a device for repairing the upper and lower parts of a dual-die memory bar provided by an embodiment of the present application, which is applied to the repackaging of defective ICs in ×16 dual-die packages;

[0104] Specifically include:

[0105] The grouping module 210 is used to group the bad ICs according to the type and bad area of ​​the bad ICs; wherein the grouping includes group A, group B, group C, group D and group E; the bad area type is the address line bit area; wherein the group A area is 0-3 bits, the group B area is 4-7 bits, the group C area is 8-11 bits, the group D area is 12-15 bits, and the group E area is 8-15 bits;

[0106] A selection module 220 is used to select two groups of bad ICs from the group A, group B, group C, group D and group E, select at least two bad ICs from one of the selected groups, select at least one bad IC from the other selected group, and divide the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and a preset rule;

[0107] The adjustment module 230 is used to adjust the layout of the PCB board of the ×16 IC dual die package according to the IC location area and the type of the defective IC.

[0108] Reference Figure 4 , showing a computer device of a dual-chip memory bar upper and lower repair method of the present invention, which may specifically include the following:

[0109] The computer device 12 is in the form of a general-purpose computing device, and the components of the computer device 12 may include but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0110] The bus 18 represents one or more of several types of bus 18 structures, including a memory bus 18 or memory controller, a peripheral bus 18, an accelerated graphics port, a processor, or a local bus 18 using any of a variety of bus 18 architectures. These architectures include, by way of example, but are not limited to, an Industry Standard Architecture (ISA) bus 18, a Micro Channel Architecture (MAC) bus 18, an Enhanced ISA bus 18, an Audio Video Electronics Standards Association (VESA) local bus 18, and a Peripheral Component Interconnect (PCI) bus 18.

[0111] The computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0112] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write to non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"). Although Figure 4 Not shown, a disk drive for reading and writing to a removable non-volatile disk (such as a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM or other optical medium) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory may include at least one program product having a set (e.g., at least one) of program modules 42, which are configured to perform the functions of various embodiments of the present invention.

[0113] A program / utility 40 having a set (at least one) of program modules 42 may be stored in, for example, a memory, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules 42, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described herein.

[0114] The computer device 12 may also communicate with one or more external devices 14 (e.g., keyboards, pointing devices, displays 24, cameras, etc.), one or more devices that enable medical personnel to interact with the computer device 12, and / or any device that enables the computer device 12 to communicate with one or more other computing devices (e.g., network cards, modems, etc.). Such communication may be performed via an input / output (I / O) interface 22. In addition, the computer device 12 may also communicate with one or more networks (e.g., local area networks (LANs)), wide area networks (WANs), and / or public networks (e.g., the Internet) via a network adapter 20. As shown, the network adapter 20 communicates with other modules of the computer device 12 via a bus 18. It should be understood that although Figure 4 Not shown, other hardware and / or software modules may be used in conjunction with the computer device 12, including but not limited to: microcode, device drivers, redundant processing units 16, external disk drive arrays, RAID systems, tape drives, and data backup storage systems 34, etc.

[0115] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the upper and lower repair methods of the dual-chip memory stick provided in the embodiment of the present invention.

[0116] That is, when the processing unit 16 executes the program, the following is achieved: grouping the bad ICs according to their types and bad areas; selecting two groups of bad ICs from the A group, the B group, the C group, the D group and the E group, and selecting at least 2 bad ICs from one of the selected groups, and selecting at least 1 bad IC from the other selected group, and dividing the IC bit areas of the address lines in the bad ICs according to the grouping of the bad ICs and preset rules; adjusting the layout of the PCB board of the ×16IC dual-crystal package according to the IC bit areas and the types of the bad ICs.

[0117] In an embodiment of the present invention, the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the upper and lower repair methods of the dual-chip memory stick provided in all embodiments of the present application are implemented:

[0118] That is, when the program is executed by the processor, it is implemented as follows: grouping the bad ICs according to their types and bad areas; selecting two groups of bad ICs from the A group, the B group, the C group, the D group and the E group, and selecting at least 2 bad ICs from one of the selected groups, and selecting at least 1 bad IC from the other selected group, and dividing the IC bit areas of the address lines in the bad ICs according to the grouping of the bad ICs and preset rules; adjusting the layout of the PCB board of the ×16IC dual-crystal package according to the IC bit areas and the types of the bad ICs.

[0119] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPOM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, device or device.

[0120] Computer-readable signal media may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0121] The computer program code for performing the operation of the present invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the medical staff computer, partially on the medical staff computer, as an independent software package, partially on the medical staff computer, partially on the remote computer, or entirely on the remote computer or server. In the case of a remote computer, the remote computer can be connected to the medical staff computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet). The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

[0122] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0123] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0124] The above is a detailed introduction to the upper and lower repair methods, devices and equipment of a dual-crystal memory bar provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for repairing the upper and lower parts of a dual-chip memory bar, characterized in that: The method is applied to the repackaging of defective IC in ×16 dual die package, and comprises: The bad ICs are grouped according to their types and bad regions; wherein the groups include group A, group B, group C, group D and group E; the bad region type is the address line bit region; wherein the group A region is 0-3 bits, the group B region is 4-7 bits, the group C region is 8-11 bits, the group D region is 12-15 bits, and the group E region is 8-15 bits; Selecting two groups of bad ICs from the group A, group B, group C, group D and group E, selecting at least two bad ICs from one of the selected groups, selecting at least one bad IC from the other selected group, and dividing the IC bit area of ​​the address line bits in the bad IC according to the grouping of the bad ICs and a preset rule; According to the IC location area and the type of the defective IC, the layout of the PCB board of the ×16 IC dual die package is adjusted.

2. The method according to claim 1, characterized in that: The steps before grouping the bad ICs according to their types and bad areas to include group A, group B, group C, group D and group E include: Determine a normal diode value and an error threshold of the address line according to a normal address line position of a normal IC corresponding to the bad IC; Detecting the diode of each address line of the bad IC, and comparing it with the normal diode value and the error threshold, if an abnormal value appears, it is determined to be a bad address line; The bad area of ​​the bad IC is determined according to the bad address line.

3. The method according to claim 1, characterized in that The step of grouping the bad ICs according to the types and bad areas of the bad ICs comprises: According to the type of the bad IC, the address line of the bad IC is detected, and the bad area of ​​the address line in the bad IC is determined; The bad ICs are divided into 5 groups according to the bad areas of the address line bits; wherein the address line groups include group A with bad areas of only 0-3 bits, group B with bad areas of only 4-7 bits, group C with bad areas of only 8-11 bits, group D with bad areas of only 12-15 bits and group E with bad areas of only 8-15 bits.

4. The method according to claim 1, characterized in that: The step of dividing the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad IC and the preset rule comprises: Determining available address line bits in the bad IC according to the grouping of the bad IC; The available address line bits in the bad IC are combined into the IC bit area according to the preset rule.

5. The method according to claim 4, characterized in that The step of combining the available address line bits in the bad IC into the IC bit area according to the preset rule comprises: When the MDQ digital sequence of the PCB board is 64 bits, the IC bit area is determined according to the available address line bits and the types of available address line bits in the defective IC; wherein the number of the IC bit areas is 8, and the IC bit area includes 8 available address line bits.

6. The method according to claim 4, characterized in that The step of combining the available address line bits in the bad IC into the IC bit area according to the preset rule comprises: When the MDQ digital sequence of the PCB board is 32 bits, the IC bit area is determined according to the available address line bits and the types of available address line bits in the defective IC; wherein the number of the IC bit areas is 4, and the IC bit area includes 8 available address line bits.

7. The method according to claim 1, characterized in that After the step of adjusting the layout of the PCB board of the ×16 IC dual die package according to the IC location area and the type of the defective IC, the method further comprises: Determining the packaging position of the bad IC according to the IC location area, the type of the bad IC and the laid-out PCB board; The defective IC is packaged on the laid-out PCB board according to the packaging position.

8. A device for repairing the upper and lower parts of a dual-chip memory bar, characterized in that: The device is applied to the repackaging of defective IC in ×16 dual die package, and comprises: A grouping module, used for grouping the bad ICs according to the type and bad area of ​​the bad ICs; wherein the grouping includes group A, group B, group C, group D and group E; the bad area type is the address line bit area; wherein the group A area is 0-3 bits, the group B area is 4-7 bits, the group C area is 8-11 bits, the group D area is 12-15 bits, and the group E area is 8-15 bits; A selection module is used to select two groups of bad ICs from the group A, group B, group C, group D and group E, select at least two bad ICs from one of the selected groups, select at least one bad IC from the other selected group, and divide the IC bit area of ​​the address line bit in the bad IC according to the grouping of the bad ICs and a preset rule; The adjustment module is used to adjust the layout of the PCB board of the ×16 IC dual-die package according to the IC location area and the type of the defective IC.

9. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the method according to any one of claims 1 to 7 when executed by the processor.

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