Memory test system and method

Abstract

The embodiment of the invention provides a memory testing system and method, and relates to the technical field of embedded system hardware manufacturing. According to the memory test system disclosed by the invention, the physical layer interface of the memory controller is calibrated, the input / output interface of the memory bus is trained, and the optimized parameters are generated, so that the memory data of the memory unit (including memory particles) can be collected under the optimal condition corresponding to the optimized parameters. And then, carrying out a pressure test on the storage unit based on the optimized parameters, and recording fault information and abnormal information of the storage unit according to a pressure test result. Therefore, the memory test system provided by the invention not only can cover the test of the memory particles, but also can cover the test of the memory controller, and can ensure the stability and reliability of the whole memory unit.

Description

Technical Field

[0001] This application relates to the technical field of embedded system hardware manufacturing, and particularly to a memory test system and method. Background Art

[0002] In the technical field of embedded system hardware manufacturing, since memory errors may cause the crash or data loss of devices such as computers and servers, or systems such as nuclear power control systems and embedded systems, the correctness and stability of the memory are crucial for the overall performance of the device or system.

[0003] To ensure the normal operation of memory (such as DDR3, DDR4, etc.), various test tools and technologies are usually required to verify the correctness and stability of the memory. In one implementation, memory testing can be performed through Memtest-class stress testing software (such as Memtest86 and Memtester). However, these tools are mainly used for stress testing of memory cells (such as memory chips), and cannot cover the testing of memory controllers or IP cores. In another implementation, memory testing can also be performed through JEDEC-compliant conformance testing. This type of memory testing is mainly used to verify the signal integrity of the memory interface, usually relying on high-end digital storage oscilloscopes and conformance testing software, which can separate read and write signals and perform waveform measurements. However, this type of memory testing usually requires complex test equipment and fixture jigs, and cannot dynamically calibrate the parameter deviations of memory controllers and memory chips in the actual operating environment of electronic devices.

[0004] Therefore, how to develop a test method that can cover both memory chips and memory controllers and provide long-term stability in the actual operating environment has become a technical problem to be solved urgently. Summary of the Invention

[0005] Based on the above problems, this application provides a memory test system and method, which can not only cover memory chips but also cover memory controllers, and can ensure the stability and reliability of the entire memory unit.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] In a first aspect, this application discloses a memory test system, which includes: a memory interface calibration and training module, a storage unit stress testing module, and a fault recording module;

[0008] The memory interface calibration and training module is used to calibrate the physical layer interface of the memory controller and train the input and output interfaces of the memory bus to generate optimized parameters, where the optimized parameters are used to ensure that the memory data of the storage unit is collected under the best conditions, and the storage unit includes memory chips;

[0009] The storage unit stress testing module is configured to perform a stress test on the storage unit according to the optimized parameters to obtain a stress test result;

[0010] The fault recording module is configured to record the fault information and abnormal information of the storage unit according to the stress test result.

[0011] Optionally, the memory controller memory interface calibration and training module is specifically configured to: during the operation of the storage unit, dynamically calibrate the physical layer interface of the memory controller according to real-time voltage information and real-time temperature information, and dynamically train the input / output interface of the memory bus.

[0012] Optionally, the fault recording module is further configured to: when a system crash caused by memory occurs, restore the error scene and automatically resume the interrupted test program.

[0013] Optionally, the storage unit stress testing module is specifically configured to: perform a stress test on the storage unit by at least one of generating different data patterns, traversing all memory addresses, generating random numbers, or performing data bit shift and flip operations.

[0014] Optionally, the memory interface calibration and training module includes:

[0015] The first calibration unit is configured to calibrate the physical layer interface of the memory controller by adjusting the on-chip termination resistance and output impedance;

[0016] The second calibration unit is configured to calibrate the physical layer interface of the memory controller by adjusting the delay of the memory controller;

[0017] The first training unit is configured to train the input / output interface of the memory bus by aligning the signal paths among the memory controller, the printed circuit board transmission line, and the memory die;

[0018] The second training unit is configured to train the input / output interface of the memory bus by automatically adjusting the reference voltage value.

[0019] In a second aspect, the present application discloses a memory testing method, the method including:

[0020] By calibrating the physical layer interface of the memory controller and training the input / output interface of the memory bus, optimized parameters are generated, where the optimized parameters are used to ensure that the memory data of the storage unit is acquired under optimal conditions, and the storage unit includes memory die;

[0021] Perform a stress test on the storage unit according to the optimized parameters to obtain a stress test result;

[0022] Record the fault information and abnormal information of the storage unit according to the stress test result.

[0023] Optionally, the calibrating the physical layer interface of the memory controller and training the input / output interface of the memory bus includes:

[0024] During the operation of the storage unit, dynamically calibrate the physical layer interface of the memory controller and dynamically train the input / output interface of the memory bus according to the real-time voltage information and real-time temperature information.

[0025] Optionally, the method further includes:

[0026] When a system crash caused by memory occurs, restore the error scene and automatically resume the interrupted test program.

[0027] Optionally, the performing a stress test on the storage unit includes:

[0028] Perform a stress test on the storage unit by generating different data patterns, traversing all memory addresses, generating random numbers, or performing at least one of data bit shift and flip operations.

[0029] Optionally, the calibrating the physical layer interface of the memory controller and training the input / output interface of the memory bus includes:

[0030] Calibrate the physical layer interface of the memory controller by adjusting the on-chip termination resistance and output impedance;

[0031] Calibrate the physical layer interface of the memory controller by adjusting the latency of the memory controller;

[0032] Train the input / output interface of the memory bus by aligning the signal paths among the memory controller, the printed circuit board transmission line, and the memory die;

[0033] Train the input / output interface of the memory bus by automatically adjusting the reference voltage value.

[0034] Compared with the prior art, the present application has the following beneficial effects:

[0035] The embodiments of the present application provide a memory test system and method. The memory test system disclosed in the present application calibrates the physical layer interface of the memory controller and trains the input / output interface of the memory bus to generate optimized parameters, so as to ensure that the memory data of the storage unit (including memory chips) can be collected under the best conditions corresponding to the optimized parameters. Subsequently, a stress test is performed on the storage unit based on these optimized parameters, and the fault information and abnormal information of the storage unit are recorded according to the stress test results. Therefore, the memory test system provided by the present application can cover both the test of memory chips and the test of the memory controller, and can ensure the stability and reliability of the entire memory unit. Therefore, the memory test system provided by the present application can cover both the test of memory chips and the test of the memory controller, and can ensure the stability and reliability of the entire memory unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0037] Figure 1A Schematic diagram of a memory test system provided by an embodiment of the present application;

[0038] Figure 1B Schematic diagram of a SOC / FPGA memory controller architecture provided by an embodiment of the present application;

[0039] Figure 2 Flowchart of a memory test method provided by an embodiment of the present application;

[0040] Figure 3 Schematic diagram of the operation of a test case provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] As described above, in order to ensure the normal operation of the memory, various test tools and technologies are usually required to verify the correctness and stability of the memory.

[0042] In one implementation, memory testing can be performed through Memtest-class stress testing software (such as Memtest86 and Memtester). However, these tools are mainly used for stress testing of memory units, can detect faults in memory chips, but cannot cover the testing of memory controllers or IP cores.

[0043] In another implementation, memory testing can also be performed through compliance testing that conforms to the JEDEC standard. This type of memory testing is mainly used to verify the signal integrity of the memory interface. It usually relies on high-end digital storage oscilloscopes and compliance testing software, which can separate read and write signals and perform waveform measurements. However, this type of memory testing generally requires complex test equipment and fixture jigs, and it is impossible to dynamically calibrate the parameter deviations of the memory controller and memory die in the actual operating environment of the electronic device.

[0044] After research, the inventors have proposed a memory testing system and method. The memory testing system disclosed in this application calibrates the physical layer interface of the memory controller and trains the input / output interfaces of the memory bus to generate optimized parameters, so as to ensure that the memory data of the storage unit (including memory die) can be acquired under the best conditions corresponding to the optimized parameters. Subsequently, based on these optimized parameters, a stress test is performed on the storage unit, and the fault information and abnormal information of the storage unit are recorded according to the stress test results. Thus, the memory testing system provided in this application can cover both the testing of memory die and the testing of memory controller, and can ensure the stability and reliability of the entire memory unit. Thus, the memory testing system provided in this application can cover both the testing of memory die and the testing of memory controller, and can ensure the stability and reliability of the entire memory unit. Further, this application can automatically record relevant fault information and abnormal information according to the stress test results, greatly improving the effectiveness and efficiency of long-term operation stability testing and environmental stress testing. And, due to integrating the above multiple functions into one, this memory testing system can more effectively screen out qualified electronic devices after board-level integration, helping to improve the quality control level in the production process and reduce the product return rate and maintenance cost caused by memory problems.

[0045] In order to enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0046] See Figure 1A , which is a schematic diagram of a memory testing system provided by an embodiment of this application. The memory testing system 10 includes a memory interface calibration and training module 11, a storage unit stress testing module 12, and a fault recording module 13.

[0047] The memory interface calibration and training module 11 is used to calibrate the physical layer interface of the memory controller and train the input / output interfaces of the memory bus to generate optimized parameters, where the optimized parameters are used to ensure that the memory data of the storage unit is acquired under optimal conditions.

[0048] The storage unit stress test module 12 is used to perform a stress test on the storage unit according to the optimized parameters to obtain a stress test result.

[0049] The fault recording module 13 is used to record the fault information and abnormal information of the storage unit according to the stress test result.

[0050] See Figure 1B , this figure is a schematic diagram of a SOC / FPGA memory controller architecture provided by an embodiment of the present application. The memory test system 10 provided by the embodiment of the present application covers the physical layer (Port Physical Layer, PHY) of the memory controller, the I / O interfaces of the memory bus, and the storage unit (including memory chips). Among them, the PHY layer is the physical interface for communication between the memory controller and the external memory. It is responsible for processing signal transmission and reception to ensure reliable transmission of memory data. By calibrating and training the PHY layer, signal quality and transmission rate can be optimized to ensure that memory data is acquired and processed under optimal conditions. The I / O interface of the memory bus is the key channel connecting the memory controller and the storage unit, responsible for input and output operations of memory data. By calibrating and training the I / O interface, the efficiency and reliability of memory data transmission can be further improved, reducing signal distortion and errors. The storage unit is the place where data is actually stored, usually composed of multiple memory chips. Through comprehensive stress testing, potential faults and abnormal conditions in the storage unit can be detected to ensure its normal operation under high-load environments.

[0051] See Figure 2 , this figure is a flowchart of a memory test method provided by an embodiment of the present application. The memory test method includes:

[0052] S201: Configure the initial configuration parameters.

[0053] The initial configuration parameters include one or more of data rate (DataRate), bus width (Bus Width), additive latency related parameters, driver strength, output impedance, and on-die termination resistance (On-Die Termination, ODT). Among them, the data rate refers to the amount of data that can be transmitted per second by the memory interface, usually in Mbps (megabits per second) or Gbps (gigabits per second). The bus width refers to the number of data bits transmitted each time by the memory interface, such as 8 bits, 16 bits, 32 bits, etc. The latency related parameters are used to compensate for various delays in circuit design, such as propagation delay, clock skew, etc., to ensure that the signal transmission between the memory controller and the memory die meets the timing requirements and guarantees that the memory data is accurately sampled and processed within the correct time window. The driver strength refers to the current capacity that the driver can provide, usually in milliamperes (mA), and the output impedance refers to the resistance characteristic of the driver, usually in ohms (Ω). The two jointly affect the signal integrity and transmission quality. The on-die termination resistance refers to the termination resistor added inside the memory chip, usually in ohms (Ω), which is used to absorb the reflected wave and reduce signal reflection, thereby improving signal integrity.

[0054] By reasonably configuring the initial configuration parameters (data rate, bus width, latency related parameters, driver strength, output impedance, and on-die termination resistance), the signal integrity and power integrity of the memory interface can be significantly improved, ensuring its reliability and stability after calibration and training.

[0055] S202: Read the predefined data from the multi-purpose register through the multi-purpose register setting command.

[0056] The predefined data includes timing parameters (such as refresh period, delay time, etc.), performance parameters (such as data rate, bus width, etc.), and environment adaptation parameters (such as temperature compensation, voltage regulation, etc.). Specifically, the predefined data can be read from the multi-purpose register through the multi-purpose register setting (Mode Register Set, MRS) command. Subsequently, according to the read predefined data, the memory test system can dynamically adjust the memory configuration during operation according to environmental changes (such as temperature, voltage fluctuations) or specific application requirements (such as performance optimization). In one example, when the detected temperature rises, the memory test system can adjust the refresh period to prevent memory data loss.

[0057] S203: Perform ZQ calibration on the physical layer interface of the memory controller by adjusting the on-die termination resistance RTT and the output impedance RON.

[0058] ZQ calibration is a crucial step for optimizing signal integrity between the DDR memory controller and the memory cells (including memory chips). By adjusting the on-chip termination resistance (RTT) and output impedance (RON), it reduces signal reflections and improves the quality of the signal waveform, thereby enhancing the reliability and efficiency of data transmission. Moreover, ZQ calibration pays particular attention to the combined effects of voltage (V), temperature (T), and process variations (PVT) to ensure optimal performance under various operating conditions.

[0059] It should be noted that when the memory test system starts up or powers on, the physical layer (PHY) of the memory controller automatically performs a ZQ calibration. This initial calibration is typically done automatically through a hardware mechanism without the need for software intervention, aiming to ensure optimal signal integrity from the start. During the operation of the memory test system, the voltage and temperature may change. To cope with these changes, the memory controller PHY can re-perform the ZQ calibration during operation through specific commands to ensure optimal performance under various operating conditions.

[0060] S204: Calibrate the physical layer interface of the memory controller by adjusting the latency of the memory controller.

[0061] In some specific implementation methods, the latency of the memory controller PHY can be adjusted by performing equalization on the memory controller PHY. Among them, equalization aims to ensure that the memory data of the memory cells is sent and received at the correct time point. By adjusting different latency parameters, the timing deviation caused by factors such as circuit design, manufacturing process, and temperature changes can be compensated.

[0062] Specifically, during the equalization process, the following four latencies mainly need to be adjusted: First, the Write Leveling latency. The Write Leveling latency refers to the latency between the generated clock CK and the write DQS (Data Strobe). In DDR memory, write operations require precise timing control. The Write Leveling latency ensures that the memory data can reach the memory chips within the correct clock cycle, avoiding data loss or errors.

[0063] Second, the Read DQS Gating latency. The Read DQS Gating latency refers to conditioning the read DQS gating using the midpoint of the read DQS preamble. In read operations, the DQS signal is used to synchronize the reception of data. By adjusting the Read DQS Gating latency, it can be ensured that the memory data is read at the correct moment, avoiding memory data misalignment or loss.

[0064] Third, Read latency. Read latency refers to the DQS latency related to the intervention of the associated DQ read. Read latency ensures that in a read operation, the DQS signal can correctly align with the data signal (DQ), enabling the memory data to be correctly sampled within the expected time window.

[0065] Fourth, Write latency. Write latency refers to the DQ / DQM latency related to the associated DQS during writing. Write latency ensures that in a write operation, the DQS signal can correctly align with the data signal (DQ), enabling the memory data to be correctly written into the memory die within the expected time window.

[0066] It should be noted that different circuit layout wirings will result in different signal propagation path lengths and characteristic impedances, thus affecting the signal transmission time and quality. For example, longer traces will increase the signal propagation delay, while shorter traces may reduce the delay but increase the crosstalk risk. Therefore, the delay adjustment needs to be determined according to the specific circuit layout wiring.

[0067] S205: Train the input / output interface of the memory bus by aligning the signal paths among the memory controller, the printed circuit board transmission line, and the memory die.

[0068] In some specific implementation manners, the signal paths among the memory controller, the printed circuit board transmission line, and the memory die can be ensured to be aligned through the IO training (Input / Output Training) of the memory controller. Among them, through aligning the signal paths among the memory controller, the printed circuit board transmission line, and the memory die, the IO training can accurately measure and compensate the time delays of each part, ensuring that the memory data is accurately sent and received within the correct clock cycle.

[0069] Specifically, the IO training mainly includes the following steps: First step, run an algorithm to align the clock CK and the data strobe DQS of the SDRAM. Second step, run an algorithm and calculate the correct DRAM read / write latency. Third step, run an algorithm and calculate the correct DRAM read / write latency. Fourth step, if the signal integrity is not good and the data cannot be reliably written or read, report an error.

[0070] S206: Train the input / output interface of the memory bus by automatically adjusting the reference voltage value.

[0071] DDR4 uses POD (Pseudo Open Drain) level. POD is a pseudo open-drain driver standard designed to improve energy efficiency and reduce power consumption. Different from the SSTL level used by DDR3, a dynamic reference voltage value VrefDQ is generated inside the DDR4 chip, which enables DDR4 to automatically adjust the reference voltage according to the actual working conditions and train the input / output interface of the memory bus.

[0072] Specifically, in DDR4, the reference voltage value VrefDQ is dynamically adjusted according to factors such as drive strength (Ron), load, and termination (ODT) to ensure that memory data can be correctly sampled within the correct voltage range during the reception and transmission of data signals (DQ). Moreover, by dynamically adjusting VrefDQ, signal noise and distortion can be reduced, thereby improving the reliability of data transmission. Also, the memory controller can automatically adjust VrefDQ according to the current working state (such as temperature, voltage change, etc.) to ensure that the system is always in the best working state.

[0073] It should be noted that the above step S206 is only applicable to the memory test method of DDR4. If it is a memory test for DDR3, the S206 step is not required.

[0074] S207: During the operation of the storage unit, according to the real-time voltage information and real-time temperature information, dynamically calibrate the physical layer interface of the memory controller and dynamically train the input / output interface of the memory bus.

[0075] This step aims to ensure that the signal transmission between the memory controller and the storage unit (including memory chips) can maintain the best performance and reliability under different working conditions (i.e., temperature and voltage) during the operation of the storage unit. Exemplarily, when the detected temperature rises, the frequency can be reduced and the voltage can be increased to maintain stable operation.

[0076] It should be noted that after each dynamic training, the memory test system will also perform a series of tests (such as read / write operations, signal integrity tests, etc.) to evaluate the performance of the storage unit under the current settings.

[0077] S208: According to the optimized parameters, perform a stress test on the storage unit to obtain the stress test results.

[0078] Performing a stress test on the storage unit according to the optimized parameters means performing a stress test on the storage unit under the condition of the best working performance of the IO to obtain the stress test results.

[0079] It should be noted that, based on the optimized parameters, transplantation and adaptation can be carried out on the open-source stress testing program Memtest, so as to perform stress testing on the storage unit on the open-source stress testing program Memtest and obtain the stress testing results. Among them, Memtest is a widely used open-source memory testing tool that detects possible errors in the random access memory (RAM) of a computer through a series of strict test cases. Transplanting and adapting Memtest means integrating the core functions of this tool into a specific hardware or software environment while ensuring its performance and reliability in the new environment.

[0080] In some specific implementation manners, stress testing the storage unit includes: stress testing the storage unit by at least one of generating different data patterns, traversing all memory addresses, generating random numbers, or performing data bit shift and flip operations. Among them, data pattern testing refers to filling the memory with different predefined data patterns to detect problems that may occur in different patterns. For example, patterns such as all 0s, all 1s, and alternating bits can help identify bit sticking or other physical defects. Address traversal refers to systematically accessing each memory address to ensure that all locations are covered and checking for address decoding problems or other local faults. Random number generation refers to writing and reading back data sets created by a pseudo-random number generator to the memory, which is used to simulate data streams in actual applications and detect whether the memory can work stably in a complex data environment. Data bit shift and flip refers to performing shift and flip operations on bit patterns, which helps to discover interference problems between adjacent bits, such as crosstalk and other phenomena.

[0081] In other specific implementation manners, more advanced error detection mechanisms can also be executed, such as supporting CRC (Cyclic Redundancy Check), ECC (Error Correction Code) check, and the ability to automatically capture and record memory error information. CRC / ECC check refers to detecting errors that occur during transmission or storage by calculating and verifying the check value of a data block. CRC is applicable to most application scenarios, while ECC is specifically designed for situations where single-bit errors can be automatically corrected and double-bit errors can be detected, which is particularly important for systems with high reliability requirements. For this, this application does not make any limitations.

[0082] It should be noted that, in actual applications, test script firmware can be generated through software tools and test cases can be run on the target machine. See Figure 3, This figure is a schematic diagram of the operation of a test case provided by an embodiment of the present application. It starts and loads from ports such as USB and network, or directly starts and runs the test program on the FLASH of the target machine. It does not depend on OS components and has independent functions such as logging and file system. During the test, it automatically tracks, locates, and records memory faults / exception information, automatically saves or outputs the fault scene information, restores the scene where the error occurred after a system crash caused by memory, and automatically resumes the interrupted test program to continue running.

[0083] S209: According to the stress test results, record the fault information and exception information of the storage unit.

[0084] When a memory error is detected according to the stress test results, it can immediately obtain and record the fault information and exception information of the storage unit, such as error type, occurrence location, timestamp, etc., so as to form a fault log. These fault logs are crucial for subsequent analysis of the fault cause, location of the problem area, and selection of repair measures.

[0085] In some specific implementation manners, this memory test method further includes: when a system crash caused by memory occurs, restore the error scene (that is, reproduce the specific conditions and environment that caused the system crash of the memory test), and automatically resume the interrupted test program. Thus, even if the memory test system crashes, it can ensure that the test task will not be completely interrupted, reducing the time required for manual restart of the test. Through the automated recovery mechanism, it can better cope with sudden memory test system failures and ensure the continuity and integrity of the test process.

[0086] In summary, the present application discloses a memory test method. The memory test method disclosed in the present application calibrates the physical layer interface of the memory controller and trains the input / output interface of the memory bus to generate optimized parameters to ensure that the memory data of the storage unit (including memory chips) can be collected under optimal conditions. Based on these optimized parameters, a stress test is performed on the storage unit, and the fault information and exception information of the storage unit are recorded according to the stress test results. Thus, the memory test method provided by the present application can cover both the test of memory chips and the test of the memory controller, and can ensure the stability and reliability of the entire memory unit. Further, the present application can automatically record relevant fault information and exception information according to the stress test results, greatly improving the effectiveness and efficiency of long-term running stability tests and environmental stress tests. And, because it integrates the above multiple functions into one, this memory test system can more effectively screen out qualified electronic devices after board-level integration, helping to improve the quality control level in the production process and reducing the product return rate and maintenance cost caused by memory problems.

[0087] It should be noted that the embodiments in this specification are all described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description of the method embodiments. The device and system embodiments described above are only illustrative. The units described as separate components may or may not be physically separated. The components referred to as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative work.

[0088] As described above, it is only a specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in this application should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A memory testing system, characterized in that: The system includes: a memory interface calibration and training module, a storage unit stress testing module and a fault recording module; The memory interface calibration and training module is used to generate optimized parameters by calibrating the physical layer interface of the memory controller and training the input and output interfaces of the memory bus, wherein the optimized parameters are used to ensure that the memory data of the storage unit is collected under optimal conditions, and the storage unit includes memory particles; The storage unit stress testing module is used to perform a stress test on the storage unit according to the optimized parameters to obtain a stress test result; The fault recording module is used to record the fault information and abnormality information of the storage unit according to the stress test result.

2. The system according to claim 1, characterized in that The memory controller memory interface calibration and training module is specifically used to: during the operation of the storage unit, dynamically calibrate the physical layer interface of the memory controller according to real-time voltage information and real-time temperature information, and dynamically train the input and output interfaces of the memory bus.

3. The system according to claim 1, characterized in that The fault recording module is also used to restore the error scene and automatically resume the interrupted test program when a system crash caused by memory occurs.

4. The system according to claim 1, characterized in that The storage unit stress testing module is specifically used to perform stress testing on the storage unit by at least one of generating different data patterns, traversing all memory addresses, generating random numbers, or performing data bit shift flipping operations.

5. The system according to claim 1, characterized in that The memory interface calibration and training module includes: The first calibration unit is used to calibrate the physical layer interface of the memory controller by adjusting the on-chip termination resistance and the output impedance; The second calibration unit is used to calibrate the physical layer interface of the memory controller by adjusting the delay of the memory controller; The first training unit is used to train the input and output interfaces of the memory bus by aligning the signal paths between the memory controller, the printed circuit board transmission lines and the memory particles; The second training unit is used to train the input and output interfaces of the memory bus by automatically adjusting the reference voltage value.

6. A memory testing method, characterized in that: The method comprises: By calibrating the physical layer interface of the memory controller and training the input and output interfaces of the memory bus, optimized parameters are generated, wherein the optimized parameters are used to ensure that the memory data of the storage unit is collected under optimal conditions, and the storage unit includes memory particles; Performing a stress test on the storage unit according to the optimized parameters to obtain a stress test result; According to the stress test result, the failure information and abnormality information of the storage unit are recorded.

7. The method according to claim 6, characterized in that The method of calibrating the physical layer interface of the memory controller and training the input and output interfaces of the memory bus includes: During the operation of the storage unit, the physical layer interface of the memory controller is dynamically calibrated according to the real-time voltage information and the real-time temperature information, and the input and output interfaces of the memory bus are dynamically trained.

8. The method according to claim 6, characterized in that The method further comprises: When a system crash caused by memory occurs, the error site is restored and the interrupted test program is automatically resumed.

9. The method according to claim 6, characterized in that The performing stress testing on the storage unit comprises: The storage unit is stress-tested by at least one of generating different data patterns, traversing all memory addresses, generating random numbers, or performing data bit shift flipping operations.

10. The method according to claim 6, characterized in that The method of calibrating the physical layer interface of the memory controller and training the input and output interfaces of the memory bus includes: Calibrate the physical layer interface of the memory controller by adjusting the on-chip termination resistance and output impedance; Calibrate the physical layer interface of the memory controller by adjusting the delay of the memory controller; Training the input and output interfaces of the memory bus by aligning the signal paths between the memory controller, the printed circuit board transmission lines and the memory particles; The input and output interfaces of the memory bus are trained by automatically adjusting the reference voltage value.

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