A radio frequency LDMOS device and a manufacturing process thereof
The LDMOS device structure, which combines a thick epitaxial layer with a semi-through hole, solves the problem of epitaxial layer thickness limiting breakdown voltage and capacitance in the prior art, and achieves high-efficiency and low-cost RF performance improvement.
Patent Information
- Application Number
- CN202010913893.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-09-03
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2040-09-03
AI Technical Summary
The epitaxial layer thickness of existing high-power LDMOS devices for radio frequency is less than 10µm, resulting in low breakdown voltage and large capacitance, which limits the improvement of device operating voltage and power density. At the same time, the through-hole process is costly and increases the reliability risks of device processing and application.
By combining a thick, high-resistivity epitaxial layer with a semi-through-hole, the device and substrate are connected through the semi-through-hole, which reduces capacitance and increases breakdown voltage. The use of semi-through-hole pads and a first-layer metal connection reduces the resistance between the device and the substrate, thus reducing reliability risks.
This improved the device's breakdown voltage range and gain, reduced capacitance, increased efficiency, reduced cost, and enhanced device stability and reliability.
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Figure CN114141735B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of radio frequency power semiconductor devices, and particularly relates to a radio frequency LDMOS device and a manufacturing process thereof. BACKGROUND
[0002] A first structure of a conventional radio frequency high-power application LDMOS (lateral double-diffused metal oxide semiconductor transistor) device is shown in FIG. 1, in which a source region 22 and a body contact region 25 of the LDMOS device are connected by a silicide, and a heavily doped region 210 is used to connect the body contact region 25 and a substrate 27. This scheme uses a heavily doped region 210 of the same doping type as the substrate 27 and an epitaxial layer 26 to connect the LDMOS device and the substrate, which increases a thermal process of wafer processing, reduces wafer consistency and yield, and meanwhile, the resistance of the heavily doped region affects the performance of the radio frequency device, and more importantly, the connection mode of the heavily doped region limits the thickness of the epitaxial layer, thereby limiting the working voltage of the device. Figure 1 A second structure of a conventional radio frequency high-power application LDMOS device is shown in FIG. 2, in which a first layer metal 19 and the substrate 17 are connected by a tungsten shallow via 110. The second device structure uses a tungsten shallow via to replace the conventional heavily doped connection scheme, which reduces the resistance between the device and the substrate and reduces the thermal process of the heavily doped region.
[0003] Figure 2 However, the thickness of the epitaxial layer of the above-mentioned two conventional device structures is less than 10 um, and a low-resistivity epitaxial layer is used. The low-resistivity thin epitaxial layer makes the breakdown voltage of the LDMOS device low and the capacitance large, which is not conducive to the improvement of the radio frequency performance and the increase of the power density by increasing the working voltage. Moreover, the full via process is high in cost and increases the risk of device processing and application reliability.
[0004] Therefore, how to provide an LDMOS device compatible with the working voltage and low capacitance, and the problem of high cost of full via is an urgent problem to be solved.
[0005] Therefore, how to provide an LDMOS device compatible with the working voltage and low capacitance, and the problem of high cost of full via is an urgent problem to be solved. SUMMARY
[0006] The main purpose of the present application is to provide a radio frequency LDMOS device to overcome the shortcomings of the prior art.
[0007] Another purpose of the present application is to provide a manufacturing process of a radio frequency LDMOS device.
[0008] To achieve the above-mentioned purposes, the technical scheme adopted by the present application comprises: a radio frequency LDMOS device, comprising:
[0009] a substrate,
[0010] an epitaxial layer disposed on the substrate, the epitaxial layer having a thickness greater than 10 um and a resistivity greater than 10000 times of the substrate, and a body contact region of a device and a semi-via formed in the epitaxial layer, one end of the semi-via penetrating the body contact region to a surface of the epitaxial layer away from the substrate, and the other end of the semi-via penetrating the epitaxial layer to connect with the substrate;
[0011] a first metal layer,
[0012] a semi-via pad between the first metal layer and the epitaxial layer, and one end of the semi-via pad connected with the first metal layer, and the other end of the semi-via pad connected with the semi-via.
[0013] In a preferred embodiment, the thickness of the epitaxial layer is 10 um to 50 um.
[0014] In a preferred embodiment, the resistivity of the epitaxial layer is 10000 to 100000 times of the substrate.
[0015] In a preferred embodiment, a plurality of semi-vias are connected with the first metal layer through the semi-via pad.
[0016] In a preferred embodiment, the LDMOS device further comprises a source region formed in the epitaxial layer, and the source region and the body contact region are connected with the first metal layer through a via.
[0017] In a preferred embodiment, the LDMOS device further comprises a drift region, a drain region, a gate oxide layer and a gate region, the drift region and the drain region are formed in the epitaxial layer, the gate oxide layer is formed on the epitaxial layer, and the gate region is formed on the gate oxide layer.
[0018] In a preferred embodiment, the depth of the semi-via is greater than the thickness of the epitaxial layer, and the semi-via is a semi-via of tungsten material.
[0019] Embodiments of the present application provide a manufacturing process of a radio frequency LDMOS device, comprising:
[0020] S100, growing an epitaxial layer on a substrate, the epitaxial layer having a thickness greater than 10 um and a resistivity greater than 10000 times of the substrate;
[0021] S200, growing a gate oxide layer on the epitaxial layer, depositing a polysilicon gate on the gate oxide layer, and etching a gate region;
[0022] S300, forming a body contact region, a source region, a drift region and a drain region in the epitaxial layer by ion implantation;
[0023] S400, etching a deep trench on the epitaxial layer, one end of the deep trench passing through the body contact region to the surface of the epitaxial layer away from the substrate, the other end passing through the epitaxial layer to the substrate, and then filling tungsten material in the deep trench to form a semi-via;
[0024] S500, depositing tungsten metal on the epitaxial layer and etching a semi-via pad on the tungsten metal, the semi-via pad connecting the semi-via;
[0025] S600, finally depositing a first metal layer on the semi-via pad and forming a via, the first metal layer being connected with the semi-via pad and the body contact region and the source region through the via.
[0026] In a preferred embodiment, the thickness of the gate oxide layer is 10nm-100nm.
[0027] In a preferred embodiment, the depth of the deep trench is 10um-60um.
[0028] Compared with the prior art, the present application has at least the following beneficial effects: the present application uses a thick and high-resistivity epitaxial layer and a semi-via to connect the device and the substrate, by combining the thick and high-resistivity epitaxial layer with the semi-via, the breakdown voltage range of the device is improved, and the capacitance of the device is reduced, at the same time, the connection mode of the semi-via, the semi-via pad and the first metal layer further reduces the resistance of the device connected to the substrate, and improves the gain and efficiency of the device. Compared with the full via, the device has lower cost, is more stable, and reduces the reliability risk in device processing and application. BRIEF DESCRIPTION OF DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0030] Figure 1 is the first structure diagram of the prior LDMOS device;
[0031] Figure 2 is the second structure diagram of the prior LDMOS device;
[0032] Figure 3 is the cross-sectional structure diagram of the LDMOS device of the present application;
[0033] Figure 4 is the top view structure diagram of the LDMOS device of the present application;
[0034] Figure 5is a structural schematic diagram of step S100 in the manufacturing process of the present application;
[0035] Figure 6 is a structural schematic diagram of step S200 in the manufacturing process of the present application;
[0036] Figure 7 is a structural schematic diagram of step S300 in the manufacturing process of the present application;
[0037] Figure 8 is a structural schematic diagram of step S400 in the manufacturing process of the present application;
[0038] Figure 9 is a structural schematic diagram of step S500 in the manufacturing process of the present application;
[0039] Figure 10 is a flowchart of the manufacturing process of the present application.
[0040] Reference signs:
[0041] 31, gate region, 311, gate oxide layer, 32, source region, 33, drift region, 34, drain region, 35, body contact region, 36, epitaxial layer, 37, substrate, 38, via, 39, first metal layer, 310, half via, 312, half via pad. DETAILED DESCRIPTION
[0042] The present application will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which: detailed embodiments of the present application are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the present application, which can be embodied in various forms. Therefore, specific functional details disclosed herein are not to be interpreted as limiting, but only as a representative basis for teaching one skilled in the art to employ the present application in virtually any appropriate detailed embodiment. The present application is based on and claims priority to U.S. Provisional Patent Application No. 62 / 947, 1 10, filed December 13, 2019, the disclosure of which is incorporated by reference in its entirety.
[0043] The radio frequency LDMOS device and its manufacturing process disclosed by the present application improve the breakdown voltage range of the device by combining a thick and high-ancestry epitaxial layer with a half via, reduce the capacitance of the device, and at the same time, the connection mode of the half via, the half via pad and the first layer of metal further reduces the resistance of the device connected to the substrate, improves the gain and efficiency of the device. Compared with the full via, it has lower cost, the device is more stable, and the reliability risk in device processing and application is reduced.
[0044] In combination Figure 3 and Figure 4 As shown in the figure, the radio frequency LDMOS device disclosed by the embodiment of the present application comprises a substrate 37, an epitaxial layer 36, a gate oxide layer 311, a gate region 31, a half via pad 312 and a first layer of metal 39, wherein,
[0045] The epitaxial layer 36 is arranged on the substrate 37. In this embodiment, the epitaxial layer 36 is formed by growing on the substrate 37. The thickness of the formed epitaxial layer 36 is greater than 10 um. In practice, the thickness of the epitaxial layer 36 is preferably between 10 um and 50 um. The resistivity of the epitaxial layer 36 is more than 10000 times the resistivity of the substrate 37. In practice, the resistivity of the epitaxial layer 36 is preferably between 10000 times and 100000 times the resistivity of the substrate 37. The resistivity of the epitaxial layer 36 is between 10 times and 100 times the resistivity of the existing epitaxial layer. By using a thick epitaxial layer with high resistivity, the depletion layer of the PN junction of the output end is wider, and the upper limit of the breakdown voltage of the device is improved. Due to the increase in the width of the depletion layer and the improvement in the resistivity, the capacitance of the output end is reduced, and the efficiency of the device, especially the high-frequency efficiency, is improved.
[0046] The gate oxide layer 311 is formed on the epitaxial layer 36. The gate region 31 of the device is formed on the gate oxide layer 311. In this embodiment, the gate oxide layer 311 is grown on the epitaxial layer 36. The thickness of the gate oxide layer 311 is between 10 nm and 100 nm. Then, the polysilicon gate is deposited on the gate oxide layer 311, and the shape of the gate is etched to form the gate region 31 of the device.
[0047] The body contact region 35, the source region 34, the drift region 33, and the drain region 34 of the device are formed in the epitaxial layer 36. In this embodiment, the body contact region 35, the source region 34, the drift region 33, and the drain region 34 of the device are formed in the epitaxial layer 36 by ion implantation.
[0048] A half-via 310 is also formed in the epitaxial layer 36. The half-via 310 is perpendicular to the epitaxial layer 36. One end of the half-via 310 passes through the body contact region 35 to the surface of the epitaxial layer 36 away from the substrate 37 (i.e., the upper end surface). The other end of the half-via 310 passes through the epitaxial layer 36 to the substrate 37. In this embodiment, a deep trench is first etched in the epitaxial layer 36. The deep trench is perpendicular to the epitaxial layer 36. One end of the deep trench passes through the body contact region 35 to the surface of the epitaxial layer 36 away from the substrate 37 (i.e., the upper end surface). The other end of the deep trench passes through the epitaxial layer 36 to the substrate 37. Then, the deep trench is filled with tungsten material to form the half-via 310 of tungsten material. In practice, the depth of the half-via 310 is greater than the thickness of the epitaxial layer 36, preferably 2 to 5 um greater than the thickness of the epitaxial layer 36. Therefore, in practice, the depth of the half-via 310 is preferably between 10 um and 60 um. The present application uses a connection method of connecting the device and the substrate 37 through the half-via 310, so that the device has a lower connection resistance. Compared with the full-via process scheme, the half-via process is compatible with the shallow via process, the back surface structure of the chip is compatible with the traditional scheme, and the cost is lower, without additional reliability risks.
[0049] A semi-through hole pad 312 is formed on the upper surface of the epitaxial layer 36 and connected with one end of the semi-through hole 310 extending to the upper end surface of the substrate 37. In the embodiment, the semi-through hole pad 312 is also a semi-through hole pad of tungsten material. One semi-through hole pad 312 can cover one or more semi-through holes 310.
[0050] A first layer metal layer 39 is formed on the semi-through hole pad 312, one end of the semi-through hole pad 312 is connected with the first layer metal layer 39, and the other end is connected with the semi-through hole 310. In addition, the first layer metal layer 39 is also connected with the body contact region 35 and the source region 32 of the device through the through hole 38, so as to realize the connection between the device and the substrate 37.
[0051] A plurality of semi-through holes 310 can be connected with the semi-through hole pad 312 at the same time, and the semi-through hole pad 312 connected with the plurality of semi-through holes 310 can be connected with the same first layer metal layer 39.
[0052] In combination Figures 5 to 10 As shown in the figure, the manufacturing process of the radio frequency LDMOS device disclosed in the embodiment comprises the following steps:
[0053] S100, growing an epitaxial layer 36 on the substrate 37, the thickness of the epitaxial layer 36 is greater than 10um, and the resistivity of the epitaxial layer 36 is more than 10000 times of the resistivity of the substrate 37.
[0054] In implementation, the thickness and concentration of the epitaxial layer 36 can be set according to the device index, wherein the thickness of the epitaxial layer 36 is generally set to be between 10um and 50um, and the resistivity of the epitaxial layer 36 is preferably 10000-100000 times of the resistivity of the substrate 37.
[0055] S200, growing a gate oxide layer 311 on the epitaxial layer 36, depositing a polysilicon gate on the gate oxide layer 311, and etching a gate region 31.
[0056] In implementation, the thickness of the gate oxide layer 311 is preferably 10nm-100nm.
[0057] S300, forming a body contact region 35, a source region 32, a drift region 33 and a drain region 34 in the epitaxial layer 36 by ion implantation.
[0058] S400, etching a deep groove on the epitaxial layer 36, one end of the deep groove passing through the body contact region 35 to the surface of the epitaxial layer 36 away from the substrate 37, and the other end passing through the epitaxial layer 36 to the substrate, and then filling tungsten material in the deep groove to form a semi-through hole 310.
[0059] In implementation, the depth of the deep groove is 10um-60um.
[0060] S500, depositing tungsten metal on the epitaxial layer 36 and etching a semi-via pad 312 on the tungsten metal, the semi-via pad 312 connecting the semi-via 310.
[0061] One semi-via pad 312 can cover one or more semi-vias 310. Multiple semi-vias 310 can be connected to the same semi-via pad 312 at the same time, and the semi-via pad 312 connecting multiple semi-vias 310 can be connected to the same first metal layer 39.
[0062] S600, finally depositing the first metal layer 39 on the semi-via pad 312 and forming a via 38, the first metal layer 39 being connected to the semi-via pad 312 and connected to the body contact 35 and the source 32 through the via 38, realizing the connection between the device and the substrate 37. The finally formed device structure is shown in Figure 3
[0063] Aspects, embodiments, features, and examples of the present application should be considered in all respects as illustrative only and not restrictive, the scope of the present application being defined only by the claims. Other embodiments, modifications, and uses can occur to those skilled in the art upon a reading of the description of the application, and such are intended to be within the scope of the present application.
[0064] The use of the title and section headings in this application is not intended to limit the application; each section can apply to any aspect, embodiment, or feature of the application.
[0065] The use of the terms "include," "includes," "including," "have," "has," "having," or the like are generally understood as open-ended and do not exclude additional, unrecited elements or methods.
[0066] It should be understood that the order of steps or order for performing certain actions is immaterial so long as the application teachings remain operable. Moreover, two or more steps or actions can be conducted simultaneously or concurrently.
[0067] While the present application has been described with reference to illustrative embodiments, those with ordinary skill in the art will understand that various other modifications, omissions, and / or additions can be made without departing from the spirit and scope of the application. Additionally, many modifications can be made to adapt a particular situation or material to the teachings of the application without departing from the scope of the application. Accordingly, the application is not intended to be limited to the particular disclosed embodiments, but rather is to cover all modifications falling within the scope of the application as defined by the appended claims. Furthermore, unless specifically stated otherwise, any use of the terms first, second, etc., does not indicate any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.
Claims
1. A radio frequency LDMOS device, characterized by, The LDMOS device comprises: a substrate, an epitaxial layer disposed on the substrate, the thickness of the epitaxial layer is greater than 10 um, and the resistivity of the epitaxial layer is 10000 times or more of the substrate resistivity, so as to widen the PN junction depletion layer of the device output end; the body contact area of the device is formed in the epitaxial layer, and a semi-via penetrates the body contact area to the surface of the epitaxial layer away from the substrate at one end and is connected with the substrate at the other end; the number of the semi-via is one or more; a first metal layer, a semi-via pad between the first metal layer and the epitaxial layer, one end of which is connected with the first metal layer, and the other end of which is connected with the semi-via, covering one or more semi-vias, so as to reduce the connection resistance of the device.
2. The RF LDMOS device of claim 1, wherein, The thickness of the epitaxial layer is 10 um to 50 um.
3. The RF LDMOS device of claim 1, wherein, The resistivity of the epitaxial layer is 10000 to 100000 times of the substrate resistivity.
4. The RF LDMOS device of claim 1, wherein, The LDMOS device further comprises a source region formed in the epitaxial layer, and the source region and the body contact area are connected with the first metal layer through a via.
5. The RF LDMOS device of claim 1, wherein, The LDMOS device further comprises a drift region, a drain region, a gate oxide layer and a gate region, wherein the drift region and the drain region are formed in the epitaxial layer, the gate oxide layer is formed on the epitaxial layer, and the gate region is formed on the gate oxide layer.
6. The radio frequency LDMOS device of claim 1, wherein, The depth of the semi-via is greater than the thickness of the epitaxial layer, and the semi-via is a tungsten semi-via.
7. A process for fabricating a radio frequency LDMOS device, characterized by, The process comprises: S100, growing an epitaxial layer on a substrate, the thickness of the epitaxial layer is greater than 10 um, and the resistivity of the epitaxial layer is 10000 times or more of the substrate resistivity, so as to widen the PN junction depletion layer of the device output end; S200, growing a gate oxide layer on the epitaxial layer, depositing a polysilicon gate on the gate oxide layer, and etching a gate region; S300, forming a body contact area, a source region, a drift region and a drain region in the epitaxial layer by ion implantation; S400, etching a deep trench on the epitaxial layer, one end of the deep trench penetrating the body contact area to the surface of the epitaxial layer away from the substrate, and the other end penetrating the epitaxial layer to the substrate, and then filling tungsten material in the deep trench to form a semi-via; the number of the semi-via is one or more; S500, depositing tungsten metal on the epitaxial layer and etching a semi-via pad on the tungsten metal, the semi-via pad connecting the semi-via and covering one or more semi-vias, so as to reduce the connection resistance of the device; S600, finally depositing a first metal layer on the semi-via pad and forming a via, the first metal layer being connected with the semi-via pad and connected with the body contact area and the source region through the via.
8. The fabrication process of a radio frequency LDMOS device according to claim 7, wherein, The thickness of the gate oxide layer is 10 nm to 100 nm.
9. The process of claim 7, wherein the process further comprises: The depth of the deep trench is 10 um to 60 um.
Citation Information
Patent Citations
Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device
CN105374879A