Method for manufacturing a 3D memory device

Abstract

The application discloses a manufacturing method of a 3D memory device, comprising: forming a first array structure, the first array structure comprising a substrate, a first stack structure above the substrate, a plurality of first channel holes penetrating the first stack structure in a core area of the first array structure, and a plurality of positioning pegs extending into the first stack structure in a mark area of the first array structure; etching the first stack structure in the mark area to expose the plurality of positioning pegs; taking the plurality of positioning pegs in the mark area as a mark, and stacking a second array structure on the first array structure, the second array structure comprising a second stack structure above the first stack structure and a plurality of second channel holes penetrating the second stack structure. The manufacturing method of the 3D memory device can realize the alignment of the upper and lower array structures in the stacked 3D memory device and the alignment of the corresponding channel holes in the upper and lower array structures.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a manufacturing method of a 3D memory device. BACKGROUND

[0002] The improvement of the storage density of a memory device is closely related to the progress of semiconductor manufacturing process. With the feature size of the semiconductor manufacturing process getting smaller and smaller, the storage density of the memory device gets higher and higher. In order to further improve the storage density, a memory device with a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked along a vertical direction, which can multiply the integration on a wafer with a unit area and effectively reduce the cost.

[0003] In the preparation process of the existing 3D NAND memory device, with the increase of the number of stacked layers, a dual stack technology is generally adopted, and the channel hole needs to be completed by two etching processes. However, due to the stress effect and process limitation, the two etching processes cannot achieve complete alignment of the upper and lower channel holes, and the top critical dimension of the lower channel hole is larger than the bottom critical dimension of the upper channel hole, which easily causes the functional layer film on the sidewall of the channel hole to be damaged in the subsequent etching process. This will affect the electrical performance of the final memory cell and reduce the yield and reliability of the product.

[0004] Therefore, an improved manufacturing method of a 3D memory device is expected to solve the above problems SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a manufacturing method of a 3D memory device, so as to realize the alignment of the upper and lower array structures in the stacked 3D memory device.

[0006] According to an aspect of the present application, a manufacturing method of a 3D memory device is provided, comprising: forming a first array structure, the first array structure comprising a substrate, a first layer structure located above the substrate, a plurality of first channel holes penetrating the first layer structure in a core area of the first array structure, and a plurality of positioning pegs extending into the first layer structure in a mark area of the first array structure; etching the first layer structure in the mark area to expose the plurality of positioning pegs; and stacking a second array structure on the first array structure with the plurality of positioning pegs in the mark area as a mark, the second array structure comprising a second layer structure located above the first layer structure and a plurality of second channel holes penetrating the second layer structure.

[0007] Optionally, the etching the first stack structure to expose the plurality of positioning pegs comprises: etching and removing at least one upper layer of the first stack structure in the mark region to form a groove, so that the plurality of positioning pegs are located in the groove and protrude above a bottom surface of the groove.

[0008] Optionally, when a second array structure is formed by stacking on the first array structure, the topography of the groove and the plurality of positioning pegs is transferred to an upper surface of the second array structure.

[0009] Optionally, the etching and removing at least one upper layer of the first stack structure in the mark region to form a groove comprises: forming a polysilicon layer on the first stack structure; forming a photoresist layer on the polysilicon layer and patterning the photoresist layer; etching the polysilicon layer to expose the first stack structure; etching and removing at least one upper layer of the first stack structure to form a groove.

[0010] Optionally, between the steps of etching the polysilicon layer and etching the first stack structure, further comprising: removing photoresist and etching residues.

[0011] Optionally, the etching the polysilicon layer to expose the first stack structure comprises: using a first gas to etch the polysilicon layer to expose the first stack structure via the patterned photoresist layer as a mask; wherein the first gas comprises any one or several of hydrogen bromide, chlorine.

[0012] Optionally, the etching and removing at least one upper layer of the first stack structure to form a groove comprises: using a second gas to etch and remove at least one upper layer of the first stack structure to form a groove via the etched polysilicon layer as a mask; wherein the second gas comprises any one or several of hexafluorobutadiene, octafluorocyclobutane or argon.

[0013] Optionally, the forming the first array structure comprises: forming a first stack structure on the substrate, the first stack structure comprising a plurality of first interlayer insulating layers and a plurality of first sacrificial layers alternately stacked; forming a positioning hole extending from a surface of the first stack structure into the first stack structure; filling a sacrificial part in the positioning hole and forming a flat surface of the first stack structure; forming a first interlayer insulating layer on the flat surface; polishing the first interlayer insulating layer to a preset thickness by chemical mechanical polishing; wherein the sacrificial part comprises any one of polysilicon or carbon material.

[0014] Optionally, the forming the positioning hole extending from the surface of the first stack structure into the first stack structure comprises: forming a positioning hole penetrating through the first stack structure.

[0015] Optionally, the mark area is a scribe area of the 3D memory device.

[0016] The manufacturing method of the 3D memory device provided by the application utilizes a dry etching process, effectively avoids the influence of process parameter deviation caused by over-etching on the performance of the 3D memory device, and further, in the process of etching the polysilicon layer and the first stacked structure to make one end of the plurality of positioning pegs protrude from the bottom surface of the groove, different etching gases are used to selectively etch different target materials, for example, plasma gas etching process is used, and only the etching gas needs to be changed to etch different target materials without damaging the structure of other materials, and the etching process can be completed in the same machine, further simplifying the process flow, accelerating the transmission of WIP (Work-in-Process), thereby reducing the production cost.

[0017] Further, the positioning peg provided by the embodiment of the application not only has recognition due to the difference in material from the first stacked structure, but also has structural difference due to the protrusion of one end of the positioning peg from the bottom surface of the groove, thereby further increasing the recognition, making the positioning peg clearly visible in the overlay process and the overlay accuracy measurement process, so that the subsequent etching process can better follow the preset position, and at the same time, it is beneficial to improve the process parameters according to the related values obtained by measurement, further reducing the offset between the second channel hole and the corresponding first channel hole.

[0018] Optionally, the sacrificial part material for forming the plurality of positioning pegs is selected from any one of polysilicon or carbon material. Further, using carbon material as the sacrificial part can not only obtain the same structural strength as the polysilicon material, but also effectively reduce the cost.

[0019] Optionally, the upper layer of the first stacked structure is a first interlayer insulating layer, which can be used as a barrier layer to prevent the positioning peg from being damaged in the process of etching the polysilicon layer, so that the positioning peg as the mark of OVL is clearer, thereby making the subsequent etching process better follow the preset position. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 a and 1b respectively show an equivalent circuit diagram and a structural schematic diagram of a memory cell string of a 3D memory device;

[0022] Figure 2 show a perspective view of a 3D memory device according to an embodiment of the application;

[0023] Figure 3 showFigure 2 A-A direction cross-sectional view of a 3D memory device

[0024] Figure 4 Manufacturing method of a 3D memory device showing an embodiment of the present application

[0025] Figures 5a to 5h Cross-sectional views showing various stages of a manufacturing method of a 3D memory device according to an embodiment of the present application DETAILED DESCRIPTION

[0026] Various embodiments of the present application will be described in detail below with reference to the attached drawings. In the various drawings, like components or modules are denoted by like reference numerals. For the sake of clarity, each portion in the drawings is not drawn to scale.

[0027] It should be understood that, in the following description, "circuitry" can include a single or multiple components of hardware, programmable circuitry, state machine circuitry, and / or elements storing instructions for execution by programmable circuitry. When an element or circuitry is referred to as being "connected to" another element, or "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements between the elements, the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that there are no intervening elements.

[0028] Meanwhile, certain terms have been used throughout this patent document and claims to refer to particular components. As one skilled in the art will appreciate, manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to." Also, the term "couple" or its derivatives refer to either an indirect or direct connection. The terms "coupled" or "connected" are used synonymously.

[0029] In this application, the term "semiconductor structure" refers to the collective semiconductor structure formed throughout the various steps of fabricating a memory device, including all layers or regions that have been formed. Many specific details of the present application are described below in order to provide a thorough understanding of the present application. However, as will be understood by those skilled in the art, the present application can be practiced without incorporating these specific details.

[0030] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0031] This invention can be presented in various forms, some of which will be described below.

[0032] Figure 1 a and 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively. In this embodiment, the storage cell string shown includes four storage cells. It is understood that the invention is not limited thereto, and the number of storage cells in the storage cell string can be any number, for example, 32 or 64.

[0033] like Figure 1 a As shown, the first end of the memory cell string 100 is connected to the bit line BL, and the second end is connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between the first and second ends, including: a first selection transistor Q1, storage transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the first selection line SSL, and the gate of the second selection transistor Q2 is connected to the second selection line GSL. The gates of the storage transistors M1 to M4 are respectively connected to the corresponding word lines WL1 to WL4.

[0034] like Figure 1 bAs shown, the first select transistor Ql and the second select transistor Q2 of the memory cell string 100 include gate conductors 109b and 109c, respectively, and the memory transistors Ml to M4 include gate conductors 109a, respectively. The gate conductors 109a, 109b, and 109c are in a stack order with the transistors in the memory cell string 100, and are separated from each other by an interlayer dielectric layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or extends through the gate stack structure. In a middle portion of the channel pillar 110, the gate conductor 109a is sandwiched between a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 and the channel layer 111, thereby forming the memory transistors Ml to M4. In both ends of the channel pillar 110, the gate conductors 109b and 109c are sandwiched between the blocking dielectric layer 114 and the channel layer 111, thereby forming the first select transistor Ql and the second select transistor Q2.

[0035] In this embodiment, the channel layer 111 is composed of doped polysilicon, for example, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are composed of oxide, for example, silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, for example, silicon nitride and silicon oxynitride containing metal or semiconductor particles, and the gate conductors 109a, 109b, and 109c are composed of metal, for example, tungsten. The channel layer 111 is used to provide the channel region of the select transistors and the memory transistors, and the doping type of the channel layer 111 is the same as the type of the select transistors and the memory transistors. For example, for the N-type select transistors and the memory transistors, the channel layer 111 can be N-type doped polysilicon.

[0036] In this embodiment, the core of the channel pillar 110 is the channel layer 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the blocking dielectric layer 114 form a stack structure around the sidewall of the core. In an alternative embodiment, the core of the channel pillar 110 is an additional insulating layer, and the channel layer 111, the tunneling dielectric layer 112, the charge storage layer 113, and the blocking dielectric layer 114 form a stack structure around the core.

[0037] In this embodiment, the first select transistor Ql and the second select transistor Q2, and the memory transistors Ml to M4 use the common channel layer 111 and the blocking dielectric layer 114. In the channel pillar 110, the channel layer 111 provides the source-drain regions and the channel layer of the plurality of transistors. In an alternative embodiment, the semiconductor layer and the blocking dielectric layer of the first select transistor Ql and the second select transistor Q2, and the semiconductor layer and the blocking dielectric layer of the memory transistors Ml to M4 can be formed in separate steps, respectively. In the channel pillar 110, the semiconductor layer of the first select transistor Ql and the second select transistor Q2 is electrically connected to the semiconductor layer of the memory transistors Ml to M4.

[0038] In a write operation, the memory cell string 100 uses the FN tunneling efficiency to write data into a selected memory transistor among the memory transistors M1 to M4. Taking the memory transistor M2 as an example, while the source line SL is grounded, the second control gate selective line (Gate Selective Line) GSL is biased to about zero volt, so that the selection transistor Q2 corresponding to the second control gate selective line GSL is turned off, and the first source selective line (Source Selective Line) SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the first source selective line SSL is turned on. Further, the bit line BIT2 is grounded, the word line WL2 is biased at a programming voltage VPG, for example, about 20V, and the rest of the word lines are biased at a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, the electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting the data into charges stored in the charge storage layer 113 of the memory transistor M2.

[0039] In a read operation, the memory cell string 100 determines the amount of charges in the charge storage layer according to the on-off state of the selected memory transistor among the memory transistors M1 to M4, thereby obtaining the data represented by the amount of charges. Taking the memory transistor M2 as an example, the word line WL2 is biased at a read voltage VRD, and the rest of the word lines are biased at a high voltage VPS2. The on-off state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charges in the charge storage layer, so that the data value can be determined according to the on-off state of the memory transistor M2. The memory transistors M1, M3 and M4 are always in the on state, so the on-off state of the memory cell string 100 depends on the on-off state of the memory transistor M2. The control circuit determines the on-off state of the memory transistor M2 according to the electrical signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

[0040] Figure 2 A perspective view of the 3D memory device is shown. For the sake of clarity, in Figure 2 The various insulating layers in the 3D memory device are not shown in

[0041] The 3D memory device 200 shown in this embodiment includes 4*4, i.e., 16 memory cell strings 100, each of which includes 4 memory cells, thereby forming a memory array of 4*4*4, i.e., 64 memory cells. It can be understood that the present application is not limited thereto, and the 3D memory device can include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string can be any number, for example, 32 or 64.

[0042] In the 3D memory device 200, the memory cell strings respectively include respective channel pillars 110, and a common gate conductor 121, 122 and 123. The gate conductors 121, 122 and 123 are in a stack order with the transistors in the memory cell string 100, and are separated from each other by an interlayer insulating layer between adjacent gate conductors, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

[0043] The internal structure of the channel pillar 110 is shown in FIG. 4, and will not be described in detail here. The channel pillar 110 penetrates the gate stack structure 120, and is arranged in an array, with the first ends of the plurality of channel pillars 110 in the same column being commonly connected to the same bit line (i.e., one of the bit lines BL1 to BL4), and the second ends being commonly connected to the substrate 101, with the second ends forming a common source connection via the substrate 100. Figure 1 b

[0044] The gate conductor 122 of the first select transistor Q1 is divided into different gate lines by the gate line slit 102. The gate lines of the plurality of channel pillars 110 in the same row are commonly connected to the same string select line (i.e., one of the string select lines SSL1 to SSL4).

[0045] The gate conductors 121 of the memory transistors M1 and M4 are respectively connected to corresponding word lines. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 161, the gate lines in the same level are interconnected via respective conductive vias 131 to the interconnection layer 132, and then connected to the same word line (i.e., one of the word lines WL1 to WL4) via a conductive via 133.

[0046] The gate conductor 123 of the second select transistor Q2 is connected in one piece. If the gate conductor 123 of the second select transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines are interconnected via respective conductive vias 131 to the interconnection layer 132, and then connected to the same ground select line GSL via a conductive via 133.

[0047] Optionally, a CMOS circuit is included in the substrate semiconductor substrate 101 of the first array structure, for example. Conductive vias are used to provide electrical connection between the CMOS circuit and external circuits.

[0048] Figure 3 An A-A direction cross-sectional view of a 3D memory device is shown in FIG. 4. The semiconductor structure 400 includes a first array structure 410 and a second array structure 420. Figure 2

[0049] ​​The first array structure 410 comprises a substrate 401, a first stack structure above the substrate 401, and a first channel hole penetrating the first stack structure, wherein the first stack structure comprises a plurality of first interlayer insulating layers 411 and a plurality of first sacrificial layers 412 alternately stacked.

[0050] The second array structure 420 comprises a second stack structure above the first stack structure 410 and a second channel hole penetrating the second stack structure, wherein the second stack structure comprises a plurality of second interlayer insulating layers 421 and a plurality of second sacrificial layers 422 alternately stacked.

[0051] In the process of adopting a dual stack technology to design a 3D memory device, the first stack structure is formed on the substrate 401, the first stack structure is etched to form a first channel hole penetrating the first stack structure, a sacrificial material such as polysilicon is filled in the first channel hole to form a first array structure with a flat surface, a second stack structure is formed on the first stack structure with the flat surface, the second stack structure is etched to form a second channel hole penetrating the second stack structure, and the sacrificial material filled in the first channel hole is removed. After forming the channel hole (the channel hole comprises the first channel hole in the first stack structure and the second channel hole in the second stack structure), a functional layer 440 and a sacrificial layer (not shown) are sequentially deposited in the channel hole, then the bottom of the functional layer 440 and the sacrificial layer is opened by an etching process, and then the sacrificial layer is removed and a channel layer (not shown) is deposited to form a circuit loop of the channel layer and a well region in the substrate 401.

[0052] Ideally, as shown on the left side, Figure 3 As shown on the left side, the first channel hole 431 and the second channel hole 432 are aligned. However, due to the influence of process limitations and stress and other factors, the first channel hole 433 in the first stack structure and the second channel hole 434 in the second stack structure 420 cannot be completely aligned and there is a certain offset, as shown on the right side. Figure 3 As shown on the right side, when the bottom of the functional layer 440 and the sacrificial layer is opened by etching, the functional layer 440 at the junction area of the first channel hole 433 and the second channel hole 434 can be damaged, which affects the electrical performance of the conductive channel structure, thereby affecting the electrical performance of the final storage unit and reducing the yield and reliability of the product.

[0053] To solve the above problems, the present application provides a manufacturing method of a 3D memory device, as shown on the left side. Figure 4 As shown on the right side. Figure 4 The manufacturing method of the 3D memory device according to the embodiment of the present application is shown, Figures 5a to 5h The cross-sectional views of each stage of the manufacturing method of the 3D memory device according to the embodiment of the present application are shown, combined with Figure 4 and Figures 5a to 5hThe manufacturing method of the 3D memory device of the embodiment of the present application is further described.

[0054] The manufacturing method of the 3D memory device of the embodiment of the present application comprises:

[0055] In step S10, a first array structure 410 is formed, which comprises a substrate 401, a first stack structure above the substrate 401, a plurality of first channel holes (not shown) penetrating the first stack structure in a core region of the first array structure 410, and a plurality of positioning pegs 450 extending into the first stack structure in a mark region of the first array structure 410. The mark region is, for example, located at a scribe lane of the first stack structure.

[0056] In step S10, a first array structure 410 is formed, which comprises a substrate 401, a first stack structure above the substrate 401, a plurality of first channel holes (not shown) penetrating the first stack structure in a core region of the first array structure 410, and a plurality of positioning pegs 450 extending into the first stack structure in a mark region of the first array structure 410. The mark region is, for example, located at a scribe lane of the first stack structure.

[0057] In step S11, a first stack structure is formed on the substrate 401. The first stack structure comprises a plurality of first interlayer insulating layers 411 and a plurality of first sacrificial layers 412 stacked alternately.

[0058] In an available embodiment, the substrate 401 is made of any suitable semiconductor material, for example, selected from single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOD), or group III-V compound such as gallium arsenide. The first interlayer insulating layer 411 is, for example, selected from insulating dielectric materials such as silicon oxide, aluminum oxide, hafnium oxide, or tantalum oxide, and the first sacrificial layer 412 is, for example, selected from silicon nitride.

[0059] In step S12, a plurality of positioning holes 435 extending into the first stack structure from the surface of the first stack structure are formed, obtaining a semiconductor structure 410 as shown in FIG. 4B. Further, the positioning holes 435 penetrate the first stack structure. Figure 5a

[0060] In step S13, the positioning holes 435 formed in step S12 are filled with a sacrificial part, and chemical mechanical polishing is used to remove the part of the sacrificial part higher than the upper surface of the first stack structure, to form the positioning pegs 450 and a flat surface of the first stack structure.

[0061] In an available embodiment, the material of the sacrificial part is selected from any one of polysilicon or carbon material. In this embodiment, carbon material, for example, amorphous carbon, is used as the sacrificial part, which not only can obtain the same structural strength as polysilicon material, but also can effectively reduce the cost.

[0062] In step S14, a first interlayer insulating layer 413 is formed on the flat surface formed in step S13, obtaining a semiconductor structure as shown in FIG. 4C. It should be understood that the first stack structure comprises the first interlayer insulating layer 413. Figure 5b In step S14, a first interlayer insulating layer 413 is formed on the flat surface formed in step S13, obtaining a semiconductor structure as shown in FIG. 4C. It should be understood that the first stack structure comprises the first interlayer insulating layer 413.

[0063] Step S15, the first interlayer insulating layer 413 is polished to a preset thickness by chemical mechanical polishing to obtain a first array structure 410 as shown. Figure 5c

[0064] In the subsequent process of etching the polysilicon layer 460, the first interlayer insulating layer 413 formed by the oxide material can be used as a barrier layer to prevent the positioning plug 450 from being damaged in the etching process, so that the positioning plug 450 as the mark of OVL is clearer, thereby enabling the subsequent etching process to be better according to the preset position.

[0065] As shown in Figure 5c , the plurality of positioning plugs 450 are distributed in the first stack structure in two groups, a total of two groups, the distance between the two positioning plugs 450 in the same group is less than the distance between the two groups of positioning plugs. It should be understood that the present application is not limited thereto, and the number of groups into which the plurality of positioning plugs 450 are divided and the number of positioning plugs included in each group can be adjusted according to actual conditions.

[0066] Step S20, etching and removing at least one upper layer of the first stack structure in the mark area to form a groove 480, so that the plurality of positioning plugs 450 are located in the groove 480 (as shown in Figure 5g ), and the plurality of positioning plugs 450 protrude above the bottom surface of the groove 480.

[0067] Wherein, step S20 comprises:

[0068] Step S21, forming a polysilicon layer 460 above the first stack structure to obtain a semiconductor structure 400 as shown. Figure 5d

[0069] Step S22, forming a photoresist layer 470 above the polysilicon layer 460 and patterning the photoresist layer 470 to obtain a semiconductor structure 400 as shown. Figure 5e

[0070] Step S23, etching the polysilicon layer 460 to expose the first stack structure. The first gas is used to etch the polysilicon layer 460 to expose the first stack structure via the patterned photoresist layer 470 as a mask to obtain a semiconductor structure 400 as shown. Figure 5f Wherein, the first gas is selected from any one or several of hydrogen bromide (HBr) and chlorine (Cl2).

[0071] ​​​The embodiment of the present application utilizes the high selectivity of the first gas to the material of the polysilicon / first interlayer insulating layer 411 to selectively etch the polysilicon layer 460 without damaging the first stack structure, avoids over-etching of the polysilicon layer 460 during etching to cause the electrical performance to decrease, and thus improves the yield and reliability of the 3D memory device.

[0072] In step S24, the photoresist layer 470 is removed. For example, the photoresist layer 470 is removed by using the built-in process of the working machine, and the photoresist remaining on the surface of the semiconductor structure 400 is further removed by using a cleaning process to obtain the semiconductor structure 400 meeting the surface cleanliness requirement.

[0073] In a feasible embodiment, the photoresist layer 470 is removed by using ashing (Asher), and the photoresist residues are removed by using wet stripping (Wet Strip).

[0074] The present application removes the photoresist by using the built-in process of the machine, and the semiconductor structure 400 does not need to be put into other machines, which is beneficial to improve the WPH (Wafer Per Hour) and thus improve the production efficiency.

[0075] In step S25, at least one upper layer of the first stack structure is etched to form a groove 480. In the mark area, the second gas is used to etch at least one upper layer of the first stack structure to form the groove 480 by taking the etched polysilicon layer 460 as a mask, so that the plurality of positioning pegs 450 are located in the groove 480, and one end of the plurality of positioning pegs 450 is higher than the bottom surface of the groove 480. The second gas is selected from any one or several of hexafluorobutadiene (C4F6), octafluorocyclobutane (C4F8) or argon (Ar).

[0076] Further, in step S25, after the etching of the exposed first stack structure is completed, the polysilicon layer 460 is removed to obtain the semiconductor structure 400 as shown in FIG. 4D. Figure 5g

[0077] The embodiment of the present application utilizes the high selectivity of the second gas to the material constituting the first interlayer insulating layer 411 / polysilicon and the material constituting the first interlayer insulating layer 411 / the material constituting the positioning peg 450 during etching of the first stack structure, and selectively etches the first interlayer insulating layer 411 and the first sacrificial layer 412 without damaging the positioning peg 450, effectively improves the overlay (OVL), and thus improves the alignment accuracy of the first array structure 410 and the second array structure 420 and the alignment accuracy of the upper channel hole and the corresponding lower channel hole, avoids damaging the functional layer 440 at the junction area of the upper and lower channel holes during etching, and further improves the yield and reliability of the 3D memory device. ​

[0078] Step S30, a plurality of positioning pegs 450 in the mark area are taken as marks, a second array structure 420 is stacked on the first array structure 410, the topography of the plurality of positioning pegs 450 and the groove 480 is transferred to the upper surface of the second array structure 420, and a semiconductor structure 400 as shown in FIG. 4C is obtained. Figure 5h The second array structure 420, for example, comprises a second layer structure above the first layer structure, and a plurality of second channel holes penetrating through the second layer structure.

[0079] The step of forming the second array structure 420 taking the plurality of positioning pegs 450 as marks, for example, comprises:

[0080] The plurality of positioning pegs 450 are taken as marks, the second layer structure is stacked on the first layer structure, and the topography of the plurality of positioning pegs 450 and the groove 480 is transferred to the upper surface of the second layer structure.

[0081] The plurality of positioning pegs 450 or selected features of the second layer structure are taken as marks, the second channel holes penetrating through the second layer structure are formed, the alignment accuracy of the second channel holes and the corresponding first channel holes is effectively improved, and the channel holes formed after the communication are used to form a storage structure.

[0082] The process of forming a complete semiconductor product thereafter is the same as that in the prior art, and will not be described herein.

[0083] The manufacturing method of the 3D memory device provided by the present application utilizes a dry etching process, effectively avoids the influence of process parameter deviation caused by over-etching on the performance of the 3D memory device, and further, in the process of etching the polysilicon layer 460 and the first layer structure so that one end of the plurality of positioning pegs 450 protrudes from the bottom surface of the groove 480, different etching gases are used to selectively etch different target materials, for example, plasma gas etching processes are used, different target materials can be etched only by changing the etching gas, and the etching process can be completed in the same machine, further simplifying the process flow, accelerating the transmission of WIP (Work-in-Process), and thus reducing the production cost.

[0084] Further, the positioning pegs 450 provided by the embodiments of the present application not only have recognition due to the difference in material from the first layer structure, but also have structural differences due to the protrusion of one end of the positioning pegs 450 from the bottom surface of the groove 480, thereby further increasing the recognition, making the positioning pegs 450 clearly visible in the process of alignment and the process of measuring the alignment accuracy, so that the subsequent etching process can be better performed according to the preset position, and it is also beneficial to improve the process parameters according to the related values obtained by measurement, and further reduce the offset between the second channel hole and the corresponding first channel hole.

[0085] In summary, the manufacturing method of the 3D memory device provided by the present application utilizes a dry etching process, effectively avoiding the influence of process parameter deviation caused by over-etching on the performance of the 3D memory device. Further, in the process of etching the polysilicon layer and the first stacked structure to make one end of the plurality of positioning pegs protrude from the bottom surface of the groove, different etching gases are used to selectively etch different target materials. For example, a plasma etching process is used to etch different target materials without damaging other material structures. Only the etching gas needs to be changed, and the etching process can be completed in the same machine, further simplifying the process flow, accelerating the transmission of WIP (Work-in-Process), and thus reducing production costs.

[0086] Further, the positioning peg provided by the embodiment of the present application not only has a high degree of recognition due to the difference in material from the first stacked structure, but also has a structural difference due to the protrusion of one end of the positioning peg from the bottom surface of the groove, thereby further increasing the degree of recognition, making the positioning peg clearly visible in the overlay process and the measurement process of overlay accuracy, so that the subsequent etching process can better follow the preset position, and it is also beneficial to improve the process parameters according to the related values obtained by measurement, further reducing the offset between the second trench hole and the first trench hole corresponding thereto.

[0087] Optionally, the sacrificial portion material forming the plurality of positioning pegs is selected from any one of polysilicon or carbon material. Further, using carbon material as the sacrificial portion not only can obtain the same structural strength as the polysilicon material, but also can effectively reduce the cost.

[0088] Optionally, the upper layer of the first stacked structure is a first interlayer insulating layer, which can be used as a barrier layer to prevent the positioning peg from being damaged in the process of etching the polysilicon layer, making the positioning peg as the mark of OVL more clear, so that the subsequent etching process can better follow the preset position.

[0089] It should be understood by those of ordinary skill in the art that the words "during," "when," and "while" as used herein in connection with circuit operation are not precise terms and are intended to allow for some small but reasonable amount of time to elapse between the initiation of a first action and the initiation of a reaction that is initiated by the first action. The use of the words "approximately" or "substantially" in connection with an element means that the element has a value or position that is intended to be close to the stated value or position. However, as is known in the art, there can always be small deviations that make it difficult to be precise in the value or position. It has been determined by those of ordinary skill in the art that a deviation of at least ten percent (10%) (and at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable deviation from the stated ideal. When used in connection with signal states, the actual voltage value or logic state (e.g., "1" or "0") of a signal depends on whether positive logic or negative logic is used.

[0090] In accordance with the present application, the embodiments as described above are not the only way to implement the application. Numerous modifications and alterations to the described embodiments are possible without departing from the scope of the present application. The disclosure of the present application is not intended to be limited to the described embodiments which are presented as specific examples. It is therefore contemplated that the application shall also cover any and all modifications, variations, combinations or equivalents that fall within the scope of the present application. The specification and drawings should be considered in an illustrative rather than a restrictive sense.

Claims

1. A method for manufacturing a 3D memory device, comprising: forming a first array structure, the first array structure comprising a substrate, a first stack structure located above the substrate, a plurality of first channel holes penetrating through the first stack structure in a core region of the first array structure, and a plurality of positioning pegs formed in a mark region of the first array structure and extending from a surface of the first stack structure into the first stack structure; etching the first stack structure in the mark region to expose the plurality of positioning pegs; stacking a second array structure on the first array structure with the plurality of positioning pegs in the mark region as a mark, the second array structure comprising a second stack structure located above the first stack structure; and forming a plurality of second channel holes penetrating through the second stack structure with the plurality of positioning pegs as a mark. 2.The method of manufacturing a 3D memory device of claim 1, wherein the etching the first stack structure to expose the plurality of positioning pegs comprises: etching and removing at least one upper layer of the first stack structure in the mark region to form a recess, such that the plurality of positioning pegs are located in the recess and protrude above a bottom surface of the recess. 3.The method of claim 2, wherein, when the second array structure is stacked on the first array structure, topographies of the recess and the plurality of positioning pegs are transferred to an upper surface of the second array structure. 4.The method of claim 2, wherein the etching and removing at least one upper layer of the first stack structure in the mark region to form a recess comprises: forming a polysilicon layer on the first stack structure; forming a photoresist layer on the polysilicon layer and patterning the photoresist layer; etching the polysilicon layer to expose the first stack structure; etching and removing at least one upper layer of the first stack structure to form a recess. 5.The method of claim 4, further comprising, between the etching the polysilicon layer and the etching the first stack structure: removing the photoresist and etching residues. 6.The method of claim 4, wherein the etching the polysilicon layer comprises: using a first gas to etch the polysilicon layer to expose the first stack structure via the patterned photoresist layer as a mask; and wherein the first gas comprises any one or more of hydrogen bromide, chlorine. 7.The method of claim 4, wherein the etching and removing at least one upper layer of the first stack structure to form a recess comprises: using a second gas to etch and remove at least one upper layer of the first stack structure to form a recess with the etched polysilicon layer as a mask; and wherein the second gas comprises any one or more of hexafluorobutadiene, octafluorocyclobutane, or argon. 8.The method of claim 1, wherein the forming a first array structure comprises: forming a first stack structure on the substrate, the first stack structure comprising a plurality of first interlayer insulating layers and a plurality of first sacrificial layers alternately stacked; forming a positioning hole extending from a surface of the first stack structure into the first stack structure; filling a sacrificial portion in the positioning hole and forming a flat surface of the first stack structure; forming a first interlayer insulating layer on the flat surface; polishing the first interlayer insulating layer to a preset thickness by chemical mechanical polishing; wherein the sacrificial portion comprises any one of polysilicon or carbon material.

9. The method of claim 8, wherein the forming a positioning hole extending from a surface of the first stack structure into the first stack structure comprises: forming a positioning hole extending through the first stack structure.

10. The method of claim 1, wherein the mark region is a scribe region of the 3D memory device.

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