Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel includes an active layer, a gate layer, and a metal layer. By forcibly pulling down the potential of the scan signal in the first scan line when the pulse rising edge of the scan signal in the second scan line arrives, the potential drop time of each scan signal in the display area can be shortened. At the same time, by constructing the control trace and the potential transmission line to at least partially overlap in the thickness direction of the display panel, the aperture ratio can be increased as much as possible.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the development of display technologies, the refresh rate has increasingly become one of the important indicators for measuring display effects. A high-refresh-rate screen can bring a smoother visual experience, reduce eye fatigue, and with the adaptation of various application software to high-refresh-rate screens, consumers can also obtain a better visual experience and entertainment experience from high-refresh-rate screens. The refresh rate of traditional display devices is generally 60Hz. In recent years, with the development of technologies, display devices with refresh rates of 90Hz, 120Hz, 150Hz, and even higher have emerged successively. From the perspective of panel design, achieving a higher refresh rate is affected by factors such as device performance, driving ability, and charging rate. For example, during progressive scanning, the falling edge or rising edge of the previous row scanning signal will be delayed in turning off or on due to its row load. When the progressive scanning speed is faster, display crosstalk caused by abnormal charging will occur.

[0003] Therefore, it is necessary to propose a display panel that can make the time taken for the falling edge or rising edge of the scanning signal shorter in its display area while obtaining as high an aperture ratio as possible.

[0004] It should be noted that the above introduction of the background art is only for the convenience of clearly and completely understanding the technical solution of the present application. Therefore, it cannot be considered that the above-mentioned technical solutions are well-known to those skilled in the art just because they appear in the background art of the present application. Summary of the Invention

[0005] The present application provides a display panel and a display device to alleviate the technical problems of the long time taken for the potential jump process of the scanning signal and the low aperture ratio in the display area.

[0006] In a first aspect, the present application provides a display panel, which includes an active layer, a gate layer, and a metal layer. The active layer includes a source connection region of an auxiliary transistor and a drain connection region of the auxiliary transistor. The gate layer includes one of a control trace / potential transmission line, a gate of the auxiliary transistor, a first scan line, and a second scan line. The first scan line and the second scan line are arranged in sequence along a first direction. One end of the control trace is electrically connected to the first scan line, and the second scan line is electrically connected to the gate of the auxiliary transistor. The metal layer includes the other of the control trace / potential transmission line, a source of the auxiliary transistor, and a drain of the auxiliary transistor. The source of the auxiliary transistor is electrically connected to the source connection region of the auxiliary transistor and the other end of the control trace, and the drain of the auxiliary transistor is electrically connected to the potential transmission line and the drain connection region of the auxiliary transistor. Wherein, in the thickness direction of the display panel, the potential transmission line and the control trace at least partially overlap.

[0007] In some embodiments, the metal layer further includes a first data line and a second data line, and the first data line and the second data line are arranged in sequence along a second direction. In the second direction, the potential transmission line and the control line are located between the first data line and the second data line and are close to the second data line.

[0008] In some embodiments, the active layer further includes a channel region of the auxiliary transistor. The channel region of the auxiliary transistor is located between the source connection region of the auxiliary transistor and the drain connection region of the auxiliary transistor, and the source connection region of the auxiliary transistor, the channel region of the auxiliary transistor, and the drain connection region of the auxiliary transistor are arranged in sequence along the first direction.

[0009] In some embodiments, the potential transmission line includes a first main portion, and the control trace includes a second main portion. The projection of the second main portion on the metal layer overlaps with the first main portion. And the extending direction of the second data line is the same as the extending direction of the first main portion or the extending direction of the second main portion.

[0010] In some embodiments, in the second direction, the distance between the first main portion and the second data line is 1.2 micrometers to 2.8 micrometers.

[0011] In some embodiments, the potential transmission line further includes a first winding portion, and the control trace further includes a second winding portion. The projection of the second winding portion on the metal layer overlaps with the first winding portion. And the distance from the projection of the drain connection region of the auxiliary transistor on the metal layer to the first winding portion is less than the distance from the projection of the drain connection region of the auxiliary transistor on the metal layer to the first main portion.

[0012] In some of these embodiments, the second scanning line includes a third main trunk portion and a third winding portion. The third winding portion includes a first straight portion, a second straight portion, and a third straight portion that are connected end to end in sequence. The extending direction of the second straight portion is parallel to the extending direction of the third main trunk portion. The third main trunk portion, the first straight portion, or the third straight portion and the second straight portion are arranged in sequence along a first direction and their projections in the first direction do not overlap with each other. The distance between the projection of the second straight portion on the active layer and the source connection region of the auxiliary transistor in the first direction is less than a first distance. The first distance is the sum of the width of the third main trunk portion in the first direction and a second distance, and the second distance is the distance between the second straight portion and the third main trunk portion in the first direction.

[0013] In some of these embodiments, the active layer further includes a semiconductor structure of a writing transistor. In the thickness direction of the display panel, the projection of the first data line on the active layer overlaps and is electrically connected to a part of the semiconductor structure. Another part of the semiconductor structure is located between the first data line and the second data line in the projection on the metal layer. Among them, the writing transistor is used to control the writing of data signals into corresponding pixels.

[0014] In some of these embodiments, the display panel further includes a gate driving circuit, and the gate driving circuit is disposed on at least one side of the display panel. The greater the distance from the gate driving circuit, the same or gradually increasing the distribution density of the auxiliary transistors. The distribution density is the number of auxiliary transistors per unit area.

[0015] In a second aspect, the present application provides a display device, which includes the display panel in at least one of the above embodiments. Among them, the first scanning line is used to transmit a first scanning signal, and the second scanning line is used to transmit a second scanning signal. In the same frame, the pulse of the first scanning signal is earlier or later than the pulse of the second scanning signal.

[0016] The display panel and the display device provided by the present application electrically connect one end of a control trace to a first scan line, electrically connect a second scan line to the gate of an auxiliary transistor, electrically connect the source of the auxiliary transistor to the source connection region of the auxiliary transistor and the other end of the control trace, and electrically connect the drain of the auxiliary transistor to a potential transmission line and the drain connection region of the auxiliary transistor, so that when the pulse rising edge of the scan signal in the second scan line arrives, the potential of the scan signal in the first scan line can be forcibly pulled down, which can shorten the potential drop time of each scan signal in the display area, or when the pulse falling edge of the scan signal in the second scan line arrives, the potential of the scan signal in the first scan line can be forcibly pulled up, which can shorten the potential rise time of each scan signal in the display area; at the same time, one of the control trace / potential transmission line is constructed in the gate layer, and the other of the control trace / potential transmission line is constructed in the metal layer, and the control trace and the potential transmission line are at least partially overlapped in the thickness direction of the display panel, so that the layout of the new structures such as the control trace, the potential transmission line and the auxiliary transistor can be completed with less space, and the aperture ratio can be increased as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The technical solutions and other beneficial effects of the present application will become obvious by describing the specific embodiments of the present application in detail with reference to the accompanying drawings.

[0018] Figure 1 It is a schematic diagram of the electrical principle of the display panel provided by the embodiment of the present application.

[0019] Figure 2 It is a schematic diagram of the distribution of the auxiliary units provided by the embodiment of the present application.

[0020] Figure 3 It is a schematic cross-sectional structure diagram of the auxiliary transistor, the control trace and the potential transmission line provided by the embodiment of the present application.

[0021] Figure 4 It is a schematic layout design diagram of the display panel provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0023] In view of the deficiency that the time taken for the falling edge or the rising edge of the scan signal in the display area is relatively long in the traditional technical solution, this embodiment provides a display panel. Please refer to Figures 1 to 4 asFigure 1 As shown, the display panel can be divided into a display area AA and a non-display area NA. In the non-display area NA, multiple cascaded gate driving units such as the Nth-stage gate driving unit 11, the (N + 1)th-stage gate driving unit 12, and the (N + 2)th-stage gate driving unit 13 are constructed to form the gate driving circuit required for the display panel. The gate driving circuit can be constructed in at least one non-display area NA on both sides of the display area AA. For example, the Nth-stage gate driving unit 11, the (N + 2)th-stage gate driving unit 13, etc. can be constructed in the non-display area NA on the left side, and the (N + 1)th-stage gate driving unit 12 can be constructed in the non-display area NA on the right side. A plurality of scan lines electrically connected to the output ends of the respective gate driving units extend into the display area AA, and these scan lines are arranged in sequence along the first direction DR1. For example, the Nth scan line GL1 for transmitting the Nth-stage scan signal G(N), the (N + 1)th scan line GL2 for transmitting the (N + 1)th-stage scan signal G(N + 1), and the (N + 2)th scan line GL3 for transmitting the (N + 2)th-stage scan signal G(N + 2). Among them, the falling edge of the Nth-stage scan signal G(N) can be at the same moment as or not much different from the rising edge of the (N + 1)th-stage scan signal G(N + 1).

[0024] Among them, the flow direction of the Nth-stage scan signal G(N) in the Nth scan line GL1 is from left to right, the flow direction of the (N + 1)th-stage scan signal G(N + 1) in the (N + 1)th scan line GL2 is from right to left, and the flow direction of the (N + 2)th-stage scan signal G(N + 2) in the (N + 2)th scan line GL3 is from left to right, and so on. The flow direction of each scan signal is always from the input end to the output end of the corresponding scan line.

[0025] At least one auxiliary unit 21 is provided in the display area AA. Each auxiliary unit 21 can include one or more auxiliary transistors T1. One of the source or drain of the auxiliary transistor T1 can be electrically connected to the potential transmission line VGLL for transmitting the low-potential signal VGL, and the other of the source or drain of the auxiliary transistor T1 can be electrically connected to one end of the control trace CTRL. The other end of the control trace CTRL can be electrically connected to the Nth scan line GL1, and the gate of the auxiliary transistor T1 can be electrically connected to the (N + 1)th scan line GL2. N can be a positive integer. As N changes, the auxiliary transistors T1 can be distributed at different positions in the display area AA to shorten the potential drop time or potential rise time of each scan signal in the display area AA.

[0026] It can be understood that after adding the auxiliary unit 21, the time required for the scanning signal to drop from the high potential to the low potential or the time required for the scanning signal to rise from the low potential to the high potential can be effectively reduced or shortened. In response to the rising edge of one of the (N + 1)-th level scanning signal G(N + 1), the (N + 2)-th level scanning signal G(N + 2), the (N + 3)-th level scanning signal, or the (N + 4)-th level scanning signal, the potential of the N-th level scanning signal G(N) can be quickly and forcibly pulled down to a predetermined low potential through the auxiliary unit 21. Or, in response to the falling edge of one of the (N + 1)-th level scanning signal G(N + 1), the (N + 2)-th level scanning signal G(N + 2), the (N + 3)-th level scanning signal, or the (N + 4)-th level scanning signal, the potential of the N-th level scanning signal G(N) can be quickly and forcibly pulled up to a predetermined high potential through the auxiliary unit 21, which can significantly improve the crosstalk phenomenon of data signals.

[0027] For example, when the scanning signal transmitted in the display panel has a positive pulse, the auxiliary transistor T1 can be an N-channel thin-film transistor, and the potential transmission line can be used to transmit a low-potential signal. If the first scanning line is the N-th scanning line GL1, the second scanning line can be one of the (N + 1)-th scanning line GL2, the (N + 2)-th scanning line GL3, or the (N + 3)-th scanning line. At this time, in response to the rising edge of one of the (N + 1)-th level scanning signal G(N + 1), the (N + 2)-th level scanning signal G(N + 2), the (N + 3)-th level scanning signal, or the (N + 4)-th level scanning signal, the potential of the N-th level scanning signal G(N) can be quickly and forcibly pulled down to a predetermined low potential through the auxiliary unit 21. When the scanning signal transmitted in the display panel has a negative pulse, the auxiliary transistor T1 can be a P-channel thin-film transistor, and the potential transmission line can be used to transmit a high-potential signal. If the first scanning line is the N-th scanning line GL1, the second scanning line can be one of the (N + 1)-th scanning line GL2, the (N + 2)-th scanning line GL3, or the (N + 3)-th scanning line. At this time, in response to the falling edge of one of the (N + 1)-th level scanning signal G(N + 1), the (N + 2)-th level scanning signal G(N + 2), the (N + 3)-th level scanning signal, or the (N + 4)-th level scanning signal, the potential of the N-th level scanning signal G(N) can be quickly and forcibly pulled up to a predetermined high potential through the auxiliary unit 21. In this way, the time taken for the falling edge or rising edge of each scanning signal can be shortened, and the crosstalk phenomenon of data signals can be significantly improved.

[0028] Such as Figure 2As shown, the display panel can be configured with multiple rows of pixels 22. Each scan line can be electrically connected to a corresponding row of pixels. Each row of pixels can be divided into multiple partitions 20, and the number of pixels 20 in each partition 20 can be equal. For example, the number of pixels in a row can be 2560, and the number of pixels 20 in each partition 20 can be 256. Each row of pixels can be divided into 10 partitions 20. That is to say, the number of partitions 20 can increase as the number of pixels in each row increases.

[0029] The number of auxiliary units 21 in each partition 20 of the same row of pixels can be zero, one, or more.

[0030] Specifically, the number of auxiliary units 21 in each partition 20 located in the same row can be, but is not limited to, the same. Specifically, as Figure 2 shown in the first row, the number of auxiliary units 21 in each partition 20 is equal. For example, it can be 3 auxiliary units 21, or 4 auxiliary units 21, etc. The display panel can include a gate driving circuit. Each gate driving circuit can include multiple cascaded gate driving units. If the output end of the gate driving unit, which is the input end of each scan line, is used as the corresponding scan signal source, the distribution density of the auxiliary transistors in each partition 20 can also gradually increase in sequence as the distance from the corresponding scan signal source increases. That is, in the same row of pixels, the distribution density of the auxiliary transistors forms a stepped arrangement, which can be from small to large, or from large to small, so that the waveforms or required times for the scan signals at different positions to drop to the low potential are the same or similar. For example, if there are 2560 pixels 22 horizontally, and they are divided into 10 partitions 20 horizontally, and the gate signal of the first row is fed from the left, then for odd rows, as the distance from the corresponding scan signal source increases, the density of the auxiliary units 21 also increases, and the number of its auxiliary units 21 can be 1, 2,..., 10 per partition; correspondingly, the number of auxiliary units 21 in even rows can be 10, 9, 8,..., 1 per partition.

[0031] Among them, the display panel can be divided into a display area and a first border area and a second border area located on both sides of the display area. The gate driving circuit can be arranged in the first border area and / or the second border area.

[0032] Specifically, as Figure 2 shown in the second row or the third row, for example, the gate driving circuit can be arranged in the first border area or the second border area. As Figure 2 shown in the second row, when the gate driving circuit is arranged in the first border area, that is, the left border area, the flow direction of the scan signal is Figure 2As shown by the arrow in the second row, from left to right. At this time, as the distance from the partition 20 to the gate driving circuit increases, the number of auxiliary units 21 in each partition 20, that is, the density of the auxiliary units 21, also increases. For example, one auxiliary unit 21 can be set in the first partition 20 from left to right, two auxiliary units 21 can be set in the second partition 20, three auxiliary units 21 can be set in the third partition 20, and so on. As Figure 2 shown in the third row, when the gate driving circuit is arranged in the second border area, that is, the right border area, the flow direction of the scanning signal is Figure 2 as shown by the arrow in the third row, from right to left. At this time, as the distance from the partition 20 to the gate driving circuit increases, the number of auxiliary units 21 in each partition 20, that is, the density of the auxiliary units 21, also increases. For example, one auxiliary unit 21 can be set in the first partition 20 from right to left, two auxiliary units 21 can be set in the second partition 20, three auxiliary units 21 can be set in the third partition 20, and so on.

[0033] For another example, a gate driving circuit can be arranged in the first border area and the second border area at the same time. Among them, the gate driving units of the odd levels in the gate driving circuit can be arranged in the first border area, and the auxiliary units 21 can adopt the Figure 2 distribution scheme in the second row as described above; the gate driving units of the even levels in the gate driving circuit can be arranged in the second border area, and the auxiliary units 21 can adopt the Figure 2 distribution scheme in the third row as described above.

[0034] For another example, the display panel can include two gate driving circuits. One gate driving circuit is arranged in the first border area, and the other gate driving circuit is arranged in the second border area, and the same scanning line is electrically connected to the corresponding output ends of the two gate driving circuits. In this way, the flow direction of the scanning signal in each scanning line is as Figure 2 shown by the arrow in the fourth row, flowing from both ends to the middle. In this way, the closer to the central area of the display panel, the greater the density of the auxiliary units 21 or the distribution density of the auxiliary transistors. For example, one auxiliary unit 21 can be set in the first partition 20 from left to right, two auxiliary units 21 can be set in the second partition 20, and so on to the middle partition 20 of the current row; one auxiliary unit 21 can be set in the first partition 20 from right to left, two auxiliary units 21 can be set in the second partition 20, and so on to the middle partition 20 of the current row.

[0035] As Figure 3 shown, the display panel can include a substrate BP1, an active layer POLY1, a gate insulating layer GI1, a gate layer GE1, an insulating layer JY1, and a metal layer SD1 stacked in sequence in its thickness direction DR3.

[0036] Among them, the active layer POLY1 may include a source connection region T1S of the auxiliary transistor, a channel region T1Z of the auxiliary transistor, and a drain connection region T1D of the auxiliary transistor.

[0037] The gate layer GE1 may include a gate T1G of the auxiliary transistor and a control trace CTRL.

[0038] The metal layer SD1 may include a potential transmission line VGLL, a source T1SS of the auxiliary transistor, a drain T1DD of the auxiliary transistor, and a data line. The control trace CTRL may be electrically connected to the source T1SS of the auxiliary transistor, and the potential transmission line VGLL may be electrically connected to the drain T1DD of the auxiliary transistor. Among them, in the thickness direction DR3, the projection of the potential transmission line VGLL on the metal layer SD1 may partially overlap or completely overlap with the control trace CTRL.

[0039] As Figure 4 shown, in this display panel, the first scan line and the second scan line are arranged in sequence along the first direction DR1. One end of the control trace CTRL is electrically connected to the first scan line, and the second scan line is electrically connected to the gate T1G of the auxiliary transistor T1; the metal layer SD1 includes a source of the auxiliary transistor T1, a drain of the auxiliary transistor T1, and a potential transmission line VGLL. The source of the auxiliary transistor T1 is electrically connected to the source connection region T1S of the auxiliary transistor T1 and the other end of the control trace CTRL, and the drain of the auxiliary transistor T1 is electrically connected to the potential transmission line VGLL and the drain connection region T1D of the auxiliary transistor T1; among them, in the thickness direction DR3 of the display panel, the projection of the potential transmission line VGLL on the gate layer GE1 at least partially overlaps with the control trace CTRL.

[0040] It can be understood that in this embodiment, the control trace CTRL is respectively constructed in the gate layer GE1, and the potential transmission line VGLL is constructed in the metal layer SD1, and at least partial overlap of the control trace CTRL and the potential transmission line VGLL is constructed in the thickness direction DR3 of the display panel, so that the layout of the new structures such as the control trace CTRL, the potential transmission line VGLL, and the auxiliary transistor T1 can be completed with less space, and the aperture ratio of the display panel can be increased as much as possible.

[0041] The first scan line may be the previous scan line, such as the Nth scan line GL1, and the second scan line may be the next scan line, such as the (N + 1)th scan line GL2.

[0042] In one embodiment, the first data line DL1 and the second data line DL2 are arranged in sequence along the second direction DR2; in the second direction DR2, the potential transmission line VGLL is located between the first data line DL1 and the second data line DL2 and is close to the second data line DL2. It can be understood that in this embodiment, constructing the potential transmission line VGLL and the control trace CTRL between the first data line DL1 and the second data line DL2 and close to the second data line DL2 can achieve a more compact layout design.

[0043] In one embodiment, the channel region T1Z of the auxiliary transistor T1 is located between the source connection region T1S and the drain connection region T1D of the auxiliary transistor T1, and the source connection region T1S, the channel region T1Z, and the drain connection region T1D of the auxiliary transistor T1 are arranged in sequence along the first direction DR1. The auxiliary transistor T1 can be vertically constructed, which can save the horizontal space of the display panel so as to be constructed between two data lines simultaneously with the writing transistor.

[0044] In one embodiment, the potential transmission line VGLL includes a first main part VG1, and the control trace CTRL includes a second main part CR1. The projection of the second main part CR1 on the metal layer SD1 overlaps with the first main part VG1; and the extending direction of the second data line DL2 is the same as the extending direction of the first main part VG1 or the extending direction of the second main part CR1. It can be understood that in this way, the potential transmission line VGLL and / or the control trace CTRL can extend synchronously or in parallel with the second data line DL2 to reduce the coverage area of the black matrix and improve the aperture ratio.

[0045] In one embodiment, in the second direction DR2, the distance d1 between the first main part VG1 and the second data line DL2 is 1.2 micrometers to 2.8 micrometers. It can be understood that in this way, the coverage area of the black matrix can be further reduced and a higher aperture ratio can be obtained. Preferably, the distance d1 between the first main part VG1 and the second data line DL2 can also be 2.2 micrometers. In this way, not only a better aperture ratio can be obtained, but also the adverse effects caused by the electrical coupling due to the distance between the potential transmission line VGLL, the control trace CTRL, and the second data line DL2 can be avoided or reduced.

[0046] Wherein, the distance between the second main part CR1 and the second data line DL2 can be the same as the distance between the first main part VG1 and the second data line DL2.

[0047] In one embodiment, the potential transmission line VGLL further includes a first winding portion VG1, and the control trace CTRL further includes a second winding portion CR2. The projection of the second winding portion CR2 on the metal layer SD1 overlaps with the first winding portion VG1; and the distance from the projection of the drain connection region T1D of the auxiliary transistor T1 on the metal layer SD1 to the first winding portion VG2 is less than the distance from the projection of the drain connection region T1D of the auxiliary transistor T1 on the metal layer SD1 to the first main trunk VG1. It can be understood that in this way, the protruding direction of the first winding portion VG2 can be constructed to face the drain connection region T1D of the auxiliary transistor T1, which can not only shorten the trace distance between the drain connection region T1D of the auxiliary transistor T1 and the first winding portion VG2, but also facilitate the setting of corresponding vias on the second data line DL2, and the area of the via can be larger than the width of the second data line DL2 in the first direction DR1.

[0048] In one embodiment, the second scan line, i.e., the (N + 1)-th scan line GL2, includes a third main trunk GL21 and a third winding portion GL22. The third winding portion GL22 may include a first straight portion 221, a second straight portion 222, and a third straight portion 223 that are connected end to end in sequence. The extending direction of the second straight portion 222 is parallel to the extending direction of the third main trunk GL21. The third main trunk GL21, the first straight portion 221, or the third straight portion 223 and the second straight portion 222 are arranged in sequence along the first direction DR1 and their projections in the first direction DR1 do not overlap; the distance between the projection of the second straight portion 222 on the active layer POLY1 and the source connection region T1S of the auxiliary transistor T1 in the first direction DR1 is less than a first distance, where the first distance is the sum of the width of the third main trunk GL21 in the first direction DR1 and a second distance, and the second distance is the distance between the second straight portion 222 and the third main trunk GL21 in the first direction DR1.

[0049] It can be understood that in this embodiment, the winding setting of the second scan line can create space for the source connection region T1S of the auxiliary transistor T1, and provide a more compact layout space for the auxiliary transistor T1 in the active layer POLY1 to increase the aperture ratio.

[0050] In one embodiment, the active layer POLY1 further includes a semiconductor structure 30 of a writing transistor. In the thickness direction DR3 of the display panel, the projection of the first data line DL1 on the active layer POLY1 overlaps with a part of the semiconductor structure 30 and is electrically connected; another part of the semiconductor structure 30 is projected on the metal layer SD1 between the first data line DL1 and the second data line DL2; wherein, the writing transistor is used to control the writing of data signals into corresponding pixels.

[0051] It can be understood that in this embodiment, without changing the original layout of the writing transistor, an auxiliary transistor T1 can be constructed between the first data line DL1 and the second data line DL2, enabling a more compact layout design.

[0052] In one of the embodiments, this embodiment provides a display device, which includes the display panel in at least one of the above embodiments; wherein, the first scan line is used to transmit a first scan signal, and the second scan line is used to transmit a second scan signal; in the same frame, the pulse of the first scan signal is earlier than the pulse of the second scan signal.

[0053] It can be understood that for the display device provided in this embodiment, the end of the control trace can also be electrically connected to the first scan line, the second scan line can be electrically connected to the gate of the auxiliary transistor, the source of the auxiliary transistor can be electrically connected to the source connection region of the auxiliary transistor and the other end of the control trace, and the drain of the auxiliary transistor can be electrically connected to the potential transmission line and the drain connection region of the auxiliary transistor, so as to forcibly pull down the potential of the scan signal in the first scan line when the pulse rising edge of the scan signal in the second scan line arrives, which can shorten the potential drop time of each scan signal in the display area; at the same time, the control trace is respectively constructed in the gate layer, the potential transmission line is constructed in the metal layer, and at least part of the control trace and the potential transmission line are overlapped in the thickness direction of the display panel, so that the layout of the new structures such as the control trace, the potential transmission line and the auxiliary transistor can be completed with less space, and the aperture ratio can be increased as much as possible.

[0054] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0055] The display panel and the display device provided in the embodiments of the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, it includes: An active layer, the active layer includes a source connection region of an auxiliary transistor and a drain connection region of the auxiliary transistor; A gate layer, the gate layer includes one of a control trace / potential transmission line, a gate of the auxiliary transistor, a first scan line, and a second scan line. The first scan line and the second scan line are arranged in sequence along a first direction. One end of the control trace is electrically connected to the first scan line, and the second scan line is electrically connected to the gate of the auxiliary transistor; and A metal layer, the metal layer includes the other of the control trace / potential transmission line, a source of the auxiliary transistor, and a drain of the auxiliary transistor. The source of the auxiliary transistor is electrically connected to the source connection region of the auxiliary transistor and the other end of the control trace. The drain of the auxiliary transistor is electrically connected to the potential transmission line and the drain connection region of the auxiliary transistor; wherein, in the thickness direction of the display panel, the potential transmission line and the control trace at least partially overlap; wherein, the second scan line includes a third main portion and a third winding portion. The third winding portion includes a first straight portion, a second straight portion, and a third straight portion that are connected end to end in sequence. The extending direction of the second straight portion is parallel to the extending direction of the third main portion. The third main portion, the first straight portion, or the third straight portion, the second straight portion are arranged in sequence along the first direction and their projections in the first direction do not overlap; The distance between the projection of the second straight portion on the active layer and the source connection region of the auxiliary transistor in the first direction is less than a first distance. The first distance is the sum of the width of the third main portion in the first direction and a second distance. The second distance is the distance between the second straight portion and the third main portion in the first direction.

2. The display panel according to claim 1, characterized in that, The metal layer further includes a first data line and a second data line. The first data line and the second data line are arranged in sequence along a second direction; in the second direction, the potential transmission line is located between the first data line and the second data line and is close to the second data line.

3. The display panel according to claim 2, characterized in that, The active layer further includes a channel region of the auxiliary transistor. The channel region of the auxiliary transistor is located between the source connection region of the auxiliary transistor and the drain connection region of the auxiliary transistor, and the source connection region of the auxiliary transistor, the channel region of the auxiliary transistor, and the drain connection region of the auxiliary transistor are arranged in sequence along the first direction.

4. The display panel according to claim 3, characterized in that, The potential transmission line includes a first main portion, the control trace includes a second main portion, and the projection of the second main portion on the metal layer overlaps with the first main portion; and the extending direction of the second data line is the same as the extending direction of the first main portion or the second main portion.

5. The display panel according to claim 4, wherein, in the second direction, the distance between the first main trunk and the second data line is 1.2 micrometers to 2.8 micrometers.

6. The display panel according to claim 4, wherein, the potential transmission line further includes a first winding portion, the control trace further includes a second winding portion, a projection of the second winding portion on the metal layer overlaps with the first winding portion; and a distance from a projection of the drain connection region of the auxiliary transistor on the metal layer to the first winding portion is less than a distance from the projection of the drain connection region of the auxiliary transistor on the metal layer to the first main trunk.

7. The display panel according to claim 2, wherein, the active layer further includes a semiconductor structure of a writing transistor. In the thickness direction of the display panel, a projection of the first data line on the active layer overlaps and is electrically connected to a part of the semiconductor structure; another part of the semiconductor structure is located between the first data line and the second data line in a projection on the metal layer; wherein, the writing transistor is configured to control writing of data signals into corresponding pixels.

8. The display panel according to any one of claims 1 to 7, wherein, the display panel further includes a gate driving circuit, the gate driving circuit is disposed on at least one side of the display panel; the greater the distance from the gate driving circuit, the distribution density of the auxiliary transistors is the same or gradually increases; wherein, the distribution density is the number of the auxiliary transistors per unit area.

9. A display device, wherein, it includes the display panel according to any one of claims 1 to 8; wherein, the first scan line is configured to transmit a first scan signal, the second scan line is configured to transmit a second scan signal; in the same frame, a pulse of the first scan signal is earlier than a pulse of the second scan signal.

Images