Display device

Abstract

A display device is provided. The display device includes: a circuit layer having a driving circuit layer, the driving circuit layer having a plurality of clock signal lines; a touch detection unit having a touch detection portion and a plurality of touch signal lines electrically connected to the touch detection unit; and a conductive portion disposed between the plurality of clock signal lines and the plurality of touch signal lines and configured to cover an overlapping region where the plurality of clock signal lines and the plurality of touch signal lines overlap.

Description

[0001] This application is a divisional application of the patent application with the application number 201710617342.1 and the invention title "display device", which was filed with the State Intellectual Property Office of China on July 26, 2017. Technical Field

[0002] The present invention generally relates to a display device, and more particularly, to a display device capable of providing substantially uniform touch sensitivity. Background Art

[0003] Various display devices are being developed for multimedia devices such as televisions, mobile phones, tablet computers, navigators, and game consoles. Input devices such as a keyboard or a mouse are included as the input device of the display device. In addition, recently, a display device includes a touch detection unit as an input device.

[0004] For example, in order to detect a very slight touch or the difference between the valleys and ridges of a fingerprint for identification applications, the touch detection unit can be extremely sensitive. When very close to the signal emitted from the display device, the sensitive touch detection unit will be affected and produce incorrect or inaccurate results.

[0005] The above information disclosed in this background art section is only for enhancing the understanding of the background of the inventive concept of the present invention. Therefore, the background art section may contain information that does not form the prior art known to those of ordinary skill in the art in this country. Summary of the Invention

[0006] One or more exemplary embodiments of the present invention provide a display device including a touch detection unit having uniform or more uniform touch sensitivity that is not affected or less affected by noise in the touch sensor lines (e.g., noise leaking from the signals in the clock lines in the display device).

[0007] Additional aspects will be set forth in the following detailed description, and will be apparent in part from the present disclosure, or may be learned by practicing the inventive concept of the present invention.

[0008] According to one aspect of the present invention, a display device includes: a substrate layer; a circuit layer disposed on the substrate layer and including a pixel circuit layer and a driving circuit layer, wherein the driving circuit layer is configured to provide signals for driving the pixel circuit layer and includes a plurality of clock signal lines; an organic light-emitting diode disposed on the circuit layer and including a first electrode electrically connected to the pixel circuit layer, an organic light-emitting layer disposed on the first electrode, and a second electrode disposed on the organic light-emitting layer; a thin-film encapsulation layer disposed on the organic light-emitting diode; a touch detection unit disposed on the thin-film encapsulation layer and including a touch detection portion and a plurality of touch signal lines electrically connected to the touch detection portion; and a conductive portion disposed between the plurality of clock signal lines and the plurality of touch signal lines and extending through an overlapping region, wherein at least some of the plurality of clock signal lines and at least some of the touch signal lines overlap each other in the overlapping region.

[0009] In an embodiment, the conductive portion may be disposed on the same layer as the second electrode.

[0010] In an embodiment, the second electrode may extend toward the conductive portion, and the second electrode and the conductive portion may be connected to each other.

[0011] In an embodiment, the second electrode may be spaced apart from the conductive portion.

[0012] In an embodiment, the display device may further include a non-overlapping region where at least one of the plurality of clock signal lines and at least one of the touch signal lines do not overlap each other.

[0013] In an embodiment, a plurality of through-holes may be defined in the conductive portion and may not overlap with the overlapping region.

[0014] In an embodiment, the conductive portion may be disposed on the same layer as one of the first electrode and the second electrode.

[0015] In an embodiment, the plurality of through-holes may not overlap with the plurality of clock signal lines.

[0016] In an embodiment, the plurality of through-holes may not overlap with the plurality of touch signal lines.

[0017] In an embodiment, the conductive portion may include: a first region that overlaps with at least one of the clock signal lines and at least one of the touch signal lines, and in which a plurality of through-holes are not defined; a second region in which the region exposed by the plurality of through-holes has a hole density of the first region; and a third region in which the region exposed by the plurality of through-holes has a second region density of holes lower than the first region density.

[0018] In an embodiment, the number of first through-holes defined in each first surface area of the second region may be greater than the number of second through-holes defined in each first surface area of the third region.

[0019] In an embodiment, the size of the first through hole defined in the second region may be greater than the size of the second through hole defined in the third region.

[0020] In an embodiment, the conductive portion may include: a first conductive layer disposed on the same layer as the first electrode and having a plurality of first through holes defined therethrough; and a second conductive layer disposed on the same layer as the second electrode.

[0021] In an embodiment, the second conductive layer may be stacked with the plurality of first through holes.

[0022] In an embodiment, a plurality of second through holes may be defined in the second conductive layer, and the plurality of first through holes and the plurality of second through holes may not be stacked with each other.

[0023] In an embodiment, a plurality of stacked through holes may be provided in the second conductive layer, and the plurality of second through holes may not be stacked with the plurality of touch signal lines and may not be stacked with the plurality of clock signal lines.

[0024] In an embodiment, the plurality of first through holes may not be stacked with the plurality of clock signal lines.

[0025] In an embodiment, the plurality of first through holes may not be stacked with the plurality of touch signal lines.

[0026] In an embodiment, the second electrode may extend toward the second conductive layer and the second electrode and the second conductive layer may be connected to each other.

[0027] In an embodiment, the second electrode and the second conductive layer may be separated from each other.

[0028] In an embodiment, a constant voltage may be provided to the conductive portion.

[0029] According to another aspect of the present invention, a display device includes: a substrate layer; a circuit layer disposed on the substrate layer and including a pixel circuit layer and a driving circuit layer, wherein the driving circuit layer is configured to provide signals for driving the pixel circuit layer and includes a plurality of clock signal lines; an organic light emitting diode disposed on the circuit layer and including a first electrode electrically connected to the pixel circuit layer, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer; a thin film encapsulation layer disposed on the organic light emitting diode; a touch detection unit directly disposed on the thin film encapsulation layer and including a touch detection portion and a plurality of touch signal lines electrically connected to the touch detection portion; and a conductive portion disposed between the plurality of clock signal lines and the plurality of touch signal lines.

[0030] In an embodiment, the conductive portion may include a first conductive layer disposed on the same layer as the first electrode and having a plurality of first through holes defined therethrough and a second conductive layer disposed on the same layer as the second electrode.

[0031] In an embodiment, the second conductive layer may be stacked with a plurality of first vias.

[0032] In an embodiment, the plurality of first vias may not be stacked with a plurality of clock signal lines.

[0033] In an embodiment, the plurality of first vias may not be stacked with a plurality of touch signal lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, are used to explain the principles of the inventive concept. The drawings, including the drawings, are provided to provide a further understanding of the inventive concept and are included in this specification and form a part of this specification.

[0035] Figure 1A is a perspective view of a first position of a first embodiment display device DD constructed according to the principles of the present invention;

[0036] Figure 1B is Figure 1A a perspective view of a second position of the display device;

[0037] Figure 1C is Figure 1A a perspective view of a third position of the display device;

[0038] Figure 2 is Figure 1A a sectional side view of the display device;

[0039] Figure 3A and Figure 3B is a perspective view of a second embodiment display device DD-1 constructed according to the principles of the present invention;

[0040] Figure 4A is a perspective view of a third embodiment display device DD-2 constructed according to the principles of the present invention;

[0041] Figure 4B is a perspective view of a fourth embodiment display device DD-3 constructed according to the principles of the present invention;

[0042] Figure 5A is a plan view of an embodiment of an organic light emitting display panel that can be used in the display device of the present invention;

[0043] Figure 5B is a block diagram of an embodiment of a driving stage of a gate driving circuit that can be used in the display device of the present invention;

[0044] Figure 5C is a schematic sectional side view of an embodiment of a display module that can be used in the display device of the present invention;

[0045] Figure 6Ais an equivalent circuit diagram of an embodiment of a pixel that can be used in the display device of the present invention;

[0046] Figure 6B is a fragmentary cross-sectional side view of an embodiment of an organic light-emitting display panel that can be used in the display device of the present invention;

[0047] Figure 6C is a fragmentary cross-sectional side view of an embodiment of an organic light-emitting panel that can be used in the display device of the present invention;

[0048] Figures 7A to 7C is a cross-sectional side view of an embodiment of a thin film encapsulation layer that can be used in the display device of the present invention;

[0049] Figure 8A is a cross-sectional side view of an embodiment of a touch detection unit that can be used in the display device of the present invention;

[0050] Figures 8B to 8E is Figure 8A a partial top view of the touch detection unit at each layer;

[0051] Figure 8F is Figure 8E an enlarged view of area BB of;

[0052] Figure 9A is Figure 5C an enlarged fragmentary cross-sectional view of an embodiment of area AA of;

[0053] Figure 9B is Figure 9A an enlarged fragmentary cross-sectional view of area WW of;

[0054] Figure 9C is similar to Figure 9A and has the dotted contour line of area WW removed;

[0055] Figure 9D is Figure 5C an enlarged fragmentary cross-sectional view of another embodiment of area AA of;

[0056] Figure 10A is Figure 5C an enlarged fragmentary cross-sectional view of another embodiment of area AA of;

[0057] Figure 10B is Figure 10A an enlarged fragmentary cross-sectional view of area XX of;

[0058] Figure 10C is Figure 5C an enlarged fragmentary cross-sectional view of another embodiment of area AA of;

[0059] Figure 10Dyes Figure 10C an enlarged fragmentary cross-sectional view of a region YY;

[0060] Figure 11A yes Figure 5C An enlarged fragmentary cross-sectional view of another embodiment of region AA;

[0061] Figure 11B yes Figure 11A an enlarged fragmentary cross-sectional view of a region ZZ;

[0062] Figure 11C yes Figure 5C An enlarged fragmentary cross-sectional view of another embodiment of region AA;

[0063] Figure 12A yes Figure 5C An enlarged fragmentary cross-sectional view of another embodiment of region AA;

[0064] Figure 12B yes Figure 12A An enlarged fragmentary plan view of a portion of an embodiment of the present invention;

[0065] Figure 12C yes Figure 12A An enlarged fragmentary plan view of another embodiment of a portion of a display device;

[0066] Figure 13A yes Figure 5C An enlarged fragmentary cross-sectional view of another embodiment of region AA;

[0067] Figure 13B yes Figure 13A An enlarged fragmentary plan view of a portion of an embodiment of the present invention;

[0068] Figure 14A yes Figure 5C an enlarged fragmentary cross-sectional view of yet another embodiment of area AA; and

[0069] Figure 14B yes Figure 14A An enlarged fragmentary plan view of an embodiment of the present invention. DETAILED DESCRIPTION

[0070] In the following description, for the purpose of illustration, numerous specific details are set forth to provide a thorough understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments may be practiced without these specific details, or may be practiced with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments.

[0071] In the accompanying drawings, for clarity and for the purpose of description, the dimensions and relative dimensions of layers, films, panels, regions, etc. may be exaggerated. Further, like reference numerals denote like elements.

[0072] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, no intervening elements or layers are present. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, by way of example, XYZ, XYY, YZ, and ZZ. Like reference numerals always denote like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0073] Although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, and / or section from another. Thus, a first element, first component, first region, first layer, and / or first section discussed below may be termed a second element, second component, second region, second layer, and / or second section without departing from the teachings of this disclosure.

[0074] For descriptive purposes, spatial relative terms such as "under", "below", "beneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "under" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary term "under" can encompass both an orientation of "above" and "under". Further, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the corresponding spatial relative descriptors used herein are to be interpreted accordingly.

[0075] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms. Additionally, when the terms "comprises" and / or its variations and / or "includes" and / or its variations are used in this specification, it is specified that there are the stated features, integers, steps, operations, elements, components and / or groups thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0076] Various exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the exemplary embodiments disclosed herein should not be construed as limited to the particular shapes shown in the regions, but will include, for example, shape deviations due to manufacturing. For example, an implanted region shown as rectangular will generally have rounded or curved features at its edges and / or gradients in implanted concentration, rather than a binary change from the implanted region to the non-implanted region. Similarly, buried regions formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to be limiting.

[0077] All terms used herein, unless otherwise defined, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms (such as those defined in a general dictionary) shall be construed to have a meaning consistent with their meaning in the context of the relevant art and will not be construed in an idealized or overly formal sense.

[0078] As Figure 1AAs shown, in the first operation mode of the display device DD, the display surface IS of the display image IM is a surface extending along a first direction DR1 and a second direction DR2. The display surface IS has a thickness in a third direction DR3 perpendicular to the first two directions. The front surface (or upper surface) and the rear surface (lower surface) of each member are separated in the third direction DR3. However, since the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be rearranged or redefined. Hereinafter, the first to third directions as the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 respectively will be indicated by the same reference numerals.

[0079] Figures 1A to 1C and Figures 3A to 4B FIG. shows a flexible foldable display device as an example of the display device DD. However, the inventive concept may relate to a rollable display device or a bendable display device, and is not particularly limited. In addition, although a flexible display device is shown in these embodiments, the inventive concept is not limited thereto. The display device DD may be a flat rigid display device or a curved rigid display device. The display device DD can be used not only for large-sized electronic devices such as televisions and monitors, but also for small-sized and medium-sized electronic devices such as mobile phones, tablets, car navigation systems, game consoles, and smart watches.

[0080] As Figure 1A shown, the display surface IS of the display device DD may include a plurality of regions. The display device DD may include a display region DD-DA for displaying the display image IM and a non-display region DD-NDA adjacent to the display region DD-DA. The non-display region DD-NDA may be a region where no image is displayed. Figure 1A FIG. shows a vase as an example of the image IM. The display region DD-DA may have a rectangular form as shown. The non-display region DD-NDA may surround the display region DD-DA. However, the inventive concept is not limited thereto, and in other embodiments, the forms or shapes of the display region DD-DA and the non-display region DD-NDA may be changed.

[0081] As Figures 1A to 1C shown, the display device DD may include a plurality of regions defined according to the operation form. The display device DD may include a bending region BA bent around a bending axis BX, a first non-bending region NBA1, and a second non-bending region NBA2.

[0082] As Figure 1BAs shown, the display device DD can be bent inward such that the display surfaces IS of the first non-bending region NBA1 and the second non-bending region NBA2 face each other. As Figure 1C shown, the display device DD can be bent outward such that the display surface IS is exposed to the outside.

[0083] Although only one bending region BA is shown in Figures 1A to 1C , the inventive concept is not limited thereto. For example, according to an embodiment of the inventive concept, the display device DD may include a plurality of bending regions BA.

[0084] According to an embodiment of the inventive concept, the display device DD may be configured to only repeat Figure 1A and Figure 1B the operation modes shown therein. However, the inventive concept is not limited thereto, and the bending region BA may be defined as the position where the user operates the display device DD. For example, different from Figure 1B and Figure 1C , the bending region BA may be defined as being parallel to the first direction DR1 and may be defined in the diagonal direction. The area of the bending region BA is not fixed and may be determined according to the radius of curvature.

[0085] Figure 2 shows a cross-sectional view taken in the plane of the first direction DR1 and the third direction DR3.

[0086] As Figure 2 shown, the display device DD includes a protective film PM, a display module DM, an optical member LM, a window WM, a first adhesive member AM1, a second adhesive member AM2, and a third adhesive member AM3. The display module DM is disposed between the protective film PM and the optical member LM. The optical member LM is disposed between the display module DM and the window WM. The first adhesive member AM1 bonds the display module DM and the protective film PM; the second adhesive member AM2 bonds the display module DM and the optical member LM; the third adhesive member AM3 bonds the optical member LM and the window WM.

[0087] The protective film PM protects the display module DM. The protective film PM provides a first outer surface OS-L exposed to the outside and provides an adhesive surface adhered to the first adhesive member AM1. The protective film PM prevents external moisture from penetrating into the display module DM and absorbs the force from external impacts.

[0088] The protective film PM may include a plastic film as a base substrate. The protective film PM may include a plastic film containing one selected from the group consisting of polyether sulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), poly(arylene ethersulfone), and combinations thereof.

[0089] The material constituting the protective film PM is not limited to plastic resins and may include organic / inorganic composite materials. The protective film PM may include an inorganic material filling the pores of a porous organic layer and the organic layer. The protective film PM may also include a functional layer formed on the plastic film. The functional layer may include a resin layer. The functional layer may be formed by a coating method. The protective film PM may also be omitted.

[0090] The window WM protects the display module DM from damage caused by external impacts and provides an input surface for the user. The window WM provides a second outer surface OS-U exposed to the outside and provides an adhesive surface adhered to the second adhesive member AM2. In Figures 1A to 1C the display surface IS shown may be the second outer surface OS-U.

[0091] The window WM may include a plastic film. The window WM may have a multilayer structure. The window WM may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The window WM may also include a border pattern. The multilayer structure may be formed by a continuous process or an adhesive process using an adhesive layer.

[0092] The optical member LM reduces the reflection of external light. The optical member LM may at least include a polarizing film. The optical member LM may also include a retardation film. According to an embodiment of the inventive concept, the optical member LM may be omitted.

[0093] The display module DM may include an organic light-emitting display panel (or display panel) DP and a touch detection unit TS. The touch detection unit TS may be directly disposed on the organic light-emitting display panel DP. In this specification, "directly disposed" means "formed" by a continuous process and does not include "attached" by an additional adhesive layer.

[0094] The organic light-emitting display panel DP generates an image IM corresponding to the input image data (see Figure 1A ). The organic light-emitting display panel DP provides a first display panel surface BS1-L and a second display panel surface BS1-U opposite in the third direction DR3. In this embodiment, although the organic light-emitting display panel DP is exemplarily described, the display panel is not limited thereto.

[0095] The touch detection unit TS obtains coordinate information of an external input. The touch detection unit TS can detect an external input by a capacitive method.

[0096] The display module DM according to an embodiment of the inventive concept may further include an anti-reflection layer (not shown). The anti-reflection layer may include a color filter or a stacked structure of a conductive layer / insulating layer / conductive layer. The anti-reflection layer may reduce reflection of external light by absorbing light incident from the outside, causing destructive interference of light incident from the outside, or polarizing light incident from the outside. The anti-reflection layer may replace the role of the optical member LM.

[0097] Each of the first adhesive member AM1, the second adhesive member AM2, and the third adhesive member AM3 may be an organic adhesive layer such as an optically clear adhesive (OCA) film, an optically clear resin (OCR), or a pressure-sensitive adhesive (PSA) film. The organic adhesive layer may include an adhesive material such as polyurethane, polyacrylate, polyester, polyepoxy resin, and polyvinyl acetate.

[0098] The display device DD may further include a frame structure (not shown) for supporting the functional layer to maintain Figures 1A to 1C the position shown therein. The frame structure may include a hinge structure or a hinge structure.

[0099] Figure 3A The display device DD-1 in an unfolded state is shown, Figure 3B and the display device DD-1 in a bent state is shown.

[0100] The display device DD-1 may include a bent region BA and a non-bent region NBA. The non-display region DD-NDA of the display device DD-1 may be bendable. In other embodiments, the bent region of the display device DD-1 may be different.

[0101] Different from Figures 1A to 1C the display device DD shown therein, the display device DD-1 may be fixed in a shape and operated. As Figure 3B shown, the display device DD-1 may be operated in a bent state. The display device DD-1 may be fixed to a frame in a bent state, and the frame may be coupled to a housing of an electronic device.

[0102] The display device DD-1 may have the same cross-sectional structure as Figure 2 the cross-sectional structure shown therein. However, the non-bent region NBA and the bent region BA may have different stacked structures. The non-bent region NBA may have the same cross-sectional structure as Figure 2 the cross-sectional structure shown therein, and the bent region BA may have the same cross-sectional structure as Figure 2Cross-sectional structures with different cross-sectional structures shown in the figure. The optical member LM and the window WM may not be provided in the bending region BA. For example, the optical member LM and the window WM may be provided only in the non-bending region NBA. Similarly, the second adhesive member AM2 and the third adhesive member AM3 may also not be provided in the bending region BA.

[0103] Now refer to Figure 4A , the display device DD-2 includes a non-bending region (or flat region) NBA that displays a main image on its front surface and a bending region (or side region) that displays a sub-image on its side surface. Although not shown in the figure, the sub-image may include an icon for providing predetermined information. In this embodiment, the terms "non-bending region NBA" and "bending region BA" define the display device DD-2 by using a plurality of regions divided by a bent form or state.

[0104] The bending region BA bent from the non-bending region NBA displays a sub-image in a fourth direction DR4 that intersects the first direction DR1, the second direction DR2, and the third direction DR3. However, other relative directions may also be used.

[0105] Refer to Figure 4B , the display device DD-3 includes a non-bending region NBA that displays a main image on its front surface and a first bending region BA1 and a second bending region BA2 that display sub-images on its side surface. The first bending region BA1 and the second bending region BA2 may be bent from opposite sides of the non-bending region NBA.

[0106] As Figure 5A shown, the organic light-emitting display panel DP includes a display region DA and a non-display region NDA located in a plane. The display region DA and the non-display region NDA of the organic light-emitting display panel DP may correspond to the display region DD-DA (see Figure 1A ) and the non-display region DD-NDA (see Figure 1A ) of the display device DD (see Figure 1A ), respectively. The display region DA and the non-display region NDA of the organic light-emitting display panel DP do not have to be the same as the display region DD-DA (see Figure 1A ) and the non-display region DD-NDA (see Figure 1A ) of the display device DD (see Figure 1A ), and may be changed according to the structure / design of the organic light-emitting display panel DP.

[0107] The organic light-emitting display panel DP includes a plurality of pixels PX. The region where the plurality of pixels PX are provided may be defined as the display region DA. In this embodiment, the non-display region NDA may be defined along the contour surrounding the display region DA.

[0108] The organic light-emitting display panel DP includes gate lines GL, data lines DL, emission lines EL, control signal lines SL-D, an initialization voltage line SL-Vint, a voltage line SL-VDD, a power supply line E-VSS, and a pad portion PD.

[0109] The gate lines GL are respectively connected to corresponding ones of a plurality of pixels PX, and the data lines DL are respectively connected to corresponding ones of the plurality of pixels PX. Each emission line EL may be arranged parallel to a corresponding one of the gate lines GL. The control signal line SL-D may supply a control signal to a gate driving circuit GDC. The initialization voltage line SL-Vint may supply an initialization voltage to the plurality of pixels PX. The voltage line SL-VDD may be connected to the plurality of pixels PX and supply a first voltage to the plurality of pixels PX. The voltage line SL-VDD may include a plurality of lines extending in a first direction DR1 and a plurality of lines extending in a second direction DR2. The power supply line E-VSS may surround three sides of the display area DA and may be disposed in a non-display area NDA. A common voltage (e.g., a second voltage) may be supplied to the plurality of pixels PX of the power supply line E-VSS. The common voltage may have a voltage level lower than that of the first voltage.

[0110] The gate driving circuit GDC at the connection of the gate line GL and the emission line EL may be disposed on one side of the non-display area NDA. Some of the gate line GL, the data line DL, the emission line EL, the control signal line SL-D, the initialization voltage line SL-Vint, the voltage line SL-VDD, and the power supply line E-VSS are disposed on the same layer, and some of them are disposed on another layer.

[0111] The pad portion PD may be connected to ends of the data line DL, the control signal line SL-D, the initialization voltage line SL-Vint, and the voltage line SL-VDD.

[0112] Figure 5B An example of a driving stage GDSi of the driving stages of a plurality of gate driving circuits GDC connected to the i-th gate line GLi and the i-th emission line ELi is shown.

[0113] The driving stage GDSi may include a light emission control stage EC-Ci and a gate driving stage GC-Ci. The light emission control signals CLK1, CLK2, VGL, VGH, and EMFLM may be provided to the light emission control stage EC-Ci of the driving stage GDSi through a first clock signal line CL1, a second clock signal line CL2, a first voltage line VL1, a second voltage line VH1, and a first start signal line EF1. The gate control signals CLK3, CLK4, VGH1, VGL1, and FLM may be provided to the gate driving stage GC-Ci through a third clock signal line CL3, a fourth clock signal line CL4, a third voltage line VL2, a fourth voltage line VH2, and a second start signal line EF2.

[0114] Although, as described, the gate driving stage GC-Ci of the light emission control stage EC-Ci is included in one driving stage GDSi, the inventive concept is not limited thereto. For example, the light emission control stage EC-Ci and the gate driving stage GC-Ci may be included in another driving stage.

[0115] The light emission control stage EC-Ci may include a first clock terminal CK1, a second clock terminal CK2, a first voltage input terminal VPL1, a second voltage input terminal VPH1, an input terminal IN, a carry terminal CR, and an output terminal OUT1.

[0116] The first clock terminal CK1 receives the first clock signal CLK1, and the second clock terminal CK2 receives the second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 may have different phases. The second clock signal CLK2 may be a signal obtained by inverting or delaying the phase of the first clock signal CLK1.

[0117] The first voltage input terminal VPL1 receives the first voltage VGL, and the second voltage input terminal VPH1 receives the second voltage VGH. The voltage level of the first voltage VGL may be lower than the voltage level of the second voltage VGH.

[0118] The input terminal IN may receive a carry signal from a previous light emission control stage EC-Ci-1 (not shown), and the carry terminal CR may output a carry signal to a next light emission control stage EC-Ci+1 (not shown). The output terminal OUT1 may provide the light emission control signal generated from the light emission control stage EC-Ci to the light emission line ELi.

[0119] The start signal EMFLM may be input to the input terminal IN of the first light emission control stage EC-C1 in the light emission control stage.

[0120] The gate driving stage GC-Ci may include a third clock terminal CK3, a fourth clock terminal CK4, a third voltage input terminal VPL2, a fourth voltage input terminal VPH2, an input terminal IN, a carry terminal CR, and an output terminal OUT2.

[0121] The third clock terminal CK3 receives a third clock signal CLK3, and the fourth clock terminal CK4 receives a fourth clock signal CLK4. The third clock signal CLK3 and the fourth clock signal CLK4 may have different phases. The fourth clock signal CLK4 may be a signal obtained by inverting or delaying the phase of the third clock signal CLK3.

[0122] The third voltage input terminal VPL2 receives a third voltage VGL1, and the fourth voltage input terminal VPH2 receives a fourth voltage VGH1. The voltage level of the third voltage VGL1 may be lower than the voltage level of the fourth voltage VGH1.

[0123] The input terminal IN may receive a carry signal from a previous gate driving stage GC-Ci-1 (not shown), and the carry terminal CR may output a carry signal to a next gate driving stage GC-Ci+1 (not shown). The output terminal OUT2 may provide a gate signal generated from the gate driving stage GC-Ci to the gate line GLi.

[0124] The start signal FLM may be input to the input terminal IN of a first gate driving stage GC-C1 (not shown) among a plurality of gate driving stages.

[0125] According to an embodiment of the inventive concept, one of the first clock terminal CK1, the second clock terminal CK2, the first voltage input terminal VPL1, the second voltage input terminal VPH1, the input terminal IN, the carry terminal CR, and the output terminal OUT1 of the light emission control stage EC-Ci may be omitted, or other terminals may also be included. For example, the carry terminal CR may be omitted.

[0126] According to an embodiment of the inventive concept, one of the third clock terminal CK3, the fourth clock terminal CK4, the third voltage input terminal VPL2, the fourth voltage input terminal VPH2, the input terminal IN, the carry terminal CR, and the output terminal OUT2 of the gate driving stage GC-Ci may be omitted, or other terminals may also be included. For example, the carry terminal CR may be omitted.

[0127] In addition, although the input terminal IN of the light emission control stage EC-Ci and the input terminal IN of the gate driving stage GC-Ci are exemplarily shown to be respectively connected to the carry terminal of the previous stage, the inventive concept is not limited thereto. In other embodiments, the connection between the driving stages may be changed in various ways.

[0128] AsFigure 5C As shown, the organic light-emitting display panel DP includes a substrate layer SUB, a circuit layer DP-CL disposed on the substrate layer SUB, a light-emitting element layer DP-OLED, and a thin-film encapsulation layer TFE.

[0129] The substrate layer SUB may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate as a flexible substrate. The plastic substrate may include at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0130] The circuit layer DP-CL may include a semiconductor layer, a plurality of insulating layers, and a plurality of conductive layers. The plurality of conductive layers of the circuit layer DP-CL may form signal lines or a control circuit of pixels. The circuit layer DP-CL may include a pixel circuit layer DP-PCL disposed in the display area DA and a driving circuit layer DP-DCL disposed in the non-display area NDA. The pixel circuit layer DP-PCL may include a circuit having a gate line GL, a data line DL, a light-emitting line EL, an initialization voltage line SL-Vint, a voltage line SL-VDD, and a pixel PX as described above with reference to Figure 5A the description.

[0131] The driving circuit layer DP-DCL may include a gate driving circuit GDC and a control signal line SL-D as described above with reference to Figure 5A the description. The control signal line SL-D may include Figure 5B a first clock signal line CL1, a second clock signal line CL2, a third clock signal line CL3, a fourth clock signal line CL4, a first voltage line VL1, a second voltage line VH1, a third voltage line VL2, a fourth voltage line VH2, a first start signal line EF1, and a second start signal line EF2 shown in

[0132] The light-emitting element layer DP-OLED includes an organic light-emitting diode and a pixel defining layer.

[0133] The thin-film encapsulation layer TFE encapsulates the light-emitting element layer DP-OLED. The thin-film encapsulation layer TFE may include at least two inorganic layers and an organic layer disposed between the two inorganic layers. The inorganic layers protect the light-emitting element layer DP-OLED from moisture and oxygen, and the organic film protects the light-emitting element layer DP-OLED from foreign substances such as dust particles.

[0134] The touch detection unit TS is disposed on the thin film encapsulation layer TFE. The touch detection unit TS may be directly disposed on the thin film encapsulation layer TFE. However, the inventive concept is not limited thereto, and a buffer layer may be disposed on the thin film encapsulation layer TFE and the touch detection unit TS may be directly disposed on the buffer layer. The buffer layer may be an inorganic layer or an organic layer. The inorganic layer may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The organic layer may include a polymer (e.g., an acrylic polymer) organic layer. However, this is exemplary and the inventive concept is not limited thereto. Although the buffer layer is described as a separate component, the buffer layer may be a component included in the thin film encapsulation layer TFE.

[0135] The touch detection unit TS includes a touch detection portion TSP and a touch signal line TSL. The touch detection portion TSP and the touch signal line TSL may have a single-layer or multi-layer structure. The touch detection portion TSP and the touch signal line TSL may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The touch detection portion TSP and the touch signal line TSL may include a metal layer, e.g., molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The touch detection portion TSP and the touch signal line TSL may have the same or different layer structures. Specific details of the touch detection unit TS will be described later.

[0136] Figure 6A It shows how the i-th pixel PXi may be connected to the k-th data line DLk among a plurality of data lines DL (see Figure 5A ).

[0137] The i-th pixel PXi includes an organic light emitting diode OLED and a pixel driving circuit for controlling the organic light emitting diode. The pixel driving circuit may include seven thin film transistors T1 to T7 and a capacitor Cst.

[0138] The driving transistor controls the driving current supplied to the organic light emitting diode OLED. The output electrode of the second transistor T2 is electrically connected to the organic light emitting diode OLED. The output electrode of the second transistor T2 may directly contact the first electrode of the organic light emitting diode OLED or may be connected to the organic light emitting diode OLED through another transistor (e.g., the sixth transistor T6 in this embodiment).

[0139] The control electrode of the control transistor may receive a control signal. The control signals applied to the i-th pixel PXi may include the (i - 1)-th gate signal Si - 1, the i-th gate signal Si, the (i + 1)-th gate signal Si + 1, the data signal Dk, and the i-th light emission control signal Ei. According to an embodiment of the inventive concept, the control transistor may include the first transistor T1 and the third transistor T3 to the seventh transistor T7.

[0140] The first transistor T1 includes an input electrode connected to the k-th data line DLk, a control electrode connected to the i-th gate line GLi, and an output electrode connected to the output electrode of the second transistor T2. The first transistor T1 is turned on by a gate signal Si (hereinafter referred to as the i-th gate signal) applied to the i-th gate line GLi and supplies a data signal DK applied to the k-th data line DLk to the capacitor Cst.

[0141] Figure 6B Is Figure 6A A cross-sectional view of the first transistor T1 of the equivalent circuit shown in. Figure 6C Is Figure 6A A cross-sectional view of the second transistor T2, the sixth transistor T6, and the organic light-emitting diode OLED of the equivalent circuit shown in.

[0142] Referring to Figure 6B And Figure 6C In, a buffer layer BFL may be provided on the substrate layer SUB. The buffer layer BFL improves the bonding strength between the substrate layer SUB and the conductive pattern or the semiconductor pattern. The buffer layer BFL may include an inorganic layer. Although not shown in the figure, a barrier layer for preventing foreign substances from entering may also be provided on the upper surface of the substrate layer SUB. In various exemplary embodiments, the buffer layer BFL and the barrier layer may be selectively included or omitted.

[0143] The semiconductor pattern OSP1 of the first transistor T1 (hereinafter referred to as the first semiconductor pattern), the semiconductor pattern OSP2 of the second transistor T2 (hereinafter referred to as the second semiconductor pattern), and the semiconductor pattern OSP6 of the sixth transistor T6 (hereinafter referred to as the sixth semiconductor pattern) are provided on the buffer layer BFL. The first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6 may be made of a material selected from amorphous silicon, polycrystalline silicon, and metal oxide semiconductors.

[0144] The first insulating layer 10 may be provided on the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. Although Figure 6B And Figure 6C In it is shown that the first insulating layer 10 is provided as an unpatterned layer for covering the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6, but the first insulating layer 10 may be provided as a patterned layer corresponding to the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6.

[0145] The first insulating layer 10 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0146] The control electrode GE1 of the first transistor T1 (hereinafter referred to as the first control electrode), the control electrode GE2 of the second transistor T2 (hereinafter referred to as the second control electrode), and the control electrode GE6 of the sixth transistor T6 (hereinafter referred to as the sixth control electrode) are disposed on the first insulating layer 10. The first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 can be fabricated according to the same lithography process as the gate line GL (see Figure 5A ).

[0147] A second insulating layer 20 for covering the first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 can be disposed on the first insulating layer 10. The second insulating layer 20 can provide a flat upper surface. The second insulating layer 20 can include an organic material and / or an inorganic material.

[0148] The input electrode SE1 of the first transistor T1 (hereinafter referred to as the first input electrode) and the output electrode DE1 (hereinafter referred to as the first output electrode), the input electrode SE2 of the second transistor T2 (hereinafter referred to as the second input electrode) and the output electrode DE2 (hereinafter referred to as the second output electrode), and the input electrode SE6 of the sixth transistor T6 (hereinafter referred to as the sixth input electrode) and the output electrode DE6 (hereinafter referred to as the sixth output electrode) are disposed on the second insulating layer 20.

[0149] Each of the first output electrode DE1 and the first input electrode SE1 is connected to the first semiconductor pattern OSP1 through a first through hole CH1 penetrating the first insulating layer 10 and the second insulating layer 20 or a second through hole CH2 penetrating the first insulating layer 10 and the second insulating layer 20. Each of the second input electrode SE2 and the second output electrode DE2 is connected to the second semiconductor pattern OSP2 through a third through hole CH3 penetrating the first insulating layer 10 and the second insulating layer 20 or a fourth through hole CH4 penetrating the first insulating layer 10 and the second insulating layer 20. Each of the sixth input electrode SE6 and the sixth output electrode DE6 is connected to the sixth semiconductor pattern OSP6 through a fifth through hole CH5 penetrating the first insulating layer 10 and the second insulating layer 20 or a sixth through hole CH6 penetrating the first insulating layer 10 and the second insulating layer 20. On the other hand, according to other embodiments of the inventive concept, some of the first transistor T1, the second transistor T2, and / or the sixth transistor T6 can be modified and implemented as a bottom gate structure.

[0150] A third insulating layer 30 for covering the first input electrode SE1, the second input electrode SE2, the sixth input electrode SE6, the first output electrode DE1, the second output electrode DE2, and the sixth output electrode DE6 is disposed on the second insulating layer 20. The third insulating layer 30 may include an organic layer and / or an inorganic layer. The third insulating layer 30 may include an organic material for providing a flat surface.

[0151] In various exemplary embodiments, one or more of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may be omitted. Each of the second insulating layer 20 and the third insulating layer 30 may be defined as an interlayer insulating layer. The interlayer insulating layer is disposed between a lower conductive pattern and an upper conductive pattern to insulate the conductive patterns from each other.

[0152] A pixel defining layer PDL and an organic light emitting diode OLED are disposed on the third insulating layer 30. Refer to Figure 6C , each organic light emitting diode OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an organic light emitting layer EML, and an electron control layer ECL. Specifically, the first electrode AE may be disposed on a circuit layer DP-CL (see Figure 5C ). The organic light emitting layer EML may be disposed on the first electrode AE. The second electrode CE may be disposed on the organic light emitting layer EML.

[0153] The first electrode AE is disposed on the third insulating layer 30. Here, the first electrode AE may be disposed as an anode or a cathode. Hereinafter, the first electrode AE is described as an anode. The first electrode AE is connected to the sixth output electrode DE6 through a seventh through hole CH7 penetrating the third insulating layer 30. An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a part of the first electrode AE.

[0154] Pixels PX may be disposed in a planar pixel region. The pixel region may include a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA. According to this embodiment, the light emitting region PXA corresponds to a partial region of the first electrode AE exposed through the opening OP.

[0155] The hole control layer HCL may be disposed in the light emitting region PXA and the non-light emitting region NPXA. Although not shown in the figure, a common layer such as the hole control layer HCL may be formed in a plurality of pixels PX (see Figure 5A ).

[0156] The organic light-emitting layer EML is disposed on the hole control layer HCL. The organic light-emitting layer EML may be disposed in a region corresponding to the opening OP. That is, the organic light-emitting layer EML may be separated and formed at each of a plurality of pixels. Using such a patterned organic light-emitting layer EML as shown in this embodiment, the organic light-emitting layer EML may be disposed at a plurality of pixels PX, where the organic light-emitting layer EML may generate white light. In addition, the organic light-emitting layer EML may have a multilayer structure.

[0157] The electron control layer ECL is disposed on the organic light-emitting layer EML. Although not shown in the figure, the electron control layer ECL may be formed at a plurality of pixels PX (see Figure 5A ).

[0158] The second electrode CE is disposed on the electron control layer ECL at a plurality of pixels PX. Here, the second electrode CE may be set as an anode or a cathode. Hereinafter, the second electrode CE is described as a cathode. That is, when the first electrode AE may be set as an anode, the second electrode CE may be set as a cathode. In addition, when the first electrode AE may be set as a cathode, the second electrode CE may be set as an anode.

[0159] The thin film encapsulation layer TFE is disposed on the second electrode CE. The thin film encapsulation layer TFE is disposed at a plurality of pixels PX. The thin film encapsulation layer TFE includes at least one inorganic layer and at least one organic layer. The thin film encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers stacked alternately.

[0160] In the illustrated exemplary embodiment, the thin film encapsulation layer TFE directly covers the second electrode CE. A cladding layer for covering the second electrode CE may also be disposed between the thin film encapsulation layer TFE and the second electrode CE. The thin film encapsulation layer TFE may directly cover the cladding layer.

[0161] Hereinafter, with reference to Figures 7A to 7C the thin film encapsulation layers TFE1, TFE2, and TFE3 are described.

[0162] As Figure 7A shown, the thin film encapsulation layer TFE1 may include n inorganic thin films IOL1 to IOLn, and the first inorganic thin film IOL1 contacts the second electrode CE (see Figure 6C ). The first inorganic thin film IOL1 may be defined as the lower inorganic thin film, and the other inorganic thin films among the n inorganic thin films IOL1 to IOLn except the first inorganic thin film IOL1 may be defined as the upper inorganic thin films.

[0163] The thin film sealing layer TFE1 may include n - 1 organic thin films OL1 to OLn - 1, and the n - 1 organic thin films OL1 to OLn - 1 and the n inorganic thin films IOL1 to IOLn may be alternately arranged. The n - 1 organic thin films OL1 to OLn - 1 may have an average thickness thicker than the average thickness of the n inorganic thin films IOL1 to IOLn.

[0164] Each of the n inorganic thin films IOL1 to IOLn may be a single layer including one material or a multi - layer in which each layer includes different materials. Each of the n - 1 organic thin films OL1 to OLn - 1 may be formed by depositing or printing organic monomers. For example, each of the n - 1 organic thin films OL1 to OLn - 1 may be formed by an ink - jet printing method or may be formed by coating a composite including an acrylic monomer. According to an embodiment of the inventive concept, the thin film sealing layer TFE1 may further include an nth organic thin film.

[0165] As Figure 7B and Figure 7C shown, the inorganic thin films included in each of the thin film sealing layers TFE2 and TFE3 may have the same or different inorganic materials and may have the same or different thicknesses. The organic thin films included in each of the thin film sealing layers TFE2 and TFE3 may have the same or different organic materials and may have the same or different thicknesses.

[0166] As Figure 7B shown, the thin film sealing layer TFE2 may include a first inorganic thin film IOL1, a first organic thin film OL1, a second inorganic thin film IOL2, a second organic thin film OL2, and a third inorganic thin film IOL3 stacked in sequence.

[0167] The first inorganic thin film IOL1 may have a two - layer structure. The first sub - layer S1 and the second sub - layer S2 may include different inorganic materials.

[0168] As Figure 7C shown, the thin film sealing layer TFE3 may include a first inorganic thin film IOL10, a first organic thin film OL1, and a second inorganic thin film IOL20 stacked in sequence. The first inorganic thin film IOL10 may have a two - layer structure. The first sub - layer S10 and the second sub - layer S20 may include different inorganic materials. The second inorganic thin film IOL20 may have a two - layer structure. The second inorganic thin film IOL20 may include a first sub - layer S100 and a second sub - layer S200 deposited in different deposition environments and / or stages. The first sub - layer S100 may be deposited under low - power conditions, and the second sub - layer S200 may be deposited under high - power conditions. The first sub - layer S100 and the second sub - layer S200 may include the same inorganic material.

[0169] As Figure 8AAs shown, the touch detection unit TS includes a first conductive layer TS-CL1, a first insulating layer TS-IL1 (hereinafter referred to as the first touch insulating layer), a second conductive layer TS-CL2, and a second insulating layer TS-IL2 (hereinafter referred to as the second touch insulating layer). The first conductive layer TS-CL1 is directly disposed on the thin film encapsulation layer TFE. The inventive concept is not limited thereto, and another buffer layer (e.g., an inorganic layer or an organic layer) may be disposed between the first conductive layer TS-CL1 and the thin film encapsulation layer TFE. According to another embodiment of the inventive concept, a plastic film, a glass substrate, or a plastic substrate may be disposed between the first conductive layer TS-CL1 and the thin film encapsulation layer TFE.

[0170] Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 may include a single-layer structure or a multi-layer structure stacked in a third direction DR3. The conductive layer of the multi-layer structure may include at least two layers of a transparent conductive layer and a metal layer. The conductive layer of the multi-layer structure may include metal layers having different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The metal layer may include silver, titanium, copper, aluminum, and their alloys.

[0171] Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 includes a plurality of patterns. Hereinafter, the first conductive layer TS-CL1 includes a first conductive pattern, and the second conductive layer TS-CL2 includes a second conductive pattern. Each of the first conductive pattern and the second conductive pattern may include a touch electrode and a touch signal line.

[0172] Each of the first touch insulating layer TS-IL1 and the second touch insulating layer TS-IL2 may have a single-layer or multi-layer structure. Each of the first touch insulating layer TS-IL1 and the second touch insulating layer TS-IL2 may include at least one of an inorganic layer and an organic layer.

[0173] The first touch insulating layer TS-IL1 insulates the first conductive layer TS-CL1 and the second conductive layer TS-CL2, and its form is not limited to the described exemplary embodiments. In various exemplary embodiments, the form of the first touch insulating layer TS-IL1 may be changed. For example, the first touch insulating layer TS-IL1 may completely cover the thin film encapsulation layer TFE and / or may include a plurality of insulating patterns. The plurality of insulating patterns may be stacked with the first connection portion CP1 and may be stacked with the second connection portion CP2, which will be described later.

[0174] Although exemplary embodiments of the double-layer touch detection unit are shown, the inventive concept is not limited to these embodiments. The single-layer touch detection unit includes a conductive layer and an insulating layer covering the conductive layer. The conductive layer includes touch sensors and touch signal lines connected to the touch sensors. The single-layer touch detection unit can obtain coordinate information by a self-capacitance (self-cap) method.

[0175] As Figure 8B shown, the touch detection unit TS may include a touch detection part TSP (see Figure 5C ), touch signal lines TSL (see Figure 5C ), and a pad part PDa.

[0176] The touch detection part TSP (see Figure 5C ) may include first touch electrodes TE1-1 to TE1-m and second touch electrodes TE2-1 to TE2-n. The touch signal lines TSL (see Figure 5C ) may include first touch signal lines SL1-1 to SL1-m connected to the first touch electrodes TE1-1 to TE1-m and second touch signal lines SL2-1 to SL2-n connected to the second touch electrodes TE2-1 to TE2-n. The pad part PDa may be electrically connected to the first touch signal lines SL1-1 to SL1-m and the second touch signal lines SL2-1 to SL2-n.

[0177] Connection electrodes TSD may be provided between the first touch electrodes TE1-1 to TE1-m and the first touch signal lines SL1-1 to SL1-m, and between the second touch electrodes TE2-1 to TE2-n and the second touch signal lines SL2-1 to SL2-n. The connection electrodes TSD may be respectively connected to the ends of the first touch electrodes TE1-1 to TE1-m and the ends of the second touch electrodes TE2-1 to TE2-n to transmit signals. In various embodiments, the connection electrodes TSD may be omitted.

[0178] Each of the first touch electrodes TE1-1 to TE1-m may have a grid form, in which a plurality of touch openings are defined. Each of the first touch electrodes TE1-1 to TE1-m includes a plurality of first touch sensor parts SP1 and a plurality of first connection parts CP1. The first touch sensor parts SP1 are arranged in a first direction DR1. Each of the first connection parts CP1 connects two adjacent first touch sensor parts SP1. Although not shown in the figure, the first touch signal lines SL1-1 to SL1-m may also have a grid form.

[0179] The second touch electrodes TE2-1 to TE2-n cross the first touch electrodes TE1-1 to TE1-m with an insulating gap therebetween. Each of the second touch electrodes TE2-1 to TE2-n may have a grid form in which a plurality of touch openings are defined. Each of the second touch electrodes TE2-1 to TE2-n includes a plurality of second touch sensor portions SP2 and a plurality of second connection portions CP2. The second touch sensor portions SP2 are arranged along the second direction DR2. Each of the second connection portions CP2 connects two adjacent second touch sensor portions SP2. The second touch signal lines SL2-1 to SL2-n may also have a grid form.

[0180] The first touch electrodes TE1-1 to TE1-m are electrostatically coupled to the second touch electrodes TE2-1 to TE2-n. When a touch detection signal is applied to the first touch electrodes TE1-1 to TE1-m, a capacitor is formed between the first touch sensor portion SP1 and the second touch sensor portion SP2.

[0181] Part of the plurality of first touch sensor parts SP1, the plurality of first connection parts CP1, the first touch signal lines SL1-1 to SL1-m, the plurality of second touch sensor parts SP2, the plurality of second connection parts CP2, and the second touch signal lines SL2-1 to SL2-n may be configured by using Figure 8A The first conductive layer TS-CL1 shown in FIG. 1 is patterned to form the other parts. Figure 8A The second conductive layer TS-CL2 shown in FIG. 1 is formed by patterning.

[0182] In order to electrically connect a conductive pattern disposed in one layer with a conductive pattern disposed in another layer, a Figure 8A The contact hole penetrating the first touch insulating layer TS-IL1 is shown in FIG. Figures 8C to 8E A touch detection unit TS according to an embodiment of the inventive concept is described.

[0183] like Figure 8C As shown, the first conductive pattern is arranged on the thin film sealing layer TFE (see Figure 8A ). The first conductive pattern may include a bridge pattern CP2. The bridge pattern CP2 is directly disposed on the thin film sealing layer TFE. In the illustrated exemplary embodiment, the thin film sealing layer TFE covers the display area DA. The bridge pattern CP2 is Figure 8B Another name for the second connection portion CP2 shown in FIG.

[0184] like Figure 8DAs shown, a first touch insulating layer TS-IL1 for covering the bridging pattern CP2 is disposed on the thin film encapsulation layer TFE. A contact hole CH for partially exposing the bridging pattern CP2 is defined in the first touch insulating layer TS-IL1. The contact hole CH can be formed through a photolithography process.

[0185] As Figure 8E shown, a second conductive pattern is disposed on the first touch insulating layer TS-IL1. The second conductive pattern may include a plurality of first touch sensor portions SP1 (see Figure 8B ), a plurality of first connection portions CP1, first touch signal lines SL1-1 to SL1-m, a plurality of second touch sensor portions SP2 (see Figure 8B ), and second touch signal lines SL2-1 to SL2-n. Although not shown in the figure, a second touch insulating layer TS-IL2 for covering the second conductive pattern is disposed on the first touch insulating layer TS-IL1.

[0186] The first conductive pattern may include first touch electrodes TE1-1 to TE1-m and first touch signal lines SL1-1 to SL1-m. The second conductive pattern may include second touch electrodes TE2-1 to TE2-n and second touch signal lines SL2-1 to SL2-n. In various exemplary embodiments, no contact hole CH is defined in the first touch insulating layer TS-IL1.

[0187] The first conductive pattern and the second conductive pattern may be interchanged. That is, the second conductive pattern may include the bridging pattern CP2.

[0188] As Figure 8F shown, the first touch sensor portion SP1 is superimposed on the non-light emitting region NPXA. The first touch sensor portion SP1 includes a plurality of first extension portions SP1-A extending in a fifth direction DR5 intersecting the first direction DR1 and the second direction DR2, and a plurality of second extension portions SP1-B extending in a sixth direction DR6 intersecting the fifth direction DR5. The plurality of first extension portions SP1-A and the plurality of second extension portions SP1-B may be defined by grid lines. The line width of the grid lines may be several micrometers.

[0189] The plurality of first extension portions SP1-A and the plurality of second extension portions SP1-B are connected to each other to form a plurality of touch openings TS-OP. That is, the first touch sensor portion SP1 has a grid form including a plurality of touch openings TS-OP. Although the touch openings TS-OP are shown to correspond to the light emitting regions PXA in a one-to-one relationship, other embodiments have other ratios of the corresponding relationship therebetween. Therefore, in various exemplary embodiments, one touch opening TS-OP may correspond to two or more light emitting regions PXA.

[0190] The size of the light-emitting region PXA may also vary. For example, the size of the light-emitting region PXA for providing blue light and the size of the light-emitting region PXA for providing red light in the light-emitting region PXA may vary. Accordingly, the size of the touch opening TS-OP may also vary. Although Figure 8F shows a variation in the size of the light-emitting region PXA, the inventive concept is not limited thereto. The sizes of the light-emitting regions PXA may be the same as each other, and the sizes of the touch openings TS-OP may also be the same as each other.

[0191] Referring to Figure 9A and Figure 9B , a touch signal line TSL is shown. For example, the touch signal line TSL may be Figure 8B the first touch signal lines SL1-1 to SL1-m shown in

[0192] A conductive part EP may be disposed between the touch signal line TSL and the plurality of clock signal lines CL1, CL2, CL3, and CL4 (collectively referred to as CL hereinafter). The conductive part EP may be formed as a layer and may be disposed on the same layer as the second electrode CE. For example, the conductive part EP and the second electrode CE may both be disposed on the pixel defining layer PDL. The meaning of "disposed on the same layer (e.g., the pixel defining layer PDL)" does not necessarily mean disposed only on a plane of the same level or height. For example, in a case where a given layer has different levels or heights such that the layer is at different heights in the third direction DR3 in a cross-sectional view, other elements disposed "on" the layer may be disposed at different levels or heights in the third direction DR3 or may not be disposed at different levels or heights in the third direction DR3. "Disposed on..." refers to a relationship in which the layers touch each other and a relationship in which the layers are separated from each other by an intermediate element or an intermediate layer.

[0193] The second electrode CE may extend toward the conductive part EP, and the second electrode CE and the conductive part EP may be connected to each other. That is, the second electrode CE and the conductive part EP may be formed through the same process.

[0194] The conductive part EP may be electrically connected to a power supply line E-VSS. The conductive part EP may receive a second voltage ELVSS from the power supply line E-VSS (see Figure 6A ).

[0195] The conductive part EP may extend over all or part of the overlapping region OA and cover all or part of the overlapping region OA, where, as shown in the overlapping region OA in Figure 9B , the touch signal line TSL and the clock signal line CL overlap in the vertical direction in the overlapping region OA. For example, as shown in Figure 9BAs shown, the conductive portion EP can completely cover (cross) the overlapping region OA such that the conductive portion EP is located between the clock signal line CL and the touch signal line TSL at all vertically overlapping portions of the clock signal line CL and the touch signal line TSL. This vertical direction may also be referred to as the overlapping direction (represented by the third direction DR3 in Figure 9A and Figure 9B ). The conductive portion EP can guide the electrical signal laterally away from the touch signal line TSL, thereby reducing or preventing noise caused by the clock signal applied to the clock signal line CL from reaching the touch signal line TSL. Thus, the conductive portion EP can in turn reduce or prevent a change in touch sensitivity that would otherwise be caused by noise from the clock signal line CL.

[0196] The first dam portion DM1 and the second dam portion DM2 can be provided in the non-display area NDA. The first dam portion DM1 and the second dam portion DM2 can be provided around the display area DA such that when printing the organic monomer to form the organic film OL1 of the thin film sealing layer TFE, the first dam portion DM1 and the second dam portion DM2 can prevent the organic monomer from overflowing outside the non-display area NDA provided with the first dam portion DM1 and the second dam portion DM2 and surrounding the display area DA.

[0197] The first dam portion DM1 can be provided on the power supply line E-VSS. The first dam portion DM1 can be formed of a single layer and can be formed simultaneously with the pixel defining layer PDL.

[0198] The second dam portion DM2 can be provided outside the first dam portion DM1. Thus, the distance between the second dam portion DM2 and the display area DA can be greater than the distance between the first dam portion DM1 and the display area DA.

[0199] The second dam portion DM2 can cover a part of the power supply line E-VSS. The second dam portion DM2 can be formed of multiple layers and include a first dam layer DM2-1 and a second dam layer DM2-2. The first dam layer DM2-1 can be formed simultaneously with the third insulating layer 30; and, the second dam layer DM2-2 can be formed simultaneously with the pixel defining layer PDL.

[0200] Although Figure 9AIt is shown that the pixel defining layer PDL extends in the third direction DR3 to overlap with all the clock signal lines CL. However, in other embodiments, the pixel defining layer PDL does not overlap with all the clock signal lines CL or does not completely overlap with the clock signal lines CL. Therefore, in various exemplary embodiments, the pixel defining layer PDL may extend only to the area overlapping with the gate driving circuit GDC, and / or may extend to the area overlapping with only some of the clock signal lines CL. For example, the pixel defining layer PDL may extend only to the area overlapping with the third clock signal line CL3, the fourth clock signal line CL4, the third voltage line VL2, the fourth voltage line VH2, and the second start signal line EF2.

[0201] Referring to Figure 9C , the conductive portion EP-1 may be disposed between the touch signal line TSL and the plurality of clock signal lines CL (see Figure 9B ). The conductive portion EP-1 may be disposed on the same layer as the second electrode CE. For example, both the conductive portion EP-1 and the second electrode CE may be disposed on the pixel defining layer PDL.

[0202] The conductive portion EP-1 may be separated from the second electrode CE. That is, the conductive portion EP-1 and the second electrode CE may not be physically connected to each other. The conductive portion EP-1 may be electrically connected to the power supply line E-VSS. The conductive portion EP-1 may receive the second voltage ELVSS from the power supply line E-VSS (see Figure 6A ). In other embodiments, a constant voltage may be applied to the conductive portion EP-1. For example, the first voltage ELVDD (see Figure 6A ) may be applied to the conductive portion EP-1, or the ground voltage may be applied to the conductive portion EP-1, or another constant voltage other than the voltages listed above may be applied to the conductive portion EP-1.

[0203] The second electrode CE may be electrically connected to the power supply line E-VSS through a pattern (not shown). Therefore, the second electrode CE may receive the second voltage ELVSS from the power supply line E-VSS (see Figure 6A ).

[0204] The conductive portion EP-1 may reduce or prevent the change in the touch sensitivity of the touch detection unit caused by the noise generated by the signal applied to the clock signal line CL.

[0205] Referring to Figure 9D , the conductive portion EP-2 may be disposed between the touch signal line TSL and the plurality of clock signal lines CL (see Figure 9B ). The conductive portion EP-2 may be disposed on the same layer as the second electrode CE.

[0206] A plurality of through-holes HL may be defined in the conductive part EP-2. The plurality of through-holes HL may be used to discharge gas emerging from a layer including an organic layer. The plurality of through-holes HL may not overlap with the overlapping region OA (see Figure 9B ), where the touch signal line TSL and the clock signal line CL overlap in the overlapping region OA. In Figure 9D , the through-hole HL is not defined in a region overlapping with the clock signal line CL (see Figure 9B ) in the third direction DR3. According to another embodiment of the inventive concept, the through-hole HL may not be defined in a region overlapping with the touch signal line TSL in the third direction DR3.

[0207] Since the through-hole HL is not defined in the overlapping region OA (see Figure 9B ), even if the through-hole HL is provided in the conductive part EP-2, it is possible to prevent the touch sensitivity of the touch detection unit from changing in response to noise caused by a signal applied to the clock signal line CL, although through-holes exist in other positions.

[0208] Referring to Figure 10A and Figure 10B , the conductive part EP-3 may be provided between the touch signal line TSL and the plurality of clock signal lines CL. The conductive part EP-3 may be provided on the same layer as the first electrode AE. For example, the conductive part EP-3 and the first electrode AE may both be provided on the third insulating layer 30. The first electrode AE and the conductive part EP-3 may be formed by the same process.

[0209] The conductive part EP-3 may be electrically connected to the power supply line E-VSS. The conductive part EP-3 may receive the second voltage ELVSS from the power supply line E-VSS (see Figure 6A ). Alternatively, a constant voltage may be applied to the conductive part EP-3. For example, the first voltage ELVDD (see Figure 6A ) may be applied to the conductive part EP-3, or the ground voltage may be applied to the conductive part EP-3, or another constant voltage other than the voltages listed above may be applied to the conductive part EP-3.

[0210] A plurality of through-holes HL-1 may be defined in the conductive part EP-3. The plurality of through-holes HL-1 may be used to discharge gas emerging from a layer including an organic layer. The plurality of through-holes HL-1 may not overlap with the overlapping region OA, where the touch signal line TSL and the clock signal line CL overlap in the third direction DR3 in the overlapping region OA. More specifically, referring to Figure 10A, the through hole HL-1 may not be defined in the region overlapping the clock signal line CL in the third direction. Therefore, the conductive portion EP-3 may completely cover the overlapping region OA, where the touch signal line TSL and the clock signal line CL overlap in the third direction DR3 in the overlapping region OA. The conductive portion EP-3 may prevent noise generated by the signal applied to the clock signal line CL on the touch signal line TSL. That is, the presence of the conductive portion EP-3 may reduce or even eliminate the change in touch sensitivity, thereby providing a touch detection unit with uniform touch sensitivity.

[0211] Now refer to Figure 10C and Figure 10D , the conductive portion EP-4 may be disposed between the touch signal line TSL and the plurality of clock signal lines CL. A plurality of through holes HL-2 may be defined in the conductive portion EP-4.

[0212] The through hole HL-2 may not overlap with the overlapping region OA, where the touch signal line TSL and the clock signal line CL overlap in the third direction DR3 in the overlapping region OA. More specifically, referring to Figure 10C , the through hole HL-2 may not be defined in the region overlapping the touch signal line TSL in the third direction DR3.

[0213] The conductive portion EP-4 under the touch signal line TSL may block the interference of the signal applied to the clock signal line CL with the signal passing through the touch signal line TSL. That is, since the through hole HL-2 is not defined in the region overlapping the touch signal line TSL, noise caused by the signal of each clock signal line CL will not be generated in the touch signal line TSL.

[0214] Refer to Figure 11A and Figure 11B , the conductive portion EP-5 may be disposed between the touch signal line TSL and the plurality of clock signal lines CL. The conductive portion EP-5 may include a first conductive layer EP-L1 and a second conductive layer EP-L2. The first conductive layer EP-L1 may be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2 may be disposed on the same layer as the second electrode CE. For example, the first conductive layer EP-L1 and the first electrode AE may be disposed on the third insulating layer 30, and the second conductive layer EP-L2 and the second electrode CE may be disposed on the pixel defining layer PDL. The first conductive layer EP-L1 and the first electrode AE may be formed by the same process, and the second conductive layer EP-L2 and the second electrode CE may be formed by the same process.

[0215] Each of the first conductive layer EP-L1 and the second conductive layer EP-L2 can be electrically connected to the power supply line E-VSS. Each of the first conductive layer EP-L1 and the second conductive layer EP-L2 can receive a second voltage ELVSS from the power supply line E-VSS (see Figure 6A ). Optionally, a constant voltage can be applied to the second conductive layer EP-L2. For example, a first voltage ELVDD (see Figure 6A ) can be applied to the second conductive layer EP-L2, or a ground voltage can be applied to the second conductive layer EP-L2, or another constant voltage other than the voltages listed above can be applied to the second conductive layer EP-L2.

[0216] A plurality of first vias HL-3 can be defined in the first conductive layer EP-L1. The plurality of first vias HL-3 can be used to discharge gases emerging from a layer including an organic layer. Although Figure 11A shows that the plurality of first vias HL-3 can be spaced apart from each other at a predetermined pitch, in other embodiments, the spacing therebetween is not constant.

[0217] The second conductive layer EP-L2 can cover all of the plurality of first vias HL-3 such that they are stacked in the third direction DR3. According to this embodiment, a double shield can be provided between the touch signal line TSL and the plurality of clock signal lines CL by the first conductive layer EP-L1 and the second conductive layer EP-L2. In addition, since the second conductive layer EP-L2 covers the plurality of first vias HL-3 in the third direction DR3, the regions not shielded by the plurality of first vias HL-3 in the third direction DR3 can also be shielded. Therefore, even if high and low levels of a voltage are alternately applied to the plurality of clock signal lines CL, the signals applied to the plurality of clock signal lines CL are blocked by the first conductive layer EP-L1 and the second conductive layer EP-L2 so that no noise is generated on the touch signal line TSL.

[0218] Now referring to Figure 11C , a conductive portion EP-6 can be provided between the touch signal line TSL and the plurality of clock signal lines CL. The conductive portion EP-6 can include a first conductive layer EP-L1 and a second conductive layer EP-L2a. When compared with the conductive portion EP-5 described above with reference to Figure 11A , Figure 11C the conductive portion EP-6 of

[0219] Referring to Figure 11A , the second electrode CE can extend toward the second conductive layer EP-L2, and the second electrode CE and the second conductive layer EP-L2 can be physically connected to each other. However, referring to Figure 11C , the second conductive layer EP-L2a can be separated from the second electrode CE. That is, as shown inFigure 11C In this case, the conductive portion EP-1 and the second electrode CE may not be physically connected to each other.

[0220] Now referring to Figure 12A , the conductive portion EP-6a may be disposed between the touch signal line TSL and the plurality of clock signal lines CL. The conductive portion EP-6a may include a first conductive layer EP-L1a and a second conductive layer EP-L2. The first conductive layer EP-L1a may be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2 may be disposed on the same layer as the second electrode CE. For example, the first conductive layer EP-L1a and the first electrode AE may be disposed on the third insulating layer 30, and the second conductive layer EP-L2 and the second electrode CE may be disposed on the pixel defining layer PDL. The first conductive layer EP-L1a and the first electrode AE may be formed by the same process, and the second conductive layer EP-L2 and the second electrode CE may be formed by the same process.

[0221] A plurality of first vias HL-4 may be defined in the first conductive layer EP-L1a. The plurality of first vias HL-4 may be used to discharge gas emerging from a layer including an organic layer. The plurality of first vias HL-4 may not be defined in a region overlapping the clock signal line CL in the third direction DR3.

[0222] Figure 12B The third clock signal line CL3, the fourth clock signal line CL4, the third voltage line VL2, the fourth voltage line VH2, and the second start signal line EF2 are shown. The plurality of first vias HL-4 may not be defined in a region overlapping the third clock signal line CL3 and the fourth clock signal line CL4.

[0223] When displaying a frame of an image, a signal whose level continuously changes may be applied to the third clock signal line CL3 and the fourth clock signal line CL4. Therefore, if the upper portions of the third clock signal line CL3 and the fourth clock signal line CL4 are not shielded, the signal may cause noise to appear on the touch signal line TSL. However, referring back to Figure 12A , since the plurality of first vias HL-4 are not defined in a portion of the first conductive layer EP-L1a that overlaps the third clock signal line CL3 and the fourth clock signal line CL4 in the third direction DR3, the upper portions of the third clock signal line CL3 and the fourth clock signal line CL4 are completely shielded. Therefore, the signal applied to the third clock signal line CL3 and the fourth clock signal line CL4 does not cause noise on the touch signal line TSL.

[0224] The first conductive layer EP-L1a may include a first region AR1, a second region AR2, and a third region AR3. The first region AR1, the second region AR2, and the third region AR3 are shown in Figure 12B .

[0225] The first region AR1 can be a region that overlaps with the clock signal line CL and does not define a plurality of first vias HL-4. Figure 12B The first region AR1 overlapping with the third clock signal line CL3 and the fourth clock signal line CL4 is shown. The second region AR2 is a region in which a plurality of first vias HL-4 and HL-4a are defined, and can be a region where the portion exposed through the plurality of first vias HL-4 and HL-4a has a first region density. The third region AR3 is a region in which a plurality of first vias HL-4 are defined, and can be a region where the portion exposed through the plurality of first vias HL-4 has a second region density. The second region density can be lower than the first region density. The exposed region can be the third insulating layer 30. For example, the number of the first vias HL-4 and HL-4a defined in each first surface area SA1 of the second region AR2 can be two, and the number of the first vias HL-4 defined in each first surface area SA1 of the third region AR3 can be one.

[0226] Since a plurality of first vias HL-4 are not defined in the first region AR1 overlapping with the third clock signal line CL3 and the fourth clock signal line CL4, in order to compensate for this, a plurality of first vias HL-4a can also be defined in the second region AR2.

[0227] The form of the hole HLa is indicated by the dashed line in the first region AR1. This is only for convenience of description and does not mean that the hole HLa is defined in the first region AR1. On the contrary, the dashed line indicates the theoretical position where the hole HLa should be located, but it is not actually defined. If the plurality of first vias HL-4 are arranged at uniform intervals, the hole HLa should be located in the first region AR1 as indicated by the dashed line. However, in reality, no hole is defined in the first region AR1. Therefore, the design condition that the layer below the first conductive layer EP-L1a (for example, the third insulating layer 30) should be exposed by the first vias HL-4 in the first conductive layer EP-L1a more than a predetermined area may not be satisfied. As a result, the gas emerging from the layer including the organic material may not be discharged smoothly. To prevent this, first vias HL-4a can be additionally defined in the second region AR2 corresponding to the number of the holes HLa not defined in the first region AR1. Therefore, even if the holes indicated by the dashed line are omitted in the first region AR1, the design condition that the layer below the first conductive layer EP-L1a (for example, the third insulating layer 30) should be exposed by the first vias HL-4 in the first conductive layer EP-L1a more than a predetermined area can be satisfied. To help understand this concept, an arrow is shown between the virtual hole HLa and the first via HL-4a to show the hole movement relationship of the movement of the hole HLa. The arrow is not an actual component of the device. On the contrary, the arrow is shown to help with conceptual understanding.

[0228] Reference Figure 12C , since the hole HLa should be in the first region AR1, but no hole is defined in the first region AR1, so to compensate for this, in Figure 12C the exemplary embodiment of, the size of the first through hole HL-4b provided in the second region AR2 is enlarged.

[0229] Since the exposed area of the third insulating layer 30 (see Figure 12A ) under the first through hole HL-4b becomes larger, the enlargement of the size of the first through hole HL-4b has the same effect as described above. As a result, even though the through hole HLa in the first region AR1 is omitted, the design condition that the first through hole HL-4 should have a larger area than a predetermined area on the conductive part EP-6 (see Figure 12A ) can still be satisfied.

[0230] Although in Figure 12C the exemplary embodiment shown, the width of the first through hole HL-4 is enlarged in the vertical direction for the first through hole HL-4b, but the present invention is not limited thereto. For example, with respect to the first through hole HL-4b, the width of the first through hole HL-4 can be enlarged in the horizontal direction or the width can be enlarged in both the horizontal and vertical directions.

[0231] Reference Figure 13A , the conductive part EP-7 can be provided between the touch signal line TSL and the plurality of clock signal lines CL. The conductive part EP-7 can include a first conductive layer EP-L1b and a second conductive layer EP-L2. The first conductive layer EP-L1b can be provided on the same layer as the first electrode AE, and the second conductive layer EP-L2 can be provided on the same layer as the second electrode CE. For example, the first conductive layer EP-L1b and the first electrode AE can be provided on the third insulating layer 30, and the second conductive layer EP-L2 and the second electrode CE can be provided on the pixel defining layer PDL. The first conductive layer EP-L1b and the first electrode AE can be formed by the same process, and the second conductive layer EP-L2 and the second electrode CE can be formed by the same process.

[0232] A plurality of first through holes HL-5 can be defined in the first conductive layer EP-L1b. The plurality of first through holes HL-5 can be used to discharge gas emerging from a layer including an organic layer. The plurality of first through holes HL-5 can not be defined in the region overlapping the touch signal line TSL in the third direction DR3.

[0233] In Figure 13B some touch signal lines TSL are exemplarily shown. The plurality of first through holes HL-5 can not be defined in the region overlapping the touch signal line TSL.

[0234] When multiple first vias HL-5 are not defined below the touch signal line TSL in the third direction DR3, the negative impact of the AC signal from the clock signal line CL applied below the touch signal line TSL in the third direction DR3 on the signal in the touch signal line TSL can be reduced. Therefore, noise is less likely to occur in the touch signal line TSL, and changes in touch sensitivity caused by noise can be reduced or prevented.

[0235] The first conductive layer EP-L1b may include a first region AR1, a second region AR2, and a third region AR3. In Figure 13B the first region AR1, the second region AR2, and the third region AR3 are shown.

[0236] The first region AR1 may be a region that overlaps with the touch signal line TSL and does not define multiple first vias HL-5. The second region AR2 may be a region in which multiple first vias HL-5 and HL-5a are defined, and may be a region in which the exposed portion through the multiple first vias HL-5 and HL-5a has a first region density. The third region AR3 may be a region in which multiple first vias HL-5 are defined, and may be a region in which the exposed portion through the multiple first vias HL-5 has a second region density. The second region density may be lower than the first region density. The exposed region may be the third insulating layer 30. The number of first vias HL-5 and HL-5a defined in each first surface area SA1 of the second region AR2 may be two, and the number of first vias HL-5 defined in each first surface area SA1 of the third region AR3 may be one.

[0237] Since multiple first vias HL-5 are not defined in the first region AR1 that overlaps with the touch signal line TSL, to compensate for this, multiple first vias HL-5a can also be defined in the second region AR2. For example, the form of the via HLa is represented by a dashed line in the first region AR1. This is only for ease of description and does not mean that the via HLa is actually defined in the first region AR1. When the multiple first vias HL-5 are arranged at uniform intervals, the via HLa should be located in the first region AR1 as shown by the dashed line; however, in reality, no via is defined in the first region AR1. Therefore, the design condition that the layer below the first conductive layer EP-L1b (e.g., the third insulating layer 30) is exposed by the first vias HL-5 in the first conductive layer EP-L1b more than a predetermined area is not satisfied. As a result, the gas emerging from the layer including the organic material may not be discharged smoothly. To prevent this, the first vias HL-5a omitted from the first region AR1 can be additionally defined in the second region AR2 corresponding to the number of vias HLa not defined in the first region AR1. Thus, the design condition that the layer below the first conductive layer EP-L1b (e.g., the third insulating layer 30) should be exposed by the first vias HL-5 in the first conductive layer EP-L1b more than a predetermined area can be satisfied.

[0238] Although Figure 13B not shown in Figure 12C it is similar, to compensate for the vias not defined in the first region AR1, instead of adding additional vias HL-5 in the second region AR2, the size of the first vias HL-5 in the second region AR2 can be increased as described above in connection with Figure 12C or additional vias HL-5 can be added in the second region AR2 and the size of the first vias HL-5 in the second region AR2 can be increased as described above in connection with Figure 12C the description.

[0239] Now referring to Figure 14A , a conductive portion EP-8 can be provided between the touch signal line TSL and the multiple clock signal lines CL. The conductive portion EP-8 can include a first conductive layer EP-L1c and a second conductive layer EP-L2b. The first conductive layer EP-L1c can be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2b can be disposed on the same layer as the second electrode CE.

[0240] Multiple first vias HL-6 can be defined in the first conductive layer EP-L1c. The multiple first vias HL-6 can be used to discharge the gas emerging from the layer including the organic layer. Multiple second vias HL-7 can be defined in the second conductive layer EP-L2b. The multiple second vias HL-7 can be used for the gas emerging from the layer including the organic layer.

[0241] The first through hole HL-6 and the second through hole HL-7 may not overlap each other in the third direction DR3. Accordingly, the region where the first through hole HL-6 is formed may be covered by the second conductive layer EP-L2b in the third direction DR3, and the region where the second through hole HL-7 is formed may be covered by the first conductive layer EP-L1c in the third direction DR3. According to this embodiment, the overlapping region between the touch signal line TSL and the plurality of clock signal lines CL may be shielded by at least one of the first conductive layer EP-L1c and the second conductive layer EP-L2b. That is, the conductive portion EP-8 may reduce the change in touch sensitivity caused by noise appearing in the touch signal line TSL caused by the signal in the clock signal line CL.

[0242] Although Figure 14B it is shown in that a plurality of first through holes HL-6 and a plurality of second through holes HL-7 are arranged in the second direction DR2 and are alternately provided along the first direction DR1, the inventive concept is not limited thereto. In various exemplary embodiments, the plurality of first through holes HL-6 and the plurality of second through holes HL-7 do not overlap each other in the third direction DR3, and these through holes HL-6, HL-7 have various other arrangements. For example, the plurality of first through holes HL-6 and the plurality of second through holes HL-7 may be alternately provided in the first direction DR1 and the second direction DR2.

[0243] A display device constructed in accordance with the principles of the present invention includes a conductive portion for covering an overlapping region, wherein a plurality of clock signal lines and a plurality of touch signal lines overlap in the overlapping region. The conductive portion may reduce or prevent noise from appearing on the touch signal line due to a change in the level of the signal applied to the clock signal line. That is, the conductive portion may reduce or prevent the touch sensitivity of the touch detection unit from being affected by noise.

[0244] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to these embodiments, but rather to the broader scope of the claimed claims and various obvious modifications and equivalent arrangements.

Claims

1. A display device, the display device comprising: A display panel, including a substrate layer, a gate driving circuit, a plurality of clock signal lines electrically connected to the gate driving circuit, a plurality of voltage lines electrically connected to the gate driving circuit and located on the same layer as the plurality of clock signal lines, a plurality of pixels, a plurality of data lines electrically connected to the plurality of pixels, a plurality of gate lines electrically connected to the gate driving circuit, and a first shielding portion; And A touch sensing unit, disposed on the display panel, and including a touch sensing portion and a plurality of touch signal lines electrically connected to the touch sensing portion and disposed on the plurality of clock signal lines, Wherein, the first shielding portion is disposed between the plurality of clock signal lines and the plurality of touch signal lines, A plurality of first vias are defined in the first shielding portion, and The plurality of first vias do not overlap with the plurality of clock signal lines.

2. The display device according to claim 1, wherein, The first shielding portion includes: A first region, in which the plurality of first vias are not defined; A second region, including a region having holes with a first region density exposed by the plurality of first vias; and A third region, including a region exposed by the plurality of first vias with holes having a second region density lower than the first region density.

3. The display device according to claim 1, wherein, Each of the plurality of pixels includes a first electrode, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer, and The first shielding portion and any one of the first electrode and the second electrode are disposed on the same layer.

4. The display device according to claim 3, wherein, The display panel further includes a second shielding portion, the second shielding portion is disposed on a layer different from the layer where the first shielding portion is located and is disposed between the plurality of clock signal lines and the plurality of touch signal lines.

5. The display device according to claim 4, wherein, The first shielding portion and the first electrode are disposed on the same layer, and the second shielding portion and the second electrode are disposed on the same layer.

6. The display device according to claim 5, wherein, The plurality of first vias overlap with the second shielding portion in a plane.

7. The display device according to claim 5, wherein, A plurality of second vias are defined in the second shielding portion, and the plurality of second vias do not overlap with the plurality of first vias.

8. The display device according to claim 4, wherein, A voltage equal to the voltage applied to the second electrode is applied to each of the first shielding portion and the second shielding portion.

9. The display device according to claim 1, wherein, At least one of the plurality of first vias overlaps with the plurality of voltage lines.

10. The display device according to claim 1, wherein, The display panel further includes a thin film encapsulation layer covering the plurality of pixels, and the touch sensing unit is directly disposed on the thin film encapsulation layer.

11. The display device according to claim 1, wherein, The gate driving circuit includes a plurality of driving stages, and the plurality of clock signal lines provide clock signals to the plurality of driving stages.

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