Display panel, display device, testing method and crack detection method

Abstract

A display panel, a display device, a test method and a crack detection method. The display panel comprises: a substrate (10) including a display area (110) and a peripheral area (120); a plurality of sub-pixels (101) located in the display area (110); a plurality of data signal lines (102) located in the display area (110) and electrically connected to the plurality of sub-pixels (101); a plurality of signal transmission lines (202) located in the peripheral area (120) and electrically connected to the plurality of data signal lines (102); a plurality of multiplexers (240) located in the peripheral area (120); and a first test circuit (210) located on a side of the plurality of multiplexers (240) away from the plurality of sub-pixels (101). The first test circuit (210) comprises a plurality of test components (214), each of at least a portion of the plurality of test components (214) being electrically connected to at least two multiplexers (240). Each test component (214) includes a first test subcircuit (221), a second test subcircuit (222) and a third test subcircuit (223).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, a testing method and a crack detection method. Background Art

[0002] At present, multiplexers are gradually being applied to display screens. Their advantage is that they can reduce the number of data signal lines, thereby reducing costs. The multiplexer is usually located on the side of the test circuit away from the display area. In this way, when the test circuit performs a detection operation, the multiplexer is not enabled. When the display module is lit, the multiplexer can play the role of transmitting data signals. Summary of the invention

[0003] According to one aspect of an embodiment of the present disclosure, a display panel is provided, comprising: a substrate, comprising a display area and a peripheral area located at least on one side of the display area; a plurality of sub-pixels located on one side of the substrate and in the display area; a plurality of data signal lines located in the display area and electrically connected to the plurality of sub-pixels; a plurality of signal transmission lines located in the peripheral area and electrically connected to the plurality of data signal lines; a plurality of multiplexers located in the peripheral area and on a side of the plurality of signal transmission lines away from the plurality of sub-pixels, at least one of the plurality of multiplexers being electrically connected to at least two signal transmission lines, respectively; and a first test circuit located in the peripheral area and on a side of the plurality of multiplexers away from the plurality of sub-pixels, the first test circuit comprising a plurality of test components, each of at least a portion of the plurality of test components being electrically connected to at least two of the plurality of multiplexers, each of the test components comprising a first test sub-circuit, a second test sub-circuit and a third test sub-circuit, the second test sub-circuit being located between the first test sub-circuit and the third test sub-circuit, and the first test sub-circuit being located on a side of the second test sub-circuit away from the plurality of sub-pixels.

[0004] In some embodiments, the display panel further includes: an orthographic projection of the first test sub-circuit on the base substrate is centrally symmetrical.

[0005] In some embodiments, two adjacent multiplexers are electrically connected to one of the plurality of test components via two connecting wires.

[0006] In some embodiments, the plurality of multiplexers include a first multiplexer and a second multiplexer; the first test subcircuit includes: a first transistor, a first electrode of the first transistor is configured to receive a first data signal, a second electrode of the first transistor is electrically connected to an input terminal of the first multiplexer, and a control electrode of the first transistor is configured to receive a first test switch signal; and a second transistor, a first electrode of the second transistor is configured to receive a second data signal, a second electrode of the second transistor is electrically connected to the input terminal of the second multiplexer, and a control electrode of the second transistor is configured to receive a second test switch signal; the second test subcircuit includes: a third transistor, a first electrode of the third transistor is configured to receive a third data signal, a second electrode of the third transistor is electrically connected to the input terminal of the first multiplexer, and a control electrode of the third transistor is configured to receive a second test switch signal. The control electrode of the body tube is configured to receive a third test switch signal; and a fourth transistor, a first electrode of the fourth transistor is configured to receive a fourth data signal, a second electrode of the fourth transistor is electrically connected to the input terminal of the first multiplexer, and the control electrode of the fourth transistor is configured to receive the fourth test switch signal; and the third test subcircuit includes: a fifth transistor, a first electrode of the fifth transistor is configured to receive a fifth data signal, a second electrode of the fifth transistor is electrically connected to the input terminal of the second multiplexer, and the control electrode of the fifth transistor is configured to receive the fifth test switch signal; and a sixth transistor, a first electrode of the sixth transistor is configured to receive a sixth data signal, a second electrode of the sixth transistor is electrically connected to the input terminal of the second multiplexer, and the control electrode of the sixth transistor is configured to receive the sixth test switch signal.

[0007] In some embodiments, the display panel also includes: a first control line, electrically connected to the control electrode of the first transistor and the control electrode of the second transistor, respectively, and configured to transmit the first test switch signal and the second test switch signal, the first test switch signal being the same as the second test switch signal; a first data line, electrically connected to the first electrode of the first transistor, and configured to transmit a first data signal; and a second data line, electrically connected to the first electrode of the second transistor, and configured to transmit the second data signal; wherein the orthographic projection of the first control line on the substrate substrate is located between the orthographic projection of the first data line on the substrate substrate and the orthographic projection of the second data line on the substrate substrate.

[0008] In some embodiments, the two connecting wires include a first connecting wire and a second connecting wire; the second electrode of the first transistor is electrically connected to the first connecting wire, and the second electrode of the second transistor is electrically connected to the second connecting wire; the orthographic projection of the control electrode of the first transistor on the substrate substrate is located between the orthographic projection of the first electrode of the first transistor on the substrate substrate and the orthographic projection of the second electrode of the first transistor on the substrate substrate; the orthographic projection of the control electrode of the second transistor on the substrate substrate is located between the orthographic projection of the first electrode of the second transistor on the substrate substrate and the orthographic projection of the second electrode of the second transistor on the substrate substrate; the orthographic projection of the first electrode of the first transistor on the substrate substrate and the orthographic projection of the first electrode of the second transistor on the substrate substrate are located between the orthographic projection of the control electrode of the first transistor on the substrate substrate and the orthographic projection of the control electrode of the second transistor on the substrate substrate.

[0009] In some embodiments, the third transistor includes two first electrodes, one second electrode and two control electrodes, and the fourth transistor includes two first electrodes, one second electrode and two control electrodes; the display panel also includes: a second control line electrically connected to the two control electrodes of the third transistor and configured to transmit the third test switch signal; a third data line electrically connected to one of the two first electrodes of the third transistor and configured to transmit the third data signal; a fourth data line electrically connected to the other of the two first electrodes of the third transistor and configured to transmit the third data signal; a third control line electrically connected to the two control electrodes of the fourth transistor and configured to transmit the fourth test switch signal; a fifth data line electrically connected to one of the two first electrodes of the fourth transistor and configured to transmit the third data signal. connection, configured to transmit the fourth data signal; and a sixth data line, electrically connected to the other of the two first electrodes of the fourth transistor, configured to transmit the fourth data signal; wherein the orthographic projection of the second control line on the substrate substrate is located between the orthographic projection of the third control line on the substrate substrate and the orthographic projection of the sixth data line on the substrate substrate; the orthographic projection of the third control line on the substrate substrate is located between the orthographic projection of the second control line on the substrate substrate and the orthographic projection of the third data line on the substrate substrate; the orthographic projection of the third data line on the substrate substrate and the orthographic projection of the sixth data line on the substrate substrate are located between the orthographic projection of the third transistor on the substrate substrate and the orthographic projection of the fourth transistor on the substrate substrate.

[0010] In some embodiments, the second electrode of the third transistor and the second electrode of the fourth transistor are both electrically connected to the first connecting wire; the positive projection of one of the two control electrodes of the third transistor on the substrate substrate is located between the positive projection of one of the two first electrodes of the third transistor on the substrate substrate and the positive projection of the second electrode of the third transistor on the substrate substrate, and the positive projection of the other of the two control electrodes of the third transistor on the substrate substrate is located between the positive projection of the other of the two first electrodes of the third transistor on the substrate substrate and the positive projection of the second electrode of the third transistor on the substrate substrate; and the positive projection of one of the two control electrodes of the fourth transistor on the substrate substrate is located between the positive projection of one of the two first electrodes of the fourth transistor on the substrate substrate and the positive projection of the second electrode of the fourth transistor on the substrate substrate, and the positive projection of the other of the two control electrodes of the fourth transistor on the substrate substrate is located between the positive projection of the other of the two first electrodes of the fourth transistor on the substrate substrate and the positive projection of the second electrode of the fourth transistor on the substrate substrate.

[0011] In some embodiments, the fifth transistor includes two first electrodes, one second electrode and two control electrodes, and the sixth transistor includes two first electrodes, one second electrode and two control electrodes; the display panel also includes: a fourth control line electrically connected to the two control electrodes of the fifth transistor and configured to transmit the fifth test switch signal; a seventh data line electrically connected to one of the two first electrodes of the fifth transistor and configured to transmit the fifth data signal; and an eighth data line electrically connected to the other of the two first electrodes of the fifth transistor and configured to transmit the fifth data signal; a fifth control line electrically connected to the two control electrodes of the sixth transistor and configured to transmit the sixth test switch signal; a ninth data line electrically connected to one of the two first electrodes of the sixth transistor an orthographic projection of the fourth control line on the substrate substrate and between the orthographic projection of the fifth control line on the substrate substrate and the orthographic projection of the ninth data line on the substrate substrate; an orthographic projection of the fifth control line on the substrate substrate and between the orthographic projection of the fourth control line on the substrate substrate and the orthographic projection of the seventh data line on the substrate substrate; and an orthographic projection of the seventh data line on the substrate substrate and an orthographic projection of the ninth data line on the substrate substrate and between the orthographic projection of the fifth transistor on the substrate substrate and the orthographic projection of the sixth transistor on the substrate substrate.

[0012] In some embodiments, the second electrode of the fifth transistor and the second electrode of the sixth transistor are both electrically connected to the second connecting wire; the orthographic projection of one of the two control electrodes of the fifth transistor on the substrate substrate is located between the orthographic projection of one of the two first electrodes of the fifth transistor on the substrate substrate and the orthographic projection of the second electrode of the fifth transistor on the substrate substrate, and the orthographic projection of the other of the two control electrodes of the fifth transistor on the substrate substrate is located between the orthographic projection of the other of the two first electrodes of the fifth transistor on the substrate substrate and the orthographic projection of the second electrode of the fifth transistor on the substrate substrate; and the orthographic projection of one of the two control electrodes of the sixth transistor on the substrate substrate is located between the orthographic projection of one of the two first electrodes of the sixth transistor on the substrate substrate and the orthographic projection of the second electrode of the sixth transistor on the substrate substrate, and the orthographic projection of the other of the two control electrodes of the sixth transistor on the substrate substrate is located between the orthographic projection of the other of the two first electrodes of the sixth transistor on the substrate substrate and the orthographic projection of the second electrode of the sixth transistor on the substrate substrate.

[0013] In some embodiments, each multiplexer includes a seventh transistor and an eighth transistor, the seventh transistor and the eighth transistor share a first electrode, the first electrode serves as an input terminal of the multiplexer, the second electrode of the seventh transistor is electrically connected to one of the at least two signal transmission lines, the control electrode of the seventh transistor is configured to receive a first selection signal, the second electrode of the eighth transistor is electrically connected to the other of the at least two signal transmission lines, and the control electrode of the eighth transistor is configured to receive a second selection signal.

[0014] In some embodiments, at least one sub-pixel includes a ninth transistor and a capacitor; the ninth transistor includes: an active layer; a first insulating layer covering the active layer; a gate on the side of the first insulating layer away from the active layer; a second insulating layer covering the gate; an interlayer insulating layer on the side of the second insulating layer away from the gate; and a source and a drain on the side of the interlayer insulating layer away from the second insulating layer, wherein the source and the drain are electrically connected to the active layer, respectively; the capacitor includes: a first conductive layer in the same layer as the gate, wherein the second insulating layer also covers the first conductive layer; and a second conductive layer on the side of the second insulating layer away from the first conductive layer, wherein the interlayer insulating layer also covers the second conductive layer.

[0015] In some embodiments, the at least one sub-pixel also includes: a third insulating layer covering the source and the drain; a planarization layer on a side of the third insulating layer away from the source and the drain; an anode layer on a side of the planarization layer away from the third insulating layer, wherein the anode layer is electrically connected to the source or the drain; a pixel defining layer having an opening on a side of the planarization layer away from the third insulating layer, the opening exposing at least a portion of the anode layer; a functional layer at least within the opening and connected to the anode layer; and a cathode layer on a side of the functional layer away from the anode layer.

[0016] In some embodiments, the first connecting wire and the second conductive layer are in the same layer, and the second connecting wire and the gate are in the same layer; the first control line to the fifth control line, and the first data line to the tenth data line are all in the same layer as the source or the drain; the control electrodes of the first transistor to the sixth transistor are in the same layer as the gate, the active layer of the first transistor to the sixth transistor is in the same layer as the active layer of the ninth transistor, the first electrodes of the first transistor to the sixth transistor are all in the same layer as the source or the drain, and the second electrodes of the first transistor to the sixth transistor are in the same layer as the source or the drain.

[0017] In some embodiments, the display panel also includes: a second test circuit, including a plurality of tenth transistors, the plurality of tenth transistors being electrically connected to the plurality of multiplexers one by one; a first electrode of the tenth transistor being configured to receive a detection voltage signal, a second electrode of the tenth transistor being electrically connected to an input terminal of a corresponding multiplexer, and a control electrode of the tenth transistor being configured to receive a seventh test switch signal.

[0018] In some embodiments, the display panel also includes: a first signal access terminal group, located in the peripheral area, located on one side of the first test circuit in the extension direction along the boundary between the display area and the peripheral area, and electrically connected to the first test circuit; and a second signal access terminal group, located in the peripheral area, located on a side of the first test circuit away from the first signal access terminal group in the extension direction along the boundary between the display area and the peripheral area, and electrically connected to the first test circuit.

[0019] According to another aspect of the embodiments of the present disclosure, a display device is provided, including: the display panel as described above.

[0020] According to another aspect of an embodiment of the present disclosure, a testing method for a display panel as described above is provided, comprising: each test component transmits a data signal to a multiplexer electrically connected to the test component under the control of a test switch signal; and the multiplexer transmits the data signal to a corresponding sub-pixel under the control of a selection signal.

[0021] According to another aspect of an embodiment of the present disclosure, there is provided a crack detection method for a display panel as described above, comprising: providing the detection voltage signal and the seventh test switch signal to each tenth transistor; providing the first selection signal to the seventh transistor, and providing the second selection signal to the eighth transistor; and determining that a crack exists in the display panel when the display panel displays a bright line.

[0022] In some embodiments, the step of determining whether the display panel has a crack includes: when the first selection signal and the second selection signal cause the seventh transistor and the eighth transistor to be alternately turned on, if the display panel displays a white bright line, it is determined that the display panel has a crack; when the first selection signal causes the seventh transistor to be turned off and the second selection signal causes the eighth transistor to be turned on, if the display panel displays a green bright line, it is determined that the display panel has a crack; or when the first selection signal causes the seventh transistor to be turned on and the second selection signal causes the eighth transistor to be turned off, if the display panel displays a magenta bright line, it is determined that the display panel has a crack.

[0023] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0025] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0026] Figure 1A is a schematic top view showing a display panel according to an embodiment of the present disclosure;

[0027] Figure 1B is a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure;

[0028] Figure 2 is a top view showing a layout of a first test circuit according to one embodiment of the present disclosure;

[0029] Figure 3 is a circuit connection diagram showing a first test circuit and a multiplexer according to an embodiment of the present disclosure;

[0030] Figure 4 is a timing diagram showing switching signals according to some embodiments of the present disclosure;

[0031] Figure 5 is a diagram showing an embodiment of the present disclosure Figure 2 An enlarged schematic diagram of the first test sub-circuit 221 in FIG.

[0032] Figure 6 is a diagram showing an embodiment of the present disclosure Figure 2 An enlarged schematic diagram of the second test sub-circuit 222 in FIG.

[0033] Figure 7 is a diagram showing an embodiment of the present disclosure Figure 2 An enlarged schematic diagram of the third test sub-circuit 223 in FIG.

[0034] Figure 8 is a cross-sectional schematic diagram showing a sub-pixel according to an embodiment of the present disclosure;

[0035] Fig. 9 The first test sub-circuit according to one embodiment of the present disclosure is shown as follows Figure 5 A cross-sectional view of the structure taken along line AA' in FIG.

[0036] Fig.10 The second test sub-circuit according to one embodiment of the present disclosure is shown as follows Figure 6 A cross-sectional view of the structure taken along line BB' in FIG.

[0037] Fig.11 The third test sub-circuit according to one embodiment of the present disclosure is shown as follows Figure 7 A cross-sectional view of the structure taken along line CC' in FIG.

[0038] Fig.12 is a schematic diagram showing a layout of a multiplexer according to an embodiment of the present disclosure;

[0039] Fig.13 is a top view showing the layout of a first test circuit and a second test circuit according to one embodiment of the present disclosure;

[0040] Fig.14 is a circuit connection diagram showing a second test circuit according to one embodiment of the present disclosure;

[0041] Fig.15 is a schematic diagram showing the detection principle of a second test circuit according to an embodiment of the present disclosure;

[0042] Fig.16 is a top view schematic diagram showing the layout of a second test circuit according to an embodiment of the present disclosure;

[0043] Fig.17 is a flow chart showing a method for testing a display panel according to an embodiment of the present disclosure;

[0044] Fig.18 is a flow chart showing a crack detection method for a display panel according to an embodiment of the present disclosure.

[0045] It should be understood that the size of each part shown in the accompanying drawings is not necessarily drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0046] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0047] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprise" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0048] In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be an intermediate device between the specific device and the first device or the second device. When a specific device is described as being connected to other devices, the specific device may be directly connected to the other device without an intermediate device, or may not be directly connected to the other device but have an intermediate device.

[0049] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0050] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0051] The inventors of the present disclosure have found that in the related art, the multiplexer is usually located on a side of the test circuit away from the display area, and the multiplexer is in the same plane as the integrated circuit. During the process of lighting the display module, the multiplexer needs to be switched frequently. For example, the multiplexer needs to be switched once within a time such as 4.17 microseconds or 5.3 microseconds. The high-frequency switching of the multiplexer will generate electromagnetic radiation in space. Since the multiplexer is close to the integrated circuit, the electromagnetic radiation generated by the multiplexer due to the high-frequency switching will cause electromagnetic interference problems to the integrated circuit, thereby affecting the operation of the integrated circuit.

[0052] In view of this, an embodiment of the present disclosure provides a display panel to reduce the electromagnetic interference problem between a multiplexer and an integrated circuit.

[0053] Figure 1A is a schematic top view of a display panel according to an embodiment of the present disclosure. Figure 2 FIG. 1 is a top view showing a layout of a first test circuit according to an embodiment of the present disclosure.

[0054] like Figure 1A As shown, the display panel includes: a base substrate 10, a plurality of sub-pixels 101, a plurality of data signal lines 102, a plurality of signal transmission lines 202, a plurality of multiplexers 240 and a first test circuit 210. The base substrate 10 includes a display area 110 and a peripheral area 120 located at least on one side of the display area 110. The plurality of sub-pixels 101 are located on one side of the base substrate and located in the display area 110. The plurality of data signal lines 102 are located in the display area 110 and are electrically connected to the plurality of sub-pixels 101. For example, the plurality of data signal lines 102 are electrically connected to the plurality of columns of sub-pixels 101 in a one-to-one correspondence. The plurality of signal transmission lines 202 are located in the peripheral area 120 and are electrically connected to the plurality of data signal lines 102. For example, the plurality of signal transmission lines 202 are electrically connected to the plurality of data signal lines 102 in a one-to-one correspondence.

[0055] The multiplexers 240 are located in the peripheral area and on a side of the signal transmission lines 202 away from the sub-pixels 101. At least one of the multiplexers 240 is electrically connected to at least two signal transmission lines 202, respectively.

[0056] like Figure 1A As shown, the first test circuit 210 is located in the peripheral area 120 and is located on a side of the multiple multiplexers 240 away from the multiple sub-pixels 101. The first test circuit 210 includes a plurality of test components (e.g., may be referred to as first test components) 214. Each test component in at least a portion of the plurality of test components 214 is electrically connected to at least two of the multiple multiplexers 240. For example, two adjacent multiplexers are electrically connected to one of the multiple test components through two connecting wires 201.

[0057] like Figure 2 As shown, each test component 214 includes a first test subcircuit 221, a second test subcircuit 222, and a third test subcircuit 223. The second test subcircuit 222 is located between the first test subcircuit 221 and the third test subcircuit 223. The first test subcircuit 221 is located on a side of the second test subcircuit 222 away from the plurality of sub-pixels. Figure 2 As shown, the orthographic projection of the first test sub-circuit 221 on the substrate is centrally symmetrical.

[0058] So far, a display panel according to some embodiments of the present disclosure is provided. In the display panel, the multiple multiplexers are arranged between the first test circuit and the multiple sub-pixels (or display areas). In this way, after the display panel is bent, the multiplexer and the integrated circuit are in different planes, which can reduce the electromagnetic interference problem between the multiplexer and the integrated circuit. Furthermore, in this embodiment, the structure of the first test circuit is also provided. That is, the first test circuit includes a plurality of test components. Each test component in at least a portion of the multiple test components is electrically connected to at least two of the multiple multiplexers. Each test component includes a first test subcircuit, a second test subcircuit and a third test subcircuit. The second test subcircuit is located between the first test subcircuit and the third test subcircuit. The first test subcircuit is located on the side of the second test subcircuit away from the multiple sub-pixels.

[0059] In some embodiments, Figure 1AAs shown, the display panel may further include a first signal access terminal group 301 and a second signal access terminal group 302. The first signal access terminal group 301 is located in the peripheral area 120. The first signal access terminal group 301 is located on one side of the first test circuit 210 along the extension direction of the boundary between the display area and the peripheral area. The first signal access terminal group 301 is electrically connected to the first test circuit 210, for example, through a lead. The first signal access terminal group 301 is configured to transmit a test switch signal and a data signal to the first test circuit 210. The second signal access terminal group 302 is located in the peripheral area 120. The second signal access terminal group 302 is located on one side of the first test circuit 210 away from the first signal access terminal group 301 along the extension direction of the boundary between the display area and the peripheral area. The second signal access terminal group 302 is electrically connected to the first test circuit 210, for example, through a lead. The second signal access terminal group 302 is configured to transmit a test switch signal and a data signal to the first test circuit 210. In this way, the control of the first test circuit can be achieved.

[0060] In some embodiments, Figure 1A As shown, the display panel may further include a plurality of connection pad areas 410, such as pad areas. The plurality of connection pad areas 410 are electrically connected to a plurality of data transmission lines. Each connection pad area is configured to transmit a driving signal, such as a data signal, to a plurality of sub-pixels.

[0061] In some embodiments, every two multiplexers can be electrically connected to one test component 214 via two connecting wires 201. Figure 2 As shown, the two connecting wires 201 may include a first connecting wire 2011 and a second connecting wire 2012. Figure 2 As shown, the multiple multiplexers 240 may include a first multiplexer 241 and a second multiplexer 242. The first multiplexer 241 is electrically connected to the test component 214 via a first connecting wire 2011, and the second multiplexer 242 is electrically connected to the test component 214 via a second connecting wire 2012. In this case, each test component 214 may be electrically connected to at least four signal transmission lines 202.

[0062] Figure 1B is a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure. Figure 1B In addition to the base substrate 10, the sub-pixel 101, the signal transmission line 202, the multiplexer 240, the first test circuit 210 and the connection pad area 410, the bending area 250 is also shown. Figure 1BIt can be seen that after the display panel is bent, the multiplexer 240 and the connection pad area 410 are in different planes. The connection pad area 410 can be electrically connected to the integrated circuit. Therefore, the above design can reduce the electromagnetic interference problem between the multiplexer and the integrated circuit.

[0063] In some embodiments, Figure 2 As shown, the first multiplexer 241 is electrically connected to two columns of sub-pixels. The second multiplexer 242 is electrically connected to the other two columns of sub-pixels. Figure 2 As shown, in the two columns of sub-pixels electrically connected to each multiplexer, one column of sub-pixels is sub-pixels in which red sub-pixels R and blue sub-pixels B are alternately arranged, and the other column of sub-pixels is all green sub-pixels G.

[0064] Figure 3 is a circuit connection diagram showing a first test circuit and a multiplexer according to an embodiment of the present disclosure.

[0065] like Figure 3 As shown, the first test sub-circuit 221 includes a first transistor T1 and a second transistor T2. The first electrode of the first transistor T1 is configured to receive the first data signal S CTD1 The second electrode of the first transistor T1 is electrically connected to the input terminal of the first multiplexer 241. The control electrode of the first transistor T1 is configured to receive the first test switch signal S CTSW1 The first electrode of the second transistor T2 is configured to receive the second data signal S CTD2 The second electrode of the second transistor T2 is electrically connected to the input terminal of the second multiplexer 242. The control electrode of the second transistor T2 is configured to receive the second test switch signal S CTSW2 .

[0066] like Figure 3 As shown, the second test sub-circuit 222 includes a third transistor T3 and a fourth transistor T4. A first electrode of the third transistor T3 is configured to receive a third data signal S CTD3 The second electrode of the third transistor T3 is electrically connected to the input terminal of the first multiplexer 241. The control electrode of the third transistor T3 is configured to receive the third test switch signal S CTSW3 The first electrode of the fourth transistor T4 is configured to receive the fourth data signal S CTD4 The second electrode of the fourth transistor T4 is electrically connected to the input terminal of the first multiplexer 241. The control electrode of the fourth transistor T4 is configured to receive the fourth test switch signal S CTSW4 .

[0067] The third test sub-circuit 223 includes a fifth transistor T5 and a sixth transistor T6. A first electrode of the fifth transistor T5 is configured to receive a fifth data signal SCTD5 The second electrode of the fifth transistor T5 is electrically connected to the input terminal of the second multiplexer 242. The control electrode of the fifth transistor T5 is configured to receive the fifth test switch signal S CTSW5 The first electrode of the sixth transistor T6 is configured to receive the sixth data signal S CTD6 The second electrode of the sixth transistor T6 is electrically connected to the input terminal of the second multiplexer 242. The control electrode of the sixth transistor T6 is configured to receive the sixth test switch signal S CTSW6 .

[0068] In some embodiments, the fifth test switch signal S CTSW5 With the third test switch signal S CTSW3 The same, the sixth test switch signal S CTSW6 With the fourth test switch signal S CTSW4 same.

[0069] like Figure 3 As shown, each multiplexer includes a seventh transistor and an eighth transistor. For example, the first multiplexer 241 includes a seventh transistor T7 and an eighth transistor T8, and the second multiplexer 242 includes a seventh transistor T7' and an eighth transistor T8'.

[0070] The following description takes the first multiplexer 241 as an example. The seventh transistor T7 and the eighth transistor T8 share a first electrode, which serves as the input terminal of the multiplexer. The second electrode of the seventh transistor T7 is electrically connected to one of the at least two signal transmission lines. For example, the one signal transmission line is electrically connected to a sub-pixel column in which red sub-pixels R and blue sub-pixels B are alternately arranged. The control electrode of the seventh transistor T7 is configured to receive a first selection signal S MUX1 The second electrode of the eighth transistor T8 is electrically connected to another of the at least two signal transmission lines. For example, the other signal transmission line is electrically connected to the green sub-pixel column G. The control electrode of the eighth transistor T8 is configured to receive the second selection signal S MUX2 .

[0071] In some embodiments, Figure 3 As shown, the first transistor to the eighth transistor are all PMOS (positive channel Metal Oxide Semiconductor) transistors. Of course, the scope of the embodiment of the present disclosure is not limited to this. For example, the first transistor to the eighth transistor may also be NMOS (Negative channel Metal Oxide Semiconductor) transistors.

[0072] In the embodiments of the present disclosure, the various test switch signals, the various data signals and the various selection signals can be used to control the various test sub-circuits and the multiplexers, thereby realizing a display test on the display panel.

[0073] Figure 4 is a timing diagram showing a switching signal according to some embodiments of the present disclosure. Figure 3 and Figure 4 A testing process for a display panel according to some embodiments of the present disclosure is described in detail.

[0074] It should be noted that the GCK signal and the GCB signal are clock control signals of the gate drive circuit. The GCK signal, the GCB signal and other signals are input into the gate drive circuit, so that the gate drive circuit outputs a gate control signal Gout(i) or Gout(i+1), where i is a positive integer. In this way, the gate drive circuit drives the pixel drive circuit of the sub-pixel in a row scanning manner. These signals are known to those skilled in the art and will not be described in detail here.

[0075] Here, description is made by taking the example that the first transistor to the eighth transistor are all PMOS transistors.

[0076] For example, when the display panel needs to display a red screen for testing, the following method can be executed:

[0077] like Figure 4 As shown, in the first stage t1, the Gout(i) signal is at a low level, causing the gate drive circuit of the i-th row to work; the Gout(i+1) signal is at a high level, causing the gate drive circuit of the i+1-th row to not work. Here, i is a positive integer.

[0078] For example, during the first half of the first phase t1, when the first selection signal S MUX1 When the third test switch signal S CTSW3 and the fifth test switch signal S CTSW5 are also at a low level, causing the third transistor T3 and the fifth transistor T5 to be turned on. CTD3 The fifth data signal S may be input to the red sub-pixel R of the i-th row. CTD5 Can be input to the blue sub-pixel B of the i-th row. In the process of displaying a red picture, the third data signal S CTD3 is a data signal that causes the red sub-pixel to emit light, and the fifth data signal S CTD5 is a data signal that cannot make the blue sub-pixel emit light. In this way, the red sub-pixel in the i-th row emits light, while the blue sub-pixel in the i-th row does not emit light.

[0079] Next, during the second half of the first phase t1, the first selection signal S MUX1 , the third test switch signal S CTSW3 and the fifth test switch signal S CTSW5 The second selection signal S MUX2 From high level to low level, the eighth transistors T8 and T8' are turned on. At this time, the first test switch signal S CTSW1 and the second test switch signal S CTSW2 Both become low level, causing the first transistor T1 and the second transistor T2 to be turned on. CTD1 and the second data signal S CTD2 is input to the green sub-pixel G of the i-th row. However, when a red image needs to be displayed, the first data signal S CTD1 and the second data signal S CTD2 These are all data signals that cannot cause the green sub-pixels to emit light, so the green sub-pixels in the i-th row do not emit light subsequently.

[0080] Next, if Figure 4 As shown, in the second phase t2, the Gout(i) signal changes from low level to high level, causing the gate drive circuit of the i-th row to not work. The Gout(i+1) signal changes from high level to low level, causing the gate drive circuit of the i+1-th row to work.

[0081] For example, during the first half of the second stage t2, when the first selection signal S MUX1 When the fourth test switch signal S CTSW4 and the sixth test switch signal S CTSW6 are also at a low level, causing the fourth transistor T4 and the sixth transistor T6 to be turned on. CTD4 is input to the blue sub-pixel B in the i+1th row, the sixth data signal S CTD6 is input to the red sub-pixel R in the i+1th row. In the process of displaying a red picture, the fourth data signal S CTD4 is a data signal that cannot make the blue sub-pixel emit light, and the sixth data signal S CTD6 is a data signal that causes the red sub-pixel to emit light. Thus, subsequently, the red sub-pixel in the i+1th row emits light, while the blue sub-pixel in the i+1th row does not emit light.

[0082] Next, during the second half of the second phase t2, the first selection signal S MUX1 , the fourth test switch signal S CTSW4and the sixth test switch signal S CTSW6 The second selection signal S MUX2 From high level to low level, the eighth transistors T8 and T8' are turned on. At this time, the first test switch signal S CTSW1 and the second test switch signal S CTSW2 Both become low level, causing the first transistor T1 and the second transistor T2 to be turned on. CTD1 and the second data signal S CTD2 is input to the green sub-pixel G in the i+1th row. However, when a red image needs to be displayed, the first data signal S CTD1 and the second data signal S CTD2 These are all data signals that cannot cause the green sub-pixels to emit light, so the green sub-pixels in the (i+1)th row do not emit light subsequently.

[0083] So far, the process of testing the red picture of the display panel has been described. In the process of displaying the red picture, all the red sub-pixels of the display panel are input with data signals that make the red sub-pixels emit light. Although the blue sub-pixels and the green sub-pixels are also input with corresponding data signals, since these data signals cannot make the blue sub-pixels and the green sub-pixels emit light, the red picture can be displayed during the test.

[0084] In other embodiments, when the display panel needs to display a blue picture for testing, a method similar to the above method may be performed. The difference is that: when the blue picture needs to be displayed, the data signals (including the fourth data signal S CTD4 and the fifth data signal S CTD5 ) is a signal that enables the blue sub-pixel to emit light, and the data signal input to the red sub-pixel (including the third data signal S CTD3 and the sixth data signal S CTD6 ) is a data signal that cannot make the red sub-pixel emit light, and the data signal input to the green sub-pixel (including the first data signal S CTD1 and the second data signal S CTD2 Both) are data signals that cannot cause the green sub-pixel to emit light, so the display panel can display a blue picture.

[0085] In some other embodiments, when a green image needs to be displayed, the data signals (including the first data signal S CTD1 and the second data signal S CTD2 ) is a signal that enables the green sub-pixel to emit light, and the data signal input to the red sub-pixel (including the third data signal SCTD3 and the sixth data signal S CTD6 ) is a data signal that cannot make the red sub-pixel emit light, and the data signal input to the blue sub-pixel (including the fourth data signal S CTD4 and the fifth data signal S CTD5 ) is a data signal that cannot make the blue sub-pixel emit light, so the display panel can display a green picture.

[0086] So far, the test process of the display panel according to some embodiments of the present disclosure has been implemented. In the test process, each test component transmits a data signal to a multiplexer electrically connected to the test component under the control of a test switch signal; and the multiplexer transmits the data signal to the corresponding sub-pixel under the control of a selection signal. This can make it easier to test the display panel.

[0087] Figure 5 is a diagram showing an embodiment of the present disclosure Figure 2 FIG. 2 is an enlarged schematic diagram of the first test sub-circuit 221 in FIG.

[0088] In some embodiments, the orthographic projection of the first test sub-circuit on the substrate is centrally symmetrical, which can reduce the layout space of the first test circuit.

[0089] In some embodiments, Figure 2 and Figure 5 As shown, the display panel may further include a first control line LC1, a first data line LD1, and a second data line LD2. The first control line LC1 is electrically connected to the control electrode 510 of the first transistor T1 and the control electrode 520 of the second transistor T2, respectively. For example, the first control line LC1 is electrically connected to the control electrode 510 of the first transistor T1 through a conductive via and a first connector 514, and the first control line LC1 is electrically connected to the control electrode 520 of the second transistor T2 through a conductive via and a second connector 524. The first control line LC1 is configured to transmit a first test switch signal S CTSW1 and the second test switch signal S CTSW2 The first test switch signal is the same as the second test switch signal. The first data line LD1 is electrically connected to the first electrode 511 of the first transistor T1. The first data line LD1 is configured to transmit a first data signal S CTD1 The second data line LD2 is electrically connected to the first electrode 521 of the second transistor T2. The second data line LD2 is configured to transmit the second data signal S CTD2 The orthographic projection of the first control line LC1 on the base substrate is located between the orthographic projection of the first data line LD1 on the base substrate and the orthographic projection of the second data line LD2 on the base substrate. Figure 5Also shown are the first active layer 513 of the first transistor T1 and the second active layer 523 of the second transistor T2.

[0090] like Figure 5 As shown, the second electrode 512 of the first transistor T1 is electrically connected to the first connection wire 2011. The second electrode 512 of the first transistor T1 is electrically connected to the first connection wire 2011 through a conductive via. The second electrode 522 of the second transistor T2 is electrically connected to the second connection wire 2012. For example, the second electrode 522 of the second transistor T2 is electrically connected to the second connection wire 2012 through a conductive via (described later).

[0091] In some embodiments, the orthographic projection of the control electrode 510 of the first transistor T1 on the substrate is located between the orthographic projection of the first electrode 511 of the first transistor T1 on the substrate and the orthographic projection of the second electrode 512 of the first transistor T1 on the substrate. The orthographic projection of the control electrode 520 of the second transistor T2 on the substrate is located between the orthographic projection of the first electrode 521 of the second transistor T2 on the substrate and the orthographic projection of the second electrode 522 of the second transistor T2 on the substrate. The orthographic projection of the first electrode 511 of the first transistor T1 on the substrate and the orthographic projection of the first electrode 521 of the second transistor T2 on the substrate are located between the orthographic projection of the control electrode 510 of the first transistor T1 on the substrate and the orthographic projection of the control electrode 520 of the second transistor T2 on the substrate.

[0092] So far, the layout structure of the first test sub-circuit has been described.

[0093] Figure 6 is a diagram showing an embodiment of the present disclosure Figure 2 FIG. 2 is an enlarged schematic diagram of the second test sub-circuit 222 in FIG.

[0094] In some embodiments, Figure 6 As shown, the third transistor T3 may include two first electrodes 5311 and 5312, one second electrode 532 and two control electrodes 5301 and 5302. The fourth transistor T4 may include two first electrodes 5411 and 5412, one second electrode 542 and two control electrodes 5401 and 5402. In addition, Figure 6 4. The third active layer 533 of the third transistor T3 and the fourth active layer 543 of the fourth transistor T4 are also shown. For example, the third active layer 533 includes a first sub-active layer 5331 and a second sub-active layer 5332, and the fourth active layer 543 includes a third sub-active layer 5431 and a fourth sub-active layer 5432.

[0095] In some embodiments, Figure 6As shown, the display panel may further include a second control line LC2, a third data line LD3, a fourth data line LD4, a third control line LC3, a fifth data line LD5, and a sixth data line LD6.

[0096] The second control line LC2 is electrically connected to the two control electrodes 5301 and 5302 of the third transistor T3. For example, the second control line LC2 can be electrically connected to the two control electrodes 5301 and 5302 of the third transistor T3 through the third connector 534 and the conductive via. The second control line LC2 is configured to transmit the third test switch signal S CTSW3 .

[0097] The third data line LD3 is electrically connected to one of the two first electrodes 5311 of the third transistor T3. The third data line LD3 is configured to transmit a third data signal S CTD3 .

[0098] The fourth data line LD4 is electrically connected to the other first electrode 5312 of the two first electrodes of the third transistor T3. The fourth data line LD4 is configured to transmit the third data signal S CTD3 .

[0099] The third control line LC3 is electrically connected to the two control electrodes 5401 and 5402 of the fourth transistor T4. For example, the third control line LC3 can be electrically connected to the two control electrodes 5401 and 5402 of the fourth transistor T4 through the fourth connector 544 and the conductive via. The third control line LC3 is configured to transmit the fourth test switch signal S CTSW4 .

[0100] The fifth data line LD5 is electrically connected to one first electrode 5411 of the two first electrodes of the fourth transistor T4. The fifth data line LD5 is configured to transmit a fourth data signal S CTD4 .

[0101] The sixth data line LD6 is electrically connected to the other first electrode 5412 of the two first electrodes of the fourth transistor T4. The sixth data line LD6 is configured to transmit the fourth data signal S CTD4 .

[0102] In some embodiments, the orthographic projection of the second control line LC2 on the substrate substrate is located between the orthographic projection of the third control line LC3 on the substrate substrate and the orthographic projection of the sixth data line LD6 on the substrate substrate. The orthographic projection of the third control line LC3 on the substrate substrate is located between the orthographic projection of the second control line LC2 on the substrate substrate and the orthographic projection of the third data line LD3 on the substrate substrate. The orthographic projection of the third data line LD3 on the substrate substrate and the orthographic projection of the sixth data line LD6 on the substrate substrate are located between the orthographic projection of the third transistor T3 on the substrate substrate and the orthographic projection of the fourth transistor T4 on the substrate substrate.

[0103] like Figure 6 As shown, the second electrode 532 of the third transistor T3 and the second electrode 542 of the fourth transistor T4 are both electrically connected to the first connection wire 2011. For example, the second electrode 532 of the third transistor T3 and the second electrode 542 of the fourth transistor T4 can be electrically connected to the first connection wire 2011 through conductive vias (described later), respectively.

[0104] In some embodiments, the positive projection of one control electrode 5301 of the two control electrodes of the third transistor T3 on the substrate substrate is located between the positive projection of one first electrode 5311 of the two first electrodes of the third transistor T3 on the substrate substrate and the positive projection of the second electrode 532 of the third transistor T3 on the substrate substrate. The positive projection of the other control electrode 5302 of the two control electrodes of the third transistor T3 on the substrate substrate is located between the positive projection of the other first electrode 5312 of the two first electrodes of the third transistor T3 on the substrate substrate and the positive projection of the second electrode 532 of the third transistor T3 on the substrate substrate.

[0105] In some embodiments, the positive projection of one control electrode 5401 of the two control electrodes of the fourth transistor T4 on the substrate substrate is located between the positive projection of one first electrode 5411 of the two first electrodes of the fourth transistor T4 on the substrate substrate and the positive projection of the second electrode 542 of the fourth transistor T4 on the substrate substrate. The positive projection of the other control electrode 5402 of the two control electrodes of the fourth transistor T4 on the substrate substrate is located between the positive projection of the other first electrode 5412 of the two first electrodes of the fourth transistor T4 on the substrate substrate and the positive projection of the second electrode 542 of the fourth transistor T4 on the substrate substrate.

[0106] Figure 7 is a diagram showing an embodiment of the present disclosure Figure 2 FIG. 2 is an enlarged schematic diagram of the third test sub-circuit 223 in FIG.

[0107] In some embodiments, Figure 7As shown, the fifth transistor T5 may include two first electrodes 5511 and 5512, one second electrode 552 and two control electrodes 5501 and 5502. The sixth transistor T6 may include two first electrodes 5611 and 5612, one second electrode 562 and two control electrodes 5601 and 5602. In addition, Figure 7 4 and 55. The fifth active layer 553 of the fifth transistor T5 and the sixth active layer 563 of the sixth transistor T6 are also shown. For example, the fifth active layer 553 includes a fifth sub-active layer 5531 and a sixth sub-active layer 5532, and the sixth active layer 563 includes a seventh sub-active layer 5631 and an eighth sub-active layer 5632.

[0108] In some embodiments, Figure 7 As shown, the display panel may further include a fourth control line LC4, a seventh data line LD7, an eighth data line LD8, a fifth control line LC5, a ninth data line LD9 and a tenth data line LD10.

[0109] The fourth control line LC4 is electrically connected to the two control electrodes 5501 and 5502 of the fifth transistor T5. For example, the fourth control line LC4 can be electrically connected to the two control electrodes 5501 and 5502 of the fifth transistor T5 through the fifth connection member 554 and the conductive through hole. The fourth control line LC4 is configured to transmit the fifth test switch signal S CTSW5 .

[0110] The seventh data line LD7 is electrically connected to one first electrode 5511 of the two first electrodes of the fifth transistor T5. The seventh data line LD7 is configured to transmit the fifth data signal S CTD5 .

[0111] The eighth data line LD8 is electrically connected to the other first electrode 5512 of the two first electrodes of the fifth transistor T5. The eighth data line LD8 is configured to transmit the fifth data signal S CTD5 .

[0112] The fifth control line LC5 is electrically connected to the two control electrodes 5601 and 5602 of the sixth transistor T6. For example, the fifth control line LC5 can be electrically connected to the two control electrodes 5601 and 5602 of the sixth transistor T6 through the sixth connector 564 and the conductive via. The fifth control line LC5 is configured to transmit the sixth test switch signal S CTSW6 .

[0113] The ninth data line LD9 is electrically connected to one first electrode 5611 of the two first electrodes of the sixth transistor T6. The ninth data line LD9 is configured to transmit the sixth data signal S CTD6 .

[0114] The tenth data line LD10 is electrically connected to the other first electrode 5612 of the two first electrodes of the sixth transistor T6. The tenth data line LD10 is configured to transmit the sixth data signal S CTD6 .

[0115] In some embodiments, the orthographic projection of the fourth control line LC4 on the substrate substrate is located between the orthographic projection of the fifth control line LC5 on the substrate substrate and the orthographic projection of the ninth data line LD9 on the substrate substrate. The orthographic projection of the fifth control line LC5 on the substrate substrate is located between the orthographic projection of the fourth control line LC4 on the substrate substrate and the orthographic projection of the seventh data line LD7 on the substrate substrate. The orthographic projection of the seventh data line LD7 on the substrate substrate and the orthographic projection of the ninth data line LD9 on the substrate substrate are located between the orthographic projection of the fifth transistor T5 on the substrate substrate and the orthographic projection of the sixth transistor T6 on the substrate substrate.

[0116] In some embodiments, Figure 7 As shown, the second electrode 552 of the fifth transistor T5 and the second electrode 562 of the sixth transistor T6 are both electrically connected to the second connection wire 2012. For example, the second electrode 552 of the fifth transistor T5 and the second electrode 562 of the sixth transistor T6 can be electrically connected to the second connection wire 2012 through conductive vias (described later), respectively.

[0117] In some embodiments, the positive projection of one control electrode 5501 of the two control electrodes of the fifth transistor T5 on the substrate substrate is located between the positive projection of one first electrode 5511 of the two first electrodes of the fifth transistor T5 on the substrate substrate and the positive projection of the second electrode 552 of the fifth transistor T5 on the substrate substrate. The positive projection of the other control electrode 5502 of the two control electrodes of the fifth transistor T5 on the substrate substrate is located between the positive projection of the other first electrode 5512 of the two first electrodes of the fifth transistor T5 on the substrate substrate and the positive projection of the second electrode 552 of the fifth transistor T5 on the substrate substrate.

[0118] In some embodiments, the positive projection of one control electrode 5601 of the two control electrodes of the sixth transistor T6 on the substrate substrate is located between the positive projection of one first electrode 5611 of the two first electrodes of the sixth transistor T6 on the substrate substrate and the positive projection of the second electrode 562 of the sixth transistor T6 on the substrate substrate. The positive projection of the other control electrode 5602 of the two control electrodes of the sixth transistor T6 on the substrate substrate is located between the positive projection of the other first electrode 5612 of the two first electrodes of the sixth transistor T6 on the substrate substrate and the positive projection of the second electrode 562 of the sixth transistor T6 on the substrate substrate.

[0119] So far, the layout diagrams of the first transistor T1 to the sixth transistor T6 according to some embodiments of the present disclosure are described. However, those skilled in the art will appreciate that the above layout diagrams are only exemplary, and the scope of the embodiments of the present disclosure is not limited thereto. For example, in the layout diagram, the positions of the third transistor T3 and the fourth transistor T4 can be interchanged, and the positions of the fifth transistor T5 and the sixth transistor T6 can also be interchanged.

[0120] Figure 8 is a schematic cross-sectional view showing a sub-pixel according to an embodiment of the present disclosure. Figure 8 As shown, at least one sub-pixel includes a ninth transistor T9 and a capacitor C0.

[0121] like Figure 8 As shown, the ninth transistor T9 includes an active layer (for example, may be referred to as a seventh active layer) 802. For example, the active layer 802 may be located on a buffer layer 801. The buffer layer 801 is on a substrate 10. For example, the active layer 802 includes a semiconductor layer. For example, the material of the active layer 802 may include at least one of polycrystalline silicon and amorphous silicon.

[0122] like Figure 8 As shown, the ninth transistor T9 further includes a first insulating layer 811 covering the active layer 802. For example, the first insulating layer 811 may be an inorganic insulating layer. For example, the material of the first insulating layer 811 may include silicon dioxide or silicon nitride.

[0123] like Figure 8 As shown, the ninth transistor T9 further includes a gate 803 on a side of the first insulating layer 811 away from the active layer 802. For example, the material of the gate 803 may include a metal such as molybdenum (Mo).

[0124] like Figure 8 As shown, the ninth transistor T9 further includes a second insulating layer 812 covering the gate 803. For example, the second insulating layer 812 is an inorganic insulating layer. For example, the material of the second insulating layer 812 may include silicon dioxide or silicon nitride.

[0125] like Figure 8 As shown, the ninth transistor T9 further includes an interlayer insulating layer 815 on the side of the second insulating layer 812 away from the gate 803. For example, the interlayer insulating layer 815 is an inorganic insulating layer. For example, the material of the interlayer insulating layer 815 may include silicon dioxide or silicon nitride.

[0126] like Figure 8As shown, the ninth transistor T9 also includes a source 804 and a drain 805 on one side of the interlayer insulating layer 815 away from the second insulating layer 812. For example, the material of the source 804 and the drain 805 may include at least one of titanium (Ti) and aluminum (Al). For example, the source 804 and the drain 805 may include a three-layer structure such as Ti layer / Al layer / Ti layer, respectively. The source 804 and the drain 805 are electrically connected to the active layer 802, respectively. For example, the source 804 is electrically connected to the active layer 802 through a conductive via passing through the first insulating layer 811, the second insulating layer 812 and the interlayer insulating layer 815, and the drain 805 is electrically connected to the active layer 802 through another conductive via passing through the first insulating layer 811, the second insulating layer 812 and the interlayer insulating layer 815.

[0127] So far, the ninth transistor for a sub-pixel according to some embodiments of the present disclosure has been described.

[0128] In some embodiments, Figure 8 As shown, the capacitor C0 includes a first conductive layer 821 in the same layer as the gate 803. For example, the material of the first conductive layer 821 can be the same as that of the gate 803. This can facilitate the manufacture of the display panel. The second insulating layer 812 also covers the first conductive layer 821. Figure 8 As shown, the capacitor C0 further includes a second conductive layer 822 on the side of the second insulating layer 812 away from the first conductive layer 821. The interlayer insulating layer 815 also covers the second conductive layer 822. For example, the materials of the first conductive layer 821 and the second conductive layer 822 may both include a metal such as molybdenum. The capacitor C0 may function to store data.

[0129] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0130] For example, the first conductive layer 821 and the gate 803 are in the same layer. The first conductive layer 821 and the gate 803 are both on the first insulating layer 811. For example, the first conductive layer 821 and the gate 803 can be formed by the same patterning process.

[0131] In some embodiments, Figure 8As shown, the sub-pixel may further include a third insulating layer 813 covering the source electrode 804 and the drain electrode 805. For example, the material of the third insulating layer 813 may include silicon dioxide or silicon nitride.

[0132] like Figure 8 As shown, the sub-pixel may further include a planarization layer 817 on a side of the third insulating layer 813 away from the source electrode 804 and the drain electrode 805. For example, the material of the planarization layer 817 may include an organic insulating material.

[0133] like Figure 8 As shown, the sub-pixel may further include an anode layer 831 on a side of the planarization layer 817 away from the third insulating layer 813. The anode layer 831 is electrically connected to the source 804 or the drain 805. For example, the anode layer 831 is electrically connected to the drain 805 through a conductive via that passes through the planarization layer 817 and the third insulating layer 813.

[0134] like Figure 8 As shown, the sub-pixel may further include a pixel defining layer 840 having an opening 8401 on a side of the planarization layer 817 away from the third insulating layer 813 . The opening 8401 exposes at least a portion of the anode layer 831 .

[0135] like Figure 8 As shown, the sub-pixel may further include a functional layer 832 at least within the opening 8401 and connected to the anode layer 831. For example, the functional layer 832 may include a light-emitting layer and the like.

[0136] like Figure 8 As shown, the sub-pixel may further include a spacer layer 819 on a side of the pixel defining layer 840 away from the planarization layer 817. For example, the material of the spacer layer 819 may include an inorganic insulating material or an organic insulating material.

[0137] like Figure 8 As shown, the sub-pixel may further include a cathode layer 833 on a side of the functional layer 832 away from the anode layer 831. The cathode layer 833 may cover the spacer layer 819 and the functional layer 832. In an embodiment of the present disclosure, the light emitting device includes the anode layer 831, the functional layer 832 and the cathode layer 833.

[0138] In some embodiments, Figure 8 As shown, the sub-pixel may further include an encapsulation layer on a side of the cathode layer 833 away from the functional layer 832. For example, the encapsulation layer may include a first inorganic encapsulation layer 851 covering the cathode layer, an organic encapsulation layer 850 on the first inorganic encapsulation layer 851 away from the cathode layer 833, and a second inorganic encapsulation layer 852 on a side of the organic encapsulation layer 850 away from the first inorganic encapsulation layer 851.

[0139] So far, the structure of the sub-pixel according to some embodiments of the present disclosure has been described.

[0140] In some embodiments, the first connecting wire 2011 and the second conductive layer 822 are in the same layer, and the second connecting wire 2012 and the gate 803 are in the same layer. In other embodiments, the first connecting wire 2011 and the gate 803 are in the same layer, and the second connecting wire 2012 and the second conductive layer 822 are in the same layer.

[0141] In some embodiments, the first to fifth control lines LC1 to LC5 and the first to tenth data lines LD1 to LD10 are all in the same layer as the source 804 or the drain 805 .

[0142] In some embodiments, the control electrodes of the first transistor T1 to the sixth transistor T6 are in the same layer as the gate electrode 803. The active layers of the first transistor T1 to the sixth transistor T6 are in the same layer as the active layer 802 of the ninth transistor T9. The first electrodes of the first transistor T1 to the sixth transistor T6 are in the same layer as the source electrode 804 or the drain electrode 805. The second electrodes of the first transistor T1 to the sixth transistor T6 are in the same layer as the source electrode 804 or the drain electrode 805.

[0143] Fig. 9 The first test sub-circuit according to one embodiment of the present disclosure is shown as follows Figure 5 A cross-sectional view of the structure taken along line AA' in FIG.

[0144] like Fig. 9 As shown, the first electrode 521 and the second electrode 522 of the second transistor T2 are located on the interlayer insulating layer 815. Figure 5 and Fig. 9 As shown, the first electrode 521 of the second transistor T2 is electrically connected to the second active layer 523 through the first conductive via V1. The second electrode 522 of the second transistor T2 is electrically connected to the second active layer 523 through the second conductive via V2. The second electrode 522 of the second transistor T2 is also electrically connected to the second connecting wire 2012 through the third conductive via V3. For example, the control electrode 520 of the second transistor T2 is in the same layer as the second connecting wire 2012.

[0145] The structure of the first transistor T1 is similar to that of the second transistor T2, and will not be described in detail here. Compared with the structure of the second transistor T2, the structure of the first transistor T1 is different in that the second electrode 512 of the first transistor T1 is electrically connected to the first connecting wire 2011 through a conductive through hole.

[0146] Fig.10 The second test sub-circuit according to one embodiment of the present disclosure is shown as follows Figure 6A cross-sectional view of the structure taken along line BB' in FIG.

[0147] like Fig.10 As shown, two first electrodes 5311 and 5312 and one second electrode 532 of the third transistor T3 are located on the interlayer insulating layer 815. Figure 6 and Fig.10 As shown, a first electrode 5311 of the third transistor T3 is electrically connected to the first sub-active layer 5331 through the fourth conductive through hole V4. Another first electrode 5312 of the third transistor T3 is electrically connected to the second sub-active layer 5332 through the fifth conductive through hole V5. The second electrode 532 of the third transistor T3 is electrically connected to the first sub-active layer 5331 through the sixth conductive through hole V6. The second electrode 532 of the third transistor T3 is also electrically connected to the second sub-active layer 5332 through the seventh conductive through hole V7. The second electrode 532 of the third transistor T3 is also electrically connected to the first connecting wire 2011 through the eighth conductive through hole V8 and the ninth conductive through hole V9. For example, the first connecting wire 2011 is in the same layer as the second conductive layer 822.

[0148] The structure of the fourth transistor T4 is similar to that of the third transistor T3 and will not be described in detail here.

[0149] Fig.11 The third test sub-circuit according to one embodiment of the present disclosure is shown as follows Figure 7 A cross-sectional view of the structure taken along line CC'.

[0150] like Fig.11 As shown, two first electrodes 5511 and 5512 and one second electrode 552 of the fifth transistor T5 are located on the interlayer insulating layer 815. Figure 7 and Fig.11 As shown, a first electrode 5511 of the fifth transistor T5 is electrically connected to the fifth sub-active layer 5531 through the tenth conductive through hole V10. Another first electrode 5512 of the fifth transistor T5 is electrically connected to the sixth sub-active layer 5532 through the eleventh conductive through hole V11. The second electrode 552 of the fifth transistor T5 is electrically connected to the fifth sub-active layer 5531 through the twelfth conductive through hole V12. The second electrode 552 of the fifth transistor T5 is also electrically connected to the sixth sub-active layer 5532 through the thirteenth conductive through hole V13. The second electrode 552 of the fifth transistor T5 is also electrically connected to the second connecting wire 2012 through the fourteenth conductive through hole V14 and the fifteenth conductive through hole V15. For example, the second connecting wire 2012 is in the same layer as the gate 803.

[0151] The structure of the sixth transistor T6 is similar to that of the fifth transistor T5 and will not be described in detail here.

[0152] Fig.12 is a schematic diagram showing the layout of a multiplexer according to an embodiment of the present disclosure.

[0153] Here, taking the first multiplexer 241 as an example, Fig.12 Describe the structure of a multiplexer. Fig.12 , a seventh transistor T7 and an eighth transistor T8 are shown. For example, the seventh transistor T7 (or the eighth transistor T8) includes an active layer (which may be referred to as an eighth active layer) 2321, a gate 2322, two first electrodes 2323 and a second electrode 2324. In some embodiments, the seventh transistor T7 and the eighth transistor T8 share a first electrode 2323, which can reduce the space occupied by the multiplexer. The first electrode 2323 is electrically connected to the first connecting wire 2011. In addition, Fig.12 Also shown is a power bus 38.

[0154] The gate 2322 includes a first gate portion 2322 a and a second gate portion 2322 b that are spaced apart from each other, and the first gate portion 2322 a and the second gate portion 2322 b are electrically connected to one control signal line 36 among the plurality of control signal lines 36 .

[0155] The second electrode 2324 is electrically connected to a signal transmission line 202. The orthographic projection of the second electrode 2324 on the substrate is located between the orthographic projections of the two first electrodes 2323 on the substrate. In some embodiments, the second electrode 2324 and the first electrode 2323 are located in the same layer.

[0156] In some embodiments, Fig.12 As shown, the seventh transistor T7 (or the eighth transistor T8) further includes at least one of an electrode connection portion 2325 and a gate connection portion 2326. For example, the two first electrodes 2323 and the electrode connection portion 2325 are integrally arranged. For example, the first gate portion 2322a, the second gate portion 2322b and the gate connection portion 2326 are integrally arranged.

[0157] The orthographic projection of the electrode connection portion 2325 on the base substrate is located between the orthographic projection of the active layer 2321 on the base substrate and the orthographic projection of the plurality of control signal lines 36 on the base substrate. The two first electrodes 2323 are electrically connected to the first connection wires 2011 via the electrode connection portion 2325 .

[0158] The orthographic projection of the gate connection portion 2326 on the substrate is located between the orthographic projection of the active layer 2321 on the substrate and the orthographic projection of the electrode connection portion 2325 on the substrate. The first gate portion 2322a and the second gate portion 2322b are electrically connected to a control signal line 36 via the gate connection portion 2326 .

[0159] In the above embodiment, the seventh transistor T7 (or the eighth transistor T8) further includes at least one of the electrode connection portion 2325 and the gate connection portion 2326. Such a structure facilitates the electrical connection between the first connection wire 2011 and the first electrode 2323, and the electrical connection between the control signal line 36 and the gate 2322.

[0160] In some embodiments, the orthographic projection of the first gate portion 2322a on the substrate is located between the orthographic projection of one of the two first electrodes 2323 on the substrate and the orthographic projection of the second electrode 2324 on the substrate, and the orthographic projection of the second gate portion 2322b on the substrate is located between the orthographic projection of the other of the two first electrodes 2323 on the substrate and the orthographic projection of the second electrode 2324 on the substrate. Such a structure is conducive to reducing the space occupied by the multiplexer.

[0161] In some embodiments, Fig.12 As shown, the active layer 2321 includes a first active portion 2321a and a second active portion 2321b spaced apart from each other. The second active portion 2321b is located between the first active portion 2321a and the display area. Each of the first electrodes 2323 and the second electrode 2324 is electrically connected to the first active portion 2321a through a plurality of sixteenth conductive vias V16, and each of the first electrodes 2323 and the second electrode 2324 is electrically connected to the second active portion 2321b through a plurality of seventeenth conductive vias V17. In this embodiment, the active layer 2321 includes a first active portion 2321a and a second active portion 2321b spaced apart from each other. Such a structure is conducive to the heat dissipation of the transistor and can improve the reliability of the multiplexer.

[0162] Fig.13 is a top view showing the layout of a first test circuit and a second test circuit according to one embodiment of the present disclosure. Fig.14 FIG. 4 is a circuit connection diagram showing a second test circuit according to an embodiment of the present disclosure.

[0163] In some embodiments, Fig.13 As shown, the display panel may further include a second test circuit 701. The second test circuit 701 is located on a side of the first test circuit away from the plurality of sub-pixels. The second test circuit is configured to detect whether there is a crack in the display panel. Fig.14 As shown, the second test circuit 701 includes a plurality of tenth transistors T10 and T10'. The plurality of tenth transistors are electrically connected to the plurality of multiplexers in a one-to-one correspondence. The first electrode of the tenth transistor T10 (or T10') is configured to receive the detection voltage signal S CTD7 (or S' CTD7The second electrode of the tenth transistor T10 (or T10') is electrically connected to the input terminal of the corresponding multiplexer. The control electrode of the tenth transistor T10 (or T10') is configured to receive the seventh test switch signal S CTSW7 . Fig.15 is a schematic diagram showing the detection principle of a second test circuit according to an embodiment of the present disclosure.

[0164] like Fig.15 As shown, the display panel further includes a first detection line LT1 electrically connected to the first electrode of the tenth transistor T10 and a signal input terminal 610 electrically connected to the first detection line LT1. The signal input terminal 610 is used to output a detection voltage signal S to the tenth transistor CTD7 The first detection line LT1 and the signal input terminal 610 are located in the peripheral area 120 .

[0165] Combine the following Fig.11 The principle of the second test circuit for detecting whether the display panel has cracks is described below. Here, transistors T7', T8' and T10' are used as examples for illustration.

[0166] The seventh test switch signal is provided to the tenth transistor T10' so that the tenth transistor T10' is turned on, and the detection voltage signal S' is provided to the tenth switch transistor T10'. CTD7 (For example, a high level). The first selection signal S is provided to the seventh transistor T7'. MUX1 and provides the second selection signal S to the eighth transistor T8' MUX2 .

[0167] In the case where the display panel has no cracks and the first detection line LT1 is not broken, the detection voltage signal S' of a high level (eg, 6V) is CTD7 The light is input to the corresponding sub-pixel through the tenth transistor T10' and the seventh transistor T7' (or the eighth transistor T8'), so that the current flowing through the light-emitting device (such as OLED) of the sub-pixel is relatively small. The light-emitting device hardly emits light. In this way, the display panel displays a black picture. Therefore, if the display panel displays a black picture, it indicates that the display panel has no cracks.

[0168] In the case of a crack in the display panel, the first detection line LT1 is broken, and the first electrode of the tenth transistor T10' is suspended, and it can be considered that the detection voltage signal at this time is approximately 0V. The 0V voltage is input to the sub-pixels of the corresponding column through the tenth transistor T10' and the seventh transistor T7' (or the eighth transistor T8'), so that the current flowing through the light-emitting device of the sub-pixel in the column is relatively large, causing the light-emitting device to emit light. In this way, the display panel displays a bright line.

[0169] Therefore, when the first selection signal and the second selection signal make the seventh transistor and the eighth transistor alternately turned on, if there is a crack in the display panel, the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B all emit light, causing the display panel to display a white bright line. Therefore, in this case, if the display panel displays a white bright line, it is determined that there is a crack in the display panel.

[0170] When the first selection signal turns off the seventh transistor and the second selection signal turns on the eighth transistor, if there is a crack in the display panel, the green sub-pixel G emits light, while the red sub-pixel R and the blue sub-pixel B do not emit light, resulting in the display panel displaying a green bright line. Therefore, in this case, if the display panel displays a green bright line, it is determined that there is a crack in the display panel.

[0171] When the first selection signal turns on the seventh transistor and the second selection signal turns off the eighth transistor, if the display panel has a crack, the red sub-pixel R and the blue sub-pixel B emit light, while the green sub-pixel G does not emit light. Here, the red sub-pixel R and the blue sub-pixel B emit light, causing the display panel to display a magenta bright line. Therefore, in this case, if the display panel displays a magenta bright line, it is determined that the display panel has a crack.

[0172] So far, the principle of the second test circuit for detecting whether there is a crack in the display panel has been described. This detection method is relatively simple and convenient for detection.

[0173] Fig.16 FIG. 4 is a top view schematically showing the layout of a second test circuit according to an embodiment of the present disclosure.

[0174] like Fig.16 As shown, the second test circuit may include a plurality of test components (eg, may be referred to as second test components). Each second test component includes two tenth transistors. For example, the second test component 710 includes two tenth transistors T10 and T10'.

[0175] like Fig.16 As shown, the tenth transistor T10 includes a control electrode 10010, a first electrode 10011 and a second electrode 10012. The control electrode 10010 of the tenth transistor T10 is electrically connected to the sixth control line LC6 through the seventh connection member 10014 and the conductive through hole. The sixth control line LC6 is configured to transmit the seventh test switch signal S CTSW7 The first electrode 10011 of the tenth transistor T10 is electrically connected to the second detection line LT2. The second detection line LT2 is configured to transmit a detection voltage signal S CTD7 The second electrode 10012 of the tenth transistor T10 is electrically connected to the first connection wire 2011 .

[0176] like Fig.16 As shown, the tenth transistor T10' includes a control electrode 10010', a first electrode 10011' and a second electrode 10012'. The control electrode 10010' of the tenth transistor T10' is electrically connected to the sixth control line LC6 through the seventh connection member 10014 and the conductive through hole. The first electrode 10011' of the tenth transistor T10' is electrically connected to the first detection line LT1. The first detection line LT1 is configured to transmit another detection voltage signal S' CTD7 The second electrode 10012 ′ of the tenth transistor T10 ′ is electrically connected to the second connection wire 2012 .

[0177] In some embodiments, the orthographic projections of the sixth control line LC6 , the first detection line LT1 , and the second detection line LT2 on the substrate substrate are located between the orthographic projections of the two tenth transistors T10 and T10 ′ of the second test assembly on the substrate substrate.

[0178] in addition, Fig.16 A third detection line LT3 and a fourth detection line LT4 are also shown in FIG. The third detection line LT3 and the fourth detection line LT4 are respectively configured to provide a detection voltage signal to the tenth transistor of the other second test component.

[0179] In an embodiment of the present disclosure, a display device is also provided. The display device may include the display panel as described above. For example, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0180] Fig.17 FIG. 1 is a flow chart showing a method for testing a display panel according to an embodiment of the present disclosure. Fig.17 As shown, the testing method includes steps S1702 to S1704.

[0181] In step S1702, each test component (ie, each test component of the first test circuit) transmits a data signal to a multiplexer electrically connected to the test component under the control of a test switch signal.

[0182] For example, the test switch signal may include at least one of the first to sixth test switch signals.

[0183] In step S1704, the multiplexer transmits the data signal to the corresponding sub-pixel under the control of the selection signal.

[0184] For example, the selection signal may include at least one of a first selection signal and a second selection signal.

[0185] So far, a test method according to some embodiments of the present disclosure is provided. The test method includes: each test component of the first test circuit transmits a data signal to a multiplexer electrically connected to the test component under the control of a test switch signal; and the multiplexer transmits the data signal to a corresponding sub-pixel under the control of a selection signal, thereby implementing a test on a display panel.

[0186] Fig.18 FIG. 1 is a flow chart showing a method for detecting cracks in a display panel according to an embodiment of the present disclosure. Fig.18 As shown, the crack detection method includes steps S1802 to S1806.

[0187] In step S1802, a detection voltage signal and a seventh test switch signal are provided to each tenth transistor.

[0188] In step S1804, a first selection signal is provided to the seventh transistor, and a second selection signal is provided to the eighth transistor.

[0189] In step S1806, when the display panel displays a bright line, it is determined that there is a crack in the display panel.

[0190] In some embodiments, step S1806 may include: when the first selection signal and the second selection signal cause the seventh transistor and the eighth transistor to be alternately turned on, if the display panel displays a white bright line, it is determined that there is a crack in the display panel; when the first selection signal turns off the seventh transistor and the second selection signal turns on the eighth transistor, if the display panel displays a green bright line, it is determined that there is a crack in the display panel; or when the first selection signal turns on the seventh transistor and the second selection signal turns off the eighth transistor, if the display panel displays a magenta bright line, it is determined that there is a crack in the display panel.

[0191] So far, a crack detection method according to some embodiments of the present disclosure is provided. The crack detection method includes: providing a detection voltage signal and a seventh test switch signal to each tenth transistor; providing a first selection signal to the seventh transistor, and providing a second selection signal to the eighth transistor; and determining that a crack exists in the display panel when the display panel displays a bright line. In this way, crack detection of the display panel is achieved. So far, the various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.

[0192] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A display panel, comprising: A substrate, comprising a display area and a peripheral area located on at least one side of the display area; A plurality of sub-pixels are located on one side of the base substrate and in the display area; A plurality of data signal lines, located in the display area and electrically connected to the plurality of sub-pixels; a plurality of signal transmission lines, located in the peripheral area and electrically connected to the plurality of data signal lines; a plurality of multiplexers located in the peripheral area and on a side of the plurality of signal transmission lines away from the plurality of sub-pixels, at least one of the plurality of multiplexers being electrically connected to at least two signal transmission lines respectively; as well as a first test circuit, located in the peripheral area and on a side of the multiple multiplexers away from the multiple sub-pixels, the first test circuit comprising a plurality of test components, each test component in at least a portion of the multiple test components being electrically connected to at least two of the multiple multiplexers, each of the test components comprising a first test sub-circuit, a second test sub-circuit and a third test sub-circuit, the second test sub-circuit being located between the first test sub-circuit and the third test sub-circuit, the first test sub-circuit being located on a side of the second test sub-circuit away from the multiple sub-pixels, and an orthographic projection of the first test sub-circuit on the substrate being centrally symmetric; Wherein, two adjacent multiplexers are electrically connected to one of the plurality of test components via two connecting wires; The plurality of multiplexers include a first multiplexer and a second multiplexer; The first test subcircuit comprises: a first transistor, a first electrode of the first transistor is configured to receive a first data signal, a second electrode of the first transistor is electrically connected to an input terminal of the first multiplexer, and a control electrode of the first transistor is configured to receive a first test switch signal; and a second transistor, a first electrode of the second transistor is configured to receive a second data signal, a second electrode of the second transistor is electrically connected to an input terminal of the second multiplexer, and a control electrode of the second transistor is configured to receive a second test switch signal; The two connecting wires include a first connecting wire and a second connecting wire; The second electrode of the first transistor is electrically connected to the first connecting wire, and the second electrode of the second transistor is electrically connected to the second connecting wire; The orthographic projection of the control electrode of the first transistor on the substrate is located between the orthographic projection of the first electrode of the first transistor on the substrate and the orthographic projection of the second electrode of the first transistor on the substrate; The orthographic projection of the control electrode of the second transistor on the substrate is located between the orthographic projection of the first electrode of the second transistor on the substrate and the orthographic projection of the second electrode of the second transistor on the substrate; The orthographic projection of the first electrode of the first transistor on the substrate and the orthographic projection of the first electrode of the second transistor on the substrate are located between the orthographic projection of the control electrode of the first transistor on the substrate and the orthographic projection of the control electrode of the second transistor on the substrate; The second test subcircuit comprises: a third transistor, a first electrode of the third transistor is configured to receive a third data signal, a second electrode of the third transistor is electrically connected to the input terminal of the first multiplexer, and a control electrode of the third transistor is configured to receive a third test switch signal; and a fourth transistor, a first electrode of the fourth transistor is configured to receive a fourth data signal, a second electrode of the fourth transistor is electrically connected to the input terminal of the first multiplexer, and a control electrode of the fourth transistor is configured to receive a fourth test switch signal; The third transistor includes two first electrodes, one second electrode and two control electrodes, and the fourth transistor includes two first electrodes, one second electrode and two control electrodes; The second electrode of the third transistor and the second electrode of the fourth transistor are both electrically connected to the first connecting wire; The orthographic projection of one of the two control electrodes of the third transistor on the substrate is located between the orthographic projection of one of the two first electrodes of the third transistor on the substrate and the orthographic projection of the second electrode of the third transistor on the substrate, and the orthographic projection of the other of the two control electrodes of the third transistor on the substrate is located between the orthographic projection of the other of the two first electrodes of the third transistor on the substrate and the orthographic projection of the second electrode of the third transistor on the substrate; and The orthographic projection of one of the two control electrodes of the fourth transistor on the substrate substrate is located between the orthographic projection of one of the two first electrodes of the fourth transistor on the substrate substrate and the orthographic projection of the second electrode of the fourth transistor on the substrate substrate, and the orthographic projection of the other of the two control electrodes of the fourth transistor on the substrate substrate is located between the orthographic projection of the other of the two first electrodes of the fourth transistor on the substrate substrate and the orthographic projection of the second electrode of the fourth transistor on the substrate substrate.

2. The display panel according to claim 1, wherein: The third test subcircuit includes: a fifth transistor, a first electrode of the fifth transistor is configured to receive a fifth data signal, a second electrode of the fifth transistor is electrically connected to the input terminal of the second multiplexer, and a control electrode of the fifth transistor is configured to receive a fifth test switch signal; and a sixth transistor, a first electrode of the sixth transistor is configured to receive a sixth data signal, a second electrode of the sixth transistor is electrically connected to the input terminal of the second multiplexer, and a control electrode of the sixth transistor is configured to receive a sixth test switch signal.

3. The display panel according to claim 2, further comprising: a first control line, electrically connected to a control electrode of the first transistor and a control electrode of the second transistor, respectively, and configured to transmit the first test switch signal and the second test switch signal, the first test switch signal being the same as the second test switch signal; a first data line electrically connected to the first electrode of the first transistor and configured to transmit a first data signal; as well as a second data line electrically connected to the first electrode of the second transistor and configured to transmit the second data signal; The orthographic projection of the first control line on the base substrate is located between the orthographic projection of the first data line on the base substrate and the orthographic projection of the second data line on the base substrate.

4. The display panel according to claim 3, wherein: The display panel further includes: a second control line electrically connected to two control electrodes of the third transistor and configured to transmit the third test switch signal; a third data line electrically connected to one of the two first electrodes of the third transistor and configured to transmit the third data signal; a fourth data line electrically connected to the other of the two first electrodes of the third transistor and configured to transmit the third data signal; a third control line, electrically connected to the two control electrodes of the fourth transistor, and configured to transmit the fourth test switch signal; a fifth data line electrically connected to one of the two first electrodes of the fourth transistor and configured to transmit the fourth data signal; and a sixth data line electrically connected to the other of the two first electrodes of the fourth transistor and configured to transmit the fourth data signal; Among them, the orthographic projection of the second control line on the substrate substrate is located between the orthographic projection of the third control line on the substrate substrate and the orthographic projection of the sixth data line on the substrate substrate; the orthographic projection of the third control line on the substrate substrate is located between the orthographic projection of the second control line on the substrate substrate and the orthographic projection of the third data line on the substrate substrate; the orthographic projection of the third data line on the substrate substrate and the orthographic projection of the sixth data line on the substrate substrate are located between the orthographic projection of the third transistor on the substrate substrate and the orthographic projection of the fourth transistor on the substrate substrate.

5. The display panel according to claim 4, wherein: The fifth transistor includes two first electrodes, one second electrode and two control electrodes, and the sixth transistor includes two first electrodes, one second electrode and two control electrodes; The display panel further includes: a fourth control line, electrically connected to the two control electrodes of the fifth transistor, and configured to transmit the fifth test switch signal; a seventh data line electrically connected to one of the two first electrodes of the fifth transistor and configured to transmit the fifth data signal; and an eighth data line electrically connected to the other of the two first electrodes of the fifth transistor and configured to transmit the fifth data signal; a fifth control line, electrically connected to the two control electrodes of the sixth transistor, and configured to transmit the sixth test switch signal; a ninth data line electrically connected to one of the two first electrodes of the sixth transistor and configured to transmit the sixth data signal; and a tenth data line electrically connected to the other of the two first electrodes of the sixth transistor and configured to transmit the sixth data signal; Among them, the orthographic projection of the fourth control line on the substrate substrate is located between the orthographic projection of the fifth control line on the substrate substrate and the orthographic projection of the ninth data line on the substrate substrate; the orthographic projection of the fifth control line on the substrate substrate is located between the orthographic projection of the fourth control line on the substrate substrate and the orthographic projection of the seventh data line on the substrate substrate; the orthographic projection of the seventh data line on the substrate substrate and the orthographic projection of the ninth data line on the substrate substrate are located between the orthographic projection of the fifth transistor on the substrate substrate and the orthographic projection of the sixth transistor on the substrate substrate.

6. The display panel according to claim 5, wherein: The second electrode of the fifth transistor and the second electrode of the sixth transistor are both electrically connected to the second connecting wire; The orthographic projection of one of the two control electrodes of the fifth transistor on the substrate is located between the orthographic projection of one of the two first electrodes of the fifth transistor on the substrate and the orthographic projection of the second electrode of the fifth transistor on the substrate, and the orthographic projection of the other of the two control electrodes of the fifth transistor on the substrate is located between the orthographic projection of the other of the two first electrodes of the fifth transistor on the substrate and the orthographic projection of the second electrode of the fifth transistor on the substrate; as well as The orthographic projection of one of the two control electrodes of the sixth transistor on the substrate substrate is located between the orthographic projection of one of the two first electrodes of the sixth transistor on the substrate substrate and the orthographic projection of the second electrode of the sixth transistor on the substrate substrate, and the orthographic projection of the other of the two control electrodes of the sixth transistor on the substrate substrate is located between the orthographic projection of the other of the two first electrodes of the sixth transistor on the substrate substrate and the orthographic projection of the second electrode of the sixth transistor on the substrate substrate.

7. The display panel according to claim 1, wherein: Each multiplexer includes a seventh transistor and an eighth transistor, wherein the seventh transistor and the eighth transistor share a first electrode, the first electrode serves as an input terminal of the multiplexer, a second electrode of the seventh transistor is electrically connected to one of the at least two signal transmission lines, a control electrode of the seventh transistor is configured to receive a first selection signal, a second electrode of the eighth transistor is electrically connected to another of the at least two signal transmission lines, and a control electrode of the eighth transistor is configured to receive a second selection signal.

8. The display panel according to claim 6, wherein: at least one sub-pixel includes a ninth transistor and a capacitor; The ninth transistor comprises: Active layer; a first insulating layer covering the active layer; a gate on a side of the first insulating layer away from the active layer; a second insulating layer covering the gate; an interlayer insulating layer on a side of the second insulating layer away from the gate; and A source electrode and a drain electrode on a side of the interlayer insulating layer away from the second insulating layer, wherein the source electrode and the drain electrode are electrically connected to the active layer respectively; The capacitor comprises: a first conductive layer in the same layer as the gate, wherein the second insulating layer also covers the first conductive layer; and A second conductive layer on a side of the second insulating layer away from the first conductive layer, wherein the interlayer insulating layer further covers the second conductive layer.

9. The display panel according to claim 8, wherein: The at least one sub-pixel further comprises: a third insulating layer covering the source electrode and the drain electrode; A planarization layer on a side of the third insulating layer away from the source electrode and the drain electrode; An anode layer on a side of the planarization layer away from the third insulating layer, wherein the anode layer is electrically connected to the source electrode or the drain electrode; a pixel defining layer having an opening on a side of the planarization layer away from the third insulating layer, wherein the opening exposes at least a portion of the anode layer; a functional layer at least within the opening and connected to the anode layer; and A cathode layer is provided on a side of the functional layer away from the anode layer.

10. The display panel according to claim 9, wherein: The first connecting wire and the second conductive layer are in the same layer, and the second connecting wire and the gate are in the same layer; The first control line to the fifth control line, and the first data line to the tenth data line are all in the same layer as the source electrode or the drain electrode; The control electrodes of the first to sixth transistors are in the same layer as the gate, the active layers of the first to sixth transistors are in the same layer as the active layer of the ninth transistor, the first electrodes of the first to sixth transistors are in the same layer as the source or the drain, and the second electrodes of the first to sixth transistors are in the same layer as the source or the drain.

11. The display panel according to claim 7, further comprising: a second test circuit, comprising a plurality of tenth transistors, the plurality of tenth transistors being electrically connected to the plurality of multiplexers in a one-to-one correspondence; A first electrode of the tenth transistor is configured to receive a detection voltage signal, a second electrode of the tenth transistor is electrically connected to an input terminal of a corresponding multiplexer, and a control electrode of the tenth transistor is configured to receive a seventh test switch signal.

12. The display panel according to claim 1, further comprising: A first signal access terminal group, located in the peripheral area, located on one side of the first test circuit in an extending direction along a boundary between the display area and the peripheral area, and electrically connected to the first test circuit; and The second signal access terminal group is located in the peripheral area, on a side of the first test circuit away from the first signal access terminal group in an extending direction along the boundary between the display area and the peripheral area, and is electrically connected to the first test circuit.

13. A display device, comprising: A display panel as claimed in any one of claims 1 to 12.

14. A method for testing the display panel according to claim 1, comprising: Each test component transmits a data signal to a multiplexer electrically connected to the test component under the control of a test switch signal; as well as The multiplexer transmits the data signal to the corresponding sub-pixel under the control of the selection signal.

15. A crack detection method for a display panel according to claim 11, comprising: providing the detection voltage signal and the seventh test switch signal to each tenth transistor; providing the first selection signal to the seventh transistor, and providing the second selection signal to the eighth transistor; as well as When the display panel displays a bright line, it is determined that the display panel has a crack.

16. The crack detection method according to claim 15, wherein: The step of determining whether the display panel has cracks includes: When the first selection signal and the second selection signal cause the seventh transistor and the eighth transistor to be alternately turned on, if the display panel displays a white bright line, it is determined that there is a crack in the display panel; When the first selection signal turns off the seventh transistor and the second selection signal turns on the eighth transistor, if the display panel displays a green bright line, it is determined that there is a crack in the display panel; or When the first selection signal turns on the seventh transistor and the second selection signal turns off the eighth transistor, if the display panel displays a magenta bright line, it is determined that a crack exists in the display panel.

Images